A high-resistance field plate shield gate trench field effect transistor device and method of manufacture

Abstract

A high-resistance field plate shield gate trench type field effect transistor device and manufacturing method, the present application belongs to power semiconductor device, it includes: the drain metal layer at the bottom, the N+ substrate layer above the drain metal layer, the N type epitaxial layer above the N+ substrate layer, the P doped body area and N+ doped source area on the device upper surface, the N+ doped source area is connected with the source metal on the device upper surface, the N type epitaxial layer is provided with the trench, the trench is filled with shield gate electrode and the gate electrode on the left and right sides or one side of shield gate electrode, the shield gate electrode is connected with the upper surface metal on the top of the device, the high-resistance field plate is arranged below the shield gate electrode, the high-resistance field plate extends to the N+ substrate layer below, the high-resistance field plate and the sidewall of the trench have thin oxide layer isolation, beneficial effect lies in, utilize high-resistance field plate, reduce the electric field intensity in the deep trench, realize the uniform electric field intensity distribution, increase breakdown voltage.

Description

Technical Field

[0001] This invention pertains to power semiconductor devices, specifically relating to a high-resistivity field-plate shielded gate trench type field-effect transistor device and its manufacturing method. Background Technology

[0002] The following section will explain the relevant technical background of existing shielded gate trench field-effect transistors. It should be noted that the positional terms used in this document, such as "upper," "lower," "left," "right," "front," "back," "vertical," "horizontal," and "vertical," correspond to the relative positions shown in the reference illustrations. No fixed orientation is restricted in actual implementation. It should also be noted that the devices in the accompanying drawings are not necessarily drawn to scale. The straight lines showing the boundaries of the doped regions and trenches in the drawings, as well as the sharp angles formed by these boundaries, are generally not straight lines or precise angles in practical applications.

[0003] Shielded trench MOSFETs are characterized by low on-resistance and fast switching speed. Figure 1 The diagram shows a cross-sectional view of a conventional N-type shielded gate trench field-effect transistor. The device structure includes: a drain metal layer (113) at the bottom; an N+ substrate layer (100) above the drain metal layer; an N-type epitaxial layer (101) above the N+ substrate layer; and a P-doped region (108) and an N+ doped source region (107) on the upper surface of the device. A series of trenches are present on the N-type epitaxial layer, each trench filled with three electrodes: gate electrodes (106) on the left and right sides, and a shielded gate electrode (105) in the middle. The gate electrode (106) is isolated from the corresponding trench sidewall by a gate oxide layer (103); the shielded gate electrode (105) is isolated from the corresponding trench sidewall by a trench oxide layer (102); and the gate electrode (106) and the shielded gate electrode (105) are isolated by an inter-electrode isolation oxide layer (104). Meanwhile, the N+ doped source region (107) is connected to the source metal (110) located on the upper surface of the device through a via on the oxide dielectric layer (114); the shielded gate electrode (105) is connected to the source metal (111) located on the upper surface of the device through a via on the oxide dielectric layer (114); and the gate electrode (106) is connected to the gate metal (112) located on the upper surface of the device through a via on the oxide dielectric layer (114).

[0004] As the breakdown voltage of a shielded gate trench MOSFET increases, the trench depth and the thickness of the trench oxide layer (102) need to be adjusted accordingly to achieve charge balance. For devices above 100V, the trench oxide layer (102) often needs a thickness of more than 5000A. However, increasing the thickness of the thick trench oxide layer increases the trench width, which in turn reduces the silicon area required for the device to conduct and increases the on-resistance of the device.

[0005] In addition, the shielded gate trench type field effect transistor device forms a high electric field at the bottom of the trench and the region below the P-doped body region (108) when reverse biased, which limits the further improvement of the breakdown voltage of the device.

[0006] Furthermore, in the shielded gate trench type field effect transistor structure described above, the shielded gate electrode (105) is connected to the source electrode, and the potential of the shielded gate electrode in the trench is equal to the potential of the source electrode when the device is reverse biased. Therefore, there is a relatively high potential difference in the horizontal direction at the semiconductor drift region near the bottom of the shielded gate electrode. Therefore, when the device undergoes avalanche breakdown, the high-energy electron current easily falls into the trench oxide layer in the horizontal direction, thereby reducing the electric field strength near the trench, resulting in instability of the breakdown voltage and even affecting the UIS performance of the device.

[0007] Finally, in high-frequency applications, the parasitic capacitance between the shielded gate electrode and the drift region is large, thus a large source-drain capacitance is generated, which easily generates a large overshoot current during switching, which is not conducive to the reliability of the circuit system. SUMMARY

[0008] To solve the above problems, the present application provides a high-resistance field plate shielded gate trench type field effect transistor device and a manufacturing method, which has lower resistance, higher breakdown voltage and improved switching performance than the existing shielded gate trench type field effect transistor device.

[0009] The present application adopts the following technical solutions:

[0010] A high-resistance field plate shielded gate trench type field effect transistor device, comprising: a drain metal layer at the bottom; an N+ substrate layer above the drain metal layer; an N-type epitaxial layer above the N+ substrate layer; a P-doped body region and an N+ doped source region on the upper surface of the device; the N+ doped source region is connected to a source metal on the upper surface of the device;

[0011] A trench is provided on the N-type epitaxial layer, the trench is filled with a shielded gate electrode and a gate electrode on the left and right sides or one side of the shielded gate electrode, the shielded gate electrode is connected to the upper surface metal at the top of the device, a high-resistance field plate is provided below the shielded gate electrode, the high-resistance field plate extends to the N+ substrate layer below, and a thin oxide layer is provided between the high-resistance field plate and the sidewall of the trench.

[0012] Optionally, the high-resistance field plate is composed of materials with varying resistivity from top to bottom or composed of multiple layers of materials with different resistivities.

[0013] Optionally, the high-resistance field plate is composed of materials with varying resistivity and is divided into at least two parts, the upper part has a lower resistivity than the lower part, and the boundary between the upper and lower parts is located at 0.1-0.5 um below the adjacent gate electrode.

[0014] Optionally, the high-resistance field plate is composed of a material with varying resistivity and is divided into at least an upper part and a lower part, wherein the upper part has a lower resistivity than the lower part, and the boundary between the upper part and the lower part is located above the junction between the adjacent N-type epitaxial layer and the N+ substrate layer.

[0015] Optionally, the high-resistance field plate is a thin conductive layer covering the thin oxide layer, and the thin conductive layer is filled with a filling material in the trench formed by the thin conductive layer.

[0016] Optionally, the trench is divided into an upper part and a lower part, wherein the width of the upper part is greater than the width of the lower part.

[0017] Optionally, a P-type implantation region is formed in the N-type epitaxial layer at the bottom of the high-resistance field plate.

[0018] Optionally, a P-type charge storage layer is provided between the thin oxide layer and the trench.

[0019] Optionally, a P-type island region is formed in the N-type epitaxial layer below the P-doped body region.

[0020] A manufacturing method of a high-resistance field plate shield gate trench type field effect transistor device, comprising the steps of:

[0021] S1, forming a trench on a semiconductor, and forming a thin oxide layer in the trench, and then removing the thin oxide layer at the bottom of the trench;

[0022] S2, filling a high-resistance field plate material in the trench, and then filling a shield gate electrode material;

[0023] S3, etching back the thin oxide layer;

[0024] S4, forming a gate oxide layer and a shield gate oxide layer;

[0025] S5, forming a gate electrode, and then forming an upper surface metal, a contact hole, and finally forming a device.

[0026] A manufacturing method of a high-resistance field plate shield gate trench type field effect transistor device, comprising the steps of:

[0027] S1, forming a trench on a semiconductor, and forming a thin oxide layer in the trench, and then removing the thin oxide layer at the bottom of the trench;

[0028] S2, forming a thin conductive layer covering the thin oxide layer in the trench, and then filling a filling material;

[0029] S3, etching back the thin oxide layer;

[0030] S4, forming a gate oxide layer and a shield gate oxide layer;

[0031] S5, forming gate electrode, then forming upper surface metal, contact hole, and finally forming device.

[0032] A manufacturing method of high-resistance field plate shield gate trench type field effect transistor device, steps include:

[0033] S1, forming trench on semiconductor, and forming thin oxide layer in the trench, then removing thin oxide layer at the bottom of the trench;

[0034] S2, filling high-resistance field plate material in the trench to form narrow trench high-resistance field plate structure,

[0035] S3, etching wide trench above semiconductor, re-etching thin oxide layer, and then filling shield gate electrode material;

[0036] S4, forming gate oxide layer and shield gate oxide layer;

[0037] S5, forming gate electrode, then forming upper surface metal, contact hole, and finally forming device.

[0038] A manufacturing method of high-resistance field plate shield gate trench type field effect transistor device, steps include:

[0039] S1, forming wide trench on semiconductor, and forming gate oxide layer and gate electrode;

[0040] S2, etching middle part of gate electrode and semiconductor below the gate electrode to form narrow trench, at this time, part of gate electrode remains in wide trench;

[0041] S3, filling high-resistance field plate material in the trench to form high-resistance field plate structure;

[0042] S4, performing thermal oxidation to form shield gate oxide layer on gate electrode, and then filling shield gate electrode material;

[0043] S5, forming upper surface metal, contact hole, and finally forming device.

[0044] The present application has the beneficial effect of providing a novel trench type field effect transistor device structure with high-resistance field plate, which utilizes high-resistance field plate to reduce electric field intensity at deep trench, thereby realizing uniform electric field intensity distribution and increasing breakdown voltage. In the device of the present application, breakdown voltage is independent of thickness of trench oxide layer, so that the trench width is narrower, the device conduction area is larger, and the conduction resistance is lower. At the same time, high-resistance field plate provides current path in vertical direction of the device, avoiding the influence of high-energy electron trapping. In addition, high-resistance field plate between source and drain in the device of the present application can act as a buffer, which can improve overshoot current during device switching and reverse recovery. BRIEF DESCRIPTION OF DRAWINGS

[0045] Figure 1This is a cross-sectional schematic diagram of an existing shielded gate trench field-effect transistor device;

[0046] Figure 2 This is a cross-sectional schematic diagram of a first embodiment of the shielded gate trench field-effect transistor device of the present invention;

[0047] Figure 3 The electric field intensity distribution with depth for a conventional shielded gate trench field-effect transistor device and the device of the present invention under reverse bias;

[0048] Figures 4A-4C for Figure 2 A cross-sectional schematic diagram of some steps of the manufacturing method of Embodiment 1;

[0049] Figure 5 This is a cross-sectional schematic diagram of a second embodiment of the shielded trench field-effect transistor of the present invention;

[0050] Figures 6A-6B for Figure 5 A cross-sectional schematic diagram of some steps in the manufacturing process of Example 2;

[0051] Figure 7 This is a cross-sectional schematic diagram of Embodiment 3 of the shielded trench field-effect transistor of the present invention;

[0052] Figure 8 This is a cross-sectional schematic diagram of Embodiment 4 of the shielded trench field-effect transistor of the present invention;

[0053] Figure 9 This is a cross-sectional schematic diagram of Embodiment 5 of the shielded trench field-effect transistor of the present invention;

[0054] Figure 10 This is a cross-sectional schematic diagram of Embodiment Six of the Shielded Grid Trench Type Field Effect Transistor of the present invention;

[0055] Figure 11 These are cross-sectional schematic diagrams of embodiments seven and eight of the shielded trench type field-effect transistor of the present invention. Detailed Implementation

[0056] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0057] It should be noted that in the following description of the shielded gate trench field-effect transistor device and its manufacturing method of the present invention, the semiconductor substrate of the shielded gate trench field-effect transistor device is considered to be made of silicon (Si) material. However, the substrate can also be made of any other material suitable for manufacturing shielded gate trench field-effect transistors, such as gallium nitride (GaN), silicon carbide (SiC), etc. In the following description, the conductivity type of the semiconductor region is divided into P-type (second conductivity type) and N-type (first conductivity type). A P-type conductivity semiconductor region can be formed by doping the original semiconductor region with one or more impurities. These impurities can be, but are not limited to, boron (B), aluminum (Al), gallium (Ga), etc. An N-type conductivity semiconductor region can also be formed by doping the original semiconductor region with one or more impurities. These impurities can be, but are not limited to, phosphorus (P), arsenic (As), tellurium (Sb), selenium (Se), proton (H+), etc. In the following description, heavily doped P-type conductive semiconductor regions are designated as P+ regions, and heavily doped N-type conductive semiconductor regions are designated as N+ regions. For example, in a silicon substrate, unless otherwise specified, the impurity concentration of a heavily doped region is typically 1 × 10⁻⁶. 19 cm⁻³ to 1 × 10⁻³ 21 Between cm-3. Those skilled in the art should know that the P-type (second conductivity type) and N-type (first conductivity type) described in this invention are interchangeable.

[0058] Example 1:

[0059] like Figure 2 As shown, this embodiment provides a high-resistivity field-plate shielded gate trench field-effect transistor device, including: a drain metal layer 213 at the bottom; an N+ substrate layer 201 above the drain metal layer 213; an N-type epitaxial layer 202 above the N+ substrate layer; a P-doped region and an N+ doped source region on the upper surface of the device; the N+ doped source region is connected to the source metal 210 on the upper surface of the device; a trench 200 is provided on the N-type epitaxial layer 202, the trench 200 is filled with a shielded gate electrode 205 and a gate electrode 206 located on the left and right sides or one side of the shielded gate electrode 205, the shielded gate electrode 205 is connected to the upper surface metal 211 at the top of the device, a high-resistivity field plate 220 is provided below the shielded gate electrode 205, the high-resistivity field plate 220 extends into the N+ substrate layer 201, and a thin oxide layer 221 isolates the high-resistivity field plate 220 and the sidewall of the trench 200.

[0060] The gate electrode 206 and the sidewall of the trench 200 are isolated by a gate oxide layer. The gate electrode 206 and the shielded gate electrode 205 are isolated by an inter-electrode isolation oxide layer.

[0061] The gate electrode 206 is usually made of polysilicon. The shield gate electrode 205 can be made of polysilicon or amorphous silicon, or made of metal or metal compound, such as Ti, TiN, W, Pt, etc.

[0062] The high-resistance field plate 220 can be made of high-resistance polysilicon SIPOS, amorphous silicon, silicon oxynitride, metal compound, such as TiN, SiTi, etc., or made of organic compound, etc. In order to limit the leakage current between the source and the drain, and considering the RC delay of the high-resistance field plate, the resistivity of the high-resistance field plate 220 from the upper end to the lower end needs to be reasonably selected according to the actual application. Generally, a narrower trench 200 is conducive to forming a high-resistance field plate 220 with a larger resistance value. For example, in an embodiment of a 100V device with an active area of 10mm 2 , the width of the high-resistance field plate is between 0.05-0.5um, and the resistivity of the high-resistance field plate is between 1e-4 Ohm-m and 1e-7 Ohm-m.

[0063] The depth of the high-resistance field plate 220 depends on the voltage resistance of the device. For example, in an embodiment of a 100V device, the optional depth of the high-resistance field plate is between 4-8um; in an embodiment of a 200V device, the optional depth of the high-resistance field plate is between 6-14um.

[0064] The thin oxide layer 221 between the high-resistance field plate 220 and the sidewall of the semiconductor trench 200 has an optional thickness of 0.05 to 0.4um.

[0065] As shown in Figure 3 , the distribution of the electric field strength with depth of the conventional shield gate trench type field effect transistor device and the above-mentioned device under reverse bias is compared. The upper graph is the conventional device, and the lower graph is the device of the present application. The conventional device will form a region with higher electric field strength at the bottom of the trench 200 and below the P-doped body region under reverse bias, which limits the breakdown voltage of the device. Compared with the conventional shield gate trench type field effect transistor device, the linear potential difference can be formed in the high-resistance field plate of the device of the present application under reverse bias, and a uniform electric field distribution is formed on the semiconductor electrically coupled between the P-doped body region and the bottom of the trench 200, realizing a higher breakdown voltage.

[0066] Optionally, the high-resistance field plate 220 is made of material with varying resistivity from top to bottom or is made of multiple layers of material with different resistivity to provide a desired coupling field distribution. Here, the top to bottom of the high-resistance field plate 220 refers to the position from the top of the high-resistance field plate 220 close to the top of the device to the bottom of the high-resistance field plate 220 close to the bottom of the device. For example, to avoid high electric field in the corner of the gate electrode 206 under reverse bias, the high-resistance field plate 220 can be made of material with low resistivity on the top and high resistivity on the bottom, so that a relatively low-high electric field distribution is presented in the semiconductor. As a result, the electric field intensity in the corner of the gate electrode 206 under the P-doped body region is reduced, and the corner of the gate electrode 206 is protected.

[0067] In an optional embodiment, the high-resistance field plate 220 is made of material with varying resistivity and is divided into at least two parts, wherein the resistivity of the upper part is lower than that of the lower part, and the boundary between the upper and lower parts is located at 0.1-0.5 um below the adjacent gate electrode 206.

[0068] In an optional embodiment, the high-resistance field plate 220 is made of material with varying resistivity and is divided into at least two parts, wherein the resistivity of the upper part is lower than that of the lower part, and the boundary between the upper and lower parts is located above the junction between the adjacent N-type epitaxial layer 202 and the N+ substrate layer 201.

[0069] Compared with conventional devices, the breakdown voltage of the device of the present application is independent of the thickness of the thin oxide layer 221, so the width of the trench 200 can be narrower, and the cell size is smaller. In an embodiment of a 100V device, the width of the trench 200 of a conventional device is between 1.5um and 3um, and the cell size is between 2um and 4um; while the width of the trench 200 of the device of the present application can be between 1um and 3um. Therefore, the device of the present application has a larger on-state area, a larger channel density, and a lower on-state resistance.

[0070] At the same time, compared with conventional structures, the potential difference in the horizontal direction of the semiconductor near the trench 200 of the device of the present application under reverse bias is smaller, and the electric field is lower, and the high-resistance field plate provides a current path in the vertical direction of the device, so the problem of unstable breakdown voltage caused by high-energy electrons falling into the trench 200 during avalanche breakdown can be avoided.

[0071] In addition, the high-resistance field plate in the device of the present application can improve the overshoot current during device switching and reverse recovery as a snubber.

[0072] Figure 2In the structure shown, the shielding gate electrode 205 serves to connect the potential of the upper surface metal 211 to the high-resistivity field plate 220, while also facilitating the formation of a thicker inter-electrode isolation oxide layer to reduce the capacitance between the source and the gate. In some embodiments, such as when an oxidizable material is used as the high-resistivity field plate material, the high-resistivity field plate 220 may be directly connected to the upper surface metal 211, omitting the shielding gate electrode 205 structure.

[0073] Furthermore, the upper surface metal 211 is typically connected to the source. However, the function of the upper surface metal 211 is to provide a lower potential than the drain to the high-resistivity field plate during reverse bias to form a current path; therefore, the upper surface metal may also be connected to other potentials besides the drain. In some embodiments, the upper surface metal 211 may be connected to additional electrodes outside the source, drain, and gate. The potential of the additional electrodes may be provided by external circuitry. In one embodiment, the field-effect transistor device has additional electrodes outside the source, drain, and gate, which are connected to the high-resistivity field plate 230 and a portion of the upper surface metal 211.

[0074] like Figures 4A to 4C As shown, the display Figure 2 A feasible manufacturing method for a high-resistivity field-plate shielded gate trench type field-effect transistor device adapted to Embodiment 1 includes the following steps:

[0075] S1. A trench 200 is formed on the semiconductor, and a thin oxide layer 221 is formed in the trench 200. Then, the thin oxide layer 221 at the bottom of the trench 200 is removed. The method for removing the thin oxide layer 221 at the bottom of the trench 200 may be dry etching.

[0076] S2. Fill the trench 200 with high-resistivity field plate material, and then fill it with shielding gate electrode material 205. For example... Figure 4A As shown. The high-resistivity field plate material may be formed by chemical vapor deposition (CVD). In one embodiment, the resistivity of the high-resistivity field plate material varies with the trench depth 200, wherein the resistivity of the high-resistivity field plate is adjusted by changes in parameters during the CVD process;

[0077] S3, return to thin oxide layer 221, such as Figure 4B As shown;

[0078] S4. Forming the gate oxide layer and the shielding gate oxide layer 222, such as Figure 4CThe shield gate oxide layer 222 and the gate oxide layer can be formed simultaneously by thermal oxidation. The shield gate oxide layer 222 is usually thicker than the gate oxide layer. Before thermal oxidation, amorphous silicon or amorphous siliconized polysilicon can be included in the shield gate electrode material 205 to increase the oxidation rate of the shield gate electrode material, so as to form a thicker shield gate oxide layer 222. In one embodiment, the shield gate electrode material 205 is polysilicon, and after filling the shield gate electrode material 205, ion implantation is performed on the polysilicon to increase the oxidation rate of the shield gate electrode material;

[0079] S5, forming the gate electrode 206, then forming the upper surface metal, the contact hole, and finally forming the device; the material of the gate electrode 206 can be polysilicon or metal, so as to further reduce the gate resistance.

[0080] Embodiment two:

[0081] In addition to the structure proposed above, the high-resistance field plate 220 described in the present application can have more variations. In order to further reduce the resistivity of the high-resistance field plate 220 and improve the process uniformity, a device structure is as shown in Figure 5 , wherein the high-resistance field plate 220 is a thin conductive layer covering the thin oxide layer 221. The trench 200 formed by the thin conductive layer is filled with a filling material 230.

[0082] In this structure, the resistivity of the high-resistance field plate 220 can be adjusted by controlling the thickness of the thin conductive layer, and it is easy to achieve a higher resistivity and better process uniformity.

[0083] As shown in Figures 6A to 6B , a feasible manufacturing method of a high-resistance field plate shield gate trench type field effect transistor device suitable for embodiment two, the steps include:

[0084] S1, forming the trench 200 on the semiconductor, and forming the thin oxide layer 221 in the trench 200, then removing the thin oxide layer 221 at the bottom of the trench 200. The method of removing the thin oxide layer 221 at the bottom of the trench 200 can be dry etching;

[0085] S2. Forming a thin conductive layer 220 over the trench 200 and filling the trench 200 with a filling material 230. The thin conductive layer 220 can be a metal compound such as indium, titanium, nickel, tin, etc. or a metal oxide or nitride such as titanium nitride, indium oxide, etc. The thin conductive layer 220 can be formed by CVD or evaporation and has a thickness of about 50A to 500A. The filling material 230 can be an insulating material such as silicon oxide, a polymer, etc. or a conductive material with a higher resistivity than the thin conductive layer 220. After forming the thin conductive layer 220 and the filling material 230, a multi-step etch-back process can be performed to adjust the height of the high-resistive field plate 220 to a desired height.

[0086] S3. Etching back the thin oxide layer 221 as shown in Figure 4B

[0087] S4. Forming a gate oxide layer and a shield gate oxide layer 222 as shown in Figure 4C The shield gate oxide layer 222 and the gate oxide layer can be formed simultaneously by thermal oxidation. The shield gate oxide layer 222 is usually thicker than the gate oxide layer. Before thermal oxidation, the shield gate electrode material 205 can include amorphous silicon or amorphous siliconized polysilicon to increase the oxidation rate of the shield gate electrode material 205 to form a thicker shield gate oxide layer 222. In one embodiment, the shield gate electrode material 205 is polysilicon. After filling the shield gate electrode material 205, the polysilicon is ion implanted to increase the oxidation rate of the shield gate electrode material.

[0088] S5. Forming a gate electrode 206 and then forming a top metal, a contact hole and finally forming a device. The gate electrode 206 can be polysilicon or a metal to further reduce the gate resistance.

[0089] In the above structure, the width of the gate electrode 206 can be limited by the thickness of the thin oxide layer 221 in the trench 200. In fact, the structure of the gate electrode 206 can be varied according to requirements, such as the embodiments shown in Figure 7 and Figure 8

[0090] Embodiment Three:

[0091] Figure 7 Another variation of the present application is shown in

[0092] Embodiment Four: ​​

[0093] As Figure 8 shown in Figure 2B is another variation of the device structure with a single-sided gate electrode structure, where the gate electrode is located on one side of the trench 200. In this structure, the thin oxide layer 221 on the left and right sides of the cell can have different thicknesses depending on the specific process. This structure can be free from the limitation of the contact hole etching process, and can achieve a higher cell density and further reduce the resistance of the offset region. Figure 7 The method for forming the special trench 200 structure described above can include at least two steps of forming the upper wider trench 200 and the lower narrower trench 200 in sequence. For example, the narrower trench 200 is first etched to form a high-resistance field plate structure, and then the upper wider trench 200 is etched to form a gate structure. For another example, the upper wider trench 200 is first etched to form a gate structure, and then the lower narrower trench 200 is etched to form a high-resistance field plate structure.

[0094] A feasible manufacturing method for the high-resistance field plate shield gate trench type field effect transistor device of the third and fourth embodiments is provided, and the steps include:

[0095] S1. Forming a trench 200 on a semiconductor and forming a thin oxide layer 221 in the trench 200, and then removing the thin oxide layer 221 at the bottom of the trench 200.

[0096] S2. Filling a high-resistance field plate material in the trench 200 to form a narrow-trench high-resistance field plate structure,

[0097] S3. Etching a wide trench on the semiconductor, etching back the thin oxide layer 221, and then filling a shield gate electrode material 205.

[0098] S4. Forming a gate oxide layer and a shield gate oxide layer 222.

[0099] S5. Forming a gate electrode 206, and then forming an upper surface metal, a contact hole, and finally forming a device.

[0100] In addition, another feasible manufacturing method for the high-resistance field plate shield gate trench type field effect transistor device of the third and fourth embodiments is provided, and the steps include:

[0101] S1. Forming a wide trench on a semiconductor and forming a gate oxide layer and a gate electrode;

[0102] S2. Etching the middle part of the gate electrode and the semiconductor below it to form a narrow trench, and at this time, part of the gate electrode remains in the wide trench 200;

[0103] S3. Filling a high-resistance field plate material in the trench 200 to form a high-resistance field plate structure.

[0104]

[0105] ​S4. Perform thermal oxidation to form a shielding gate oxide layer on the gate electrode, and then fill it with shielding gate electrode material.

[0106] S5. Form the upper surface metal, contact holes, and finally form the device.

[0107] In the above embodiments, the bottom of the high-resistivity field plate is typically connected to the N+ substrate layer 201, but it may also be connected to the N-type epitaxial layer 202, depending on the range and depth of the electric field coupling of the device to the high-resistivity field plate.

[0108] Example 5:

[0109] Typically, the bottom of a high-resistivity field plate can be connected to a semiconductor region with a higher doping concentration to form an ohmic contact. In some embodiments, low-energy, high-doping-concentration ion implantation can be performed beforehand at the bottom of trench 200 to form an ohmic contact region 301, such as... Figure 9 As shown.

[0110] Example 6:

[0111] Figure 10 The diagram illustrates another variation of the present invention. In this structure, a P-type implantation region 302 is provided at the bottom of the high-resistivity field plate in the N-type epitaxial layer 202. The P-type implantation region may be formed as follows: after the trench 200 is formed and before the high-resistivity field plate material is filled, multi-step vertical ion implantation with different implantation energies is performed. This P-type implantation region can form a depletion region when the device is reverse-biased to increase the reverse-bias breakdown voltage of the device, while reducing the leakage current in the high-resistivity field plate during device switching transients and accelerating the transient response speed of the high-resistivity field plate.

[0112] Example 7:

[0113] Furthermore, to further improve the breakdown voltage of the device while reducing the delay effect of the high-resistivity field plate, a charge storage layer can be added near the high-resistivity field plate. For example... Figure 11 In the illustrated embodiment, a P-type charge storage layer 303 is provided between the thin oxide layer 221 and the trench 200. Under reverse bias, a depletion region can be rapidly formed in the P-type charge storage layer, accelerating the response speed of the field plate. The method for forming the aforementioned P-type charge storage layer may involve: after forming the trench 200, performing ion diffusion or tilted ion implantation.

[0114] Example 8:

[0115] like Figure 11As shown, in this embodiment, a P-type island region 304 is formed in the N-type epitaxial layer 202 under the P-doped body region. The P-type island region can further reduce the input capacitance of the device and improve the switching performance of the device. The P-type island region can be formed by high-energy ion implantation after contact hole etching, with an implantation energy of 200 keV to 1 MkeV.

[0116] The structural features mentioned in the above embodiments of the present application can be combined to form more embodiments of the device structure.

[0117] The present application has the advantages of providing a novel trench field effect transistor device structure with a high-resistance field plate. The high-resistance field plate reduces the electric field intensity at the bottom of the trench, thereby achieving uniform electric field intensity distribution and increasing the breakdown voltage. In the device of the present application, the breakdown voltage is independent of the thickness of the trench oxide layer, so the trench width is narrower, the on-state area of the device is larger, and the on-state resistance is lower. At the same time, the high-resistance field plate provides a current path in the vertical direction of the device, avoiding the impact of high-energy electron trapping. In addition, the high-resistance field plate between the source and the drain in the device of the present application can act as a buffer, which can improve the overshoot current during device switching and reverse recovery.

Claims

1. A high-resistance field plate shielded gate trench field effect transistor device, characterized by, Comprise: Drain metal layer (213) located at the bottom; N+ substrate layer (201) located above the drain metal layer (213); N-type epitaxial layer (202) located above the N+ substrate layer; P-doped body region and N+ doped source region on the top surface of the device; N+ doped source region is connected with the source metal (210) on the top surface of the device; The N-type epitaxial layer (202) is provided with a trench (200), the trench (200) is filled with a shielding gate electrode (205) and a gate electrode (206) located on the left and right sides or one side of the shielding gate electrode (205), the shielding gate electrode (205) is connected with the upper surface metal (211) located at the top of the device, the shielding gate electrode (205) is provided with a high resistance field plate (220) below, the high resistance field plate (220) extends to the N+ substrate layer (201) below, the high resistance field plate (220) and the sidewall of the trench (200) are isolated by a thin oxide layer (221); The high resistance field plate (220) is a thin conductive layer covering the thin oxide layer (221), and the trench (200) formed by the thin conductive layer is filled with a filling material (230), the filling material is an insulating material, or the filling material is a conductive material with a higher resistivity than the thin conductive layer.

2. The high resistance field plate shielded gate trench field effect transistor device of claim 1, wherein, The high resistance field plate (220) is composed of materials with varying resistivity from top to bottom or is composed of multiple layers of materials with different resistivity.

3. The high resistance field plate shielded gate trench field effect transistor device of claim 1, wherein, The high resistance field plate (220) is composed of materials with varying resistivity and is divided into at least two parts, wherein the upper part has a lower resistivity than the lower part, and the boundary between the upper and lower parts is located at 0.1-0.5 um below the adjacent gate electrode (206).

4. The high resistance field plate shielded gate trench field effect transistor device of claim 1, wherein, The high resistance field plate (220) is composed of materials with varying resistivity and is divided into at least two parts, wherein the upper part has a lower resistivity than the lower part, and the boundary between the upper and lower parts is located above the junction of the adjacent N-type epitaxial layer (202) and N+ substrate layer (201).

5. The high resistance field plate shielded gate trench field effect transistor device of claim 1, wherein, The trench (200) is divided into upper and lower parts, wherein the width of the upper trench is greater than that of the lower trench.

6. The high resistance field plate shielded gate trench field effect transistor device of claim 1, wherein, A P-type charge storage layer (303) is provided between the thin oxide layer (221) and the trench (200).

7. The high resistance field plate shielded gate trench field effect transistor device of claim 1, wherein, A P-type island region (304) is formed in the N-type epitaxial layer (202) below the P-doped body region.

8. A method of manufacturing a high-resistance field plate shield gate trench field effect transistor device, characterized by the steps of Comprise: S1, form a trench on a semiconductor, and form a thin oxide layer in the trench, then remove the thin oxide layer at the bottom of the trench; S2, fill the trench with high resistance field plate material, and then fill shielding gate electrode material; S3, etch back the thin oxide layer; S4, form a gate oxide layer and a shielding gate oxide layer; S5, form a gate electrode, then form an upper surface metal, a contact hole, and finally form a device.

9. A method of manufacturing a high-resistance field plate shield gate trench field effect transistor device, characterized by the steps of Comprise: S1, form a trench on a semiconductor, and form a thin oxide layer in the trench, then remove the thin oxide layer at the bottom of the trench; S2, form a thin conductive layer covering the thin oxide layer in the trench, then fill a filling material, which is an insulating material, or a conductive material with a higher resistivity than the thin conductive layer; S3, etch back the thin oxide layer; S4, forming gate oxide layer and shield gate oxide layer; S5, forming gate electrode, then forming upper surface metal, contact hole, and finally forming device.

10. A manufacturing method for manufacturing the high-resistance field plate shield gate trench field effect transistor device according to claim 5.

Images