Radio frequency time slot control apparatus and method

Abstract

The application provides a radio frequency time slot control device and method, which comprises a radio frequency time sequence management unit, the radio frequency time sequence management unit comprising: multiple sets of control registers, each set of control registers comprising: a first configuration unit for triggering a first control signal when downloading a next time slot event to the control registers; a second configuration unit for triggering a second control signal under the action of the first control signal; a second configuration unit for triggering a third control signal under the action of the second control signal; multiple time sequence control cores, each time sequence control core being connected to a set of control registers, and each time sequence control core being switched between an idle mode and a working mode under the action of the third control signal output by the corresponding control registers. Advantageous effects: by adding three signals, the position of instruction acquisition is determined according to the current state of the three signals, invalid instructions NOP are not configured, the software implementation complexity is reduced, the software scheduling flexibility is increased, and the power consumption is reduced.

Description

Technical Field

[0001] This invention relates to the field of communication technology, and in particular to a radio frequency time slot control device and method. Background Technology

[0002] In wireless communication systems, the control of RF (radio frequency) has strict timing requirements. Typically, a dedicated integrated circuit (ASIC) is used in the baseband chip to perform timing control; this ASIC is called the radio frequency timing management unit (TMU). The TMU is located within the baseband processor (BBIC), such as... Figure 1 As shown, the TMU consists of a timing control core (TCC), a time command buffer (TCB), a timing module (03), an RF interface module (04), and a data path control module. Typically, it includes multiple timing control cores, each with its own statically allocated control register. The software allocates independent TCCs and TCBs for each mode (LTE / NR, etc.). The TCB allocated to a particular mode includes two spaces: PING and PONG. When the hardware is operating in PING mode, the software downloads the control command set for the next RF time slot event to PONG, thus not affecting the execution of the command set for the current time slot event. Furthermore, the commands need to support command prefetching; that is, when executing the first command, the TCC fetches the next command in advance, and executes the corresponding command when the corresponding time point arrives, avoiding situations where commands cannot be fetched in time. Simultaneously, the timing control core is the core component of the entire TMU, enabling the corresponding TCC to execute the appropriate command set before the specified time arrives.

[0003] With the development of communication technology, the demand for low latency (such as Ultra-Reliable Low-Latency Communication (URLLC) in NR) is increasing daily, and the timing of RF event control is becoming increasingly critical. RF event control is generally configured according to time slots. Figure 2As shown, a timing diagram of a typical working scenario of the TMU; wherein, a first time software task (CTRL TASK1) of RF is performed on the current time slot slot N, thus generating the instruction of the next time slot event slot N+1; when the configuration of CTRL TASK1 is completed, since it is the first time to start the timing control core TCC, the TCC enable signal (TCC_EN) needs to be pulled high immediately to start the TCC, so that the TCC is in a running state, and after that the TCC enable signal is always on. Then, when the trigger time point of the first valid instruction E1 arrives, the TCC will execute the instruction of the first valid instruction E1, and then execute the subsequent instructions in turn. Similarly, the configuration of the second software task (CTRL TASK2) is performed on the next time slot (slot N+1), thus generating the instruction of the next next time slot slot N+2, at this time the TCC has been started, and the TCC_EN signal does not need to be configured. Since there is no valid event in the next next time slot slot N+2, an invalid instruction NOP needs to be configured for the PING / PONG jump of TCB. Subsequently, each time slot is in turn in the same way until the sleep event is configured by CTRL TASK, so that the TCC is disabled, and the control TCC enters the idle mode. The prior art has the following disadvantages:

[0004] 1) The last instruction of each time slot must add a null instruction NOP as an invalid instruction for the PING / PONG jump instruction of TCB. Since each instruction needs to specify the execution time point, and the invalid instruction must meet two conditions: one is that the tail of CTRL TASK2 must be before the invalid instruction N1 after the software task of the current time slot event is executed; the other is that the invalid instruction N1 must be before all possible events that may occur in slot N+2, otherwise the first event of slot N+2 will not be executed. In short, the invalid instruction must be configured, and the execution time of the configuration has strict requirements, which is limited by the MIPS (physical layer software scheduling timing of each event) of the current time slot and the instruction position of the next time slot, thus greatly increasing the software complexity, which is not conducive to software maintenance.

[0005] 2) Calculating the time point of N1 invalid instruction needs to predict all possible scenarios of the next time slot, and downloading NOP event to TCB needs to consume a lot of MIPS, which further worsens the CTRL TASK time of the current time slot, making the position calculation of N1 more demanding;

[0006] 3) The addition of NOP instruction needs to consider the RF event position of the previous CTRL TASK and the next time slot possible scenario, and it is almost impossible to support more than 2 symbol time advance (TA) in the case of encountering a large TA in uplink transmission.

[0007] 4) Once the physical layer is woken up, since the physical layer software is configured to perform the next time slot RF event in advance by one time slot, even if there is no task in the current time slot, the CTRL TASK needs to configure the NOP event to maintain the possible event configuration of the next time slot, which to some extent increases the power consumption of the baseband chip. SUMMARY

[0008] In order to solve the above technical problems, the present application provides a radio frequency time slot control device and method.

[0009] The technical problems solved by the present application can be implemented by the following technical solutions:

[0010] A radio frequency time slot control device, comprising a radio frequency time sequence management unit, the radio frequency time sequence management unit comprising:

[0011] A plurality of control registers, each of the control registers comprising:

[0012] A first configuration unit configured to trigger a first control signal when downloading a next time slot event to the control register;

[0013] A second configuration unit configured to trigger a second control signal under the action of the first control signal;

[0014] A second configuration unit configured to trigger a third control signal under the action of the second control signal;

[0015] A plurality of time sequence control cores, each of the time sequence control cores being connected to a group of the control registers, and each of the time sequence control cores being switched between an idle mode and an operating mode under the action of the third control signal output by the corresponding control register.

[0016] Preferably, the first configuration unit comprises:

[0017] A first setting module configured to set the first control signal when downloading the next time slot event to the control register, so as to trigger the first control signal;

[0018] A first clear module configured to clear the first control signal when the second control signal is cleared.

[0019] Preferably, the second configuration unit comprises:

[0020] a second setting module, configured to set the second control signal when the first control signal is set and the second control signal is cleared;

[0021] a second clearing module, configured to clear the second control signal when the timing control core starts to execute the instruction set corresponding to the current time slot event.

[0022] Preferably, the third configuration unit comprises:

[0023] a third setting module, configured to set the third control signal when the second control signal is set and the third control signal is cleared, so that the timing control core is switched from the idle mode to the working mode and starts to execute the instruction set corresponding to the current time slot event.

[0024] Preferably, the third configuration unit further comprises:

[0025] a third clearing module, configured to clear the third control signal when the timing control core finishes executing the instruction set corresponding to the current time slot event, so that the timing control core is switched from the working mode to the idle mode.

[0026] The application further provides a radio frequency time slot control method comprising the radio frequency time slot control device as described above, and the method comprises:

[0027] triggering a first control signal when downloading a next time slot event to a control register;

[0028] triggering a second control signal under the action of the first control signal;

[0029] triggering a third control signal under the action of the second control signal;

[0030] each timing control core is switched between the idle mode and the working mode under the action of the third control signal output by the corresponding control register.

[0031] Preferably, the triggering of the first control signal when downloading the next time slot event to the control register comprises:

[0032] setting the first control signal when downloading the next time slot event to the control register, so as to trigger the first control signal;

[0033] clearing the first control signal when the second control signal is cleared.

[0034] Preferably, the triggering of the second control signal under the action of the first control signal comprises:

[0035] setting the second control signal when the first control signal is set and the second control signal is cleared;

[0036] clearing the second control signal when the timing control core starts to execute the instruction set corresponding to the current time slot event.

[0037] Preferably, the third control signal is triggered under the action of the second control signal, and specifically includes:

[0038] setting the third control signal when the second control signal is set and the third control signal is cleared, so that the timing control core is switched from the idle mode to the working mode and starts to execute the instruction set corresponding to the current time slot event.

[0039] Preferably, the third control signal is triggered under the action of the second control signal, and specifically includes:

[0040] clearing the third control signal when the timing control core finishes executing the instruction set corresponding to the current time slot event, so that the timing control core is switched from the working mode to the idle mode.

[0041] The advantages or beneficial effects of the technical scheme of the present application are as follows:

[0042] The present application adds three control signals in the hardware device of the radio frequency timing management unit TMU, so that the position of instruction acquisition can be determined according to the current state of the three control signals, thereby preventing the software from being implemented complicatedly, and effectively preventing the instruction pre-fetch from taking the wrong instruction; valid instructions can be configured at any position in the time slot, so that the RF control does not need to depend on the MIPS of the physical layer software, thereby increasing the flexibility of software scheduling; when there is no valid instruction to be configured, the TMU can enter the idle mode, thereby reducing the power consumption in the physical layer data transmission and reception scenario. BRIEF DESCRIPTION OF DRAWINGS

[0043] Figure 1 The structure block diagram of the radio frequency timing management unit in the prior art;

[0044] Figure 2 The timing schematic diagram of the typical working scenario of the TMU in the prior art;

[0045] Figure 3 The structure block diagram of the radio frequency time slot control device in the preferred embodiment of the present application;

[0046] Figure 4 The structure block diagram of the register in the preferred embodiment of the present application;

[0047] Figure 5 For the preferred embodiment of the present application, the timing diagram for the implementation of the radio frequency time slot control device is shown. DETAILED DESCRIPTION

[0048] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0049] It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict.

[0050] Explanation of terms in the present application:

[0051] NOP: null instruction, i.e. invalid instruction;

[0052] MIPS: the scheduling timing sequence of each event in the physical layer software of the present application;

[0053] RF: refers to a radio frequency chip and a radio frequency front-end device in the present application;

[0054] CTRL TASK: RF configuration software task;

[0055] TMU: time management unit, radio frequency timing management unit;

[0056] TCB: time command buffer, control register;

[0057] TCC: Time control core, timing control core;

[0058] PING / PONG: two instruction storage spaces in the TCB;

[0059] ASIC: application specific integrated circuit;

[0060] NR: New radio, new air interface;

[0061] LTE: Long term evolution, long-term evolution technology;

[0062] TA: Time advance, advance.

[0063] The present application will be further described below in combination with the drawings and specific embodiments, but not as a limitation of the present application.

[0064] Reference is made toFigures 3-4 In the preferred embodiment of the present application, based on the above problems existing in the prior art, a radio frequency time slot control device is provided, which specifically comprises a radio frequency time sequence management unit TMU, and the radio frequency time sequence management unit comprises:

[0065] a plurality of groups of control registers (21, 22…2N), each group of control registers comprising:

[0066] a first configuration unit for triggering a first control signal S1 when downloading a next time slot event to the control registers;

[0067] a second configuration unit for triggering a second control signal S2 under the action of the first control signal S1;

[0068] a second configuration unit for triggering a third control signal S3 under the action of the second control signal S2;

[0069] a plurality of time sequence control cores (11, 12…1N), each time sequence control core being connected to a group of control registers, and each time sequence control core being switched between an idle mode and an operating mode under the action of the third control signal S3 output by the corresponding control registers.

[0070] In the prior art, the PING / PONG jump of the TCB is controlled by adding an invalid instruction at the last instruction of the time slot, but the configuration condition of the invalid instruction is relatively strict, which increases the software complexity, and in the physical layer non-sleeping scenario, the time sequence control core is always in an enabled state, which increases the system power consumption. In the present embodiment, the radio frequency time sequence management unit comprises a plurality of time sequence control cores (11, 12…1N) and a plurality of control registers (21, 22…2N), and the time sequence control cores and the control registers correspond one-to-one; by adding three control signals in each group of control registers, the position of instruction acquisition can be determined according to the current state of the three control signals, so that the instruction PING / PONG jump without configuring the invalid instruction NOP is realized, which prevents the instruction prefetch from taking the wrong instruction and reduces the software implementation complexity; valid instructions can be configured at any position in the time slot, so that the RF control does not need to rely on the MIPS of the physical layer software, thereby increasing the flexibility of software scheduling; when there is no valid instruction to be configured, the TMU can enter the idle mode, thereby reducing the power consumption in the physical layer data transmission and reception service scenario.

[0071] Further, the radio frequency timing management unit comprises: sequentially connected timing processing module, instruction control storage module, timing module 3 and radio frequency interface 4, the timing processing module comprises the plurality of timing control cores (11, 12…1N) described above, the instruction control storage module comprises the plurality of control registers (21, 22…2N) described above, and the radio frequency interface specifically comprises control path and data path, software allocates independent timing control core and control register for each mode (long term evolution technology LTE / new radio NR and the like), and the timing control core and the control register are one-to-one correspondence, each control register includes two instruction storage spaces, one is PING, and the other is PONG.

[0072] It should be noted that the timing module and the radio frequency interface are common technical means in the prior art, and the present application will not be described again, but should be included in the protection scope of the present application.

[0073] Further, three signals are added in each control register, first control signal S1, second control signal S2 and third control signal S3. Wherein, the first control signal S1 is configured by software in CTRL TASK, and the second control signal S2 and the third control signal S3 are configured by TCC hardware.

[0074] Further, the trigger conditions of the three control signals are shown in Table 1 as follows:

[0075]

[0076]

[0077] As a preferred embodiment, wherein the first configuration unit comprises:

[0078] The first setting module is configured to set the first control signal S1 when downloading the next time slot event to the control register, so as to trigger the first control signal S1.

[0079] The first clear module is configured to clear the first control signal S1 when the second control signal S2 is cleared.

[0080] Specifically, in the embodiment, for the first control signal S1, the software is configured, the next time slot event is parsed in CTRL TASK, and the parsed next time slot event is downloaded to the control register, and then the first control signal S1 is set to "1" by the first setting module.

[0081] When the first control signal is set to "1" and the second control signal is cleared, the first control signal S1 is set to "0" by the first clear module.

[0082] As a preferred embodiment, wherein the second configuration unit comprises:

[0083] a second setting module, configured to set the second control signal S2 to 1 when the first control signal S1 is set to 1 and the second control signal S2 is reset to 0.

[0084] a second resetting module, configured to reset the second control signal S2 to 0 when the timing control core starts to execute the instruction set corresponding to the current time slot event.

[0085] Specifically, in the embodiment, the second control signal S2 is 0 by default, and when the first control signal S1 is set to 1, the second control signal S2 is triggered to be set to 1.

[0086] When the timing control core starts to process the instruction set corresponding to the current time slot event in the working mode, the second control signal S2 is set to 0 by the second resetting module.

[0087] As a preferred implementation, the third configuration unit comprises:

[0088] a third setting module, configured to set the third control signal to 1 when the second control signal is set to 1 and the third control signal is reset to 0, so that the timing control core is switched from the idle mode to the working mode and starts to execute the instruction set corresponding to the current time slot event.

[0089] Specifically, in the embodiment, the third control signal S3 is 0 by default, and when the second control signal S2 is set to 1, the third control signal S3 is triggered to be set to 1.

[0090] As a preferred implementation, the third configuration unit further comprises:

[0091] a third resetting module, configured to reset the third control signal to 0 when the timing control core finishes executing the instruction set corresponding to the current time slot event, so that the timing control core is switched from the working mode to the idle mode.

[0092] Specifically, in the embodiment, when the timing control core finishes processing all the valid instructions in the instruction set corresponding to the current time slot event, the third control signal S3 is set to 0 by the third resetting module, and then the timing control core immediately enters the idle mode, so that the timing control core can enter the idle state in the physical layer non-sleep scenario, thereby reducing the power consumption in the physical layer non-sleep scenario.

[0093] Further, the specific working process of the above three control signals is as follows:

[0094] A1, the next time slot event is parsed in the CTRL TASK, and the next time slot event is downloaded into the control register, and then the first control signal S1 (REG) is set to 1;

[0095] A2, the second control signal S2 has a default value of 0, and if the first control signal S1 = 1, the first control signal S1 will pass 1 to the second control signal S2, and the second control signal S2 and the third control signal S3 signal interact;

[0096] After the first control signal S1 passes 1 to the second control signal S2, the first control signal S1 is automatically cleared to 0. At this time, if the second control signal S2 has been set to 1, the first control signal S1 will pass 1 again after the second control signal S2 = 0;

[0097] A3, the third control signal S3 has a default value of 0, and if the second control signal S2 = 1, the third control signal S3 is set to 1, and after the third control signal S3 is set to 1, the timing control core enters the working mode to start executing the instruction set processing;

[0098] A4, after the first event is executed, the second control signal S2 is cleared to 0;

[0099] A5, after the timing control core executes all events or actions, the third control signal S3 is cleared to 0;

[0100] A6, after the third control signal S3 is cleared to 0, it is judged again whether to start the next round of event / action execution, and the judgment method is: detecting whether the second control signal S2 is set to 1, if the second control signal S2 = 1, the next round of event / action execution is started; Otherwise, do not execute and continue to judge until the timing control core is configured to sleep mode.

[0101] Further, in combination with Figure 5 Further explanation:

[0102] In the CTRL TASK1 scenario, since the current timing control core is in a non-run (unstarted) state, the third control signal S3 can be directly set to 1 to start the TCC; wherein the complete signal flow for completing this configuration is s11->s21->s31;

[0103] In the CTRL TASK2 scenario, when the first control signal S1 is pulled high, since the current TCC is in a started state, it waits for the current event to be executed before continuing to start execution; wherein the complete signal flow for completing this configuration is s12->s23->s31->s24->s32

[0104] In the CTRL TASK3 scenario, when the first control signal S1 is pulled high (s13), the second control signal S2 is pulled low by the s32 signal because the second control signal S2 is still in the high state at this time, and then the second control signal S2 is pulled high again by s13, and after the third control signal S3 is 0, the third control signal S3 is pulled high again by s25 to enable the TCC to enter the working mode; wherein the complete signal flow for completing this configuration is s13->s25->s32->s26->s33.

[0105] The above s11, s12, s13 are the time sequences of the first control signal S1 in different software task CTRL TASK scenarios; s21, s22, s23, s24, s25, s26 are the time sequences of the second control signal S2 in different software task CTRL TASK scenarios, wherein s21, s23, s25 are rising edges, and s22, s24, s26 are falling edges; s31, s32, s33 are the time sequences of the third control signal S3 in different software task CTRL TASK scenarios, all of which are falling edges.

[0106] It should be noted that the execution process of the instruction set corresponding to the time slot event in the scenario where the above-mentioned time sequence control core TCC is in the working mode is a common technical means in the prior art, and the present application will not be described again, but it should be included in the protection scope of the present application.

[0107] Further, the above-mentioned instruction set has two types: one is the event type, which works in the absolute timer mode, that is, when the instruction time is consistent with the time of the timing module, the TCC will start the current event; the other is the action type, which works in the relative timer mode, that is, the time in the instruction is the time interval relative to the previous action. Usually, one event is followed by one or more actions.

[0108] The present application also provides a radio frequency time slot control method, comprising the radio frequency time slot control device as described above, and the method comprises:

[0109] A first control signal is triggered when the next time slot event is downloaded to the control register;

[0110] A second control signal is triggered under the action of the first control signal;

[0111] A third control signal is triggered under the action of the second control signal;

[0112] Each time sequence control core switches between the idle mode and the working mode under the action of the third control signal output by the corresponding control register.

[0113] As a preferred implementation, wherein a first control signal is triggered when the next time slot event is downloaded to the control register, specifically comprising:

[0114] The first control signal is set when the next time slot event is downloaded to the control register to trigger the first control signal;

[0115] The first control signal is cleared when the second control signal is cleared.

[0116] As a preferred implementation, wherein a second control signal is triggered under the action of the first control signal, specifically comprising:

[0117] The second control signal is set when the first control signal is set and the second control signal is cleared;

[0118] The second control signal is cleared when the timing control core starts executing the instruction set corresponding to the current time slot event.

[0119] As a preferred implementation, wherein a third control signal is triggered under the action of the second control signal, specifically comprising:

[0120] The third control signal is set when the second control signal is set and the third control signal is cleared, so that the timing control core switches from idle mode to working mode and starts executing the instruction set corresponding to the current time slot event.

[0121] As a preferred implementation, wherein a third control signal is triggered under the action of the second control signal, specifically comprising:

[0122] The third control signal is cleared when the timing control core finishes executing the instruction set corresponding to the current time slot event, so that the timing control core switches from working mode to idle mode.

[0123] The advantages or benefits of the technical scheme of the present application are:

[0124] 1) Each time slot does not need to add NOP instructions with strict timing restrictions to serve as the switching of PING / PONG, two instruction storage spaces in TCB; the physical layer software only needs to analyze the instructions of the next time slot event of the actual required RF, and then configure the first control signal S1 to complete the time slot control of the RF, greatly reducing the software implementation complexity;

[0125] 2) The analysis of the RF time slot event no longer depends on the start and end time of the CTRL TASK, but can be completed within the same time slot, greatly enhancing the flexibility of software scheduling;

[0126] 3) Without the restriction of NOP instructions, a larger uplink transmission advance (TA) can be supported;

[0127] 4) Since NOP instruction is removed, TCC only works at the position where there is valid RF event, and can enter idle mode at other non-working time (here refers to physical layer non-sleep scenario), thereby reducing the power consumption in physical layer non-sleep scenario.

[0128] The above merely describes preferred embodiments of the present application, but does not limit the embodiments and protection scope of the present application. It should be understood by those skilled in the art that any equivalent replacement and obvious change made according to the content of the present application and drawings should be included in the protection scope of the present application.

Claims

1. A radio time slot control apparatus comprising a radio time sequence management unit, characterized by, The radio frequency time sequence management unit comprises: a plurality of sets of control registers, each set of the control registers comprising: a first configuration unit configured to trigger a first control signal when downloading a next time slot event to the control registers; a second configuration unit configured to trigger a second control signal under the action of the first control signal; a third configuration unit configured to trigger a third control signal under the action of the second control signal; a plurality of time sequence control cores, each of the time sequence control cores being connected to a set of the control registers, and each of the time sequence control cores being switched between an idle mode and an operating mode under the action of the third control signal output by the corresponding control registers.

2. The radio frequency time slot control device of claim 1, wherein, The first configuration unit comprises: a first setting module configured to set the first control signal when downloading the next time slot event to the control registers, so as to trigger the first control signal; a first clearing module configured to clear the first control signal when the second control signal is cleared.

3. The radio frequency time slot control device of claim 1, wherein, The second configuration unit comprises: a second setting module configured to set the second control signal when the first control signal is set and the second control signal is cleared; a second clearing module configured to clear the second control signal when the time sequence control core starts to execute an instruction set corresponding to a current time slot event.

4. The radio frequency time slot control device of claim 1, wherein, The third configuration unit comprises: a third setting module configured to set the third control signal when the second control signal is set and the third control signal is cleared, so as to switch the time sequence control core from the idle mode to the operating mode and start to execute the instruction set corresponding to the current time slot event.

5. The radio frequency time slot control device of claim 1, wherein, The third configuration unit further comprises: a third clearing module configured to clear the third control signal when the time sequence control core finishes executing the instruction set corresponding to the current time slot event, so as to switch the time sequence control core from the operating mode to the idle mode.

6. A radio time slot control method, characterized by, The method is applied to the radio frequency time slot control device as claimed in any one of claims 1 to 5, and the method comprises: triggering a first control signal when downloading a next time slot event to control registers; triggering a second control signal under the action of the first control signal; triggering a third control signal under the action of the second control signal; each time sequence control core being switched between an idle mode and an operating mode under the action of the third control signal output by the corresponding control registers.

7. The radio frequency time slot control method of claim 6, wherein, The triggering of the first control signal when downloading the next time slot event to the control registers specifically comprises: setting the first control signal when downloading the next time slot event to the control registers, so as to trigger the first control signal; clearing the first control signal when the second control signal is cleared.

8. The radio frequency time slot control method of claim 6, wherein, The triggering of the second control signal under the action of the first control signal specifically comprises: setting the second control signal when the first control signal is set and the second control signal is cleared; clearing the second control signal when the time sequence control core starts to execute an instruction set corresponding to a current time slot event.

9. The radio frequency time slot control method of claim 6, wherein, The triggering of the third control signal under the action of the second control signal specifically comprises: The third control signal is set when the second control signal is set and the third control signal is cleared, so that the timing control core is switched from the idle mode to the working mode to start executing an instruction set corresponding to a current time slot event.

10. The radio frequency time slot control method of claim 6, wherein, The third control signal is triggered under the action of the second control signal, and specifically includes: The third control signal is cleared when the timing control core finishes executing the instruction set corresponding to the current time slot event, so that the timing control core is switched from the working mode to the idle mode.

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