Dimming interface using a combination of analog and digital dimming

Abstract

The present disclosure relates to a dimming interface using a combination of analog and digital dimming. An LED lighting system includes a switching circuit arrangement that adjustably drives a string of LEDs and is controlled by a reference current and an enable signal. A controller generates the reference current and the enable signal based on a PWM signal such that the switching circuit arrangement: when a duty cycle of the PWM signal is greater than a threshold duty cycle, supplies a first LED current to the string of LEDs that is proportional to the duty cycle, thereby performing analog dimming; and when the duty cycle of the PWM signal is less than the threshold duty cycle, supplies a second LED current to the string of LEDs that has a duty cycle that is proportional to the duty cycle of the PWM signal such that an average LED current delivered to the string of LEDs is proportional to the duty cycle of the PWM signal, thereby performing digital dimming.

Description

Technical Field

[0001] This disclosure relates to the field of dimmable LED lighting systems, and more specifically to a circuit for dimming LED lighting from maximum light intensity to low light intensity by switching from analog dimming control to digital dimming control at a threshold intensity level, the circuit being controlled by a single pulse width modulation (PWM) signal. Background Technology

[0002] Currently, light-emitting diode (LED) arrays are commonly used to manufacture light bulbs, light strips, and other lighting solutions. LED-based lighting has two main advantages compared to other types of lighting, such as fluorescent-based and incandescent-based lighting: lower power consumption and longer lifespan for a given light output.

[0003] Example LED lighting system 1 in Figure 1A The diagram is shown and includes a power factor correction (PFC) circuit 2 that shapes the input AC current to achieve unity power factor and charges the energy storage capacitor C to the input voltage Vin. A regulator 3 accepts the input voltage Vin and drives a series of LEDs 4 connected in series.

[0004] Voltage regulator 3 can be a reverse buck regulator, such as... Figure 1B As shown in the diagram. In this arrangement, LED 4 is shown as diodes D2-Dn connected in series, where the anode of diode D2 is coupled to the input voltage Vin and the cathode of D2 is coupled to the anode of diode D3, and the cathode of D3 is coupled to the anode of diode Dn. The output capacitor Cout is coupled in parallel with LED 4 to reduce high-frequency ripple. Also here, voltage regulator 3 includes diode D1, whose cathode is coupled to the input voltage Vin and whose anode is coupled to the cathode of diode Dn through inductor L1. Note that the "n" in the context of diode Dn indicates that there can be any number of diodes D2-Dn, where n is any integer.

[0005] The drain of the n-channel transistor MN1 is coupled to the anode of D1, its source is coupled to ground through resistor R1, and its gate is controlled by a gate driver. The current sensing circuit receives the voltage across R1.

[0006] During operation, the gate driver periodically turns the n-channel transistor MN1 on and off. An example on-time is shown in... Figure 1C The medium is denoted as Ton_sw and the example medium time period is denoted as Toff_sw, where time Ts represents the total time of each time period. As an example, the switching frequency Fsw = 1 / Ts can be in the range of 50kHz to 300kHz.

[0007] The inductor current Il increases during the on-time Ton_sw and decreases during the off-time Toff_sw, resulting in the current Iled through LED 4 being the average of the inductor current Il over time. It should be understood that... Figure 1C The operating mode shown is the continuous conduction mode because the inductor current Il does not drop to zero during operation.

[0008] LED lighting system 1 may wish to allow dimming of LED 4, and thus allow setting LED 4 to a desired intensity level. The intensity of light produced by an LED is related to the average current flowing through the LED. Generally, the higher the average current flowing through the LED, the higher the intensity of light produced by the LED. Therefore, it is generally desirable to use a current driver to drive the LED to accurately control the average current flowing through the LED. Thus, LED 4 can be dimmed by controlling the average current flowing through LED 4. For example, the intensity of light produced by LED 4 can be reduced by decreasing the average current flowing through LED 4.

[0009] One way to perform this dimming is to modify the operation of regulator 3 so that the amplitude of the current Iled through LED 4 is reduced, thereby achieving dimming in an analog manner. To achieve this, voltage regulator 3 can operate in a discontinuous conduction mode, such as... Figure 1D As shown in the diagram. In discontinuous conduction mode, the inductor current Il is allowed to drop to zero during the falling period Tfw and then remain zero during the zero-holding period Tr, where Tfw and Tr together define the fixed cutoff period Toff_sw. The average inductor current Il, i.e., the LED current Iled, can be modified by adjusting the peak value reached by the inductor current Il, and / or by adjusting the fixed cutoff period Toff_sw. As shown in the diagram, Figure 1E This allows the LED current Iled to be set to a desired level, thereby achieving the desired intensity level through analog dimming control.

[0010] Another way to perform dimming is through digital dimming control. For digital dimming control, the LED current Iled is allowed to drop to zero, and the duty cycle of the LED current Iled is adjusted accordingly to change the average LED current Iled_avg, thereby achieving the desired intensity level. Digital dimming control is as follows: Figure 1F As shown in the figure, the average LED current Iled_avg is defined by the ratio of the LED current Iled's on-time Ton_pwm to its off-time Toff_pwm, where Tpwm indicates the total time of each PWM period. For example, the PWM frequency Fpwm = 1 / Tpwm can be in the range of 500Hz to 5kHz.

[0011] Analog and digital dimming controls each have their drawbacks. Analog dimming is inefficient in terms of lumens per watt and the color of the light produced may shift at lower intensity levels. Furthermore, analog dimming typically cannot dim to very low intensity levels (e.g., below 10%). Digital dimming can produce flicker (both perceptible and imperceptible), which can have physiological effects on users, such as causing headaches. Digital dimming can also generate electromagnetic interference and may produce undesirable bending effects when used to illuminate scenes captured in video.

[0012] Analog and digital dimming controls each have their advantages. Analog dimming controls do not produce flickering or bending effects. Digital dimming controls do not affect efficiency, do not produce color shift, may be easier to implement than analog dimming controls, and allow dimming to very low intensity levels (e.g., 0.1%).

[0013] Therefore, it is necessary to further develop LED dimming to produce dimming circuits that combine the advantages of analog and digital dimming while avoiding the disadvantages of both. Summary of the Invention

[0014] This document discloses an LED lighting system, comprising: a switching circuit configured to adjustably drive an LED string, the switching circuit being controlled by a reference current and an enable signal; and a controller. The controller is configured to generate the reference current and the enable signal based on a PWM signal, such that, under the control of the reference current and the enable signal, the switching circuit supplies a first LED current proportional to the duty cycle to the LED string when the duty cycle of the PWM signal is greater than a threshold duty cycle; and supplies a second LED current to the LED string when the duty cycle of the PWM signal is less than the threshold duty cycle, the second LED current having a duty cycle proportional to the duty cycle of the PWM signal, such that when the duty cycle of the PWM signal is less than the threshold duty cycle, the amplitude of the average LED current delivered to the LED string is proportional to the duty cycle of the PWM signal.

[0015] A resistor can be coupled between the controller's input terminals and ground, and the controller is configured to determine the threshold duty cycle based on the resistor's resistance.

[0016] The controller may include: an analog dimming circuit configured to generate an analog dimming voltage based on the resistance of a resistor and a PWM signal; a reference current generation circuit configured to generate a reference current based on the analog dimming voltage; and an enable voltage generation circuit configured to generate an enable signal based on the PWM signal, a first internal voltage, and a second internal voltage.

[0017] The first comparator circuit can be configured to generate an intermediate PWM signal with the same frequency and duty cycle as the PWM signal, wherein the analog dimming circuit generates an analog dimming voltage based on the resistance of the resistor and the intermediate PWM signal.

[0018] The enable voltage generation circuit may include: a monostable circuit configured to generate a switch control voltage from an intermediate PWM signal; a comparator having an inverting terminal and a non-inverting terminal; an internal reference capacitor coupled between the inverting terminal of the comparator and ground, generating a first internal voltage across the internal reference capacitor; an internal reference current source configured to supply an internal reference current to the inverting terminal of the comparator; a fourth switch configured to selectively couple the inverting terminal of the comparator to ground when the switch control voltage is asserted; a first internal capacitor coupled between the non-inverting terminal of the comparator and ground, generating a second internal voltage across the first internal capacitor; a second internal capacitor coupled between an internal node and ground; an internal current source proportional to the analog dimming voltage configured to supply internal current to the internal node; a third switch configured to selectively couple the non-inverting terminal of the comparator to the internal node when the switch control voltage is asserted; and a second switch configured to selectively couple the internal node to ground when a delayed version of the switch control voltage is asserted.

[0019] The analog dimming circuit may include: a threshold current source coupled between an input terminal of the controller and a first switch; wherein the first switch is coupled between the threshold current source and ground, and the first switch closes in response to an assertion of a PWM signal and opens in response to a cancellation assertion of a PWM signal.

[0020] The reference current generation circuit may include: a first current mirror having an input coupled to a first input circuit and an output coupled to supply a first current; a second current mirror having an input coupled to a second input circuit and an output coupled to supply a base reference current; and a current adder node configured to add the first current to the base reference current to generate a reference current.

[0021] The first input circuit may include: a first NPN transistor having an emitter coupled to a threshold voltage source via a first resistor, a collector coupled to an input of a first current mirror, and a base; and an operational amplifier having a non-inverting terminal coupled to receive an analog dimming voltage, an inverting terminal coupled to the emitter of the first NPN transistor, and an output coupled to the base of the first NPN transistor.

[0022] The second input circuit may include: a second NPN transistor having an emitter coupled to ground via a second resistor, a collector coupled to the input of a second current mirror, and a base; and an operational amplifier having a non-inverting terminal coupled to receive a threshold voltage, a non-inverting terminal coupled to the emitter of the second NPN transistor, and an output coupled to the base of the second NPN transistor.

[0023] The switching circuit may include: a switching regulator that is alternately coupled to an LED string between an input voltage and ground based on a gate drive signal, wherein an output capacitor is coupled in parallel with the LED string between the input voltage and ground, the switching regulator generating a sense voltage indicating the current flowing through the LED string, the current flowing through the LED string being a first LED current or a second LED current; and a gate drive circuit configured to generate a gate drive signal.

[0024] The gate drive circuit may include: a logic circuit configured to pass a modulator signal when an enable signal is asserted, thereby generating a first signal; a comparator circuit configured to compare a reference voltage with a sensed voltage and generate a second signal having a logic level depending on whether the sensed voltage is greater than the sensed voltage, wherein the reference voltage is generated from a reference current; a flip-flop that receives the first and second signals as inputs and generates a gate pre-drive signal as an output; and a driver configured to generate a gate drive signal from the gate pre-drive signal.

[0025] The logic circuit may include an AND gate. The comparator circuit may include a comparator having a non-inverting input coupled to receive a sensed voltage and an inverting terminal coupled to receive a reference voltage. The flip-flop may be an SR flip-flop having an S input that receives a first signal from the AND gate and an R input that receives a second signal from the comparator.

[0026] The gate drive circuit can be configured to assert the gate drive signal when the received modulator signal is at logic high and the enable signal is asserted; and to deassert the gate drive signal when the sensed voltage exceeds a reference voltage, the reference voltage being generated based on a reference current.

[0027] This document also discloses a method for operating an LED lighting system, the method comprising: a) receiving a PWM signal; b) when the duty cycle of the PWM signal is greater than a threshold duty cycle, supplying a first LED current to a string of LEDs proportional to the duty cycle; and c) when the duty cycle of the PWM signal is less than the threshold duty cycle, supplying a second LED current to the string of LEDs, the second LED current having a duty cycle proportional to the duty cycle of the PWM signal, such that when the duty cycle of the PWM signal is less than the threshold duty cycle, the amplitude of the average LED current delivered to the string of LEDs is proportional to the duty cycle of the PWM signal.

[0028] The threshold duty cycle can be determined based on the resistance of the resistor.

[0029] The method may also include using a switching circuit device controlled by a reference current and an enable signal to perform b) and c).

[0030] The method may include determining a threshold duty cycle based on the resistance of a resistor. The method may also include: generating an analog dimming voltage based on the resistance of the resistor and a PWM signal; generating a reference current based on the analog dimming voltage; and generating an enable signal based on the PWM signal, a first internal voltage, and a second internal voltage.

[0031] The method may further include: asserting a gate drive signal when the received modulator signal is at logic high and an enable signal is asserted; canceling the assertion of the gate drive signal when the sensed voltage exceeds a reference voltage, the reference voltage being generated based on a reference current; switching an LED string between the input voltage and ground based on the gate drive signal; and generating a sensed voltage to indicate the current flowing through the LED string, the current flowing through the LED string being a first LED current or a second LED current. Attached Figure Description

[0032] Figure 1A This is a block diagram of an existing LED lighting system.

[0033] Figure 1B yes Figure 1A A schematic diagram of the regulator for an LED lighting system.

[0034] Figure 1C This illustrates the operation in continuous conduction mode. Figure 1B The curve of the inductor current of the regulator.

[0035] Figure 1D This illustrates the operation in discontinuous conduction mode. Figure 1B The curve of the inductor current of the regulator.

[0036] Figure 1E This indicates that when analog dimming is being performed... Figure 1B The curve of the LED current of the regulator.

[0037] Figure 1F This indicates when digital dimming is being performed. Figure 1B The curve of the LED current of the regulator.

[0038] Figure 2 This is a block diagram of the LED lighting system disclosed in this article.

[0039] Figure 3 yes Figure 2A schematic block diagram of the switching circuit device for an LED lighting system.

[0040] Figure 4 This demonstrates the switching between analog and digital dimming modes. Figure 2 The graph shows the LED current of the LED lighting system.

[0041] Figure 5 yes Figure 2 A schematic diagram of the dimming interface.

[0042] Figure 6 yes Figure 5 A schematic diagram of the reference current generation circuit.

[0043] Figure 7 It is a graph showing the variation of the enable signal duty cycle within the duty cycle range of the PWM signal.

[0044] Figure 8 It is a graph showing the variation of the reference current within the duty cycle range of the PWM signal.

[0045] Figure 9 Includes an illustration of performing analog dimming. Figure 2 A graph showing the operating conditions of an LED lighting system.

[0046] Figure 10 Includes illustrations of digital dimming during operation. Figure 2 A graph showing the operating conditions of an LED lighting system.

[0047] Figures 11A-11B Includes an illustration of performing analog dimming. Figure 2 A graph showing the operating conditions of an LED lighting system.

[0048] Figures 11C-11E Includes illustrations of digital dimming during operation. Figure 2 A graph showing the operating conditions of an LED lighting system.

[0049] Figure 12A Includes an illustration of performing analog dimming. Figure 2 A graph showing the operating conditions of an LED lighting system.

[0050] Figure 12B Includes illustrations of digital dimming during operation. Figure 2 A graph showing the operating conditions of an LED lighting system. Detailed Implementation

[0051] The following disclosure enables those skilled in the art to make and use the subject matter disclosed herein. The general principles described herein can be applied to embodiments and applications other than those detailed above, without departing from the spirit and scope of this disclosure. This disclosure is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed or suggested herein. Note that in the following description, unless otherwise stated, any described resistor or resistor is a discrete device and not merely an electrical lead between two points. Therefore, any described resistor or resistor coupled between two points has a greater resistance than a lead between those two points, and such a resistor or resistor should not be interpreted as a lead.

[0052] Now for reference Figure 2 and Figure 3 The LED lighting system 10 is described herein. The LED lighting system 10 includes a power factor correction (PFC) circuit 2 that shapes the input AC current and charges the energy storage capacitor C to the input voltage Vin. A switching DC-DC converter 200 receives the input voltage Vin and, when enabled by an enable signal EN from a dimming interface 100, switches under the control of a reference current Iref to generate a current Iled through the series-connected LEDs D2-Dn, causing these LEDs to emit light at a desired intensity level. The dimming interface 100 receives a pulse width modulation (PWM) signal as input and has an input terminal coupled to which a parallel RC circuit formed by a capacitor Cf and a resistor Rth is connected. The capacitor Cf and resistor Rth can be external to the LED lighting system 10 and are connected by the equipment manufacturer incorporating the LED lighting system into the lighting product.

[0053] like Figure 3 As shown in more detail, the switching DC-DC converter 200 has an inverting buck regulator 202, which includes a diode D1, the cathode of which is coupled to the input voltage Vin, and the anode of which is coupled to the cathode of diode Dn through an inductor L1. An output capacitor Cout is coupled in parallel with LEDs D2-Dn. The drain of an n-channel transistor MN1 is coupled to the anode of D1, its source is coupled to ground through a resistor R1, and its gate is controlled by a gate drive signal GDrv.

[0054] The energy storage capacitor C outside the buck regulator 202 is coupled between the anode of diode D2 and ground.

[0055] Gate drive circuit 201 includes a driver 209 that generates a gate drive signal GDrv, which is supplied to the gate of n-channel transistor MN1. Driver 209 receives an input from SR flip-flop 208. Comparator 207 supplies an input to the reset input of SR flip-flop 208. Comparator 207 has a non-inverting terminal coupled to the source of n-channel transistor MN1 to receive a sensed voltage formed across R1 by a sensed current Isense (which is a portion of the current supplied by the source of n-channel transistor MN1), and an inverting terminal receiving a reference voltage Vref formed across a resistor R2 coupled between the inverting terminal and ground, the reference current Iref being supplied to a tap between resistor R2 and the inverting terminal. AND gate 206 supplies an input to the set input of SR flip-flop 208. AND gate receives inputs from a fixed-off-time modulator 205 and an enable signal EN. Fixed-off-time modulator 205 asserts the S-input of flip-flop 208 after a fixed time.

[0056] In the operation where the enable signal EN is asserted as logic high, the output of AND gate 206 follows the output signal from modulator 205, and therefore, when the output signal from modulator 205 becomes logic high, the output of SR flip-flop 208 is set, and when the sensed voltage Vsense exceeds the reference voltage Vref, the output of comparator 207 is asserted as logic high, thereby resetting the output of SR flip-flop 208 when Vsense exceeds Vref. As a result of this operation, when the enable signal EN is logic high, the start of each rising edge of the gate drive signal GDrv occurs synchronously with the rising edge of the output signal from modulator 205, wherein each falling edge of the gate drive signal GDrv occurs when Vsense exceeds Vref. (Return to Reference) Figure 1D Therefore, the total time Ts for each period is set by the sum of the durations of the output signals of modulator 205 (Toff_sw = fixed), where the duration of the on-time Ton_sw is set as a function of Vref (and thus Iref), resulting in a variable switching frequency (Ts = Ton_sw + Toff_sw). Toff_sw is set by modulator 205. Note that in some instances, the modulator may generate a fixed cutoff time based on operating conditions to maintain...

[0057] Within each cutoff period Toff_sw, the duration of each sub-period Tfw, from the end of Ton_sw to the time when the inductor current Il drops to zero, is a function of the magnitude of the inductor current Il reached during the previous on period Ton_sw.

[0058] It's important to understand that the duration of each sub-period Tr is a function of the reference current Iref. This means that the switching DC-DC converter 200 operates in continuous conduction mode (e.g., ...). Figure 1C The inductor current shown is either in discontinuous conduction mode (e.g., the inductor current shown) or in non-continuous conduction mode (e.g., the inductor current shown) Figure 1D The inductor current shown depends on the reference current Iref.

[0059] Therefore, it can be said that the switching DC-DC converter 200 operates in peak current mode control (power switch MN1 is turned off once the peak value of the inductor current reaches the desired value) and in fixed off-time operation. Thus, once power switch MN1 is turned on, the inductor current increases linearly until it reaches the internal current reference (e.g., until Ilpk = Vref / R1), and then power switch MN1 remains off for a fixed off-time (Toff_sw). During Toff_sw, the inductor current decreases linearly (the dIL / dt slope is determined by the (Vin - Vled) / L1 ratio), and if the inductor current reaches 0 before the end of Toff_sw, the converter operates in DCM mode (Tr > 0).

[0060] Since the LED current Iled is a function of the inductor current Il, and since the inductor current Il depends on the reference current Iref, the LED current Iled depends on the reference current Iref. The higher the amplitude of the reference current Iref, the higher the amplitude of the LED current Iled, and the lower the amplitude of the reference current Iref, the lower the amplitude of the LED current Iled.

[0061] If the inductor current is greater than 0 during Toff_sw, the DC-DC converter 202 operates in CCM mode, while if the inductor current reaches 0, it operates in DCM mode. This depends on the programmed peak inductor value (Vref / R1) and the converter parameters (Vin, Vled, L1). Typically, Toff_sw is programmed to operate in CCM mode at maximum output current (Iled = 100%), so when the LED current is reduced by dimming, the converter operates in DCM mode (e.g., for Iled < 30%). Thus, analog dimming is performed when the enable signal is asserted to be logic high.

[0062] When the enable signal EN is deasserted to logic low, the output of the SR flip-flop 208 will remain deasserted to logic low regardless of the state of the output signal of the modulator 205. Therefore, the LED current Iled can be reduced to zero by deasserting the enable signal EN for a sufficiently long period. This means that by properly modulating the enable signal EN and performing duty cycle processing on the LED current Iled, digital dimming control of LEDs D2-Dn can be achieved.

[0063] Therefore, by controlling the reference current Iref and the enable signal EN, the operation of the switching DC-DC converter 200 can be switched between analog dimming of LED D2-Dn and digital dimming (pulse width modulation dimming) of LED D2-Dn. The advantages of analog dimming described above make it suitable for changing between higher intensities (e.g., between 33% and 100% of the maximum possible intensity), while the advantages of digital dimming, as described above, make it suitable for switching between lower intensities (e.g., between 0.1% and 33%). Therefore, the dimming interface 100 that generates the reference current Iref and the enable signal EN, and the switching DC-DC converter 200, are particularly useful.

[0064] The dimming interface 100 that generates a reference current Iref and an enable signal EN, and its operation, are now described such that the DC-DC switching converter 200 performs analog dimming control on LEDs D2-Dn, decreasing their intensity from 100% to a given threshold intensity level (e.g., 33%), but performs digital dimming control on LEDs D2-Dn, decreasing their intensity from the threshold intensity level (e.g., 32%) to a minimum intensity level (e.g., 0.1%). The effect of this switching in the dimming control method can be seen in… Figure 4 The curves showing the LED current Iled and the average LED current Iled_avg are shown in the figure.

[0065] Now refer to Figure 5 The controller is described. The dimming interface 100 includes an analog dimming setting circuit 110, which includes a capacitor Cf and a resistor Rth coupled in parallel between the input node Na1 and ground, and a current source 111 switched between the input node Na1 and ground via a switch SW1 in response to an intermediate PWM signal PWM_Int. During operation, an analog dimming voltage Vadim is formed at node Na1.

[0066] The dimming interface 100 includes a reference current generation circuit 130 with a voltage subtractor 131, which subtracts a threshold voltage Vth from the analog dimming voltage Vadim and provides the difference to a voltage adder 132 via a current limiter. The voltage adder 132 adds the threshold voltage Vth to the voltage output from the voltage subtractor 131 to generate a voltage Va, which is used as the control voltage for an adjustable current source 133. The adjustable current source 133 generates a reference current Iref based on the voltage Va. Note that the purpose of subtracting Vth from Vadim and then adding Vth back to Vadim after passing through the current limiter is to clamp the Iref current.

[0067] The dimming interface 100 also includes a comparator 109, which has an inverting terminal for receiving a 1.5V voltage and a non-inverting terminal for receiving a PWM signal, and generates an intermediate PWM signal PWM_Int.

[0068] The enable voltage generation circuit 120 includes a monostable circuit 121 that receives an intermediate PWM signal PWM_Int and generates a voltage Vm from it to node Nm1. A delay circuit 122 receives the voltage Vm and controls switch SW2 accordingly. Switch SW2 is coupled between node Nm2 and ground. Capacitor Ctr is coupled between node Nm2 and ground. Current source 123 supplies current Id to node Nm2. Switch SW3 is coupled between node Nm2 and the non-inverting terminal of comparator 125, and is controlled by the voltage Vm. Capacitor Ch is coupled between the non-inverting terminal of comparator 125 and ground.

[0069] Switch SW4 is coupled between the inverting terminal of comparator 125 and ground, and is controlled by voltage Vm. Current source 124 supplies current Ir to the inverting terminal of comparator 125. Capacitor Cr is coupled between the inverting terminal of comparator 125 and ground. An enable signal EN is generated at the output of comparator 125.

[0070] Now for reference Figure 6 More detailed assertion details are described for the reference current generation circuit 130. The reference current generation circuit 130 includes a first NPN transistor Qn1, whose emitter is coupled to a threshold voltage Vth (shown as voltage source 302) via a resistor Ra1, its collector is coupled to a first current mirror 303, and its base is coupled to receive the output of operational amplifier 301. The non-inverting terminal of operational amplifier 301 receives an analog dimming voltage Vadim, its inverting terminal is coupled to the emitter of NPN transistor Qn1 at node Nn1, and its output is coupled to the base of NPN transistor Qn1.

[0071] The first current mirror 303 has an input coupled to the collector of an NPN transistor Qn1 and an output coupled to node Nn3. The first current mirror 303 is formed by: a first PNP transistor Qp1, whose emitter is coupled to the power supply voltage Vcc, whose collector is coupled to the collector of the NPN transistor Qn1, and whose base is coupled to its collector; and a second PNP transistor Qp2, whose emitter is coupled to the power supply voltage Vcc, whose collector is coupled to node Nn3, and whose base is coupled to the base of the PNP transistor Qp1. Current I1 is supplied to node Nn3 from the output of the current mirror 303.

[0072] The reference current generation circuit 130 also includes a second NPN transistor Qn2, whose emitter is coupled to ground via resistor Ra2, whose collector is coupled to the second current mirror 304, and whose base is coupled to receive the output of operational amplifier 305. The non-inverting terminal of amplifier 305 receives the threshold voltage Vth, its inverting terminal is coupled to the emitter of NPN transistor Qn2 at node Nn2, and its output is coupled to the base of NPN transistor Qn2.

[0073] The second current mirror 304 has an input coupled to the collector of NPN transistor Qn2 and an output coupled to node Nn3. The second current mirror 304 is formed by: a third PNP transistor Qp3, whose emitter is coupled to the power supply voltage Vcc, whose collector is coupled to the collector of NPN transistor Qn2, and whose base is coupled to its collector; and a fourth PNP transistor Qp4, whose emitter is coupled to the power supply voltage Vcc, whose collector is coupled to node Nn3, and whose base is coupled to the base of PNP transistor Qp3. The current Iref0 is supplied to node Nn3 from the output of the current mirror 304. The reference current Iref supplied from node Nn3 is therefore the sum of currents I1 and Iref0.

[0074] The operation of the dimming interface 100 in generating a reference current Iref and an enable signal EN will now be described. Note that the inputs to the dimming interface 100 are a parallel capacitor Cf and a resistor Rth, along with a PWM signal, and the outputs Iref and EN are therefore based on the capacitance of Cf, the resistance of Rth, and the PWM signal. Since the capacitor Cf and resistor Rth are connected before operation and thus remain constant during operation, the user-variable input to the dimming interface 100 is the PWM signal. Therefore, under the control of the PWM signal, the dimming interface 100 switches from generating a reference current Iref and an enable signal EN to achieve the desired dimming level from 100% down to a threshold intensity level, to generating a reference current Iref and an enable signal EN to achieve the desired dimming level from the threshold intensity level down to a minimum intensity level.

[0075] Comparator 109 compares the PWM signal with a 1.5V signal, and therefore, when the PWM signal exceeds 1.5V, the resulting intermediate PWM signal PWM_Int is asserted. PWM_Int is asserted within the same duty cycle as the PWM signal (because the voltage amplitude of the PWM signal is set to exceed 1.5V when asserted). During each PWM period Tpwm, the sub-period in which PWM_Int is asserted is the on-time Ton, and the sub-period in which PWM_Int is deasserted is the off-time Toff. During the on-time Ton, switch SW1 is closed, thereby charging the filter capacitor Cf, while during the off-time Toff, switch SW1 is open, thereby discharging the filter capacitor Cf through resistor Rth during these off-time periods. Therefore, assuming Cf × Rth >> Tpwm, the charge balance on Cf produces the equation... Given For analog dimming voltage, the equation can be solved as Vadim = Rth × Ith × Dpwm. Therefore, the analog dimming voltage Vadim is proportional to the duty cycle Dpwm of the PWM signal and does not depend on the analog level (voltage amplitude) of the PWM signal, because the duty cycle Dpwm is set on the transitions between the digital logic levels of the PWM signal.

[0076] In the reference current generation circuit 130, the current I1 can be calculated as

[0077]

[0078] And the current Iref0 can be calculated as:

[0079] Assume Ra1 = Ra2, and therefore

[0080] The reference current Iref can be calculated as Iref = I1 + Iref0. Therefore, Iref can be expressed as:

[0081]

[0082] Given Vadim = Rth × Ith × Dpwm, this means the reference current Iref can be written as:

[0083]

[0084] Taking this into account, the condition Iref = Iref0 results in the duty cycle threshold Dpwm_th being:

[0085]

[0086] Thus, it is observed that the threshold duty cycle Dpwm_th depends on the resistor Rth and the internal fixed parameters Vth and Ith.

[0087] Considering that the capacitor Ctr is charged with a constant current Id from the current source 123 during the PWM period Tpwm:

[0088] Id = gmd × Vadim, thus the voltage across the capacitor Ctr can be written as:

[0089]

[0090] Given that Vadim = Rth × Ith × Dpwm, thus Vctr can be rewritten as:

[0091]

[0092] Assuming Ch << Ctr, at the end of Tpwm, the charge on Ctr is transferred to the capacitor Ch, thus the voltage on Ch will be:

[0093]

[0094] The capacitor Cr is charged with a constant Ir during Tpwm, and the amplitude of the triangular wave of the voltage on Cr resulting therefrom is:

[0095]

[0096] Considering that when the voltage Vch across the capacitor Ch and the voltage Vr across the capacitor Cr are equal, the comparator 125 will assert the enable signal EN, the resulting duty cycle of the enable signal is thus:

[0097]

[0098] Given and the duty cycle Deq of the enable signal EN can be written as:

[0099]

[0100] Selecting the gain such that Deq ≤ 1 when Vadim ≤ Vth results in:

[0101]

[0102] Given Vth = Rth × Ith × Dpwm, this means that the above equation for the duty cycle Deq of the enable signal EN can be rewritten as:

[0103]

[0104] Therefore, the duty cycle Deq of the enable signal EN is:

[0105]

[0106] This relationship is shown to Figure 7 In the middle, and as a function of the duty cycle Dpwm of the PWM signal, the reference current Iref is as follows: Figure 8 As shown in the image.

[0107] Considering that the current Iled_avg is proportional to the reference current Iref and the duty cycle Deq, it is expressed as:

[0108]

[0109] and:

[0110] and

[0111]

[0112] The current Iled_avg can be written as:

[0113]

[0114] Therefore, it should be noted that during both analog and digital dimming control, the current Iled_avg is proportional to the PWM duty cycle Dpwm. Thus, it should be understood that the dimming interface 100 has switched from generating a reference current Iref and an enable signal EN to achieve the desired dimming level decreasing from 100% to a threshold intensity level, to generating a reference current Iref and an enable signal EN to achieve the desired dimming level decreasing from the threshold intensity level to a minimum intensity level.

[0115] Note that the duty cycle threshold Dpwm_th is set by the resistance value of resistor Rth, and the desired LED current Iled_avg is set by the current sensing resistor Rs. Mathematically, this is shown as:

[0116] therefore

[0117] The graph used to illustrate the operational scenario is in Figures 9-10 The image shows... In Figure 9 In the current context, analog dimming control is being executed. Here, Vadim is greater than Vth, which ultimately causes Iref to be greater than Iref0, and the enable signal remains logic high during operation (e.g., with a 100% duty cycle). Figure 10In the current context, digital dimming control is being executed. Here, Vadim is less than Vth, which ultimately causes Iref to equal Iref0, and the enable signal EN is subjected to duty cycle processing during operation.

[0118] Now for reference Figures 11A-11E Further examples of operating conditions under different PWM signal duty cycles are discussed. In these examples, the PWM duty cycle threshold Dpwm_th is 10%.

[0119] like Figure 11A The example shown is a PWM signal with a duty cycle Dpwm of 100%. As a result, Vadim is greater than Vth (which can be considered 0.4V here), Iref is greater than I0 (which can be considered 0.15mA here), and the enable signal EN remains logic high during operation. The LED current Iled becomes 1.041A. Figure 11B The example shown is a PWM signal with a duty cycle Dpwm of 15%. As a result, Vadim remains greater than Vth, and Iref remains greater than Iref0, so the enable signal EN remains logic high during operation. The LED current drops to 140mA. Thus, Figures 11A-11B The series demonstrates analog dimming control.

[0120] like Figure 11C The example shown is a PWM signal with a duty cycle Dpwm of 8%. As a result, Vadim drops below Vth, Iref becomes equal to Iref0, and the enable signal EN is processed with a duty cycle of 81% Deq. Therefore, it is observed that the LED current Iled is processed with the enable signal EN, and here it has a current of 72mA (when on). This indicates that in Figure 11C Digital dimming control was implemented.

[0121] like Figure 11D The example shown is a PWM signal with a duty cycle Dpwm of 5%. As a result, Vadim is lower than Vth, Iref equals Iref0, and the enable signal EN is processed with a duty cycle of 51% Deq. It is observed that the LED current Iled is therefore processed with the enable signal EN, and here has a current of 0.046A (when on). Thus, in Figure 11D Digital dimming control is performed in the middle, and Figures 11C-11D The series of illustrations demonstrates digital dimming control.

[0122] like Figure 11E The example shown has a PWM signal duty cycle Dpwm of 5%, but the PWM signal frequency is increased tenfold. It is observed that the LED current Iled here is therefore higher than... Figure 11D The example uses a higher frequency to perform duty cycle processing with the enable signal EN, while still having a current of 0.046A (when on).

[0123] Now for reference Figure 12A-12B Additional examples of operating conditions are discussed under different PWM signal duty cycles. In these examples, the PWM duty cycle is 15%, while the threshold PWM duty cycle Dpwm_th varies.

[0124] exist Figure 12A In the example, the duty cycle threshold Dpwm_th is 10%. As a result, Vadim is greater than Vth, Iref is greater than I0, and the enable signal EN remains logic high during operation. The LED current Iled becomes 140mA and is constant. Therefore, Figure 12A The example utilizes analog dimming control.

[0125] like Figure 12B The example shown is a PWM signal with a duty cycle threshold Dpwm_th of 20%. As a result, Vadim is lower than Vth, Iref equals Iref0, and the enable signal EN is processed with a duty cycle of 74% Deq. Therefore, it is observed that the LED current Iled is processed with the enable signal EN, and here it has a current of 134mA (when on). Thus, in Figure 12B Digital dimming control is implemented in the middle.

[0126] In summary, the LED lighting system 10 described above allows programming of the dimming interface reference current Iref and the enable signal EN, which regulates the output current Iled_avg applied to LEDs D2-Dn, which is proportional to the duty cycle of the PWM signal Dpwm. As described, the LED lighting system 10 automatically switches between analog or digital dimming control depending on the user-programmable PWM threshold Dpwm_th to optimize system performance.

[0127] Finally, it is obvious that modifications and variations may be made to the content described and illustrated herein without departing from the scope of this disclosure, as defined in the appended claims.

[0128] Although this disclosure has been described with respect to a limited number of embodiments, those skilled in the art who benefit from this disclosure will understand that other embodiments can be conceived without departing from the scope of this disclosure. Therefore, the scope of this disclosure should be limited only by the appended claims.

Claims

1. An LED lighting system, comprising: A switching circuit device is configured to adjustably drive an LED string, the switching circuit device being controlled by a reference current and an enable signal; as well as The controller is configured to generate the reference current and the enable signal based on the PWM signal, such that the switching circuit device, under the control of the reference current and the enable signal, performs the following: When the duty cycle of the PWM signal is greater than the threshold duty cycle, a first LED current proportional to the duty cycle of the PWM signal is supplied to the LED string; When the duty cycle of the PWM signal is less than the threshold duty cycle, a second LED current is supplied to the LED string. The duty cycle of the second LED current is proportional to the duty cycle of the PWM signal, such that when the duty cycle of the PWM signal is less than the threshold duty cycle, the amplitude of the average LED current delivered to the LED string is proportional to the duty cycle of the PWM signal. A resistor, coupled between the input terminal of the controller and ground, is configured to determine the threshold duty cycle based on the resistance of the resistor. The controller includes: An analog dimming circuit is configured to generate an analog dimming voltage based on the resistance of the resistor and the PWM signal; A reference current generation circuit is configured to generate the reference current based on the analog dimming voltage; and The enable voltage generation circuit is configured to generate the enable signal based on the PWM signal, a first internal voltage, and a second internal voltage.

2. The LED lighting system of claim 1 further includes a first comparator circuit configured to generate an intermediate PWM signal having the same frequency and the same duty cycle as the PWM signal, wherein the analog dimming circuit generates the analog dimming voltage based on the resistance of the resistor and the intermediate PWM signal.

3. The LED lighting system according to claim 2, wherein the enabling voltage generation circuit comprises: A monostable circuit is configured to generate a switching control voltage from the intermediate PWM signal; A comparator having an inverting terminal and a non-inverting terminal; An internal reference capacitor is coupled between the inverting terminal of the comparator and ground, and the first internal voltage is generated across the internal reference capacitor; An internal reference current source is configured to supply an internal reference current to the inverting terminal of the comparator; A fourth switch is configured to selectively couple the inverting terminal of the comparator to ground when the switch control voltage is asserted; A first internal capacitor is coupled between the non-inverting terminal of the comparator and ground, and a second internal voltage is generated across the first internal capacitor; The second internal capacitor is coupled between the internal node and ground; An internal current source, proportional to the analog dimming voltage, is configured to supply internal current to the internal node; A third switch is configured to selectively couple the non-inverting terminal of the comparator to the internal node when the switch control voltage is asserted; as well as The second switch is configured to selectively couple the internal node to ground when a delayed version of the switch control voltage is asserted.

4. The LED lighting system according to claim 1, wherein the analog dimming circuit comprises: A threshold current source is coupled between the input terminal of the controller and the first switch; The first switch is coupled between the threshold current source and ground, and the first switch closes in response to an assertion of the PWM signal and opens in response to a deassertion of the PWM signal.

5. The LED lighting system according to claim 1, wherein the reference current generating circuit comprises: A first current mirror has an input coupled to a first input circuit and an output coupled to supply a first current; The second current mirror has an input coupled to the second input circuit and an output coupled to supply the base reference current; as well as A current adder node is configured to add the first current to the base reference current to generate the reference current.

6. The LED lighting system according to claim 5, wherein the first input circuit comprises: The first NPN transistor has an emitter coupled to a threshold voltage source via a first resistor, a collector coupled to the input of the first current mirror, and a base; as well as An operational amplifier having a non-inverting terminal coupled to receive the analog dimming voltage, an inverting terminal coupled to the emitter of the first NPN transistor, and an output coupled to the base of the first NPN transistor.

7. The LED lighting system of claim 6, wherein the second input circuit comprises: The second NPN transistor has an emitter coupled to ground via a second resistor, a collector coupled to the input of the second current mirror, and a base; as well as An operational amplifier having a non-inverting terminal coupled to receive the threshold voltage, a non-inverting terminal coupled to the emitter of the second NPN transistor, and an output coupled to the base of the second NPN transistor.

8. The LED lighting system according to claim 1, wherein the switching circuit device comprises: A switching regulator that is switched between an input voltage and ground based on a gate drive signal, has an output capacitor coupled in parallel with the LED string between the input voltage and ground, and generates a sensing voltage indicating the current flowing through the LED string, wherein the current flowing through the LED string is either the first LED current or the second LED current. as well as A gate drive circuit device is configured to generate the gate drive signal.

9. The LED lighting system according to claim 8, wherein the gate driving circuit device comprises: A logic circuit is configured to transmit a modulator signal when the enable signal is asserted, thereby generating a first signal; A comparator circuit is configured to compare a reference voltage with the sensed voltage and generate a second signal having a logic level depending on whether the sensed voltage is greater than the sensed voltage, wherein the reference voltage is generated from the reference current; The trigger receives the first signal and the second signal as inputs and generates a gate pre-drive signal as output. as well as The driver is configured to generate the gate drive signal from the gate pre-drive signal.

10. The LED lighting system of claim 9, wherein the logic circuit includes an AND gate; wherein the comparison circuit includes a comparator having a non-inverting input coupled to receive the sensed voltage and an inverting terminal coupled to receive the reference voltage; and wherein the trigger includes an SR trigger having an S input receiving the first signal from the AND gate and an R input receiving the second signal from the comparator.

11. The LED lighting system of claim 8, wherein the gate driving circuit device is configured as follows: When the received modulator signal is at logic high and the enable signal is asserted, the gate drive signal is asserted; and When the sensed voltage exceeds the reference voltage, the assertion of the gate drive signal is released, and the reference voltage is generated based on the reference current.

12. A method of operating an LED lighting system, the method comprising: a) Receive PWM signals; b) When the duty cycle of the PWM signal is greater than the threshold duty cycle, a first LED current proportional to the duty cycle of the PWM signal is supplied to the LED string; c) When the duty cycle of the PWM signal is less than the threshold duty cycle, a second LED current is supplied to the LED string, the duty cycle of the second LED current being proportional to the duty cycle of the PWM signal, such that when the duty cycle of the PWM signal is less than the threshold duty cycle, the amplitude of the average LED current delivered to the LED string is proportional to the duty cycle of the PWM signal, wherein b) and c) are performed using a switching circuit device controlled by a reference current and an enable signal; The threshold duty cycle is determined based on the resistance of the resistor; An analog dimming voltage is generated based on the resistance of the resistor and the PWM signal; The reference current is generated based on the simulated dimming voltage; as well as The enable signal is generated based on the PWM signal, the first internal voltage, and the second internal voltage.

13. The method of claim 12, further comprising: When the received modulator signal is at logic high and the enable signal is asserted, the gate drive signal is asserted. The assertion of the gate drive signal is released when the sensed voltage exceeds the reference voltage, which is generated based on the reference current. The LED string is coupled between the input voltage and ground based on the gate drive signal; as well as The sensed voltage is generated to indicate the current flowing through the LED string, wherein the current flowing through the LED string is either the first LED current or the second LED current.

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