Differential line wiring structure, storage device, and memory control circuit unit

Abstract

The present application provides a differential line wiring structure, a memory storage device and a memory control circuit unit. The differential line wiring structure includes a wiring layer, a first conductor and a second conductor. The first conductor is disposed on the wiring layer and is used to transmit a first differential signal. The second conductor is disposed on the wiring layer and is used to transmit a second differential signal. A first end of the first conductor and a first end of the second conductor are connected to a first electrical element. A second end of the first conductor and a second end of the second conductor are connected to a second electrical element. The first end of the first conductor has a first bending structure. One of the second end of the first conductor and the second end of the second conductor has a second bending structure. Thus, the transmission quality of the differential signal can be improved.

Description

Technical Field

[0001] This invention relates to a circuit board wiring technology, and more particularly to a differential line wiring structure, a memory storage device, and a memory control circuit unit. Background Technology

[0002] Generally, the wires used to transmit differential signals are paired and are also called differential lines. Differential signals transmitted through paired differential lines have the characteristics of the same amplitude and opposite phase. Paired differential lines are usually designed to be of equal length to make the delay time of the transmitted differential signals as consistent as possible. However, in practice, even if the lengths of the paired differential lines are adjusted to be almost identical, the transmitted differential signals may still exhibit inconsistent delay times, thus affecting the signal transmission quality. Summary of the Invention

[0003] This invention provides a differential line wiring structure, a memory storage device, and a memory control circuit unit, which can improve the transmission quality of differential signals.

[0004] An exemplary embodiment of the present invention provides a differential line wiring structure, comprising a wiring layer, a first conductor, and a second conductor. The first conductor is disposed on the wiring layer and is used to transmit a first differential signal. The second conductor is disposed on the wiring layer and is used to transmit a second differential signal. A first end of the first conductor and a first end of the second conductor are connected to a first electrical component. A second end of the first conductor and a second end of the second conductor are connected to a second electrical component. The first end of the first conductor has a first bend structure. One of the second ends of the first conductor and the second end of the second conductor has a second bend structure.

[0005] In one exemplary embodiment of the present invention, the first bending structure and the second bending structure are used to jointly influence the terminal voltages of the first conductor and the second conductor.

[0006] In one exemplary embodiment of the present invention, due to the influence of the first bending structure and the second bending structure, the difference between the total length of the first conductor and the total length of the second conductor is greater than a preset length.

[0007] In one exemplary embodiment of the present invention, neither the first bending structure nor the second bending structure is configured to bypass a specific element.

[0008] In an exemplary embodiment of the present invention, the length of the first curved structure in the first direction is not greater than a first critical value, the length of the first curved structure in the second direction is not greater than a second critical value, and the first direction and the second direction are perpendicular to each other.

[0009] In one exemplary embodiment of the present invention, the first direction is parallel to the wiring direction of the first conductor.

[0010] In an exemplary embodiment of the present invention, the first end of the first conductor and the first bending structure are located within a first region of the first conductor, and the coverage of the first region accounts for a predetermined proportion of the total length of the first conductor.

[0011] An exemplary embodiment of the present invention provides a memory storage device, which includes a differential line wiring structure and a rewritable non-volatile memory module. The rewritable non-volatile memory module is connected to the differential line wiring structure. The differential line wiring structure includes a wiring layer, a first conductor, and a second conductor. The first conductor is disposed on the wiring layer and is used to transmit a first differential signal. The second conductor is disposed on the wiring layer and is used to transmit a second differential signal. A first end of the first conductor and a first end of the second conductor are connected to a first electrical component, and a second end of the first conductor and a second end of the second conductor are connected to a second electrical component. The first end of the first conductor has a first bending structure, and one of the second ends of the first conductor and the second conductor has a second bending structure.

[0012] An exemplary embodiment of the present invention provides a memory control circuit unit for controlling a rewritable non-volatile memory module. The memory control circuit unit includes a differential wiring structure comprising a wiring layer, a first conductor, and a second conductor. The first conductor is disposed on the wiring layer and is used to transmit a first differential signal. The second conductor is disposed on the wiring layer and is used to transmit a second differential signal. A first end of the first conductor and a first end of the second conductor are connected to a first electrical component, and a second end of the first conductor and a second end of the second conductor are connected to a second electrical component. The first end of the first conductor has a first bending structure, and one of the second ends of the first conductor and the second conductor has a second bending structure.

[0013] Based on the above, in the differential line wiring structure, both the first conductor and the second conductor are disposed on the wiring layer and used to transmit the first differential signal and the second differential signal, respectively. In particular, by providing a first bending structure at the first end of the first conductor and a second bending structure at one of the second ends of the first conductor and the second conductor, the transmission quality of the differential signal can be effectively improved. Attached Figure Description

[0014] Figure 1 This is an equivalent circuit diagram of the differential line wiring structure shown in an exemplary embodiment of the present invention;

[0015] Figure 2 This is a schematic diagram of the differential line wiring structure shown in an exemplary embodiment of the present invention;

[0016] Figure 3 This is a schematic diagram of a curved structure shown in an exemplary embodiment of the present invention;

[0017] Figure 4 This is a schematic diagram of the differential lines and the curved structure shown in an exemplary embodiment of the present invention;

[0018] Figure 5 This is a schematic diagram of the differential lines and the curved structure shown in an exemplary embodiment of the present invention;

[0019] Figure 6 This is a schematic diagram of the differential lines and the curved structure shown in an exemplary embodiment of the present invention;

[0020] Figure 7 This is a schematic diagram of a memory storage device according to an exemplary embodiment of the present invention. Detailed Implementation

[0021] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.

[0022] Figure 1 This is an equivalent circuit diagram of the differential line wiring structure shown in an exemplary embodiment of the present invention.

[0023] Please refer to Figure 1 The wiring structure (also known as the differential wiring structure) includes a wiring layer 10, conductors (also known as first conductors) 11, and conductors (also known as second conductors) 12. Conductors 11 and 12 are both disposed on the wiring layer 10. One end of conductor 11 (also known as the first end) is connected to an impedance element R (1). One end of conductor 12 (i.e., the first end) is connected to an impedance element R (2). The other end of conductor 11 (i.e., the second end) is connected to an impedance element R (3). The other end of conductor 12 (i.e., the second end) is connected to an impedance element R (4).

[0024] In one exemplary embodiment, impedance elements R(1) and R(2) may be collectively referred to as first electrical elements, and / or impedance elements R(3) and R(4) may be collectively referred to as second electrical elements. In one exemplary embodiment, impedance elements R(1) to R(4) are all resistors. However, in one exemplary embodiment, impedance elements R(1) to R(4) may be replaced with or further connected to other types of electrical elements (e.g., capacitors, inductors, or transistors) according to practical needs, and the present invention does not limit this.

[0025] Wire 11 is used to transmit a signal (also called a first differential signal) S(1). Wire 12 is used to transmit a signal (also called a second differential signal) S(2). Signals S(1) and S(2) are paired differential signals. For example, signal S(1) may include a D+ signal, and signal S(2) may include a D- signal. At a certain point in time, signals S(1) and S(2) have the same amplitude but opposite phase. For example, at a certain point in time, the phase of signal S(1) and the phase of signal S(2) may differ by approximately 180 degrees. In an exemplary embodiment, wires 11 and 12 may also be considered as paired differential lines (or differential signal lines). Those skilled in the art should know what differential signals and differential lines are, so they will not be described in detail here.

[0026] It should be noted that the first end of conductor 11 may have a bend structure 101. The second end of conductor 11 may have a bend structure 111 and / or the second end of conductor 12 may have a bend structure 121. Bend structure 101 is also referred to as a first bend structure, and at least one of bend structures 111 and 121 is also referred to as a second bend structure. In bend structures 101 and 111, a portion of the conductor 11 is bent (or folded). Similarly, in bend structure 121, a portion of the conductor 12 is bent (or folded). Furthermore, conductors 11 or 12 may each have one or more bend structures, which is not limited by the present invention.

[0027] In one exemplary embodiment, a first bending structure (e.g., bending structure 101) and a second bending structure (e.g., bending structures 111 and / or 121) can be used to jointly influence the terminal voltages of conductors 11 and 12. For example, the terminal voltage of conductor 11 may include voltage V(1), and the terminal voltage of conductor 12 may include voltage V(2). For example, by properly configuring the first bending structure and the second bending structure, the terminal voltages of conductors 11 and 12 (i.e., voltages V(1) and V(2)) can be effectively controlled (e.g., precisely controlled at a certain point in time so that the absolute value of voltage V(1) (i.e., the amplitude of signal S(1)) is almost exactly equal to the absolute value of voltage V(2) (i.e., the amplitude of signal S(2))), thereby improving the transmission quality of signals S(1) and S(2) synchronously transmitted through conductors 11 and 12.

[0028] In one exemplary embodiment, a first bending structure (e.g., bending structure 101) and a second bending structure (e.g., bending structures 111 and / or 121) can be used to jointly influence the delays of signals S(1) and S(2). For example, by properly configuring the first bending structure and the second bending structure, the delay of signal S(1) in conductor 11 and the delay of signal S(2) in conductor 12 can be effectively controlled (e.g., precisely controlled so that the delay of signal S(1) is almost exactly the same as the delay of signal S(2) or the delay deviation between signals S(1) and S(2) is reduced), thereby improving the transmission quality of signals S(1) and S(2) transmitted synchronously through conductors 11 and 12.

[0029] Figure 2 This is a schematic diagram of the differential line wiring structure shown in an exemplary embodiment of the present invention.

[0030] Please refer to Figure 1 and Figure 2 Wire 11 may include wire 21, and wire 12 may include wire 22. Wires 21 and 22 may be used to transmit pairs of differential signals (e.g., signals S(1) and S(2)).

[0031] It should be noted that the first end of conductor 21 has a bending structure 201 (i.e., a first bending structure). In the bending structure 201, a portion of the conductor 21 is bent (or folded). Furthermore, the second end of conductor 21 has a bending structure 202 (i.e., a second bending structure). In the bending structure 202, another portion of the conductor 21 is also bent (or folded). Alternatively, in an exemplary embodiment, the bending structure 202 may also be provided at the second end of conductor 22, depending on practical requirements.

[0032] The bent structures 201 and 202 can be used to jointly influence (e.g., adjust) the terminal voltages of wires 21 and 22. Alternatively, the bent structures 201 and 202 can be used to jointly influence (e.g., adjust) the delay of the differential signal transmitted through wires 21 and 22. This can effectively improve the transmission quality of the differential signal transmitted synchronously through wires 21 and 22, for example, improving the synchronization rate of the differential signal transmitted through wires 21 and 22.

[0033] In one exemplary embodiment, due to the influence of the first and second bending structures, the difference between the total length of the first conductor (i.e., the bus length of the first conductor) and the total length of the second conductor (i.e., the bus length of the second conductor) will be greater than a preset length. For example, this preset length can be 3 mils. One mil equals 25.4 micrometers (μm). It should be noted that the preset length can be adjusted according to practical needs, and this invention does not impose any limitations on it.

[0034] In one exemplary embodiment, neither the first bending structure nor the second bending structure is configured to bypass a specific element. Figure 2 For example, the bending structures 201 and 202 are not designed to bypass specific components. For instance, in the bending structures 201 and 202, there may be no electronic circuit components that need to be bypassed within the bending range of the wires 21 and 22.

[0035] In one exemplary embodiment, the length of the first curved structure in one direction (also referred to as the first direction) is no greater than a critical value (also referred to as the first critical value), and the length of the first curved structure in another direction (also referred to as the second direction) is no greater than another critical value (also referred to as the second critical value), and the first direction and the second direction are perpendicular to each other. For example, the first critical value may be 30 mils, and / or the second critical value may be 15 mils. In one exemplary embodiment, the first direction may be parallel to the wiring direction of the first conductor. In one exemplary embodiment, the first direction may also be other directions. It should be noted that both the first critical value and the second critical value can be adjusted according to practical needs, and the present invention does not impose any limitations on them.

[0036] Figure 3 This is a schematic diagram of a curved structure shown in an exemplary embodiment of the present invention.

[0037] Please refer to Figure 3 Conductors 31 and 32 are paired differential lines. The first and / or second end of conductor 32 has a bend structure 301. The length L(1) of the bend structure 301 in the first direction is not greater than a first critical value (e.g., 30 mils), and the length L(2) of the bend structure 301 in the second direction is not greater than a second critical value (e.g., 15 mils). Furthermore, the first direction may be parallel to the wiring direction of conductor 32, such as... Figure 3 As shown.

[0038] In one exemplary embodiment, the length of the first curved structure in the first direction and / or the length of the first curved structure in the second direction may both be greater than or less than a specific critical value or fall within a specific numerical range; this invention does not impose any limitations on these aspects. Furthermore, the same or similar limitations may also be applied to the second curved structure.

[0039] In one exemplary embodiment, the first end of the first conductor and the first bend structure may be located within a specific region of the first conductor (also referred to as the first region). For example, the coverage area of ​​the first region may occupy a predetermined proportion of the total length of the first conductor. For example, this predetermined proportion may be 3 / 8. The same or similar limitations may also be applied to the second bend structure. For example, the second end of the first conductor and the second bend structure may be located within another specific region of the first conductor (also referred to as the second region). For example, the coverage area of ​​the second region may also occupy the predetermined proportion of the total length of the first conductor. Alternatively, the second end of the second conductor and the second bend structure may be located within a specific region of the second conductor (also referred to as the third region). For example, the coverage area of ​​the third region may occupy the predetermined proportion of the total length of the second conductor. It should be noted that the predetermined proportion may be adjusted according to practical needs, and the present invention is not limited thereto.

[0040] by Figure 2 For example, assuming the total length of conductor 21 is N mils and the total length of conductor 22 is M mils, then the bending structure 201 can be located within the range of N×3 / 8 mils of conductor 21 including the first end of conductor 21, and the bending structure 202 can be located within the range of N×3 / 8 mils of conductor 21 including the second end of conductor 21 (or the bending structure 202 can be located within the range of M×3 / 8 mils of conductor 22 including the second end of conductor 22).

[0041] It should be noted that the actual placement of the first and / or second bending structures can be adjusted according to practical needs, and this invention does not impose any limitations on this. Furthermore, the bending angle of at least one bending point of the first and / or second bending structures can also be determined or adjusted according to practical needs, and this invention does not impose any limitations on this.

[0042] Figure 4 This is a schematic diagram of the differential lines and the curved structure shown in an exemplary embodiment of the present invention.

[0043] Please refer to Figure 4 Conductors 41 and 42 are paired differential lines. One end of conductor 41 has a bend structure 401. In particular, the bend structure 401 can be used to affect the terminal voltage of conductors 41 and / or 42, and the bend structure 401 is not arranged to bypass any specific component.

[0044] Figure 5 This is a schematic diagram of the differential lines and the curved structure shown in an exemplary embodiment of the present invention.

[0045] Please refer to Figure 5 Conductors 51 and 52 are paired differential lines. One end of conductor 52 has a bend structure 501. In particular, the bend structure 501 can be used to affect the terminal voltage of conductors 51 and / or 52, and the bend structure 501 is not designed to bypass any specific component.

[0046] Figure 6 This is a schematic diagram of the differential lines and the curved structure shown in an exemplary embodiment of the present invention.

[0047] Please refer to Figure 6 Conductors 61 and 62 are paired differential lines. One end of conductor 62 has a bend structure 601. In particular, the bend structure 601 can be used to affect the terminal voltage of conductors 61 and / or 62, and the bend structure 601 is not arranged to bypass any specific component.

[0048] In one exemplary embodiment, the aforementioned differential line wiring structure may be disposed in a memory storage device. Alternatively, in one exemplary embodiment, the aforementioned differential line wiring structure may also be disposed in any type of electronic device, and the present invention is not limited thereto.

[0049] Figure 7 This is a schematic diagram of a memory storage device according to an exemplary embodiment of the present invention.

[0050] Please refer to Figure 7 The memory storage device 70 includes a connection interface unit 701, a memory control circuit unit 702, and a rewritable non-volatile memory module 703. The aforementioned differential line wiring structure can be disposed in the memory storage device 70.

[0051] The connection interface unit 701 is used to connect the memory storage device 70 to the host system 71. The memory storage device 70 can communicate with the host system 71 via the connection interface unit 701. In an exemplary embodiment, the connection interface unit 701 is compatible with the Peripheral Component Interconnect Express (PCI Express) standard. However, it must be understood that the present invention is not limited thereto, and the connection interface unit 701 may also conform to the Serial Advanced Technology Attachment (SATA) standard, the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronics Engineers (IEEE) 1394 standard, the Universal Serial Bus (USB) standard, the SD interface standard, the Ultra High Speed-I (UHS-I) interface standard, the Ultra High Speed-II (UHS-II) interface standard, the Memory Stick (MS) interface standard, the MCP interface standard, the MMC interface standard, the eMMC interface standard, the Universal Flash Storage (UFS) interface standard, the eMCP interface standard, the CF interface standard, the Integrated Device Electronics (IDE) standard, or other suitable standards. The connection interface unit 501 may be packaged in a chip with the memory control circuit unit 702, or the connection interface unit 701 may be disposed outside a chip containing the memory control circuit unit 702.

[0052] The memory control circuit unit 702 is connected to the connection interface unit 701 and the rewritable non-volatile memory module 703. The memory control circuit unit 702 executes multiple logic gates or control instructions implemented in hardware or firmware, and performs operations such as writing, reading, and erasing data in the rewritable non-volatile memory module 703 according to instructions from the host system. For example, the memory control circuit unit 702 may include a flash memory controller.

[0053] The rewritable non-volatile memory module 703 is used to store data written by the host system 71. The rewritable non-volatile memory module 703 may include a single-level cell (SLC) NAND flash memory module (i.e., a flash memory module that can store 1 bit in one memory cell), a multi-level cell (MLC) NAND flash memory module (i.e., a flash memory module that can store 2 bits in one memory cell), a triple-level cell (TLC) NAND flash memory module (i.e., a flash memory module that can store 3 bits in one memory cell), a quadruple-level cell (QLC) NAND flash memory module (i.e., a flash memory module that can store 4 bits in one memory cell), other flash memory modules, or other memory modules with the same characteristics.

[0054] Each memory cell in the rewritable non-volatile memory module 703 stores one or more bits by changing a voltage (hereinafter also referred to as the threshold voltage). Specifically, each memory cell has a charge trapping layer between its control gate and channel. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be changed, thereby changing the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also called "writing data to the memory cell" or "programming the memory cell". As the threshold voltage changes, each memory cell in the rewritable non-volatile memory module 703 has multiple storage states. By applying a read voltage, it can be determined which storage state a memory cell belongs to, thereby retrieving the one or more bits stored in that memory cell.

[0055] In one exemplary embodiment, the memory cells of the rewritable non-volatile memory module 703 can constitute multiple physical programmable units, and these physical programmable units can constitute multiple physical erase units. Specifically, memory cells on the same word line can form one or more physical programmable units. If a memory cell can store more than two bits, then physical programmable units on the same word line can be classified into lower physical programmable units and upper physical programmable units. For example, the least significant bit (LSB) of a memory cell belongs to the lower physical programmable unit, and the most significant bit (MSB) of a memory cell belongs to the upper physical programmable unit. Generally, in MLC NAND flash memory, the write speed of the lower physical programmable unit is greater than that of the upper physical programmable unit, and / or the reliability of the lower physical programmable unit is higher than that of the upper physical programmable unit.

[0056] In one exemplary embodiment, a physical programming unit is the smallest unit of programming. That is, a physical programming unit is the smallest unit for writing data. For example, a physical programming unit can be a physical page or a physical sector. If the physical programming unit is a physical page, these physical programming units may include data bit areas and redundancy bit areas. The data bit area contains multiple physical sectors for storing user data, while the redundancy bit area is used to store system data (e.g., management data such as error correction codes). In one exemplary embodiment, the data bit area contains 32 physical sectors, and the size of one physical sector is 512 bytes (B). However, in other exemplary embodiments, the data bit area may also contain 8, 16, or more or fewer physical sectors, and the size of each physical sector may also be larger or smaller. On the other hand, a physical erase unit is the smallest unit of erasure. That is, each physical erase unit contains a minimum number of storage units to be erased together. For example, a physical erase unit is a physical block.

[0057] In one exemplary embodiment, the aforementioned differential line wiring structure (including Figure 1 The conductors 11 and 12 may be disposed in the connection interface unit 701 to transmit differential signals in the connection interface unit 701. Alternatively, in an exemplary embodiment, the aforementioned differential line wiring structure (including...) Figure 1The wires 11 and 12 can also be disposed in the memory control circuit unit 702 and / or the rewritable non-volatile memory module 703 to transmit differential signals in the memory control circuit unit 702 and / or the rewritable non-volatile memory module 703. Furthermore, at least one of the connection interface unit 701, the memory control circuit unit 702, and the rewritable non-volatile memory module 703 can be connected to... Figure 1 Wiring layer 10.

[0058] In summary, the differential line wiring structure, memory storage device, and memory control circuit unit proposed in the exemplary embodiments of the present invention can effectively improve the transmission quality of differential signals transmitted through the differential lines by providing additional bending structures at the first and / or second ends of each pair of differential lines.

[0059] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A differential line wiring structure, characterized in that, include: Wiring layer; A first conductor is disposed in the wiring layer and used to transmit a first differential signal; as well as A second conductor is disposed in the wiring layer and used to transmit a second differential signal. The first end of the first conductor and the first end of the second conductor are connected to a first electrical component, and the second end of the first conductor and the second end of the second conductor are connected to a second electrical component. The first end of the first conductor has a first bending structure, and one of the second ends of the first conductor and the second end of the second conductor has a second bending structure. The first end of the first conductor and the first bending structure are located within a first region of the first conductor, and the coverage area of ​​the first region accounts for a preset proportion of the total length of the first conductor.

2. The differential line wiring structure according to claim 1, wherein the first bending structure and the second bending structure are used to jointly affect the terminal voltages of the first conductor and the second conductor.

3. The differential wiring structure according to claim 1, wherein the difference between the total length of the first conductor and the total length of the second conductor is greater than a preset length due to the influence of the first bending structure and the second bending structure.

4. The differential line wiring structure according to claim 1, wherein the first bending structure and the second bending structure are not configured to bypass a specific component.

5. The differential line wiring structure according to claim 1, wherein the length of the first bending structure in the first direction is not greater than a first critical value, the length of the first bending structure in the second direction is not greater than a second critical value, and the first direction and the second direction are perpendicular to each other.

6. The differential line wiring structure according to claim 5, wherein the first direction is parallel to the wiring direction of the first conductor.

7. A memory storage device, characterized in that, include: Differential line wiring structure; as well as A rewritable non-volatile memory module is connected to the wiring structure of the differential lines. The wiring structure of the differential lines includes: Wiring layer; A first conductor is disposed in the wiring layer and used to transmit a first differential signal; and A second conductor is disposed in the wiring layer and used to transmit a second differential signal. The first end of the first conductor and the first end of the second conductor are connected to a first electrical component, and the second end of the first conductor and the second end of the second conductor are connected to a second electrical component. The first end of the first conductor has a first bending structure, and one of the second ends of the first conductor and the second end of the second conductor has a second bending structure. The first end of the first conductor and the first bending structure are located within a first region of the first conductor, and the coverage area of ​​the first region accounts for a preset proportion of the total length of the first conductor.

8. The memory storage device of claim 7, wherein the first bending structure and the second bending structure are used to jointly influence the terminal voltages of the first conductor and the second conductor.

9. The memory storage device according to claim 7, wherein the difference between the total length of the first wire and the total length of the second wire is greater than a preset length due to the influence of the first bending structure and the second bending structure.

10. The memory storage device of claim 7, wherein the arrangement of the first bending structure and the second bending structure is not for bypassing a specific element.

11. The memory storage device according to claim 7, wherein the length of the first curved structure in the first direction is not greater than a first critical value, the length of the first curved structure in the second direction is not greater than a second critical value, and the first direction and the second direction are perpendicular to each other.

12. The memory storage device of claim 11, wherein the first direction is parallel to the wiring direction of the first wire.

13. A memory control circuit unit, characterized in that, The memory control circuit unit, used to control the rewritable non-volatile memory module, includes: The wiring structure of differential lines includes: Wiring layer; A first conductor is disposed in the wiring layer and used to transmit a first differential signal; and A second conductor is disposed in the wiring layer and used to transmit a second differential signal. The first end of the first conductor and the first end of the second conductor are connected to a first electrical component, and the second end of the first conductor and the second end of the second conductor are connected to a second electrical component. The first end of the first conductor has a first bending structure, and one of the second ends of the first conductor and the second end of the second conductor has a second bending structure. The first end of the first conductor and the first bending structure are located within a first region of the first conductor, and the coverage area of ​​the first region accounts for a preset proportion of the total length of the first conductor.

14. The memory control circuit unit of claim 13, wherein the first bending structure and the second bending structure are used to jointly influence the terminal voltages of the first conductor and the second conductor.

15. The memory control circuit unit according to claim 13, wherein the difference between the total length of the first wire and the total length of the second wire is greater than a preset length due to the influence of the first bending structure and the second bending structure.

16. The memory control circuit unit of claim 13, wherein the arrangement of the first bending structure and the second bending structure is not for bypassing a specific element.

17. The memory control circuit unit according to claim 13, wherein the length of the first curved structure in the first direction is not greater than a first critical value, the length of the first curved structure in the second direction is not greater than a second critical value, and the first direction and the second direction are perpendicular to each other.

18. The memory control circuit unit of claim 17, wherein the first direction is parallel to the wiring direction of the first wire.

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