Semiconductor structure and method for forming the same
By forming a side wall structure with a multi-layer insulating layer on the substrate and conductive structure surface of the semiconductor memory device, the problem of increasing parasitic capacitance between conductive structures under high integration is solved, and the readout capacity is improved.
Patent Information
- Application Number
- CN202111046005.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2021-09-07
- Publication Date
- 2025-02-21
- Estimated Expiration
- 2041-09-07
AI Technical Summary
With the high integration of semiconductor memory devices, the distance between conductive structures becomes shorter, thereby increasing parasitic capacitance and affecting the readout capacity.
By forming a series of insulating layers, including a first insulating layer, a second insulating layer and a third insulating layer on the surface of the substrate, a bit line contact hole, a bit line contact and a bit line structure, a side wall structure covering these insulating layers is formed, Reduce the parasitic capacitance between the bit line and the bit line contact to the memory node contact.
The parasitic capacitance between the bit line and the bit line contact and the storage node contact is effectively reduced, and the readout capacity is improved.
Smart Images
Figure CN116056446B_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and relates to but is not limited to a semiconductor structure and a method for forming the same. Background Art
[0002] Dynamic Random Access Memory (DRAM) is a semiconductor memory device commonly used in computers. DRAM includes many repeated storage cells. Each storage cell usually includes a capacitor and a transistor, wherein the gate of the transistor is connected to the word line, the drain region or source region of the transistor is connected to the bit line, and the source region or drain region of the transistor is connected to the capacitor. Applying a voltage signal on the word line can control the opening or closing of the transistor, and then read the data information stored in the capacitor through the bit line, or write the data information into the capacitor through the bit line for storage.
[0003] As semiconductor memory devices become more highly integrated, distances between conductive structures become shorter, thereby increasing parasitic capacitance. Summary of the invention
[0004] Embodiments of the present application provide a semiconductor structure and a method for forming the same.
[0005] In a first aspect, an embodiment of the present application provides a method for forming a semiconductor structure, comprising:
[0006] providing a substrate;
[0007] forming, on the substrate, spaced-apart bit line contact holes, bit line contacts partially contacting the bit line contact holes, and a bit line structure;
[0008] Forming a first insulating layer on the surface of the substrate, the bit line contact hole, the bit line contact and the bit line structure; wherein the first insulating layer does not completely fill the bit line contact hole;
[0009] forming a second insulating layer on the surface of the first insulating layer located on the bit line contact surface and the bit line structure portion surface;
[0010] A third insulating layer covering the first insulating layer and the second insulating layer is formed.
[0011] In a second aspect, an embodiment of the present application provides a semiconductor structure, including:
[0012] substrate;
[0013] Bit line contact holes arranged at intervals on the substrate, bit line contacts partially contacting the bit line contact holes, and a bit line structure;
[0014] A first insulating layer located on the substrate, the bit line contact hole, the bit line contact and the surface of the bit line structure; wherein the first insulating layer does not completely fill the bit line contact hole;
[0015] A second insulating layer located on the surface of the first insulating layer on the bit line contact surface and the surface of the bit line structure portion;
[0016] A third insulating layer is located on surfaces of the first insulating layer and the second insulating layer.
[0017] In a third aspect, an embodiment of the present application provides a semiconductor structure, including:
[0018] substrate;
[0019] The substrate includes spaced-apart bit line contact holes, bit line contacts partially contacting the bit line contact holes, and a bit line structure;
[0020] An insulating layer located on both side walls of the bit line contact and the bit line structure; wherein the insulating layer comprises a first insulating layer, a second insulating layer and a third insulating layer stacked in sequence, and at least the insulating layer of the first side wall comprises the first insulating layer, the second insulating layer and the third insulating layer whose heights decrease in sequence;
[0021] A storage node contact located between adjacent third insulating layers;
[0022] a landing pad covering the storage node contact and the surface of the insulating layer of the first sidewall, the landing pad being electrically connected to the storage node contact;
[0023] An isolation structure is located between adjacent landing pads and on the surface of the landing pad.
[0024] In the embodiment of the present application, a first insulating layer is formed on the surface of a substrate, a bit line contact hole, a bit line contact and a bit line structure; a second insulating layer is formed on the surface of the first insulating layer located on the bit line contact surface and the surface of a portion of the bit line structure; and a third insulating layer is formed covering the first insulating layer and the second insulating layer. A new method for forming a sidewall structure of a bit line (Bit Line, BL) and a bit line contact structure (Bit Line Contact, BL) is provided, thereby reducing the parasitic capacitance between the BL and the BLC to the storage node contact (Storage Node Contact, SNC) and improving the read capacity. BRIEF DESCRIPTION OF THE DRAWINGS
[0025] In the accompanying drawings (which are not necessarily drawn to scale), like reference numerals may describe similar components in different views. Like reference numerals with different letter suffixes may represent different examples of similar components. The accompanying drawings generally illustrate various embodiments discussed herein by way of example and not limitation.
[0026] Figure 1a A schematic diagram of a process for forming a semiconductor structure provided in an embodiment of the present application;
[0027] Figure 1b to Figure 1e A schematic diagram of a semiconductor structure forming process provided in an embodiment of the present application;
[0028] Figure 2a Another schematic diagram of a process for forming a semiconductor structure provided in an embodiment of the present application;
[0029] Figure 2b to Figure 2e Another structural schematic diagram of a semiconductor structure forming process provided by an embodiment of the present application;
[0030] Figure 3a A schematic diagram of a process for forming a semiconductor structure provided in an embodiment of the present application;
[0031] Figure 3b to Figure 3k Another structural schematic diagram of a semiconductor structure forming process provided by an embodiment of the present application;
[0032] Figure 4a A schematic diagram of a process for forming a semiconductor structure provided in an embodiment of the present application;
[0033] Figure 4b to Figure 4e Another structural schematic diagram of the semiconductor structure formation process provided in an embodiment of the present application. DETAILED DESCRIPTION
[0034] The exemplary embodiments disclosed in the present application will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the specific embodiments described herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope disclosed in the present application to those skilled in the art.
[0035] In the following description, a large number of specific details are given to provide a more thorough understanding of the present application. However, it is obvious to those skilled in the art that the present application can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present application, some technical features known in the art are not described; that is, all features of the actual embodiments are not described here, and well-known functions and structures are not described in detail.
[0036] The present application provides a method for forming a semiconductor structure. Figure 1a As shown, the method comprises the following steps:
[0037] Step S101: providing a substrate.
[0038] Here, the substrate can be a silicon (Si) substrate, a germanium (Ge) substrate, a silicon germanium (SiGe) substrate, a gallium arsenide substrate, a ceramic substrate, a quartz substrate or a glass substrate for a display, and can also include multiple layers, such as a silicon on insulator (Silicon On Insulator, SOI) substrate, or a germanium on insulator (Germanium On Insulator, GOI) substrate, etc.
[0039] Shallow Trench Isolation (STI) may also be formed in the substrate to isolate a number of active areas in the substrate. STI may be formed by forming a trench in the substrate and then filling the trench with an isolation material layer. The material filled in STI may include silicon nitride or silicon oxide, etc., and silicon oxide may be formed by thermal oxidation. STI may isolate a number of active areas in an array distribution or other distribution types in the substrate.
[0040] Step S102, forming bit line contact holes arranged at intervals, bit line contacts partially contacting the bit line contact holes, and a bit line structure on the substrate.
[0041] Here, the bit line contact hole has a space not occupied by the bit line contact. The bit line contact can connect the bit line structure to the active area, and the material used for the bit line contact can include but is not limited to conductive materials such as polysilicon, for example, polysilicon doped with impurities or polysilicon not doped with impurities.
[0042] In practical applications, the bit line structure may include a diffusion barrier layer, a conductive layer and an insulating cap layer; wherein the diffusion barrier layer is located between the bit line contact and the conductive layer, and the insulating cap layer is located on the conductive layer. The diffusion barrier layer may insulate the conductive layer from the active region and prevent metal ions in the conductive layer from entering the active region, and may include a single-layer structure, such as a metal titanium layer; or a multi-layer structure, such as a metal titanium layer and a titanium nitride layer.
[0043] In practical applications, the material of the conductive layer can be one or more of polysilicon, metal silicide compounds, conductive metal nitrides (such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), etc.) and metals (such as tungsten (W), titanium (Ti), tantalum (Ta), etc.).
[0044] In practical applications, the material of the insulating cap layer may be one or more of oxide, silicon nitride and silicon oxynitride, and may be formed by a chemical vapor deposition process.
[0045] Step S103, forming a first insulating layer on the surface of the substrate, the bit line contact hole, the bit line contact and the bit line structure; wherein the first insulating layer does not completely fill the bit line contact hole.
[0046] Here, the material used for the first insulating layer may include but is not limited to silicon nitride, silicon oxynitride, etc. In some embodiments, in order to facilitate the control of the thickness of the first insulating layer, the first insulating layer may be formed by an atomic layer deposition process. In other embodiments, other processes may also be used to form the first insulating layer, such as a physical vapor deposition process, a chemical vapor deposition process, a low-pressure chemical vapor deposition process, a molecular layer deposition process, a plasma enhanced vapor deposition process, etc. The first insulating layer may be used to protect the bit line structure and the bit line contact structure (Bit Line Contact, BLC) from damage in subsequent processes.
[0047] Step S104 , forming a second insulating layer on the surface of the first insulating layer located on the bit line contact surface and the surface of the bit line structure portion.
[0048] Here, the second insulating layer may be an air gap or an oxide layer, wherein the material of the oxide layer may be silicon oxide, and may be formed by the same process as the first insulating layer.
[0049] Step S105 , forming a third insulating layer covering the first insulating layer and the second insulating layer.
[0050] Here, the material used for the third insulating layer may be the same as or different from the material used for the first insulating layer; the formation process of the third insulating layer may be the same as or different from the formation process of the first insulating layer.
[0051] In the embodiment of the present application, a method for forming a sidewall structure of a new bit line (BitLine, BL) and a bit line contact structure is provided by forming a first insulating layer on the surface of a substrate, a bit line contact hole, a bit line contact and a bit line structure; forming a second insulating layer on the surface of the first insulating layer located on the bit line contact surface and a partial surface of the bit line structure; and forming a third insulating layer covering the bit line structure, the first insulating layer and the second insulating layer, thereby reducing the parasitic capacitance between the BL and the BLC and the storage node contact (Storage Node Contact, SNC) and improving the read capacity.
[0052] Figure 1b to Figure 1e The schematic diagram of the semiconductor structure forming process provided in the embodiment of the present application is as follows. Figure 1b to Figure 1e The above steps S102 to S105 are further explained.
[0053] like Figure 1b As shown, bit line contact holes 101 arranged at intervals, bit line contacts 102 partially contacting the bit line contact holes 101 , and a bit line structure 103 are formed on a substrate 100 .
[0054] Combination Figure 1b He Ru Figure 1c The substrate 100, the bit line contact hole 101, the bit line contact 102 and the bit line structure 103 are formed as follows. Figure 1c The first insulating layer 104 is shown. When the first insulating layer 104 is formed, the gap 101a is formed, that is, the first insulating layer 104 is not completely filled. Figure 1b The bit line contact hole 101 is shown in FIG.
[0055] like Figure 1d As shown, a second insulating layer 105 is formed on the surface of the first insulating layer 104 located on the surface of the bit line contact 102 and a part of the surface of the bit line structure 103. At this time, the second insulating layer is filled with Figure 1c In the gap 101a shown, the sidewall structures of BL and BLC are NON structures or NAN structures, which can reduce the parasitic capacitance between BL and BLC and SNC.
[0056] like Figure 1e As shown, after the second insulating layer 105 is formed, a third insulating layer 106 covering the first insulating layer 104 and the second insulating layer 105 is formed by deposition.
[0057] In some embodiments, see Figure 1e The bit line structure 103 may include a diffusion barrier layer 103a, a conductive layer 103b and an insulating cap layer 103c. The diffusion barrier layer 103a is located between the bit line contact 102 and the conductive layer 103b, and the insulating cap layer 103c is located on the conductive layer 103b.
[0058] based on Figure 1a A method for forming a semiconductor structure is shown in the figure. The present application embodiment provides a semiconductor structure, such as Figure 1e As shown, the structure includes:
[0059] Base 100;
[0060] Bit line contact holes arranged at intervals on the substrate 100, bit line contacts 102 partially contacting the bit line contact holes, and a bit line structure 103;
[0061] A first insulating layer 104 is located on the surface of the substrate 100, the bit line contact hole, the bit line contact 102 and the bit line structure 103; wherein the first insulating layer 104 does not completely fill the bit line contact hole;
[0062] A second insulating layer 105 located on the surface of the first insulating layer 104 on the surface of the bit line contact 102 and a portion of the surface of the bit line structure 103;
[0063] The third insulating layer 106 is located on the surfaces of the first insulating layer 104 and the second insulating layer 105 .
[0064] The present application also provides a method for forming a semiconductor structure. Figure 2a As shown, the method comprises the following steps:
[0065] Figure 1a The steps S101 to S105 shown in the figure further include after step S105:
[0066] Step S201: forming a fourth insulating layer on the surface of the third insulating layer.
[0067] Here, the role of the fourth insulating layer is to prevent the third insulating layer on the surface of the bit line structure from being etched away during subsequent etching, thereby damaging the insulating layer. The material used for the fourth insulating layer may include but is not limited to silicon nitride, silicon oxynitride, etc., and the material used may be the same as the material used for the third insulating layer. The fourth insulating layer may be formed by an atomic layer deposition process, or other processes may be used, such as a physical vapor deposition process, a chemical vapor deposition process, a low-pressure chemical vapor deposition process, a molecular layer deposition process, a plasma enhanced vapor deposition process, etc.
[0068] Step S202: etching the fourth insulating layer and the third insulating layer and a portion of the substrate located on the surface of the substrate to expose the substrate.
[0069] Step S203 , forming storage node contacts between adjacent third insulating layers.
[0070] Here, the storage node contact may include polysilicon doped with impurities or polysilicon not doped with impurities.
[0071] Step S204 , etching part of the bit line structure, part of the first insulating layer, part of the second insulating layer and part of the third insulating layer, and the remaining first insulating layer, second insulating layer and third insulating layer form an insulating layer.
[0072] In the embodiment of the present application, an insulating layer is formed between the bit line contact and the storage node contact, wherein the insulating layer between the bit line and the bit line contact and the storage node contact comprises a first insulating layer, a second insulating layer and a third insulating layer, thereby reducing the parasitic capacitance from the bit line structure to the storage node contact.
[0073] Steps S201 to S204 refer to Figure 2b to Figure 2e .
[0074] like Figure 2b As shown, a fourth insulating layer 107 is formed on the surface of the third insulating layer 106 .
[0075] See also Figure 2b , the fourth insulating layer 107 and the third insulating layer 106 and a portion of the substrate 100 located on the surface of the substrate 100 are etched to expose the substrate 100, forming Figure 2c The structure shown.
[0076] like Figure 2d As shown, storage node contacts 108 are formed between adjacent third insulating layers 106 , the storage node contacts 108 are spaced apart from each other, and each storage node contact 108 may have a concave top surface.
[0077] See also Figure 2d , a portion of the bit line structure 103, a portion of the first insulating layer 104, a portion of the second insulating layer 105 and a portion of the third insulating layer 106 are etched, and the remaining first insulating layer 104, the remaining second insulating layer 105 and the remaining third insulating layer 106 are formed as shown in Figure 2e The insulating layer 109 is shown.
[0078] The present application also provides a method for forming a semiconductor structure. Figure 3a As shown, the method comprises the following steps:
[0079] Figure 1a The steps S101 to S105 shown in the figure further include after step S105:
[0080] Step S301 : forming storage node contacts between adjacent third insulating layers.
[0081] Step S302 , etching part of the bit line structure, part of the first insulating layer, part of the second insulating layer and part of the third insulating layer, and the remaining first insulating layer, second insulating layer and third insulating layer form an insulating layer.
[0082] Step S301 and step S302 are the same as step S203 and step S204, respectively, and can be referred to respectively. Figure 2d and Figure 2e .
[0083] Step S303 : forming a metal layer on the surface of the insulating layer contacting the storage node.
[0084] Here, the material used for the metal layer can be a conductive material, such as tungsten (W). The conductive material is deposited by a plasma enhanced chemical vapor deposition process (PECVD) to avoid voids during filling. In some embodiments, the conductive material can also be deposited by a chemical vapor deposition process, a low pressure chemical vapor deposition process, an atomic layer deposition process, or other suitable process.
[0085] Step S303 can refer to Figure 3b , a metal layer 110 a is formed on surfaces of the insulating layer 109 and the storage node contact 108 .
[0086] Step S304 , etching a portion of the metal layer to expose a portion of the insulating layer, and the remaining metal layer forms a landing pad that is electrically connected to the storage node.
[0087] Here, a dry etching process or a wet etching process may be used to selectively etch the metal layer, and the etching gas may be HBr / Cl 2. The landing pad functions to electrically connect the storage node contact with the capacitor.
[0088] Step S304 can refer to Figure 3b and Figure 3c See also Figure 3b , a portion of the metal layer 110a is etched to expose a portion of the insulating layer 109, and the remaining metal layer 110a is formed to be electrically connected to the storage node contact 108. Figure 3c A landing pad 110 is shown.
[0089] In some embodiments, step S304 further includes: step S305, see Figure 3d An isolation structure 111 is formed between adjacent landing pads 110 and on the surface of the landing pad 110 .
[0090] Here, the material of the isolation structure may be silicon oxide, silicon nitride (eg, silicon nitride (Si3N4)), or silicon oxynitride, etc.
[0091] In some embodiments, step S302 further includes:
[0092] Step A1: See Figure 3e At least two barrier layers 112 are formed on the surfaces of the storage node contact 108, the bit line structure 103 and the insulating layer 109. Here, the at least two barrier layers 112 include a first barrier layer 112a and a second barrier layer 112b formed in sequence.
[0093] Accordingly, step S304 includes: step 304a, and referring to Figure 3b and 3e , etching a portion of the metal layer 110a and a portion of the at least two barrier layers 112, exposing a portion of the insulating layer 109, and the remaining metal layer 110a forms a structure electrically connected to the storage node contact 108. Figure 3f Then, step S305 may be continued to form an isolation structure 111 between adjacent landing pads 110 and on the surface of the landing pad 110, so as to obtain Figure 3g The structure shown.
[0094] In practical applications, the barrier layer may be formed of a material selected from titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) and stacked structures thereof. For example, the material used for the first barrier layer may be Ti, and the material used for the second barrier layer may be TiN.
[0095] In some embodiments, step A1 includes step A11 and step A12, wherein:
[0096] Step A11, forming a storage node ohmic layer on the storage node contact;
[0097] Step A12: forming at least two barrier layers on the surfaces of the storage node ohmic layer, the bit line structure and the insulating layer.
[0098] See also Figure 3h , a storage node ohmic layer 113 is formed on the storage node contact 108. Figure 3i At least two barrier layers 112 are formed on the surfaces of the storage node ohmic layer 113, the bit line structure 103 and the insulating layer 109. After executing step A12, step S303, step 304a and step S305 may be continued to obtain the following Figure 3j The structure shown.
[0099] In practical applications, the storage node ohmic layer can reduce the contact resistance between the storage node contact and the landing pad. The material used for the storage node ohmic layer can be cobalt silicide (CoSi x ), nickel silicide (NiSi x ) and at least one of manganese silicide (MnSix).
[0100] In some embodiments, see Figure 1e, the bit line structure 103 may include a diffusion barrier layer 103a, a conductive layer 103b and an insulating cap layer 103c. The diffusion barrier layer 103a is located between the bit line contact 102 and the conductive layer 103b. The insulating cap layer 103c is located on the conductive layer 103b. Accordingly, etching a portion of the bit line structure 103 in step S302 includes: etching a portion of the insulating cap layer 103b. Figure 3j As shown, the insulating cap layer 103c forms a convex structure after etching.
[0101] The present application also provides a method for forming a semiconductor structure. Figure 4a As shown, the method comprises the following steps:
[0102] Step S401: providing a substrate.
[0103] Step S402: forming bit line contact holes arranged at intervals, bit line contacts partially contacting the bit line contact holes, and a bit line structure on the substrate.
[0104] Step S403, forming a first insulating layer on the surface of the substrate, the bit line contact hole, the bit line contact and the bit line structure; wherein the first insulating layer does not completely fill the bit line contact hole.
[0105] Here, steps S401 to S403 are the same as steps S101 to S103, and can be understood by referring to steps S101 to S103.
[0106] Step S404: forming an initial second insulating layer on the surface of the first insulating layer.
[0107] Here, the first insulating layer and the initial second insulating layer fully fill the bit line contact hole.
[0108] Step S405, etching the initial second insulating layer located on the surface of the first insulating layer on the substrate and the top surface of the bit line structure, and the remaining initial second insulating layer located on the bit line contact surface and the surface of part of the bit line structure forms the second insulating layer.
[0109] Here, the surface of the first insulating layer and the initial second insulating layer on the top surface of the bit line structure may be etched by dry etching. In some embodiments, a portion of the initial second insulating layer above the sidewall of the bit line structure may also be etched.
[0110] Step S406: forming a third insulating layer covering the first insulating layer and the second insulating layer.
[0111] Step S407 , forming storage node contacts between adjacent third insulating layers.
[0112] Step S408 , etching part of the bit line structure, part of the first insulating layer, part of the second insulating layer and part of the third insulating layer, and the remaining first insulating layer, second insulating layer and third insulating layer form an insulating layer.
[0113] Step S409 , forming a metal layer on the surface of the insulating layer contacting the storage node.
[0114] Step S410: etching a portion of the metal layer to expose a portion of the insulating layer, and the remaining metal layer forms a landing pad electrically connected to the storage node.
[0115] Step S411, etching the exposed portion of the insulating layer along a first direction, with the height of the etching stop position being higher than the height of the storage node contact, to form an opening; wherein the first direction is the direction from the bit line structure to the bit line contact.
[0116] Here, the substrate may include a top surface at the front side and a bottom surface at the back side opposite to the front side; ignoring the flatness of the top surface and the bottom surface, the direction perpendicular to the top surface and the bottom surface of the substrate is defined as the first direction. In the direction of the top surface and the bottom surface of the substrate (i.e., the plane where the substrate is located), two second directions and a third direction that intersect each other (e.g., are perpendicular to each other) are defined. For example, the extension direction of the opening can be defined as the first direction, and the planar direction of the substrate can be determined based on the second direction and the third direction. The first direction, the second direction, and the third direction are perpendicular to each other. In the embodiment of the present application, the first direction is defined as the X-axis direction, the second direction is defined as the Y-axis direction, and the third direction is defined as the Z-axis direction.
[0117] In some embodiments, etching the exposed portion of the insulating layer may be performed by dry etching. In step S410, a portion of the insulating layer is first exposed, and in step S411, the insulating layer is further etched. This two-step etching to expose the remaining second insulating layer is beneficial to preventing the sidewall from collapsing.
[0118] Step S412: etching the remaining second insulating layer to form a first air gap and a second air gap connected to the opening.
[0119] Here, the remaining second insulating layer can be wet-etched along the X-axis direction and the Z-axis direction. The first insulating layer or the third insulating layer on both sides of the opening can play a protective role. For example, after the wet etching, the residual etching solution will be removed by pickling. Therefore, the first insulating layer or the third insulating layer on both sides of the opening can prevent the acid solution used in the pickling process from damaging the storage node contact, the bit line structure and the bit line contact, thereby reducing the impact on its conductivity.
[0120] Step S413: forming an isolation structure in the opening on the second air gap and on the surface of the landing pad.
[0121] Figure 4b to Figure 4e The schematic diagram of the semiconductor structure forming process provided in the embodiment of the present application is as follows. Figure 4b to Figure 4e The above steps S402 to S405 are further explained.
[0122] Step S404, see Figure 4b , an initial second insulating layer 105 is formed on the surface of the first insulating layer 104. After executing step S405, the following is obtained: Figure 1d The second insulating layer 105 is shown. That is, the second insulating layer 105 is located as shown in FIG. Figure 1c The gap 101a in the embodiment and the sidewall of the first insulating layer.
[0123] After executing step S406, the following is formed: Figure 1e A third insulating layer 106 is shown.
[0124] After executing step S407, the following is formed: Figure 2d Storage node contacts 108 are shown.
[0125] Here, after forming the storage node contact, step A1 may be further included: forming at least two barrier layers on the surface of the storage node contact, the bit line structure and the insulating layer. Step A1 may be implemented by steps A11 and A12, wherein:
[0126] Step A11, forming a storage node ohmic layer on the storage node contact;
[0127] Step A12: forming at least two barrier layers on the surfaces of the storage node ohmic layer, the bit line structure and the insulating layer.
[0128] See also Figure 3h , a storage node ohmic layer 113 is formed on the storage node contact 108. Figure 3i At least two barrier layers 112 are formed on the surfaces of the storage node ohmic layer 113, the bit line structure 103 and the insulating layer 109. The at least two barrier layers 112 include a first barrier layer 112a and a second barrier layer 112b formed in sequence.
[0129] After executing step S408, the following is formed: Figure 2e The insulating layer 109 shown includes the remaining first insulating layer 104 , the remaining second insulating layer 105 and the remaining third insulating layer 106 .
[0130] After executing step S409, the following is formed: Figure 3bAs shown in the metal layer 110 a , the height of the metal layer 110 a is greater than the height of the insulating layer 109 .
[0131] After executing step S410, the following is formed: Figure 3k A landing pad 110 is shown.
[0132] Step S411, see Figure 3k , the exposed part of the insulating layer 109 and the barrier layer 112 are etched along the X-axis direction, and the height of the etching stop position of the insulating layer 109 is higher than the height of the storage node ohmic layer 113 and the storage node contact 108, forming a Figure 4c Here, the etching rate of the barrier layer 112 is not greater than the etching rate of the insulating layer 109 , so as to further ensure that the storage node ohmic layer 113 and the storage node contact 108 are not exposed in the opening 114 .
[0133] Step S412, see Figure 4c , the remaining second insulating layer 105 is etched to form Figure 4d A first air gap 115 and a second air gap 116 communicating with the opening 114 are shown.
[0134] Step S413, see Figure 4d , a layer such as the following is formed in the opening 114 on the second air gap 116 and on the surface of the landing pad 110 Figure 4e An isolation structure 111 is shown.
[0135] In some embodiments, step S413 may include steps S413a and S413b.
[0136] S413a, depositing a first filling layer on the side wall of the opening, at the opening interface connected to the second air gap, and on the surface of the landing pad; wherein the first filling layer closes the opening of the second air gap to form a closed second air gap.
[0137] S413b, depositing a second filling layer on the surface of the first filling layer.
[0138] Here, the material used for the first filling layer can be the same as the material used for the second filling layer, and both can be silicon nitride. The first filling layer first seals the second air gap, and then the second filling layer fills the opening, so that the isolation structure is formed by two fillings to avoid filling defects.
[0139] The present application embodiment provides a semiconductor structure, such as Figure 3g As shown, the structure includes:
[0140] Base 100;
[0141] The substrate 100 includes spaced-apart bit line contact holes, bit line contacts 102 partially contacting the bit line contact holes, and a bit line structure 103;
[0142] An insulating layer 109 located on both side walls of the bit line contact 102 and the bit line structure 103; wherein the insulating layer 109 includes a first insulating layer 104, a second insulating layer 105 and a third insulating layer 106 stacked in sequence, and at least the insulating layer 109 on the first side wall includes the first insulating layer 104, the second insulating layer 105 and the third insulating layer 106 with decreasing heights in sequence;
[0143] a storage node contact 108 located between adjacent third insulating layers 106;
[0144] a landing pad 110 covering the storage node contact 108 and the surface of the insulating layer 109 of the first sidewall, the landing pad 110 being electrically connected to the storage node contact 108;
[0145] An isolation structure 111 is located between adjacent landing pads 110 and on the surface of the landing pad 110 .
[0146] In some embodiments, the material of the first insulating layer includes nitride, and the material of the third insulating layer is the same as that of the first insulating layer. Here, the nitride may be silicon nitride.
[0147] In some embodiments, based on Figure 3a A method for forming a semiconductor structure as shown is formed as follows Figure 3d The semiconductor structure shown. Figure 3d The insulating layer 109 of the second side wall of the two side walls includes a first insulating layer 104, a second insulating layer 105 and a third insulating layer 106, the heights of which decrease in sequence, and the material of the second insulating layer 105 includes oxide. Here, the oxide may be silicon oxide.
[0148] In some embodiments, see Figure 3g The structure further includes: at least two barrier layers 112 located between the insulating layer 109 and the bit line structure 103 and the landing pad 110 .
[0149] In some embodiments, see Figure 3j The structure further includes: a storage node ohmic layer 113 located between the storage node contact 108 and the at least two barrier layers 112 .
[0150] In some embodiments, based on Figure 4a A method for forming a semiconductor structure as shown is formed as follows Figure 4e The semiconductor structure shown. Figure 4eThe material of the first insulating layer 104 includes nitride, and the material of the third insulating layer 106 is the same as that of the first insulating layer 104; the insulating layer 109 of the second sidewall of the two sidewalls includes the first insulating layer 104, the second insulating layer 105 and the third insulating layer 106 of the same height, and the second insulating layer 105 includes an air gap 116. Here, the nitride can be silicon nitride.
[0151] The features disclosed in several method or structural embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments or structural embodiments.
[0152] The description of the semiconductor structure embodiment above is similar to the description of the method embodiment above, and has similar beneficial effects as the method embodiment. For technical details not disclosed in the semiconductor structure embodiment of the present application, please refer to the description of the method embodiment of the present application for understanding.
[0153] The above description is merely an exemplary embodiment of the present application and is not intended to limit the scope of protection of the present application. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present application shall be included in the scope of protection of the present application.
Claims
1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; forming, on the substrate, spaced-apart bit line contact holes, bit line contacts partially contacting the bit line contact holes, and a bit line structure; Forming a first insulating layer on the surface of the substrate, the bit line contact hole, the bit line contact and the bit line structure; wherein the first insulating layer does not completely fill the bit line contact hole; forming a second insulating layer on the surface of the first insulating layer located on the bit line contact surface and the surface of the bit line structure portion; forming a third insulating layer covering the first insulating layer and the second insulating layer; forming a storage node contact between adjacent third insulating layers; Etching part of the bit line structure, part of the first insulating layer, part of the second insulating layer and part of the third insulating layer, and the remaining first insulating layer, second insulating layer and third insulating layer form an insulating layer; forming a metal layer on a surface of the insulating layer contacting the storage node; Etching a portion of the metal layer to expose a portion of the insulating layer, and the remaining metal layer forms a landing pad electrically connected to the storage node; Etching the exposed portion of the insulating layer along a first direction, wherein the height of the etching stop position is higher than the height of the storage node contact, to form an opening; wherein the first direction is the direction from the bit line structure to the bit line contact; Etching the remaining second insulating layer to form a first air gap and a second air gap communicating with the opening; forming an isolation structure in the opening on the second air gap and on a surface of the landing pad; The isolation structure comprises a first filling layer and a second filling layer, and the isolation structure is formed in the opening on the second air gap and on the surface of the landing pad, comprising: Depositing a first filling layer on the side wall of the opening, the interface of the opening communicating with the second air gap, and the surface of the landing pad; wherein the first filling layer closes the opening of the second air gap to form a closed second air gap; A second filling layer is deposited on the surface of the first filling layer.
2. The method according to claim 1, characterized in that Before forming storage node contacts between adjacent third insulating layers, the method comprises: forming a fourth insulating layer on the surface of the third insulating layer; The fourth insulating layer and the third insulating layer and a portion of the substrate located on a surface of the substrate are etched to expose the substrate.
3. The method according to claim 1, characterized in that After the insulating layer is formed, the method further comprises: forming at least two barrier layers on the surfaces of the storage node contact, the bit line structure and the insulating layer; The etching of a portion of the metal layer to expose a portion of the insulating layer, and the remaining metal layer forming a landing pad electrically connected to the storage node, comprises: A portion of the metal layer and a portion of the at least two barrier layers are etched to expose a portion of the insulating layer, and the remaining metal layer forms a landing pad electrically connected to the storage node.
4. The method according to claim 3, characterized in that At least two barrier layers are formed on the surfaces of the storage node contact, the bit line structure and the insulating layer, including: forming a storage node ohmic layer on the storage node contact; At least two barrier layers are formed on the surfaces of the storage node ohmic layer, the bit line structure and the insulating layer.
5. The method according to any one of claims 1 to 4, characterized in that: The forming of a second insulating layer on the surface of the first insulating layer located on the surface of the bit line contact and the bit line structure comprises: forming an initial second insulating layer on the surface of the first insulating layer; The initial second insulating layer located on the surface of the first insulating layer on the substrate and the top surface of the bit line structure is etched, and the remaining initial second insulating layer located on the bit line contact surface and the surface of part of the bit line structure forms the second insulating layer.
6. The method according to claim 1, characterized in that The bit line structure at least comprises a diffusion barrier layer, a conductive layer and an insulating cap layer; wherein the diffusion barrier layer is located between the bit line contact and the conductive layer, and the insulating cap layer is located on the conductive layer.
7. The method according to claim 6, characterized in that The etching part of the bit line structure includes: A portion of the insulating cap layer is etched.
8. The method according to any one of claims 1 to 4, characterized in that: The material of the first insulating layer includes nitride; The material of the second insulating layer includes oxide; The material of the third insulating layer is the same as that of the first insulating layer.
9. The method according to claim 2, characterized in that: The material of the fourth insulating layer is the same as that of the third insulating layer.
10. A semiconductor structure formed by the semiconductor structure forming method according to any one of claims 1 to 9, characterized in that: include: substrate; The substrate includes spaced-apart bit line contact holes, bit line contacts partially contacting the bit line contact holes, and a bit line structure; An insulating layer located on both side walls of the bit line contact and the bit line structure; wherein the insulating layer comprises a first insulating layer, a second insulating layer and a third insulating layer stacked in sequence, and at least the insulating layer of the first side wall comprises the first insulating layer, the second insulating layer and the third insulating layer whose heights decrease in sequence; A storage node contact located between adjacent third insulating layers; a landing pad covering the storage node contact and the surface of the insulating layer of the first sidewall, the landing pad being electrically connected to the storage node contact; An isolation structure is located between adjacent landing pads and on the surface of the landing pad.
11. The structure according to claim 10, characterized in that The material of the first insulating layer includes nitride, and the material of the third insulating layer is the same as that of the first insulating layer; The insulating layer of the second side wall of the two side walls comprises a first insulating layer, a second insulating layer and a third insulating layer whose heights decrease in sequence, and a material of the second insulating layer comprises oxide.
12. The structure according to claim 10, characterized in that The material of the first insulating layer includes nitride, and the material of the third insulating layer is the same as that of the first insulating layer; the insulating layer of the second side wall of the two side walls includes a first insulating layer, a second insulating layer and a third insulating layer with the same height, and the second insulating layer includes an air gap.
13. The structure according to claim 10, characterized in that Also includes: At least two barrier layers are located between the insulating layer and the bit line structure and the landing pad.
14. The structure according to claim 13, characterized in that Also includes: A storage node ohmic layer is located between the storage node contact and the at least two barrier layers.
Citation Information
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