Semiconductor structure and method of manufacturing a semiconductor structure

Abstract

The semiconductor structure and the manufacturing method thereof provided by the embodiments of the present disclosure include: a substrate, the substrate including an array region and a peripheral region located at the periphery of the array region, the peripheral region of the substrate having an active part; a dielectric layer, the dielectric layer being located on the substrate in the peripheral region; an insulating layer, the insulating layer being located on the substrate in the array region; a plurality of spaced-apart capacitor contact structures, each capacitor contact structure penetrating the insulating layer and being in contact with the substrate; and a barrier layer, the barrier layer being located in the dielectric layer in the peripheral region, located on the side of the active part close to the array region, and arranged around the array region, the dielectric layer exposing the top surface of the barrier layer, wherein the material of the barrier layer is different from the material of the dielectric layer. The embodiments of the present disclosure are beneficial to improving the yield and performance of the semiconductor structure.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to the technical field of semiconductor technology, and particularly relate to a semiconductor structure and a manufacturing method of a semiconductor structure. BACKGROUND

[0002] A dynamic random access memory (DRAM) is composed of a plurality of memory cells, each of which includes a capacitor and a transistor. A gate of the transistor is connected with a word line, a drain of the transistor is connected with a bit line, and a source of the transistor is connected with the capacitor. The opening and closing of the transistor are controlled by a voltage signal on the word line, and then data information stored in the capacitor is read through the bit line or written into the capacitor through the bit line for storage. The capacitor is connected with a capacitor contact structure through a lower electrode thereof to form an access path with the bit line through the transistor.

[0003] However, the method for manufacturing the capacitor contact structure still needs to be improved. SUMMARY

[0004] Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method of a semiconductor structure, which are at least beneficial to improve the yield and performance of the semiconductor structure.

[0005] According to some embodiments of the present disclosure, the present disclosure provides a semiconductor structure, which includes: a substrate, the substrate including an array region and a peripheral region located at a periphery of the array region, the peripheral region of the substrate having an active part; a dielectric layer located on the substrate of the peripheral region; an insulating layer located on the substrate of the array region; a plurality of spaced capacitor contact structures, each of the capacitor contact structures penetrating the insulating layer and being in contact with the substrate; and a barrier layer located in the dielectric layer of the peripheral region, located on a side of the active part close to the array region, and arranged around the array region, the dielectric layer exposing a top surface of the barrier layer, wherein a material of the barrier layer is different from a material of the dielectric layer.

[0006] In some embodiments, the barrier layer includes: a first sub-barrier layer extending along a first direction, and in a second direction, a width of the first sub-barrier layer is greater than or equal to a width of the insulating layer between adjacent capacitor contact structures arranged along the second direction, the first direction intersecting the second direction.

[0007] In some embodiments, the barrier layer further comprises a second sub-barrier layer connected to the first sub-barrier layer and extending along the second direction, wherein along the first direction, a width of the second sub-barrier layer is greater than or equal to a width of the insulating layer between adjacent ones of the capacitive contact structures arranged along the first direction.

[0008] In some embodiments, the barrier layer is a continuous film layer around the array region.

[0009] In some embodiments, the semiconductor structure comprises a plurality of spaced-apart barrier layers, and one of the barrier layers is located further away from a periphery of the array region than another one of the barrier layers.

[0010] In some embodiments, the plurality of spaced-apart barrier layers comprises a first barrier layer, a second barrier layer, and a third barrier layer, the second barrier layer is located between the first barrier layer and the third barrier layer, and the third barrier layer is located between the insulating layer and the second barrier layer, wherein a bottom surface of the second barrier layer is lower than or flush with a bottom surface of the first barrier layer, and a bottom surface of the third barrier layer is lower than or flush with the bottom surface of the first barrier layer.

[0011] In some embodiments, the first barrier layer comprises a third sub-barrier layer extending along a first direction, the second barrier layer comprises a fourth sub-barrier layer extending along the first direction, and the third barrier layer comprises a fifth sub-barrier layer extending along the first direction, wherein along a second direction, a sum of widths of the third sub-barrier layer, the fourth sub-barrier layer, and the fifth sub-barrier layer is greater than or equal to a width of the insulating layer between adjacent ones of the capacitive contact structures arranged along the second direction, the first direction intersecting the second direction.

[0012] In some embodiments, the first barrier layer further comprises a sixth sub-barrier layer extending along a second direction, the sixth sub-barrier layer connected to the third sub-barrier layer, the second barrier layer comprises a seventh sub-barrier layer extending along the second direction, the seventh sub-barrier layer connected to the fourth sub-barrier layer, and the third barrier layer comprises an eighth sub-barrier layer extending along the second direction, the eighth sub-barrier layer connected to the fifth sub-barrier layer, wherein along the first direction, a sum of widths of the sixth sub-barrier layer, the seventh sub-barrier layer, and the eighth sub-barrier layer is greater than or equal to a width of the insulating layer between adjacent ones of the capacitive contact structures spaced apart along the first direction.

[0013] In some embodiments, the barrier layer comprises a plurality of spaced-apart sub-barrier layers to form a discontinuous film layer around the array region.

[0014] In some embodiments, the barrier layer includes a first barrier layer and a second barrier layer, the second barrier layer is located between the first barrier layer and the insulating layer, the first barrier layer includes a plurality of third sub-barrier layers extending along a first direction, the plurality of third sub-barrier layers are arranged at intervals along the first direction, the second barrier layer includes a plurality of fourth sub-barrier layers extending along the first direction, the plurality of fourth sub-barrier layers are arranged at intervals along the first direction, wherein, along a second direction, the third sub-barrier layers are arranged at intervals with the fourth sub-barrier layers.

[0015] In some embodiments, a bottom surface of the barrier layer is lower than or flush with a bottom surface of the insulating layer.

[0016] In some embodiments, a top surface of the dielectric layer between the barrier layer and the array region is lower than a top surface of the insulating layer.

[0017] In some embodiments, a material of the insulating layer is the same as a material of the barrier layer.

[0018] In some embodiments, the semiconductor structure further includes a trench structure located in the peripheral region and close to the array region, a bottom surface of the trench structure is lower than a bottom surface of the insulating layer, the barrier layer and the dielectric layer between the active part and the array region are located in the trench structure.

[0019] According to some embodiments of the present disclosure, another aspect of the present disclosure further provides a manufacturing method of a semiconductor structure, including: providing a substrate, the substrate including an array region and a peripheral region located peripherally to the array region, the peripheral region of the substrate having an active part; forming a plurality of sacrificial patterns arranged at intervals in the array region and a dielectric layer covering the substrate in the peripheral region, the dielectric layer having a first trench, the first trench being located on a side of the active part close to the array region and surrounding the array region; forming an insulating layer and a barrier layer, the insulating layer filling gaps between adjacent sacrificial patterns, the barrier layer filling the first trench, a material of the barrier layer being different from a material of the dielectric layer; removing the sacrificial patterns to obtain the insulating layer having a first via, the first via being located on the substrate opposite to the sacrificial pattern; forming a capacitor contact structure, the capacitor contact structure filling the first via.

[0020] In some embodiments, the step of forming the sacrificial pattern and the medium layer comprises: forming an initial medium layer covering the substrate; forming a mask pattern and a first mask layer, the mask pattern is arranged at intervals on the initial medium layer in the array region, and the first mask layer is on the initial medium layer in the peripheral region, and the first mask layer has a second groove, and the orthographic projection of the second groove on the substrate is located on the side of the active part close to the array region; removing the initial medium layer exposed by the mask pattern in the array region and the initial medium layer located at the position opposite to the second groove, and the remaining initial medium layer in the array region constitutes the sacrificial pattern, and the remaining initial medium layer in the peripheral region constitutes the medium layer having the first groove; and removing the mask pattern and the first mask layer.

[0021] In some embodiments, the step of removing the sacrificial pattern comprises: forming a second mask layer covering the medium layer, the barrier layer, and part of the insulating layer adjacent to the peripheral region; removing the sacrificial pattern with the second mask layer as a mask; and removing the second mask layer.

[0022] The technical solutions provided by the embodiments of the present disclosure have at least the following advantages:

[0023] The semiconductor structure provided by the embodiments of the present disclosure has a barrier layer in the medium layer on the side of the active part close to the array region, and the barrier layer can play a blocking role. In the process of forming the capacitor contact structure, a plurality of sacrificial patterns arranged at intervals and an insulating layer filling the region between adjacent sacrificial patterns are first formed on the substrate in the array region, and the sacrificial pattern is positioned at the position of the capacitor contact structure formed in the subsequent step. The subsequent step further comprises etching and removing the sacrificial pattern to obtain an insulating layer having a plurality of through holes arranged at intervals, and filling the through holes with the capacitor contact structure. In the process of etching and removing the sacrificial pattern, since the barrier layer is arranged in the medium layer on the side of the active part close to the array region, the barrier layer can protect the medium layer on the side of the active part from being eroded, and since the material of the barrier layer is different from that of the medium layer, the etching rate of the barrier layer is different from that of the medium layer, so that whether the medium layer is eroded can be determined by the etching rate, thereby reducing the possibility of erosion of the medium layer in the formed semiconductor structure, and facilitating to improve the yield and performance of the semiconductor structure. BRIEF DESCRIPTION OF DRAWINGS

[0024] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 This is a top view of a semiconductor structure provided in an embodiment of the present disclosure;

[0026] Figure 2 This is a top view of a semiconductor structure provided in an embodiment of the present disclosure;

[0027] Figure 3 for Figure 1 and Figure 2 A schematic diagram of a cross-sectional structure of a semiconductor structure along the AA1 direction is shown.

[0028] Figure 4 for Figure 1 and Figure 2 A schematic diagram of a cross-sectional structure of a semiconductor structure along the AA1 direction is shown.

[0029] Figure 5 This is a top view of a semiconductor structure provided in an embodiment of the present disclosure;

[0030] Figure 6 This is a top view of a semiconductor structure provided in an embodiment of the present disclosure;

[0031] Figure 7 for Figure 5 and Figure 6 A schematic diagram of a cross-sectional structure of a semiconductor structure along the AA1 direction is shown.

[0032] Figure 8 for Figure 5 and Figure 6 A schematic diagram of a cross-sectional structure of a semiconductor structure along the AA1 direction is shown.

[0033] Figure 9 This is a top view of a semiconductor structure provided in an embodiment of the present disclosure;

[0034] Figure 10 for Figure 9 A schematic diagram of a cross-sectional structure of a semiconductor structure along the AA1 direction is shown.

[0035] Figure 11 for Figure 9A schematic diagram of a cross-sectional structure of a semiconductor structure along the AA1 direction is shown.

[0036] Figures 12 to 16 This is a schematic cross-sectional view of each step in a method for manufacturing a semiconductor structure according to another embodiment of the present disclosure.

[0037] Figure 17 for Figure 12 A top view of a semiconductor structure is shown.

[0038] Figure 18 for Figure 16 The image shows a top view of a semiconductor structure. Detailed Implementation

[0039] As can be seen from the background technology, the current methods for manufacturing capacitor contact structures need to be improved.

[0040] Analysis revealed that the current steps for manufacturing capacitor contact structures may include: forming multiple sacrificial patterns spaced apart on a substrate of an array region and an insulating layer filling the area between adjacent sacrificial patterns; etching away the sacrificial patterns to obtain an insulating layer with multiple spaced vias; and filling the vias with a capacitor contact structure. The method for etching away the sacrificial patterns may include a wet etching process, in which an etchant reacts with the sacrificial patterns to remove them. However, the etchant may also enter the peripheral region and erode the dielectric layer of the adjacent array region in the peripheral region.

[0041] This disclosure provides a semiconductor structure in which a barrier layer is provided in the dielectric layer on the side of the active portion near the array region. The barrier layer can act as a barrier. In the process of forming the capacitor contact structure, a plurality of sacrificial patterns arranged at intervals and an insulating layer filling the area between adjacent sacrificial patterns are first formed on the substrate of the array region. The sacrificial patterns position the capacitor contact structure to be formed in subsequent steps. The subsequent steps also include etching to remove the sacrificial patterns to obtain an insulating layer with a plurality of vias arranged at intervals. The capacitor contact structure fills the vias. In the process of etching to remove the sacrificial patterns, since a barrier layer is provided in the dielectric layer on the side of the active portion near the array region, the barrier layer can protect the dielectric layer on the side of the barrier layer facing the active portion from erosion. Since the material of the barrier layer is different from that of the dielectric layer, the etching rate of the barrier layer is different from that of the dielectric layer. The etching rate can be used to confirm whether the dielectric layer is eroded, thereby improving the phenomenon of dielectric layer erosion in the formed semiconductor structure and improving the yield and performance of the semiconductor structure.

[0042] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0043] Figure 1 This is a top view of a semiconductor structure provided in an embodiment of the present disclosure. Figure 2 This is a top view of a semiconductor structure provided in an embodiment of the present disclosure. Figure 3 for Figure 1 and Figure 2 The diagram shows a cross-sectional view of a semiconductor structure along the AA1 direction. Figure 4 for Figure 1 and Figure 2 The diagram shows a cross-sectional view of a semiconductor structure along the AA1 direction. Figure 5 This is a top view of a semiconductor structure provided in an embodiment of the present disclosure. Figure 6 This is a top view of a semiconductor structure provided in an embodiment of the present disclosure. Figure 7 for Figure 5 and Figure 6 The diagram shows a cross-sectional view of a semiconductor structure along the AA1 direction. Figure 8 for Figure 5 and Figure 6 The diagram shows a cross-sectional view of a semiconductor structure along the AA1 direction. Figure 9 This is a top view of a semiconductor structure provided in an embodiment of the present disclosure. Figure 10 for Figure 9 The diagram shows a cross-sectional view of a semiconductor structure along the AA1 direction. Figure 11 for Figure 9 The diagram shows a cross-sectional view of a semiconductor structure along the AA1 direction.

[0044] refer to Figures 1 to 11The semiconductor structure can include: a substrate 100 including an array region 10 and a peripheral region 11 located at the periphery of the array region 10, the peripheral region 11 of the substrate 100 having an active part 101; a dielectric layer 102 located on the substrate 100 in the peripheral region 11; an insulating layer 103 located on the substrate 100 in the array region 10; a plurality of spaced-apart capacitor contact structures 104, each capacitor contact structure 104 penetrating the insulating layer 103 and being in contact with the substrate 100; and a barrier layer 105 located in the dielectric layer 102 in the peripheral region 11 and located on the side of the active part 101 close to the array region 10 and surrounding the array region 10, the dielectric layer 102 exposing the top surface of the barrier layer 105, wherein the material of the barrier layer 105 can be different from the material of the dielectric layer 102.

[0045] It can be understood that the specific steps of forming the capacitor contact structure 104 can include: forming a plurality of sacrificial patterns on the substrate 100 in the array region 10 and filling the insulating layer 103 in the region between adjacent sacrificial patterns, and removing the sacrificial patterns by etching to obtain an insulating layer 103 having a plurality of through holes, the capacitor contact structure 104 filling the through holes, wherein in the process of etching and removing the sacrificial patterns, the etching liquid used in etching can enter the peripheral region 11 and corrode the dielectric layer 102 in the peripheral region 11. In the related art, after the formation of the sacrificial patterns and the insulating layer 103, a mask layer covering the dielectric layer 102 is formed on the dielectric layer 102 in the peripheral region 11 before the etching and removal of the sacrificial patterns, and the mask layer also covers the plurality of sacrificial patterns arranged adjacent to the peripheral region 11 and the insulating layer 103 between the plurality of sacrificial patterns, so as to protect the dielectric layer 102 in the peripheral region 11 from corrosion in the etching and removal of the sacrificial patterns. However, due to the arrangement of the mask layer, the plurality of sacrificial patterns covered by the mask layer can not be completely removed, the effective area of the array region 10 is reduced, and the subsequent formation of the capacitor contact structure 104 is reduced, which is not conducive to the performance of the semiconductor structure formed.

[0046] The semiconductor structure provided by the embodiment is provided with the barrier layer 105 in the dielectric layer 102 close to the active part 101 on the side of the array area 10. Before the etching and removal of the sacrifice pattern, a mask layer covering the dielectric layer 102 can also be formed on the dielectric layer 102. Due to the arrangement of the barrier layer 105, the mask layer only needs to cover the insulating layer 103 between the sacrifice pattern closest to the peripheral area and the dielectric layer 102 in addition to covering the dielectric layer 102. In the etching and removal process of the sacrifice pattern, the barrier layer 105 and the mask layer can effectively protect the dielectric layer 102 on the side of the barrier layer 105 facing the active part 101 from being eroded. In addition, the material of the barrier layer 105 is different from the material of the dielectric layer 102, so that the etching rate of the barrier layer 105 is different from the etching rate of the dielectric layer 102. Whether the dielectric layer 102 is eroded can be confirmed by monitoring the etching rate. In addition, due to the arrangement of the barrier layer 105, the mask layer does not need to cover multiple sacrifice patterns and the insulating layer 103 between adjacent sacrifice patterns in the semiconductor structure provided by the embodiment. Compared with the related art, the effective area of the array area 10 is increased, the capacitor contact structure 104 is increased, and the performance and yield of the semiconductor structure are improved.

[0047] The substrate 100 can be a semiconductor substrate or a silicon-on-insulator substrate. In some embodiments, the substrate 100 can be a silicon substrate. In some embodiments, the substrate 100 can also be a germanium substrate, a silicon germanium substrate, or a silicon carbide substrate, etc.

[0048] The material of the dielectric layer 102 can be one or more of silicon oxide, silicon nitride, silicon oxynitride, and titanium nitride. The dielectric layer 102 can also cover the active part 101 in the peripheral area 11.

[0049] The material of the insulating layer 103 can be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon nitride, and titanium nitride.

[0050] The material of the barrier layer 105 can be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon nitride, and titanium nitride.

[0051] In some embodiments, the material of the insulating layer 103 can be the same as the material of the barrier layer 105. For example, the material of the insulating layer 103 can be silicon nitride, and the material of the barrier layer 105 can also be silicon nitride. In some embodiments, the material of the insulating layer 103 can also be different from the material of the barrier layer 105.

[0052] The material of the capacitor contact structure 104 can be a conductive material such as polysilicon, titanium, tantalum, ruthenium, palladium, platinum, cobalt, tungsten, etc. The plurality of capacitor contact structures 104 can be arranged in an array, for example, the plurality of capacitor contact structures 104 can include a plurality of capacitor contact structures 104 arranged at intervals along a first direction X, and the plurality of capacitor contact structures 104 can also include a plurality of capacitor contact structures 104 arranged at intervals along a second direction Y, wherein the first direction X intersects the second direction Y, in the first direction X, the insulating layer 103 between adjacent capacitor contact structures 104 arranged in the first direction X has a first width, in the second direction Y, the insulating layer 103 between adjacent capacitor contact structures 104 arranged in the second direction Y has a second width, the first width can be equal to or different from the second width, and the present disclosure does not make a specific limitation on the first width and the second width. In some embodiments, in addition to being disposed through the insulating layer 103, the bottom surface of the capacitor contact structure 104 can also be lower than the bottom surface of the insulating layer 103, so as to increase the contact area of the capacitor contact structure 104 and the substrate 100.

[0053] The semiconductor structure can further include a trench structure 106, the trench structure 106 is located in the peripheral region 11 and is disposed close to the array region 10, the bottom surface of the trench structure 106 is lower than the bottom surface of the insulating layer 103, and the blocking layer 105 and the dielectric layer 102 located between the active part 101 and the array region 10 are located in the trench structure 106.

[0054] The semiconductor structure can further include a gate 128, the gate 128 is located on the active part 101, and the dielectric layer 102 can also cover the gate 128.

[0055] It can be understood that in the step of removing the sacrificial pattern, a portion of the dielectric layer 102 located between the blocking layer 105 and the array region 10 can also be etched and removed, so that in the semiconductor structure formed, the top surface of the dielectric layer 102 located between the blocking layer 105 and the array region 10 can be lower than the top surface of the insulating layer 103.

[0056] In some embodiments, the semiconductor structure can further comprise a conductive layer 107 on the dielectric layer 102 on the side of the blocking layer 105 close to the array region 10. It can be understood that, due to the etching removal of part of the dielectric layer 102 between the blocking layer 105 and the array region 10 in the step of removing the sacrificial pattern, the material of the capacitor contact structure 104 can also fill the position of the etched-removed part of the dielectric layer 102 in the step of filling the via hole in the insulating layer 103, i.e., the conductive layer 107 is formed synchronously with the capacitor contact structure 104, so that the top surface of the conductive layer 107 is flush with the top surface of the capacitor contact structure 104, and the material of the conductive layer 107 is the same as the material of the capacitor contact structure 104, for example, the material of the capacitor contact structure 104 can be polysilicon, and the material of the conductive layer 107 can also be polysilicon. It can be understood that, in the step of removing the sacrificial pattern, the insulating layer 103 can also block the etching liquid from etching the dielectric layer 102, so that the dielectric layer 102 between the blocking layer 105 and the array region 10 can not be etched, and the semiconductor structure can not comprise the conductive layer 107, or, after the formation of the conductive layer 107, the conductive layer 107 can be removed, so that the semiconductor structure does not comprise the conductive layer 107.

[0057] It can be understood that, if the bottom surface of the blocking layer 105 is higher than the bottom surface of the insulating layer 103, in the process of etching removal of the sacrificial pattern, the etching liquid can etch part of the dielectric layer 102 at the position opposite to the blocking layer 105, and penetrate from the dielectric layer 102 at the position to the dielectric layer 102 on the side of the blocking layer 105 close to the active part 101, and then etch the dielectric layer 102 on the side of the blocking layer 105 close to the active part 101.

[0058] Reference Figure 3 In some embodiments, the bottom surface of the blocking layer 105 can be flush with the bottom surface of the insulating layer 103. In this way, the blocking layer 105 can better protect the dielectric layer 102 on the side of the blocking layer 105 close to the active part 101.

[0059] Reference Figure 4 In some embodiments, the bottom surface of the blocking layer 105 can also be lower than the bottom surface of the insulating layer 103, for example, the bottom surface of the blocking layer 105 can contact the substrate 100 in the trench structure 106. In this way, compared with the above-mentioned embodiment in which the bottom surface of the blocking layer 105 is flush with the bottom surface of the insulating layer 103, the blocking layer 105 provided in this embodiment has better protection effect to protect the dielectric layer 102 on the side of the blocking layer 105 close to the active part 101 from being etched.

[0060] Reference Figure 1 and Figure 2The barrier layer 105 can include a first sub-barrier layer 108 extending along the first direction X.

[0061] In the second direction Y, the width of the first sub-barrier layer 108 can be greater than or equal to the width of the insulating layer 103 between adjacent capacitor contact structures 104 arranged in the second direction Y. In this way, the first sub-barrier layer 108 has a better protection effect and can protect the dielectric layer 102 on the side of the first sub-barrier layer 108 facing the active part 101 from erosion.

[0062] The barrier layer 105 can further include a second sub-barrier layer 109 connected to the first sub-barrier layer 108, the second sub-barrier layer 109 extending along the second direction Y.

[0063] In the first direction X, the width of the second sub-barrier layer 109 can be greater than or equal to the width of the insulating layer 103 between adjacent capacitor contact structures 104 arranged in the second direction Y. In this way, the second sub-barrier layer 109 has a better protection effect and can protect the dielectric layer 102 on the side of the second sub-barrier layer 109 facing the active part 101 from erosion.

[0064] In some embodiments, the barrier layer 105 can be a continuous film layer around the array region 10.

[0065] Reference Figure 1 In some embodiments, the barrier layer 105 can include a first sub-barrier layer 108 and a second barrier layer 109, each barrier layer 105 can have one first sub-barrier layer 108 and one second barrier layer 109, the first sub-barrier layer 108 extending along the first direction X and connected to the second sub-barrier layer 109 at one end.

[0066] It can also be understood that the barrier layer 105 can also include a plurality of sub-barrier layers arranged at intervals to form an intermittent film layer around the array region 10.

[0067] Reference Figure 2 In some embodiments, the barrier layer 105 can include a plurality of first sub-barrier layers 108 arranged at intervals along the first direction X and a plurality of second sub-barrier layers 109 arranged at intervals along the second direction Y,

[0068] In the second direction Y, the width of the first sub-barrier layer 108 can be greater than or equal to the width of the insulating layer 103 between adjacent capacitor contact structures 104 arranged in the second direction Y, and in the first direction X, the width of the second sub-barrier layer 109 can be greater than or equal to the width of the insulating layer 103 between adjacent capacitor contact structures 104 arranged in the first direction X.

[0069] In some embodiments, the semiconductor structure can further include a plurality of barrier layers 105 arranged at intervals, and one barrier layer 105 is located away from the periphery of the array region 10 from another barrier layer 105.

[0070] Referring to Figures 5 to 8 In some embodiments, the barrier layer 105 includes a first barrier layer 110 and a second barrier layer 111, and the second barrier layer 111 is located between the first barrier layer 110 and the insulating layer 103.

[0071] The bottom surface of the first barrier layer 110 and the bottom surface of the second barrier layer 111 are lower than or flush with the bottom surface of the insulating layer 103, so as to ensure the protection effect on the dielectric layer 102 located on the side of the barrier layer 105 facing the active part 101. Referring to Figure 7 In some embodiments, the bottom surface of the first barrier layer 110 can also be flush with the bottom surface of the second barrier layer 111, for example, the bottom surface of the first barrier layer 110 and the bottom surface of the second barrier layer 111 can both be in contact with the substrate 100 located in the trench structure 106. Referring to Figure 8 In some embodiments, the bottom surface of the first barrier layer 110 can be lower than the bottom surface of the second barrier layer 111.

[0072] Referring to Figure 5 In some embodiments, the first barrier layer 110 and the second barrier layer 111 can be continuous film layers around the array region 10, the first barrier layer 110 can include a third sub-barrier layer 113 extending along the first direction X and a sixth sub-barrier layer 116 extending along the second direction Y, and the second barrier layer 111 can include a fourth sub-barrier layer 114 extending along the first direction X and a seventh sub-barrier layer 117 extending along the second direction Y.

[0073] Referring to Figure 6 In some embodiments, the first barrier layer 110 can include a plurality of third sub-barrier layers 113 extending along the first direction X, and the plurality of third sub-barrier layers 113 are arranged at intervals along the first direction X, and the second barrier layer 111 can include a plurality of fourth sub-barrier layers 114 extending along the first direction X, and the plurality of fourth sub-barrier layers 114 are arranged at intervals along the first direction X, wherein, along the second direction Y, the third sub-barrier layer 113 and the fourth sub-barrier layer 114 are arranged in a staggered manner.

[0074] The first barrier layer 110 can further include a plurality of sixth sub-barrier layers 116 extending along the second direction Y, among the plurality of third sub-barrier layers 113 and the plurality of sixth sub-barrier layers 116, the most adjacent third sub-barrier layer 113 and the most adjacent sixth sub-barrier layer 116 can be connected. The second barrier layer 111 can further include a seventh sub-barrier layer 117 extending along the second direction Y, among the plurality of fourth sub-barrier layers 114 and the plurality of seventh sub-barrier layers 117, the most adjacent fourth sub-barrier layer 114 and the most adjacent seventh sub-barrier layer 117 can be connected.

[0075] In some embodiments, among the plurality of third sub-barrier layers 113 and the plurality of sixth sub-barrier layers 116, the most adjacent third sub-barrier layer 113 and the most adjacent sixth sub-barrier layer 116 can also not be connected, and among the plurality of fourth sub-barrier layers 114 and the plurality of seventh sub-barrier layers 117, the most adjacent fourth sub-barrier layer 114 and the most adjacent seventh sub-barrier layer 117 can also not be connected.

[0076] In some embodiments, along the second direction Y, the sum of the widths of the third sub-barrier layer 113 and the fourth sub-barrier layer 114 is a third width, and the third width can be greater than or equal to the width of the insulating layer 103 between adjacent capacitor contact structures 104 arranged along the second direction Y. Along the first direction X, the sum of the widths of the sixth sub-barrier layer 116 and the seventh sub-barrier layer 117 is a fourth width, and the fourth width can be greater than or equal to the width of the insulating layer 103 between adjacent capacitor contact structures 104 arranged along the first direction X, so as to ensure that the barrier layer 105 has a better protection effect on the dielectric layer 102 located on the side of the barrier layer 105 facing the active part 101.

[0077] It can be understood that the number of barrier layers 105 in the semiconductor structure provided by the embodiments of the present disclosure can also be greater than 2, and the plurality of barrier layers 105 are arranged at intervals around the array region 10. For example, the semiconductor structure can include three barrier layers 105, and the plurality of barrier layers 105 are arranged at intervals around the array region 10.

[0078] Reference Figures 9 to 11 In some embodiments, the semiconductor structure can include a plurality of barrier layers 105 arranged at intervals, and the plurality of barrier layers 105 arranged at intervals can include a first barrier layer 110, a second barrier layer 111, and a third barrier layer 112. The second barrier layer 111 is located between the first barrier layer 110 and the third barrier layer 112, and the third barrier layer 112 is located between the insulating layer 103 and the second barrier layer 111.

[0079] Reference Figure 9In some embodiments, the first barrier layer 110 can include a third sub-barrier layer 113 extending along the first direction X, the second barrier layer 111 can include a fourth sub-barrier layer 114 extending along the first direction X, and the third barrier layer 112 can include a fifth sub-barrier layer 115 extending along the first direction X, wherein along the second direction Y, the sum of the widths of the third sub-barrier layer 113, the fourth sub-barrier layer 114, and the fifth sub-barrier layer 115 is a fifth width, and the fifth width can be greater than or equal to the width of the insulating layer 103 between adjacent capacitor contact structures 104 arranged along the second direction Y, so as to ensure that the plurality of barrier layers 105 provide better protection to the dielectric layer 102 on the side of the barrier layers 105 facing the active part 101.

[0080] In some embodiments, the first barrier layer 110 further includes a sixth sub-barrier layer 116 extending along the second direction Y, the sixth sub-barrier layer 116 being connected to the third sub-barrier layer 113, the second barrier layer 111 can include a seventh sub-barrier layer 117 extending along the second direction Y, the seventh sub-barrier layer 117 being connected to the fourth sub-barrier layer 114, and the third barrier layer 113 can include an eighth sub-barrier layer 118 extending along the second direction Y, the eighth sub-barrier layer 118 being connected to the fifth sub-barrier layer 115, wherein along the first direction X, the sum of the widths of the sixth sub-barrier layer 116, the seventh sub-barrier layer 117, and the eighth sub-barrier layer 118 is a sixth width, and the sixth width can be greater than or equal to the width of the insulating layer 103 between adjacent capacitor contact structures 104 arranged along the first direction X, so as to ensure that the plurality of barrier layers 105 provide better protection to the dielectric layer 102 on the side of the barrier layers 105 facing the active part 101.

[0081] In some embodiments, the first barrier layer 110 can include a plurality of third sub-barrier layers 113 arranged along the first direction X, a plurality of sixth sub-barrier layers 116 arranged along the second direction Y, the second barrier layer 111 can include a plurality of fourth sub-barrier layers 114 arranged along the first direction X, a plurality of seventh sub-barrier layers 117 arranged along the second direction Y, and the third barrier layer 112 can include a plurality of fifth sub-barrier layers 115 arranged along the first direction X, a plurality of eighth sub-barrier layers 118 arranged along the second direction Y, wherein along the first direction X, the third sub-barrier layers 113, the fourth sub-barrier layers 114, and the fifth sub-barrier layers 115 are arranged in a staggered manner, and along the second direction Y, the sixth sub-barrier layers 116, the seventh sub-barrier layers 117, and the eighth sub-barrier layers 118 are arranged in a staggered manner.

[0082] Reference Figure 10 In some embodiments, the bottom surface of the second barrier layer 111 can be lower than the bottom surface of the first barrier layer 110, and the bottom surface of the third barrier layer 112 can be lower than the bottom surface of the second barrier layer 111.

[0083] ReferenceFigure 11 In some embodiments, the bottom surface of the second barrier layer 111 can also be flush with the bottom surface of the first barrier layer 110, and the bottom surface of the second barrier layer 111 can also be flush with the bottom surface of the third barrier layer 112. In this embodiment, the bottom surface of the second barrier layer 111 can be lower than the bottom surface of the first barrier layer 110, and the bottom surface of the third barrier layer 112 can be lower than the bottom surface of the second barrier layer 111, which is different from the above-mentioned embodiment. In this embodiment, the protection effect of the dielectric layer 102 on the side of the barrier layer 105 facing the active region 101 is better.

[0084] It can also be understood that in the semiconductor structure provided by the embodiments of the present disclosure, the number of barrier layers 105 can also be greater than 3. For example, the semiconductor structure can include four barrier layers, and each of the four barrier layers can be a continuous film layer around the array region 10. In some embodiments, the number of barrier layers 105 in the semiconductor structure can also be 2 or greater than 3. Each barrier layer 105 can include sub-barrier layers arranged at intervals to form an intermittent film layer around the array region 10. It can also be understood that the semiconductor structure can include a plurality of barrier layers 105, and at least one of the plurality of barrier layers 105 is a continuous film layer around the array region 10.

[0085] Correspondingly, another embodiment of the present disclosure also provides a manufacturing method of a semiconductor structure. The semiconductor structure provided by the above-mentioned embodiments can be manufactured by the manufacturing method of the semiconductor structure provided by the present embodiment. The semiconductor structure provided by another embodiment of the present disclosure will be described in detail below with reference to the drawings. The same or corresponding parts of the present embodiment can refer to the corresponding description of the above-mentioned embodiments, which will not be described in detail below. Figures 12 to 16 FIG. 1 shows a cross-sectional structure of a semiconductor structure corresponding to each step of a manufacturing method of a semiconductor structure provided by another embodiment of the present disclosure, Figure 17 FIG. 2 shows a top view of a semiconductor structure, Figure 12 FIG. 3 shows a top view of a semiconductor structure. Figure 18 FIG. 4 shows a top view of a semiconductor structure. Figure 16 FIG. 5 shows a top view of a semiconductor structure.

[0086] Referring to FIG. 1, a substrate 100 is provided, which can include an array region 10 and a peripheral region 11 located at the periphery of the array region 10. The peripheral region 11 of the substrate 100 has an active region 101. Figure 13 In some embodiments, the peripheral region 11 can also be formed with a gate 128, and the gate 128 is located on the active region 101.

[0087]

[0088] ​The substrate 100 on the side close to the array region 10 of the active part 101 can also have a trench structure 106, the bottom surface of the trench structure 106 being lower than the top surface of the substrate 100 in the array region 10, so that the bottom surface of the barrier layer formed in the subsequent step can be lower than the top surface of the substrate 100 in the array region 10.

[0089] Referring to Figure 13 and Figure 17 , a plurality of sacrificial patterns 119 are formed to be arranged at intervals in the array region 10, and a dielectric layer 102 is formed to cover the substrate 100 in the peripheral region 11, the dielectric layer 102 having a first trench 120 located on the side of the active part 101 close to the array region 10 and surrounding the array region 10, wherein the sacrificial patterns 119 are used to position the capacitor contact structures formed in the subsequent step, and the first trench 120 is used to position the barrier layer formed in the subsequent step.

[0090] The dielectric layer 102 can also cover the active part 101 and the gate 128.

[0091] The plurality of sacrificial patterns 119 can have an array arrangement, for example, the plurality of sacrificial patterns 119 can include a plurality of sacrificial patterns 119 arranged at intervals along a first direction X, and the plurality of sacrificial patterns 119 can also include a plurality of sacrificial patterns 119 arranged at intervals along a second direction Y, wherein the first direction X intersects the second direction Y, so that the capacitor contact structures formed in the subsequent step can also have an array arrangement.

[0092] Referring to Figure 12 , the specific steps of forming the sacrificial patterns 119 and the dielectric layer 102 can include: forming an initial dielectric layer 121 covering the substrate 100 and the active part 101; forming a first mask layer 122 on the initial dielectric layer 121 of the peripheral region 11 and a mask pattern 123 arranged at intervals on the initial dielectric layer 121 of the array region 10, the first mask layer 122 having a second trench 124, the orthographic projection of the second trench 124 on the substrate 100 being located on the side of the active part 101 close to the array region 10.

[0093] The first mask layer 122 can be a single layer structure, and the material of the first mask layer 122 can be one of an amorphous carbon layer (ACL), silicon oxide, silicon nitride, silicon oxynitride, and titanium nitride. The material of the first mask layer 122 is different from the material of the initial dielectric layer 121. For example, the material of the first mask layer 122 can be silicon nitride, and the material of the initial dielectric layer 121 can be silicon oxide. In a subsequent step, the first mask layer 122 is used as a mask to etch and remove part of the initial dielectric layer 121. Whether the etching object is the first mask layer 122 or the initial dielectric layer 121 can be determined by the different etching rates.

[0094] In some embodiments, the first mask layer 122 can also include multiple film layers, and the materials of adjacent film layers are different. In a subsequent step, the first mask layer 122 is used as a mask to etch and remove part of the initial dielectric layer 121. The etching conditions of the first mask layer 122 and the initial dielectric layer 121 can be monitored by the different etching rates.

[0095] For example, the first mask layer 122 can include a first mask, a second mask, a third mask, and a fourth mask stacked in sequence on the initial dielectric layer 121.

[0096] For example, the material of the first mask can be one of an amorphous carbon layer (ACL), silicon oxide, silicon nitride, silicon oxynitride, and titanium nitride. The material of the second mask can be one of an amorphous carbon layer (ACL), silicon oxide, silicon nitride, silicon oxynitride, and titanium nitride. The material of the third mask can be one of an amorphous carbon layer (ACL), silicon oxide, silicon nitride, silicon oxynitride, and titanium nitride. The material of the fourth mask can be one of an amorphous carbon layer (ACL), silicon oxide, silicon nitride, silicon oxynitride, and titanium nitride. For example, the material of the first mask can be an amorphous carbon layer (ACL), the material of the second mask can be silicon nitride, the material of the third mask can be an amorphous carbon layer (ACL), and the material of the fourth mask can be silicon oxynitride.

[0097] In some embodiments, the second trench 124 surrounds the array region 10, and the second trench 124 can have a first sub-trench 129 extending along the first direction X and a second sub-trench 130 extending along the second direction Y. The position of the capacitive contact structure formed in a subsequent step is related to the second trench 124. The capacitive contact structure can also have a portion extending along the first direction X and a portion extending along the second direction Y.

[0098] The material of the mask pattern 123 can be one or more of an amorphous carbon layer (ACL), silicon oxide, silicon nitride, silicon oxynitride, and titanium nitride.

[0099] In some embodiments, the mask pattern 123 and the first mask layer 122 can be formed in the same step, and the material of the mask pattern 123 can be the same as the material of the first mask layer 122. In some embodiments, the mask pattern 123 and the first mask layer 122 can also be formed in different steps.

[0100] Referring to Figure 13 , the step of forming the sacrificial pattern 119 and the dielectric layer 102 can further include removing the portion of the initial dielectric layer 121 exposed by the mask pattern 123 in the array region 10, the portion of the initial dielectric layer 121 located opposite the second trench 124, and the remaining portion of the initial dielectric layer 121 in the array region 10 to form the sacrificial pattern 119, and the remaining portion of the initial dielectric layer 121 in the peripheral region 11 to form the dielectric layer 102 with the first trench 120, with the first mask layer 122 and the mask pattern 123 as masks.

[0101] After the formation of the sacrificial pattern 119 and the dielectric layer 102, the first mask layer 122 and the mask pattern 123 can also be removed.

[0102] Referring to Figure 14 , the insulating layer 103 and the barrier layer 105 are formed, the insulating layer 103 fills the gap between adjacent sacrificial patterns 119, and the barrier layer 105 fills the first trench 120.

[0103] In some embodiments, the material of the barrier layer 105 can be different from the material of the dielectric layer 102, so that the etching rate of the barrier layer 105 is different from the etching rate of the dielectric layer 102, and in the subsequent step of etching and removing the sacrificial pattern 119, the etching rate can be monitored to confirm whether the dielectric layer 102 is eroded.

[0104] The subsequent step can further include removing the sacrificial pattern 119 to obtain the insulating layer 103 with the first via, the first via being located on the substrate 100 opposite the sacrificial pattern 119, and the sacrificial pattern 119 being used to position the position of the subsequently formed capacitor contact structure, i.e., the subsequently formed capacitor contact structure being located in the first via.

[0105] Referring to Figure 14 and Figure 15 , the specific steps of removing the sacrificial pattern 119 can include: forming a second mask layer 126, the second mask layer 126 covering the dielectric layer 102, the barrier layer 105, and a portion of the insulating layer 103 adjacent to the peripheral region 11, wherein the second mask layer 126 can be a photoresist layer; removing the sacrificial pattern 119 with the second mask layer 126 as a mask to obtain the insulating layer 103 with the first via 125; and removing the second mask layer 126.

[0106] Since the portion of the dielectric layer 102 on the side of the blocking layer 105 close to the array region 10 is not protected by the blocking layer 105, in the step of removing the sacrificial pattern 119, the portion of the dielectric layer 102 on the side of the blocking layer 105 close to the array region 10 can also be removed. It can be understood that the insulating layer 103 can also block the etching liquid from etching the dielectric layer 102, and thus the portion of the dielectric layer 102 on the side of the blocking layer 105 close to the array region 10 can also not be etched in the step of removing the sacrificial pattern 119.

[0107] In the step of removing the sacrificial pattern 119, the portion of the substrate 100 on the side of the blocking layer 105 close to the array region 10 can also be etched to increase the contact area between the capacitor contact structure and the substrate 100 in the subsequent step.

[0108] Referring to Figure 16 and Figure 18 , the capacitor contact structure 104 is formed to fill the first via 125.

[0109] Since the portion of the dielectric layer 102 on the side of the blocking layer 105 close to the array region 10 can also be removed in the step of removing the sacrificial pattern 119, the material used to form the capacitor contact structure 104 can also fill the position of the removed dielectric layer 102 in the step of forming the capacitor contact structure 104. The material filling the position of the removed dielectric layer 102 forms a conductive layer 107 on the dielectric layer 102 on the side of the blocking layer 105 close to the array region 10, and the top surface of the conductive layer 107 can be flush with the top surface of the capacitor contact structure 104. In some embodiments, after the conductive layer 107 is formed, the conductive layer 107 can also be removed, and the position of the conductive layer 107 can be filled with the material of the dielectric layer 102.

[0110] The manufacturing method of the semiconductor structure provided by the above embodiments forms the blocking layer 105 in the dielectric layer 102 on the side of the active part 101 close to the array region 10 and forms the second mask layer 126 covering the blocking layer 105 and the dielectric layer 102 before removing the sacrifice pattern 119, and the second mask layer 126 also covers the part of the insulating layer 103 between the sacrifice pattern 119 closest to the peripheral region 11 and the peripheral region 11, so that in the step of removing the sacrifice pattern 119, the second mask layer 126 can prevent the etching liquid from eroding the dielectric layer 102 from the top surface of the dielectric layer 102, and the blocking layer 105 can protect the dielectric layer 102 on the side of the blocking layer 105 toward the active part 101 from erosion, thereby facilitating to improve the performance and yield of the formed semiconductor structure. It can also be understood that in the related art, the second mask layer 126 covering the dielectric layer 102 is formed before removing the sacrifice pattern 119, and the second mask layer 126 also covers the plurality of sacrifice patterns 119 arranged adjacent to the peripheral region 11 and the insulating layer 103 between the plurality of sacrifice patterns 119, so as to ensure that the dielectric layer 102 is not eroded in the step of removing the sacrifice pattern 119. However, due to the arrangement of the second mask layer 126, the plurality of sacrifice patterns 119 covered by the second mask layer 126 cannot be completely removed, thereby reducing the effective area of the array region 10, and thereby reducing the capacitance contact structure 104 formed subsequently, which is not conducive to the performance of the formed semiconductor structure. Compared with the related art, the manufacturing method of the semiconductor structure provided by the above disclosed embodiments does not need to cover the plurality of sacrifice patterns 119 by the second mask layer 126, so that the effective area of the array region 10 will not be reduced, and the capacitance contact structure 104 is increased, which is conducive to improving the performance and yield of the semiconductor structure.

[0111] Those skilled in the art can understand that the above embodiments are specific embodiments for implementing the present disclosure, and in actual applications, various changes can be made in form and details without departing from the spirit and scope of the present disclosure. Any person skilled in the art can make various modifications and changes without departing from the spirit and scope of the present disclosure, and therefore the protection scope of the present disclosure should be limited by the scope defined by the claims.

Claims

1. A semiconductor structure, comprising: a substrate comprising an array region and a peripheral region located peripherally to the array region, the peripheral region of the substrate having an active portion; a dielectric layer located on the substrate in the peripheral region; an insulating layer located on the substrate in the array region; a plurality of spaced-apart capacitor contact structures, each of the capacitor contact structures penetrating the insulating layer and contacting the substrate; a barrier layer located in the dielectric layer in the peripheral region, located on a side of the active portion proximate to the array region, and disposed around the array region, the dielectric layer exposing a top surface of the barrier layer, wherein the barrier layer is of a different material than the dielectric layer; the semiconductor structure comprising a plurality of spaced-apart barrier layers, with one barrier layer located peripherally to another barrier layer away from the array region; the plurality of spaced-apart barrier layers comprising a first barrier layer, a second barrier layer located between the first barrier layer and a third barrier layer, and the third barrier layer located between the insulating layer and the second barrier layer, wherein a bottom surface of the second barrier layer is lower than or flush with a bottom surface of the first barrier layer, and a bottom surface of the third barrier layer is lower than or flush with the bottom surface of the first barrier layer. 2.The semiconductor structure of claim 1, wherein: the barrier layer comprises: a first sub-barrier layer extending in a first direction, and in a second direction, a width of the first sub-barrier layer is greater than or equal to a width of the insulating layer between adjacent capacitor contact structures arranged in the second direction, the first direction intersecting the second direction. 3.The semiconductor structure of claim 2, wherein: the barrier layer further comprises: a second sub-barrier layer connected to the first sub-barrier layer and extending in the second direction, and in the first direction, a width of the second sub-barrier layer is greater than or equal to a width of the insulating layer between adjacent capacitor contact structures arranged in the first direction. 4.The semiconductor structure of any one of claims 1 to 3, wherein: the barrier layer is a continuous film layer around the array region. 5.The semiconductor structure of claim 1, wherein: the first barrier layer comprises a third sub-barrier layer extending in a first direction, the second barrier layer comprises a fourth sub-barrier layer extending in the first direction, and the third barrier layer comprises a fifth sub-barrier layer extending in the first direction, and in a second direction, a sum of widths of the third sub-barrier layer, the fourth sub-barrier layer, and the fifth sub-barrier layer is greater than or equal to a width of the insulating layer between adjacent capacitor contact structures arranged in the second direction, the first direction intersecting the second direction. 6.The semiconductor structure of claim 5, wherein: ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ The first barrier layer further comprises a sixth sub-barrier layer extending along the second direction, the sixth sub-barrier layer being connected with the third sub-barrier layer, the second barrier layer comprises a seventh sub-barrier layer extending along the second direction, the seventh sub-barrier layer being connected with the fourth sub-barrier layer, and the third barrier layer comprises an eighth sub-barrier layer extending along the second direction, the eighth sub-barrier layer being connected with the fifth sub-barrier layer, wherein, along the first direction, the sum of the widths of the sixth sub-barrier layer, the seventh sub-barrier layer and the eighth sub-barrier layer is greater than or equal to the width of the insulating layer between adjacent capacitor contact structures arranged along the first direction.

7. The semiconductor structure of claim 1, wherein, The barrier layer comprises a first barrier layer and a second barrier layer, the second barrier layer being located between the first barrier layer and the insulating layer, the first barrier layer comprises a plurality of third sub-barrier layers extending along a first direction, the plurality of third sub-barrier layers being arranged at intervals along the first direction, and the second barrier layer comprises a plurality of fourth sub-barrier layers extending along the first direction, the plurality of fourth sub-barrier layers being arranged at intervals along the first direction, wherein, along a second direction, the third sub-barrier layers and the fourth sub-barrier layers are arranged in a staggered manner.

8. The semiconductor structure of claim 1, wherein, The bottom surface of the barrier layer is lower than or flush with the bottom surface of the insulating layer.

9. The semiconductor structure of claim 1, wherein, The top surface of the dielectric layer between the barrier layer and the array region is lower than the top surface of the insulating layer.

10. The semiconductor structure of claim 1, wherein, The material of the insulating layer is the same as the material of the barrier layer.

11. The semiconductor structure of claim 1, further comprising: a trench structure located in the peripheral region and close to the array region, the bottom surface of the trench structure being lower than the bottom surface of the insulating layer, and the barrier layer and the dielectric layer between the active part and the array region being located in the trench structure.

12. A semiconductor structure, comprising: a substrate comprising an array region and a peripheral region located peripherally of the array region, the peripheral region of the substrate having an active part; a dielectric layer located on the substrate of the peripheral region; an insulating layer located on the substrate of the array region; a plurality of capacitor contact structures arranged at intervals, each of the capacitor contact structures penetrating the insulating layer and being in contact with the substrate; a barrier layer located in the dielectric layer of the peripheral region and located on the side of the active part close to the array region, the barrier layer being arranged around the array region, and the dielectric layer exposing the top surface of the barrier layer, wherein the material of the barrier layer is different from the material of the dielectric layer; the barrier layer comprises a plurality of sub-barrier layers arranged at intervals to form an interrupted film layer around the array region.

13. A manufacturing method of a semiconductor structure, comprising: ​ ​ ​ A substrate is provided, which includes an array region and a peripheral region located peripherally of the array region, the peripheral region of the substrate having an active portion; a plurality of sacrificial patterns are formed to be spaced apart from the array region, and a dielectric layer is formed to cover the substrate in the peripheral region, the dielectric layer having a first trench located at a side of the active portion close to the array region and arranged to surround the array region; an insulating layer is formed to fill gaps between adjacent ones of the sacrificial patterns, and a barrier layer is formed to fill the first trench, the barrier layer being made of a material different from that of the dielectric layer; the sacrificial patterns are removed to obtain the insulating layer having first vias formed on the substrate opposite to the sacrificial patterns; a capacitive contact structure is formed to fill the first vias; wherein the step of removing the sacrificial patterns comprises: a second mask layer is formed to cover the dielectric layer, the barrier layer, and a portion of the insulating layer adjacent to the peripheral region; the sacrificial patterns are removed with the second mask layer as a mask; the second mask layer is removed.

14. The method of claim 13, wherein the steps of forming the sacrificial patterns and the dielectric layer comprise: an initial dielectric layer is formed to cover the substrate; a mask pattern is formed to be spaced apart on the initial dielectric layer in the array region, and a first mask layer is formed on the initial dielectric layer in the peripheral region, the first mask layer having a second trench whose orthographic projection on the substrate is located at the side of the active portion close to the array region; the initial dielectric layer is removed with the mask pattern and the first mask layer as masks, the initial dielectric layer exposed by the mask pattern in the array region, and the initial dielectric layer located opposite to the second trench being removed, the initial dielectric layer remaining in the array region constituting the sacrificial patterns, and the initial dielectric layer remaining in the peripheral region constituting the dielectric layer having the first trench; the mask pattern and the first mask layer are removed.

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