Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same, comprising: providing a substrate, the substrate comprising a first region, a second region, and a third region, the first region, the second region, and the third region having a first oxide layer on their surfaces; forming a mask material layer on the surface of the first oxide layer; performing a first patterning step on the mask material layer to reduce the thickness of the mask material layer in the second region and the third region to form an initial mask layer; performing a second patterning step on the initial mask layer to form a mask layer having a mask opening therein; etching the first oxide layer using the mask layer as a mask to form a tunneling layer opening; and forming a tunneling layer within the tunneling layer opening, wherein the thickness of the tunneling layer is less than the depth of the tunneling layer opening. The formation method can improve the integration density and performance of the resulting semiconductor structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] In the current semiconductor industry, integrated circuit products can be mainly divided into three types: logic, memory and analog circuits, among which memory devices account for a considerable proportion of integrated circuit products.

[0003] With the development of storage technology, various types of semiconductor memories have emerged, such as static random access memory (SRAM), dynamic random access memory (DRAM), erasable programmable read-only memory (EPROM), flash memory, and so on.

[0004] However, the integration and performance of the EPROM memory in the prior art still need to be improved. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure and a semiconductor structure, so as to improve the integration and performance of the semiconductor structure.

[0006] To solve the above technical problems, the technical solution of the present invention provides a semiconductor structure, comprising: a substrate, the substrate comprising a first region, a second region, and a third region adjacent to each other and arranged along a first direction, the surfaces of the first region and the third region having a first oxide layer, the first oxide layer having a tunneling layer opening therein, the bottom of the tunneling layer opening exposing the surface of the second region, and in the first direction, the width of the tunneling layer opening is less than a preset width; a tunneling layer located in the tunneling layer opening, and the thickness of the tunneling layer is less than the depth of the tunneling layer opening.

[0007] Optionally, the preset width is 0.2 microns.

[0008] Optionally, the first oxide layer is a high-voltage oxide layer, and the tunneling layer is a low-voltage oxide layer.

[0009] Optionally, in the first direction, the total width of the first region and the second region is greater than 0.4 micrometers, and the total width of the second region and the third region is greater than 0.4 micrometers.

[0010] Optionally, the thickness of the first oxide layer is less than 200 angstroms, and the thickness of the tunneling layer is less than 80 angstroms.

[0011] Optionally, the substrate further includes a plurality of active regions and a plurality of isolation regions alternately arranged along a second direction, the second direction being perpendicular to the first direction, and in the second direction, the first region, the second region and the third region all penetrate the plurality of active regions and the plurality of isolation regions, the first oxide layer is also located on the surface of the active region, and an isolation structure is provided in and on the isolation region, and the surface of the isolation structure is higher than the surface of the first oxide layer.

[0012] Optionally, it further includes: a floating gate located on the surface of the connected first oxide layer and tunneling layer, the floating gate spanning across several active areas and several isolation areas along the second direction; and a control gate located on the surface of the floating gate.

[0013] Correspondingly, the technical solution of the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a first region, a second region and a third region adjacent to each other and arranged along a first direction, the surfaces of the first region, the second region and the third region having a first oxide layer; forming a mask material layer on the surface of the first oxide layer; performing a first patterning step on the mask material layer to thin the thickness of the mask material layer in the second region and the third region in a direction perpendicular to the substrate surface to form an initial mask layer; performing a second patterning step on the initial mask layer to form a mask layer, the mask layer having a mask opening, the bottom of the mask opening exposing the surface of the first oxide layer on the second region; etching the first oxide layer using the mask layer as a mask to form a tunneling layer opening in the first oxide layer, the bottom of the tunneling layer opening exposing the surface of the second region; forming a tunneling layer in the tunneling layer opening, and the thickness of the tunneling layer is less than the depth of the tunneling layer opening.

[0014] Optionally, the method for performing a first patterning step on the mask material layer includes: forming a first photoresist layer on the first area, the first photoresist layer exposing the mask material layer on the second area and the third area; etching the mask material layer using the first photoresist layer as a mask to thin the mask material layer in the second area and the third area.

[0015] Optionally, the process of etching the mask material layer using the first photoresist layer as a mask includes an anisotropic dry etching process.

[0016] Optionally, the method further includes: removing the first photoresist layer after forming the initial mask layer.

[0017] Optionally, the method of performing a second patterning step on the initial mask layer includes: after removing the first photoresist layer, forming a second photoresist layer on the third area, the second photoresist layer exposing the initial mask layer on the first area and the second area; etching the initial mask layer using the second photoresist layer as a mask until the surface of the first oxide layer in the second area is exposed to form the mask layer.

[0018] Optionally, the process of etching the initial mask layer using the second photoresist layer as a mask includes an anisotropic dry etching process, or a dry etching process and a wet etching process.

[0019] Optionally, the process of etching the first oxide layer using the mask layer as a mask includes a wet etching process.

[0020] Optionally, in the wet etching process of etching the first oxide layer using the mask layer as a mask, an etching selectivity ratio of the materials of the first oxide layer and the mask layer is greater than 5:1.

[0021] Optionally, the material of the mask layer includes a dielectric material, and the material of the mask layer is different from the material of the first oxide layer.

[0022] Optionally, the material of the first oxide layer includes silicon oxide, and the material of the mask layer includes silicon oxynitride.

[0023] Optionally, the material of the tunneling layer includes silicon oxide.

[0024] Optionally, the thickness of the mask material layer is less than 600 angstroms, and the depth of the mask opening ranges from 200 angstroms to 300 angstroms.

[0025] Optionally, in the first direction, the width of the tunnel layer opening is less than 0.2 microns.

[0026] Optionally, in the first direction, the total width of the first region and the second region is greater than 0.4 micrometers, and the total width of the second region and the third region is greater than 0.4 micrometers.

[0027] Optionally, the substrate further includes a plurality of active regions and a plurality of isolation regions alternately arranged along a second direction, the second direction being perpendicular to the first direction, and in the second direction, the first region, the second region and the third region all penetrate the plurality of active regions and the plurality of isolation regions, the first oxide layer is also located on the surface of the active region, an isolation structure is provided in and on the isolation region, and the surface of the isolation structure is higher than the surface of the first oxide layer, and the mask material layer is also located on the surface of the isolation structure.

[0028] Optionally, the method further includes: after forming the tunneling layer, forming a floating gate on the surface of the connected first oxide layer and the tunneling layer, wherein the floating gate spans across several of the active areas and several of the isolation areas along the second direction; and forming a control gate on the floating gate.

[0029] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0030] In the method for forming a semiconductor structure provided by the technical solution of the present invention, a first patterning step is performed on the mask material layer to reduce the thickness of the mask material layer in the second and third regions to form an initial mask layer, and a second patterning step is performed on the initial mask layer to form a mask layer having a mask opening. By transferring the pattern of the mask opening in two patterning steps, it is possible to form a mask opening with a smaller critical dimension while ensuring that the critical dimension of the photolithography layer formed in each patterning step is much larger than the limit dimension of the photolithography process, thereby improving the morphology of the photolithography layer and, in turn, the pattern morphology of the mask opening. As a result, the tunneling layer opening formed by transferring the pattern of the mask opening to the first oxide layer achieves both a smaller critical dimension and a better morphology, thereby forming a small-sized tunneling layer with a better morphology, thereby improving the integration and performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figures 1 to 3 It is a structural schematic diagram of each step in a method for forming a semiconductor structure;

[0032] Figure 4 yes Figure 3 Measured three-dimensional structure diagram of the middle area D;

[0033] Figures 5 to 13 It is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0034] As described in the background art, the integration and performance of the EPROM memory in the prior art are relatively poor.

[0035] Figures 1 to 3 It is a structural schematic diagram of each step in a method for forming a semiconductor structure. Figure 4 yes Figure 3 Measured three-dimensional structure diagram of the middle area D.

[0036] Please refer to Figure 1 and Figure 2 , Figure 1 yes Figure 2 Schematic diagram of the top view of the structure, Figure 2 yes Figure 1 A schematic cross-sectional structure diagram along direction A1-A2 is provided, wherein a substrate 100 is provided, wherein the substrate 100 includes a tunneling layer region A arranged along a first direction X, and adjacent regions B on both sides of the tunneling layer region A. The substrate 100 also includes active regions S and isolation regions OX alternately arranged along a second direction Y, wherein the first direction X and the second direction Y are perpendicular to each other.

[0037] The tunneling layer region A and the adjacent region B penetrate the active region S and the isolation region OX. The tunneling layer region A is used to form a tunneling layer.

[0038] An isolation structure 110 is provided in the isolation region OX, and an oxide layer 120 is provided on the surface of the substrate 100 of the active region S. Moreover, the surface of the isolation structure 110 is higher than the surface of the oxide layer 120 to improve the isolation reliability of the isolation structure 110 for the active regions S on both sides of the isolation region OX.

[0039] Please refer to Figure 3 , Figure 3 and Figure 2 In the same viewing direction, a photoresist layer 130 is formed on the surface of the isolation structure 110 and the oxide layer 120. A mask opening 131 is provided in the photoresist layer 130. The bottom of the mask opening 131 exposes the tunneling layer region A.

[0040] Next, the oxide layer 120 is etched using the photoresist layer 130 as a mask until the surface of the active region S is exposed, forming a tunnel opening (not shown) in the oxide layer 120 to provide a reserved space for the subsequent formation of a tunnel layer.

[0041] However, in the above method, on the one hand, the surfaces of the isolation structure 110 and the oxide layer 120 are uneven and have a large height difference (such as Figure 4 As shown in the region E in FIG), on the other hand, with the improvement of the requirements for the integration of semiconductor structures, in order to form a tunneling layer with a smaller critical dimension, the critical dimension AW of the mask opening 131 (as shown in FIG) Figure 3 As shown in FIG, the thickness of the mask opening 131 is close to the limit of the photolithography process, resulting in a poor morphology of the mask opening 131. As a result, not only can a tunnel opening that reaches the target critical dimension fail to be formed, but the critical dimension of the tunnel layer also fails to reach the target dimension, resulting in poor integration of the semiconductor structure. At the same time, the sidewall morphology of the formed tunnel opening is also poor, resulting in poor performance of the tunnel layer and, in turn, poor performance of the semiconductor structure.

[0042] Specifically, the sidewall surface of the mask opening 131 is raised along with the isolation structure 110 (eg, Figure 4 As shown in the region F in FIG), and the sidewall of the mask opening 131 is relatively inclined or even tilted (as shown in FIG. Figure 5 As shown in region J in the middle, when etching oxide layer 120 using mask layer 130 as a mask, not only is the transferred pattern morphology poor, but oxide layer 120 in adjacent region B is also easily etched, causing the critical dimension of the formed tunnel opening to be larger than the target critical dimension, preventing the critical dimension of the tunnel layer from reaching the target dimension. As a result, the semiconductor structure suffers from poor integration and performance.

[0043] To address the aforementioned technical issues, the present invention provides a semiconductor structure and a method for forming the same. By performing two patterning steps on a mask material layer, a mask opening with well-defined sidewall morphology is formed in the mask material layer above the second region. Consequently, the tunneling layer opening formed in the first oxide layer can achieve both a small critical dimension and good morphology. This allows for the formation of a small, well-defined tunneling layer, thereby improving the integration and performance of the semiconductor structure.

[0044] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0045] Figures 5 to 13 It is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure according to an embodiment of the present invention.

[0046] Please refer to Figure 5 and Figure 6 , Figure 5 yes Figure 6 Schematic diagram of the top view of the structure, Figure 6 yes Figure 5 A schematic cross-sectional structure diagram along the direction X1-X2 is provided, wherein a substrate 200 is provided.

[0047] In this embodiment, the substrate 200 is made of a semiconductor material. Specifically, the substrate 200 is made of silicon.

[0048] In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multinary semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI), etc. Among them, the multinary semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP, etc.

[0049] In this embodiment, the substrate 200 includes a first region I, a second region II, and a third region III that are adjacent to each other and arranged along a first direction X.

[0050] In this embodiment, in the first direction X, the total width W1 of the first region I and the second region II is greater than 0.4 micrometers, and the total width W2 of the second region II and the third region III is greater than 0.4 micrometers.

[0051] Since the total width W1 of the first region I and the second region II is greater than 0.4 microns, and the total width W2 of the second region II and the third region III is greater than 0.4 microns, the total width W1 and the total width W2 are both larger than the limit size of the photolithography process. Therefore, in the subsequent two patterning steps, the first photolithography layer and the second photolithography layer with good morphology that are less affected by the size limit of the photolithography process can be formed to form a tunneling layer opening with a good morphology and a width of less than 0.2 microns.

[0052] A first oxide layer 201 is formed on the surfaces of the first region I, the second region II and the third region III.

[0053] The first oxide layer 201 has a thickness d1 along a direction perpendicular to the surface of the substrate 200 .

[0054] Preferably, the thickness d1 is less than 200 angstroms.

[0055] The material of the first oxide layer 201 includes oxide.

[0056] Specifically, the material of the first oxide layer 201 includes silicon oxide.

[0057] In this embodiment, the substrate 200 further includes a plurality of active regions S1 and a plurality of isolation regions S2 alternately arranged along a second direction Y. The first direction X and the second direction Y are perpendicular to each other.

[0058] In the second direction Y, the first region I, the second region II, and the third region III all penetrate a plurality of active regions S1 and a plurality of isolation regions S2.

[0059] Specifically, the first oxide layer 201 is located on the surface of the active area S1.

[0060] In this embodiment, an isolation structure 202 is defined in the isolation region S2 .

[0061] The surface of the isolation structure 202 is higher than or flush with the surface of the first oxide layer 201 .

[0062] Preferably, the surface of the isolation structure 202 is higher than the surface of the first oxide layer 201 , so as to better isolate the adjacent active area S1 .

[0063] The isolation structure 202 is made of a dielectric material, which includes at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbon oxynitride.

[0064] In this embodiment, the method for forming the isolation structure 202 includes: providing an initial substrate (not shown); forming an isolation structure mask layer (not shown) on the surface of the initial substrate, the isolation structure mask layer exposing the initial substrate surface of the isolation region S2; using the isolation structure mask layer as a mask, etching the initial substrate to form an isolation opening (not shown) in the isolation region S2; and forming the isolation structure 202 in the isolation opening.

[0065] In this embodiment, the isolation structure 202 extends upward out of the isolation opening so that the surface of the isolation structure 202 is higher than the initial substrate surface. Thus, the isolation structure 202 is not only located in the isolation region S2 but also located on the isolation region S2.

[0066] In this embodiment, the method of forming the first oxide layer 201 includes: after forming the isolation structure 202 , performing an oxidation process on the initial substrate of the active region S1 to form the first oxide layer 201 with a thickness d1 , and forming the substrate 200 .

[0067] Please refer to Figure 7 , Figure 7 and Figure 6 A mask material layer 210 is formed on the surface of the first oxide layer 201 and the surface of the isolation structure 202 in the same viewing direction.

[0068] The mask material layer 210 provides material for subsequently forming an initial mask layer, so as to realize the formation of the mask layer.

[0069] The mask material layer 210 is made of a different material from the first oxide layer 201 , so that in the subsequent etching process for forming the tunnel opening, a larger etching selectivity ratio can be achieved between the material of the first oxide layer 201 and the material of the mask layer.

[0070] The mask material layer 210 is made of a dielectric material, which includes at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbon oxynitride.

[0071] In this embodiment, silicon oxynitride is used as the material of the mask material layer 210 so as to achieve a larger etching selectivity ratio between the material of the first oxide layer 201 and the material of the mask layer in the subsequent etching process for forming the tunnel opening.

[0072] In this embodiment, the process for forming the mask material layer 210 includes a deposition process. Preferably, a chemical vapor deposition process is used as the deposition process for forming the mask material layer 210 .

[0073] In this embodiment, the thickness d2 of the mask material layer 210 (eg Figure 7As shown) is greater than 300 angstroms, and the thickness d2 of the mask material layer 210 is less than 600 angstroms.

[0074] If the thickness d2 of the mask material layer 210 is too small, then when the mask material layer 210 is subsequently patterned for the first time, on the one hand, the mask layer formed subsequently may be too thin, resulting in the mask layer being easily completely consumed when the tunnel opening is subsequently formed. This can cause the etching process for forming the tunnel opening to damage the surface of the first oxide layer 201 in the first region I and the third region III, thereby affecting device performance. On the other hand, it also increases the risk of etching through the mask material layer 210 in the second region II and the third region III in a direction perpendicular to the surface of the substrate 200, resulting in the inability to subsequently form a mask layer with a mask opening through two patterning steps. If the thickness d2 of the mask material layer 210 is too large, not only will the etching time for forming the mask opening be increased, resulting in poor process efficiency, but the aspect ratio of the mask opening formed will also be too large, increasing the difficulty of etching the tunnel opening. Therefore, by selecting an appropriate thickness d2 of the mask material layer 210, namely, when the thickness d2 is greater than 300 angstroms and less than or equal to 600 angstroms, a mask opening with a suitable aspect ratio can be formed with high process efficiency, while also reducing the difficulty of forming the tunneling opening. Furthermore, the risk of failure in the double patterning steps can be reduced, and the impact of the double patterning steps on device performance can be minimized or avoided.

[0075] Next, the mask material layer 210 is subjected to a first patterning step, in which the thickness d2 of the mask material layer 210 in the second region II and the third region III is reduced in a direction perpendicular to the surface of the substrate 200 to form an initial mask layer. For the specific process of the first patterning step of the mask material layer 210, please refer to Figures 8 and 9 .

[0076] Please refer to Figure 8 , Figure 8 and Figure 7 In the same viewing direction, a first photoresist layer 220 is formed on the first region I, and the first photoresist layer 220 exposes the mask material layer 210 on the second region II and the third region III.

[0077] In this embodiment, the method for forming the first photoresist layer 220 includes: forming a first photoresist material layer (not shown) on the surface of the mask material layer 210; performing a photolithography process (exposure, development, etc.) on the first photoresist material layer to form the first photoresist layer 220.

[0078] Since the first photolithography layer 220 exposes the mask material layer 210 of the second region II and the third region III, the critical dimension of the first photolithography layer 220 is relatively large. Therefore, the critical dimension of the formed first photolithography layer 220 can be much larger than the limit dimension of the photolithography process, so that the sidewall morphology of the first photolithography layer 220 is better.

[0079] It should be understood that since the first photoresist layer 220 exposes the mask material layer 210 of the second region II and the third region III, the critical dimension of the first photoresist layer 220 is equal to or greater than the total width W2 of the second region II and the third region III.

[0080] In this embodiment, the material of the first photoresist layer 220 includes photoresist.

[0081] Please refer to Figure 9 , Figure 9 and Figure 8 The mask material layer 210 is etched using the first photoresist layer 220 as a mask, and the mask material layer 210 in the second region II and the third region III is thinned to form an initial mask layer 211.

[0082] Since the first photoresist layer 220 has a good sidewall morphology, the initial mask layer 211 formed has a good sidewall morphology at the step where the first region I and the second region II are adjacent.

[0083] The purpose of thinning the mask material layer 210 in the second region II and the third region III is to create a height difference between the initial mask layer 211 in the first region I and the initial mask layer 211 in the second region II and the third region III in a direction perpendicular to the surface of the substrate 200. This allows the formation of mask openings through a subsequent second patterning process.

[0084] Preferably, the thickness d3 of the initial mask layer 211 in the second region II and the third region III is in a range of 200 angstroms to 300 angstroms, thereby subsequently forming mask openings with an opening depth in a range of 200 angstroms to 300 angstroms.

[0085] The process of etching the mask material layer 210 using the first photoresist layer 220 as a mask to thin the mask material layer 210 in the second region II and the third region III includes at least one of a dry etching process and a wet etching process.

[0086] Preferably, the process of etching the mask material layer 210 using the first photoresist layer 220 as a mask includes an anisotropic dry etching process. This can further increase the verticality of the sidewalls of the initial mask layer 211 at the step where the first region I and the second region II are adjacent, thereby further optimizing the morphology of the subsequently formed mask opening.

[0087] In this embodiment, after the initial mask layer 211 is formed, the first photoresist layer 220 is removed.

[0088] The process of removing the first photoresist layer 220 includes an ashing process, etc.

[0089] Next, the initial mask layer 211 is patterned for the second time to form a mask layer having a mask opening therein, wherein the bottom of the mask opening exposes the surface of the first oxide layer 201 on the second region II. For the specific process of the second patterning step of the initial mask layer 211, please refer to Figures 10 and 11 .

[0090] Please refer to Figure 10 , Figure 10 and Figure 9 In the same viewing direction, after removing the first photoresist layer 220, a second photoresist layer 230 is formed on the third region III, and the second photoresist layer 230 exposes the initial mask layer 211 on the first region I and the second region II.

[0091] In this embodiment, the method for forming the second photoresist layer 230 includes: forming a second photoresist material layer (not shown) on the surface of the initial mask layer 211; performing a photolithography process (exposure, development, etc.) on the second photoresist material layer to form the second photoresist layer 230.

[0092] Since the second photolithography layer 230 exposes the initial mask layer 211 of the first region I and the second region II, the critical dimension of the second photolithography layer 230 is larger. Therefore, the critical dimension of the formed second photolithography layer 230 can be much larger than the limit dimension of the photolithography process, so that the sidewall morphology of the second photolithography layer 230 is better.

[0093] It should be understood that since the second photoresist layer 230 exposes the initial mask layer 211 of the first region I and the second region II, the critical dimension of the second photoresist layer 230 is equal to or greater than the total width W1 of the first region I and the second region II.

[0094] In this embodiment, the material of the second photoresist layer 230 includes photoresist.

[0095] Please refer to Figure 11 , Figure 11 and Figure 10 The initial mask layer 211 is etched using the second photoresist layer 230 as a mask until the surface of the first oxide layer 201 in the second region II is exposed, thereby forming a mask layer 212.

[0096] The mask layer 212 has a mask opening 213, and the bottom of the mask opening 213 exposes the surface of the first oxide layer 201 on the second region II. In addition, the mask opening 213 has a critical dimension CD1 (e.g. Figure 11 shown).

[0097] Thus, the mask layer 212 is formed by two patterning steps of the mask material layer 210. Specifically, the sidewall morphology of the mask opening 213 is formed by pattern transfer of the sidewall of the first photoresist layer 220 close to the second region II and the sidewall of the second photoresist layer 230 close to the second region II.

[0098] In this embodiment, the mask opening 213 is used to transfer a pattern to the first oxide layer 201 to subsequently form a tunneling layer opening.

[0099] Because the initial mask layer 211 has good sidewall morphology at the step adjacent to the first region I and the second region II, and because the second photoresist layer 230 also has good sidewall morphology, etching the initial mask layer 211 using the second photoresist layer 230 as a mask can simultaneously form a mask opening 213 with a small critical dimension CD1 while maintaining good sidewall morphology. Consequently, the tunneling layer opening formed by transferring the pattern of the mask layer 212 (mask opening 213) to the first oxide layer 201 achieves both a small critical dimension and good sidewall morphology. Consequently, a small, well-shaped tunneling layer can subsequently be formed within the tunneling layer opening, thereby simultaneously improving the integration density and performance of the semiconductor structure.

[0100] Specifically, the critical dimension CD1 in this embodiment is less than 0.2 micrometers (close to or less than the photolithography process limit).

[0101] In this embodiment, the depth d4 of the mask opening 213 is in the range of 200 angstroms to 300 angstroms.

[0102] If the depth d4 of the mask opening 213 is too large, the aspect ratio of the mask opening 213 is too large, increasing the difficulty of etching to form the tunnel opening. If the depth d4 of the mask opening 213 is too small, that is, the thickness of the mask layer 212 is too small, the mask layer 212 is easily consumed when the tunnel opening is subsequently formed, causing the etching process for forming the tunnel opening to damage the surface of the first oxide layer 201 in the first region I and the third region III, thereby affecting device performance. Therefore, selecting an appropriate range for the depth d4 of the mask opening 213, that is, a range of 200 angstroms to 300 angstroms, not only helps reduce the difficulty of forming the tunnel opening process, but also reduces or avoids the impact on device performance.

[0103] The mask layer 212 is made of a dielectric material, which includes at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbon oxynitride.

[0104] In this embodiment, silicon oxynitride is used as the material of the mask layer 212 so that a larger etching selectivity ratio can be achieved between the material of the first oxide layer 201 and the material of the mask layer 212 in the subsequent etching process for forming the tunnel opening.

[0105] The process of etching the initial mask layer 211 using the second photoresist layer 230 as a mask includes at least one of a dry etching process and a wet etching process.

[0106] Preferably, the process of etching the initial mask layer 211 using the second photoresist layer 230 as a mask includes an anisotropic dry etching process, thereby further increasing the verticality of the sidewalls of the mask opening 213 .

[0107] In this embodiment, after the mask layer 212 is formed, the second photoresist layer 230 is removed.

[0108] The process of removing the second photoresist layer 230 includes an ashing process, etc.

[0109] Please refer to Figure 12 , Figure 12 and Figure 11 In the same viewing direction, the first oxide layer 201 is etched using the mask layer 212 as a mask to form a tunneling layer opening 240 in the first oxide layer 201, and the bottom of the tunneling layer opening 240 exposes the surface of the second region II.

[0110] The tunneling layer opening 240 provides space for subsequent formation of a tunneling layer.

[0111] In this embodiment, since the critical dimension CD1 of the mask opening 213 is less than 0.2 microns and the mask opening 213 with good sidewall morphology is formed, the width W3 of the tunneling layer opening 240 in the first direction X can be less than 0.2 microns (close to or less than the limit of the photolithography process).

[0112] It should be understood that the depth of the tunneling layer opening 240 in a direction perpendicular to the surface of the substrate 200 is the same as the thickness d1 of the first oxide layer 201 .

[0113] The process of etching the first oxide layer 201 using the mask layer 212 as a mask includes at least one of a dry etching process and a wet etching process.

[0114] Preferably, the process of etching the first oxide layer 201 using the mask layer 212 as a mask includes a wet etching process, or a dry etching process and a wet etching process.

[0115] Because the process for etching the first oxide layer 201 includes a wet etching process, or a dry etching process and a wet etching process, the first oxide layer 201 in the second region II can be better removed through the isotropic wet etching process, and residues and contaminants on the inner wall surface of the tunneling layer opening 240 can be better reduced, thereby facilitating the subsequent formation of a tunneling layer with better quality and fewer defects. As a result, the performance and reliability of the semiconductor structure can be further improved.

[0116] Preferably, in the wet etching process for etching the first oxide layer 201 using the mask layer 212 as a mask, an etching selectivity ratio of the materials of the first oxide layer 201 and the mask layer 212 is greater than 5:1.

[0117] In this embodiment, after the tunneling layer opening 240 is formed, the mask layer 212 is removed.

[0118] Please refer to Figure 13 A tunneling layer 241 is formed in the tunneling layer opening 240 , and a thickness d5 of the tunneling layer 241 is smaller than a depth of the tunneling layer opening 240 .

[0119] Since the mask material layer 210 is subjected to the first patterning step to reduce the thickness d2 of the mask material layer 210 in the second region II and the third region III (eg Figure 7 As shown) to form an initial mask layer 211 (as shown Figure 9 As shown), and the initial mask layer 211 is subjected to a second patterning step to form a mask layer 212 having a mask opening 213 (as shown Figure 11 Therefore, the pattern of the mask opening 213 is transferred in two patterning steps, so that the critical dimension CD1 (as shown) can be formed. Figure 11 While making the mask opening 213 smaller (as shown), the critical dimension of the photoresist layer (first photoresist layer 220 and second photoresist layer 230) formed in each patterning step is much larger than the limit dimension of the photoresist process, so that the morphology of the photoresist layer is better, and further, the pattern morphology of the mask opening 213 is better. As a result, the tunneling layer opening 240 formed by transferring the pattern of the mask opening 213 to the first oxide layer 201 takes into account the smaller critical dimension (as shown). Figure 12 The width W3 shown in FIG. 1 and the good morphology thereof can form a tunneling layer 241 with a small size and good morphology, thereby improving the integration and performance of the semiconductor structure.

[0120] The tunneling layer 241 is made of oxide.

[0121] Specifically, in this embodiment, the material of the tunneling layer 241 includes silicon oxide.

[0122] In this embodiment, the thickness d5 of the tunneling layer 241 is less than 80 angstroms.

[0123] In this embodiment, the process of forming the tunneling layer 241 includes an oxidation process, a deposition process, and the like.

[0124] In this embodiment, after the tunneling layer 241 is formed, a floating gate (not shown) is formed on the surface of the connected first oxide layer 201 and the tunneling layer 241, and the floating gate spans several active regions S1 and several isolation regions S2 along the second direction Y; and a control gate (not shown) is formed on the floating gate.

[0125] Accordingly, an embodiment of the present invention further provides a semiconductor structure formed by the above-mentioned formation method, please continue to refer to Figure 13 ,include:

[0126] The substrate 200 includes a first region I, a second region II, and a third region III adjacent to each other and arranged along a first direction X. The surfaces of the first region I and the third region III have a first oxide layer 201. The first oxide layer 201 has a tunneling layer opening 240. The bottom of the tunneling layer opening 240 exposes the surface of the second region II. In the first direction X, the width W3 of the tunneling layer opening 240 (e.g., Figure 12 located within the tunneling layer opening 240 of the tunneling layer 241, and the thickness d5 of the tunneling layer 241 is less than the depth of the tunneling layer opening 240.

[0127] In this embodiment, the preset width is 0.2 micrometers, that is, the width W3 of the tunneling layer opening 240 is less than 0.2 micrometers.

[0128] In this embodiment, in the first direction X, the total width W1 of the first region I and the second region II is greater than 0.4 micrometers, and the total width W2 of the second region II and the third region III is greater than 0.4 micrometers.

[0129] In this embodiment, the substrate 200 is made of a semiconductor material. Specifically, the substrate 200 is made of silicon.

[0130] In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multinary semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI), etc. Among them, the multinary semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP, etc.

[0131] The voltage threshold of the first oxide layer 201 is higher than the voltage threshold of the tunneling layer 241. Specifically, the first oxide layer 201 is a high-voltage oxide layer, and the tunneling layer 241 is a low-voltage oxide layer.

[0132] The first oxide layer 201 has a thickness d1 along a direction perpendicular to the surface of the substrate 200 .

[0133] Preferably, the thickness d1 is less than 200 angstroms.

[0134] The material of the first oxide layer 201 includes oxide.

[0135] Specifically, the material of the first oxide layer 201 includes silicon oxide.

[0136] It should be understood that the depth of the tunneling layer opening 240 is the same as the thickness d1 of the first oxide layer 201 . That is, the thickness d5 of the tunneling layer 241 is less than the thickness d1 of the first oxide layer 201 .

[0137] The tunneling layer 241 is made of oxide.

[0138] Specifically, in this embodiment, the material of the tunneling layer 241 includes silicon oxide.

[0139] In this embodiment, the thickness of the tunneling layer 241 is less than 80 angstroms.

[0140] In this embodiment, the substrate 200 further includes a Figure 5 Several active regions S1 (as shown) are arranged alternately Figure 5 as shown) and several isolation areas S2 (as Figure 5 Wherein, the first direction X and the second direction Y are perpendicular to each other.

[0141] In the second direction Y, the first region I, the second region II, and the third region III all penetrate a plurality of active regions S1 and a plurality of isolation regions S2.

[0142] Specifically, the first oxide layer 201 and the tunneling layer 241 are located on the surface of the active region S1 .

[0143] In this embodiment, the isolation region S2 has an isolation structure 202 (eg Figure 5 shown).

[0144] The surface of the isolation structure 202 is higher than or flush with the surface of the first oxide layer 201 .

[0145] Preferably, the surface of the isolation structure 202 is higher than the surface of the first oxide layer 201 to better isolate the adjacent active region S1. Thus, the isolation structure 202 is not only located in the isolation region S2, but also located on the isolation region S2.

[0146] The isolation structure 202 is made of a dielectric material, which includes at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbon oxynitride.

[0147] In this embodiment, the semiconductor structure further includes: a floating gate (not shown) located on the surface of the connected first oxide layer 201 and the tunneling layer 241, wherein the floating gate spans a plurality of active regions S1 and a plurality of isolation regions S2 along the second direction Y; and a control gate (not shown) located on the surface of the floating gate.

[0148] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a first region, a second region, and a third region adjacent to each other and arranged along a first direction, wherein surfaces of the first region, the second region, and the third region have a first oxide layer; forming a mask material layer on a surface of the first oxide layer; performing a first patterning step on the mask material layer to reduce the thickness of the mask material layer in the second region and the third region in a direction perpendicular to the substrate surface to form an initial mask layer; Performing a second patterning step on the initial mask layer to form a mask layer, wherein the mask layer has a mask opening, and the bottom of the mask opening exposes the surface of the first oxide layer on the second region; Etching the first oxide layer using the mask layer as a mask to form a tunneling layer opening in the first oxide layer, wherein the bottom of the tunneling layer opening exposes the surface of the second region; A tunneling layer is formed in the tunneling layer opening, and a thickness of the tunneling layer is smaller than a depth of the tunneling layer opening.

2. The method for forming a semiconductor structure according to claim 1, wherein: The method for performing a first patterning step on the mask material layer includes: forming a first photoresist layer on the first area, the first photoresist layer exposing the mask material layer on the second area and the third area; etching the mask material layer using the first photoresist layer as a mask to thin the mask material layer in the second area and the third area.

3. The method for forming a semiconductor structure according to claim 2, wherein: The process of etching the mask material layer using the first photoresist layer as a mask includes an anisotropic dry etching process.

4. The method for forming a semiconductor structure according to claim 2, wherein: Also includes: After forming the initial mask layer, the first photoresist layer is removed.

5. The method for forming a semiconductor structure according to claim 4, wherein: The method for performing a second patterning step on the initial mask layer includes: after removing the first photoresist layer, forming a second photoresist layer on the third area, the second photoresist layer exposing the initial mask layer on the first area and the second area; etching the initial mask layer using the second photoresist layer as a mask until the surface of the first oxide layer in the second area is exposed to form the mask layer.

6. The method for forming a semiconductor structure according to claim 5, wherein: The process of etching the initial mask layer using the second photoresist layer as a mask includes an anisotropic dry etching process.

7. The method for forming a semiconductor structure according to claim 1, wherein: The process of etching the first oxide layer using the mask layer as a mask includes a wet etching process, or a dry etching process and a wet etching process.

8. The method for forming a semiconductor structure according to claim 7, wherein: In the wet etching process of etching the first oxide layer using the mask layer as a mask, an etching selectivity ratio of the materials of the first oxide layer and the mask layer is greater than 5:

1.

9. The method for forming a semiconductor structure according to claim 1, wherein: The material of the mask layer includes a dielectric material, and the material of the mask layer is different from the material of the first oxide layer.

10. The method for forming a semiconductor structure according to claim 9, wherein: The material of the first oxide layer includes silicon oxide, and the material of the mask layer includes silicon oxynitride.

11. The method for forming a semiconductor structure according to claim 1, wherein: The material of the tunneling layer includes silicon oxide.

12. The method for forming a semiconductor structure according to claim 1, wherein: The thickness of the mask material layer is less than 600 angstroms, and the depth of the mask opening is in the range of 200 angstroms to 300 angstroms.

13. The method for forming a semiconductor structure according to claim 1, wherein: In the first direction, the width of the tunnel layer opening is less than 0.2 micrometers.

14. The method for forming a semiconductor structure according to claim 1, wherein: In the first direction, the total width of the first region and the second region is greater than 0.4 micrometers, and the total width of the second region and the third region is greater than 0.4 micrometers.

15. The method for forming a semiconductor structure according to claim 1, wherein: The substrate also includes a plurality of active areas and a plurality of isolation areas alternately arranged along a second direction, the second direction being perpendicular to the first direction. In the second direction, the first area, the second area, and the third area all penetrate the plurality of active areas and the plurality of isolation areas. The first oxide layer is also located on the surface of the active area. An isolation structure is provided in and on the isolation area. The surface of the isolation structure is higher than the surface of the first oxide layer. The mask material layer is also located on the surface of the isolation structure.

16. The method for forming a semiconductor structure according to claim 15, wherein: Also includes: After the tunneling layer is formed, a floating gate is formed on the surfaces of the connected first oxide layer and the tunneling layer, wherein the floating gate crosses the active regions and the isolation regions along the second direction; and a control gate is formed on the floating gate.

17. A semiconductor structure, characterized in that The semiconductor structure is formed by the method for forming a semiconductor structure according to any one of claims 1 to 16; the semiconductor structure comprises: A substrate comprising a first region, a second region, and a third region adjacent to each other and arranged along a first direction, wherein surfaces of the first region and the third region have a first oxide layer, the first oxide layer has a tunneling layer opening therein, the bottom of the tunneling layer opening exposing the surface of the second region, and the width of the tunneling layer opening in the first direction is less than a preset width; the preset width is close to a photolithography process limit of the tunneling layer opening; A tunneling layer is located in the tunneling layer opening, and a thickness of the tunneling layer is less than a depth of the tunneling layer opening.

18. The semiconductor structure according to claim 17, wherein: The preset width is 0.2 microns.

19. The semiconductor structure according to claim 17, wherein: The first oxide layer is a high-voltage oxide layer, and the tunneling layer is a low-voltage oxide layer.

20. The semiconductor structure according to claim 17, wherein In the first direction, the total width of the first region and the second region is greater than 0.4 micrometers, and the total width of the second region and the third region is greater than 0.4 micrometers.

21. The semiconductor structure according to claim 17, wherein The thickness of the first oxide layer is less than 200 angstroms, and the thickness of the tunneling layer is less than 80 angstroms.

22. The semiconductor structure according to claim 17, wherein The substrate also includes a plurality of active areas and a plurality of isolation areas alternately arranged along a second direction, the second direction being perpendicular to the first direction. In the second direction, the first area, the second area, and the third area all penetrate the plurality of active areas and the plurality of isolation areas. The first oxide layer is also located on the surface of the active area. An isolation structure is provided in and on the isolation area, and the surface of the isolation structure is higher than the surface of the first oxide layer.

23. The semiconductor structure according to claim 22, wherein: Also includes: a floating gate located on surfaces of the connected first oxide layer and the tunneling layer, wherein the floating gate spans across the plurality of active regions and the plurality of isolation regions along the second direction; A control gate is located on the surface of the floating gate.

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