Semiconductor devices and their manufacturing methods

Abstract

The present invention relates to a semiconductor device and a method for manufacturing the same. The semiconductor device may include: a first conductive line; a second conductive line disposed on the first conductive line and spaced apart from the first conductive line; a variable resistance layer disposed above the first conductive line and below the second conductive line; at least one of a first dielectric layer or a second dielectric layer; at least one of a first contact or a second contact; and at least one of a first doped selector layer or a second doped selector layer.

Description

[0001] Cross-reference to related applications

[0002] This patent document claims priority to Korean Patent Application No. 10-2021-0145463, filed on October 28, 2021, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The patent document relates to storage circuits or devices and their application in electronic devices or systems. Background Technology

[0004] The latest trends in miniaturization, low power consumption, high performance, and versatility in the electrical and electronics industries are driving semiconductor manufacturers to focus on high-performance, high-capacity semiconductor devices. Examples of such high-performance, high-capacity semiconductor devices include memory devices capable of storing data by switching between different resistance states based on applied voltage or current. These semiconductor devices can include RRAM (Resistive Random Access Memory), PRAM (Phase Change Random Access Memory), FRAM (Ferroelectric Random Access Memory), MRAM (Magnetic Random Access Memory), and electronic fuses (E-FUSE). Summary of the Invention

[0005] The disclosed technology in the patent document includes storage circuits or devices and their application in electronic devices or systems, as well as various embodiments of electronic devices, wherein the electronic devices include semiconductor devices capable of improving hard mask margin during patterning processes and preventing etch damage during patterning of selector layers.

[0006] In one aspect, a semiconductor device may include: a first conductive line; a second conductive line disposed above and spaced apart from the first conductive line; a variable resistive layer disposed above the first conductive line and below the second conductive line; at least one of a first dielectric layer or a second dielectric layer, the first dielectric layer including a first through-hole disposed between the first conductive line and the variable resistive layer, the second dielectric layer including a second through-hole disposed between the variable resistive layer and the second conductive line; at least one of a first contact or a second contact, wherein the first contact is configured to include a conductive material filling the first through-hole and includes a first contact portion and a second contact portion spaced apart from each other, and the second contact is configured to include a conductive material filling the first through-hole. The conductive material with two through holes includes a third contact portion and a fourth contact portion spaced apart from each other; and at least one of a first doped selector layer or a second doped selector layer, wherein the first doped selector layer includes: a first selector element portion between the first contact portion and the second contact portion, and a second selector element portion disposed in the first dielectric layer and spaced apart from the upper surface and the lower surface of the first dielectric layer; and the second doped selector layer includes: a third selector element portion between the third contact portion and the fourth contact portion, and a fourth selector element portion disposed in the second dielectric layer and spaced apart from the upper surface and the lower surface of the second dielectric layer.

[0007] In another aspect, a method of manufacturing a semiconductor device may include: forming a first conductive line over a substrate; forming a variable resistance layer over the first conductive line; forming a second conductive line over the variable resistance layer; forming a first dielectric layer including a through-hole between the first conductive line and the variable resistance layer, between the variable resistance layer and the second conductive line, or between the first conductive line and the variable resistance layer and between the variable resistance layer and the second conductive line; forming a contact in the through-hole; performing a first ion implantation process to form a first sub-dielectric layer in the contact and a second sub-dielectric layer in the first dielectric layer, such that the first sub-dielectric layer is spaced apart from an upper and lower surface of the contact, and the second sub-dielectric layer is spaced apart from an upper and lower surface of the first dielectric layer, by converting a portion of the contact into the first sub-dielectric layer and a portion of the first dielectric layer into the second sub-dielectric layer; and performing a second ion implantation to implant a dopant into the first and second sub-dielectric layers to form a doped selector layer, wherein the doped selector layer includes: a first portion including the first sub-dielectric layer and a dopant; and a second portion including the second sub-dielectric layer and a dopant. Attached Figure Description

[0008] Figure 1A and Figure 1B Semiconductor devices based on certain embodiments of the technology disclosed herein are shown.

[0009] Figure 1C An example of a magnetic tunnel junction (MTJ) structure contained in a variable resistance layer based on certain embodiments of the present disclosure is shown.

[0010] Figures 2A to 2G This is a cross-sectional view illustrating an example method of manufacturing a semiconductor device based on certain embodiments of the technology disclosed herein.

[0011] Figures 3A to 3D This is a cross-sectional view illustrating another example method of manufacturing a semiconductor device based on certain embodiments of the technology disclosed herein.

[0012] Figures 4A to 4D This is a cross-sectional view illustrating yet another example method of manufacturing a semiconductor device based on certain embodiments of the technology disclosed herein. Detailed Implementation

[0013] Various embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0014] Figure 1A and Figure 1B Semiconductor devices based on certain embodiments of the technology disclosed herein are shown. Figure 1A It's a floor plan. Figure 1B It is along Figure 1A A sectional view taken by line A-A'.

[0015] refer to Figure 1A and Figure 1B The semiconductor device may include a crossover structure comprising: a substrate 100; a first conductor 110 formed above the substrate 100 and extending in a first direction; a second conductor 130 formed above the first conductor 110 and spaced apart from the first conductor 110 and extending in a second direction intersecting the first direction; and a memory cell 120 disposed at the intersection of the first conductor 110 and the second conductor 130 between the first conductor 110 and the second conductor 130.

[0016] Substrate 100 may include a semiconductor material, such as silicon. Desired understructures (not shown) may be formed in substrate 100. For example, substrate 100 may include driving circuitry (not shown) electrically connected to a first wire 110 and / or a second wire 130 to control the operation of memory cell 120. In this patent document, wires may guide electrical structures that electrically connect two or more circuit elements in a semiconductor device. In some embodiments, wires include word lines for controlling access to memory cells in the memory device and bit lines for reading information stored in the memory cells. In some embodiments, wires include interconnects for transmitting signals between different circuit elements in a semiconductor device.

[0017] The first wire 110 and the second wire 130 can be connected to the lower and upper ends of the memory cell 120, respectively, and can transmit voltage or current to the memory cell 120 to drive it. When the first wire 110 is used as a word line, the second wire 130 can be used as a bit line. Conversely, when the first wire 110 is used as a bit line, the second wire 130 can be used as a word line. The first wire 110 and the second wire 130 can include a single-layer or multi-layer structure, comprising one or more different conductive materials. Examples of conductive materials include, but are not limited to, metals, metal nitrides, or conductive carbon materials or combinations thereof. For example, the first conductor 110 and the second conductor 130 may include tungsten (W), titanium (Ti), tantalum (Ta), platinum (Pt), aluminum (Al), copper (Cu), zinc (Zn), nickel (Ni), cobalt (Co), lead (Pb), tungsten nitride (WN), tungsten silicide (WSi), titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum aluminum nitride (TaAlN), carbon (C), silicon carbide (SiC), or silicon carbon nitride (SiCN) or combinations thereof.

[0018] Storage cells 120 may be arranged in a matrix having rows and columns along a first direction and a second direction to overlap with the intersection regions between the first conductor 110 and the second conductor 130. In one embodiment, the size of each storage cell 120 may be substantially equal to or smaller than the size of the intersection region between each corresponding pair of first conductors 110 and second conductors 130. In another embodiment, the size of each storage cell 120 may be larger than the size of the intersection region between each corresponding pair of first conductors 110 and second conductors 130.

[0019] The space between the first conductor 110, the second conductor 130, and the storage cell 120 may be filled with dielectric layers 101, 102-1, 102-2, 103, 104-1, and 104-2. Each dielectric layer 101, 102-1, 102-2, 103, 104-1, and 104-2 may comprise a dielectric material. Examples of dielectric materials may include oxides, nitrides, or combinations thereof. Dielectric layers 101, 102-1, 102-2, 103, 104-1, and 104-2 may comprise the same material or different materials.

[0020] The memory cell 120 may include a stacked structure comprising a first lower electrode contact 121-1, a first blanket-doped selector layer 122, a second lower electrode contact 121-2, a variable resistor layer 123, a first upper electrode contact 124-1, a second blanket-doped selector layer 125, and a second upper electrode contact 124-2. Each blanket-doped layer in a region is uniformly doped within that region, and no mask or pattern is used during doping within that doped region.

[0021] The first lower electrode contact 121-1 may be located between the first conductor 110 and the first uniform-thickness doped selector layer 122. The first lower electrode contact 121-1 may be disposed at the lowest portion of the memory cell 120 and serve as a circuit node for transmitting voltage or current between a corresponding first conductor 110 and the remainder of each memory cell 120. The second upper electrode contact 124-2 may be disposed at the uppermost portion of the memory cell 120 and serve as a voltage or current transmission path between the remainder of the memory cell 120 and a corresponding second conductor 130. In this patent document, the electrode contacts may include: contacts, contact plugs, or any other structure having small gaps filled with a conductive material such as metal.

[0022] The first lower electrode contact 121-1 and the second lower electrode contact 121-2, as well as the first upper electrode contact 124-1 and the second upper electrode contact 124-2, may include materials that can be used to form a dielectric material layer by, for example, ion implantation processes using oxygen, nitrogen, or a combination of oxygen and nitrogen. For example, the first lower electrode contact 121-1 and the second lower electrode contact 121-2, as well as the first upper electrode contact 124-1 and the second upper electrode contact 124-2, may include tungsten (W), titanium (Ti), tantalum (Ta), vanadium (V), chromium (Cr), platinum (Pt), aluminum (Al), copper (Cu), zinc (Zn), nickel (Ni), cobalt (Co), lead (Pb), manganese (Mn), niobium (Nb), tungsten nitride (WN), tungsten silicide (WSi), titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), or tantalum aluminum nitride (TaAlN), or combinations thereof.

[0023] The first lower electrode contact 121-1 and the second lower electrode contact 121-2, as well as the first upper electrode contact 124-1 and the second upper electrode contact 124-2, may be made of the same material or different materials.

[0024] The first lower electrode contact 121-1 and the second lower electrode contact 121-2 may have the same thickness or different thicknesses.

[0025] The first upper electrode contact 124-1 and the second upper electrode contact 124-2 may have the same thickness or different thicknesses.

[0026] At least one of the first lower electrode contact 121-1 and the second lower electrode contact 121-2, as well as the first upper electrode contact 124-1 and the second upper electrode contact 124-2, can be omitted.

[0027] The variable resistance layer 123 can be used to store data by setting the variable resistance layer 123 to a desired resistance state (e.g., using a high resistance state and a low resistance state to represent digital levels "1" and "0"), and to change the stored data bits by switching between different resistance states according to the applied voltage or current. The variable resistance layer 123 can have a single-layer or multi-layer structure, comprising at least one material for RRAM, PRAM, MRAM, FRAM, or other applications. For example, the variable resistance layer 123 can include: metal oxides such as transition metal oxides or perovskite-based oxides, phase change materials such as chalcogenide-based materials, ferromagnetic materials, ferroelectric materials, or other materials. However, the implementation is not limited to this, and the storage cell 120 may include other storage layers capable of storing data in various ways instead of the variable resistance layer 123.

[0028] In some implementations, the variable resistance layer 123 may include a magnetic tunnel junction (MTJ) structure. This will be referenced... Figure 1C Please provide an explanation.

[0029] Figure 1C An example of a magnetic tunnel junction (MTJ) structure included in the variable resistance layer 123 is shown.

[0030] The variable resistance layer 123 may include an MTJ structure, which includes: a free layer 13 having a variable magnetization direction, a pinned layer 15 having a fixed magnetization direction, and a tunnel blocking layer 14 between the free layer 13 and the pinned layer 15.

[0031] Free layer 13 can have one of different magnetization directions or different electron spin directions to switch the polarity of free layer 13 in the MTJ structure, thereby causing a change in resistance value. In some embodiments, the polarity of free layer 13 changes or flips when a voltage or current signal (e.g., a drive current above a certain threshold) is applied to the MTJ structure. As the polarity of free layer 13 changes, free layer 13 and fixed layer 15 have different magnetization directions or different electron spin directions, which allows variable resistance layer 123 to store different data or represent different data bits. Free layer 13 can also be referred to as a storage layer. The magnetization direction of free layer 13 can be substantially perpendicular to the surfaces of free layer 13, tunnel blocking layer 14, and fixed layer 15. In other words, the magnetization direction of free layer 13 can be substantially parallel to the stacking direction of free layer 13, tunnel blocking layer 14, and fixed layer 15. Therefore, the magnetization direction of free layer 13 can vary between a downward direction and an upward direction. The change in the magnetization direction of free layer 13 can be caused by a spin-transfer torque generated by an applied current or voltage.

[0032] The free layer 13 may have a single-layer or multi-layer structure, comprising a ferromagnetic material. For example, the free layer 13 may comprise an alloy based on Fe, Ni, or Co, such as Fe-Pt alloy, Fe-Pd alloy, Co-Pd alloy, Co-Pt alloy, Co-Fe alloy, Fe-Ni-Pt alloy, Co-Fe-Pt alloy, Co-Ni-Pt alloy, or Co-Fe-B alloy or others, or may comprise a stack of metals, such as Co / Pt or Co / Pd or others.

[0033] The tunnel barrier layer 14 allows electron tunneling during data read and write operations. In a write operation to store new data, a high write current can be directed through the tunnel barrier layer 14 to change the magnetization direction of the free layer 13, thereby altering the resistance state of the MTJ to write new data bits. In a read operation, a low read current can be directed through the tunnel barrier layer 14 without changing the magnetization direction of the free layer 13 to measure the existing resistance state of the MTJ under the existing magnetization direction of the free layer 13, thereby reading the data bits stored in the MTJ. The tunnel barrier layer 14 may comprise a dielectric oxide such as MgO, CaO, SrO, TiO, VO, or NbO.

[0034] The fixed layer 15 may have a fixed magnetization direction that remains unchanged as the magnetization direction of the free layer 13 changes. The fixed layer 15 may be referred to as a reference layer. In some embodiments, the magnetization direction of the fixed layer 15 may be fixed in a downward direction. In some embodiments, the magnetization direction of the fixed layer 15 may be fixed in an upward direction.

[0035] The fixing layer 15 may have a single-layer or multi-layer structure, comprising a ferromagnetic material. For example, the fixing layer 15 may comprise an alloy based on Fe, Ni, or Co, such as Fe-Pt alloy, Fe-Pd alloy, Co-Pd alloy, Co-Pt alloy, Co-Fe alloy, Fe-Ni-Pt alloy, Co-Fe-Pt alloy, Co-Ni-Pt alloy, or Co-Fe-B alloy, or may comprise a stack of metals, such as Co / Pt or Co / Pd or others.

[0036] By applying a voltage or current to the variable resistance layer 123, the magnetization direction of the free layer 13 can be changed via spin torque transfer. In some embodiments, when the magnetization directions of the free layer 13 and the fixed layer 15 are parallel to each other, the variable resistance layer 123 can be in a low-resistance state, which can represent a digital data bit "0". Conversely, when the magnetization directions of the free layer 13 and the fixed layer 15 are antiparallel to each other, the variable resistance layer 123 can be in a high-resistance state, which can represent a digital data bit "1". In some embodiments, the variable resistance layer 123 can be configured to store a data bit "1" when the magnetization directions of the free layer 13 and the fixed layer 15 are parallel to each other, and to store a data bit "0" when the magnetization directions of the free layer 13 and the fixed layer 15 are antiparallel to each other.

[0037] In some embodiments, the variable resistance layer 123 may further include one or more layers that perform various functions to improve the characteristics of the MTJ structure. For example, the variable resistance layer 123 may further include at least one of a buffer layer 11, a lower layer 12, a spacer layer 16, a magnetic correction layer 17, and a cover layer 18.

[0038] The lower layer 12 can be disposed below the free layer 13 and can be used to improve the vertical magnetocrystalline anisotropy of the free layer 13. The lower layer 12 can have a single-layer or multi-layer structure, which includes metal, metal alloy, metal nitride or metal oxide or a combination thereof.

[0039] A buffer layer 11 may be disposed beneath the lower layer 12 to promote crystal growth of the lower layer 12, thereby improving the perpendicular magnetocrystalline anisotropy of the free layer 13. The buffer layer 11 may have a single-layer or multi-layer structure, comprising a metal, a metal alloy, a metal nitride, or a metal oxide, or a combination thereof. Furthermore, the buffer layer 11 may be formed of or include a material that is well compatible with the bottom electrode (not shown) to resolve the lattice constant mismatch between the bottom electrode and the lower layer 12. For example, the buffer layer 11 may comprise tantalum (Ta).

[0040] Spacer layer 16 may be situated between magnetic correction layer 17 and fixed layer 15 and serve as a buffer between them. Spacer layer 16 may be used to improve the characteristics of magnetic correction layer 17. Spacer layer 16 may include a noble metal, such as ruthenium (Ru).

[0041] The magnetic correction layer 17 can be used to counteract the stray magnetic field generated by the fixed layer 15. In this case, the effect of the stray magnetic field of the fixed layer 15 can be reduced, thereby reducing the bias magnetic field in the free layer 13. The magnetic correction layer 17 can have a magnetization direction antiparallel to the magnetization direction of the fixed layer 15. In this embodiment, when the fixed layer 15 has a downward magnetization direction, the magnetic correction layer 17 can have an upward magnetization direction. Conversely, when the fixed layer 15 has an upward magnetization direction, the magnetic correction layer 17 can have a downward magnetization direction. The magnetic correction layer 17 can be exchange-coupled with the fixed layer 15 via the spacer layer 16 to form a synthetic antiferromagnetic (SAF) structure. The magnetic correction layer 17 can have a single-layer or multi-layer structure, which includes ferromagnetic materials.

[0042] In this embodiment, the magnetic correction layer 17 is located above the fixed layer 15, but the magnetic correction layer 17 can be disposed in different locations. For example, the magnetic correction layer 17 can be located above, below, or beside the MTJ structure, and the magnetic correction layer 17 is patterned separately from the MTJ structure.

[0043] The capping layer 18 can be used to protect the variable resistance layer 123 and / or serve as a hard mask for patterning the variable resistance layer 123. In some embodiments, the capping layer 18 may comprise various conductive materials, such as metals. In some embodiments, the capping layer 18 may comprise a metallic material with few or no pinholes and high resistance to wet and / or dry etching. In some embodiments, the capping layer 18 may comprise a metal, a nitride, or an oxide, or a combination thereof. For example, the capping layer 18 may comprise a noble metal such as ruthenium (Ru).

[0044] The capping layer 18 may have a single-layer or multi-layer structure. In some embodiments, the capping layer 18 may have a multi-layer structure, comprising oxides, metals, or combinations thereof. For example, the capping layer 18 may have a multi-layer structure comprising an oxide layer, a first metal layer, and a second metal layer.

[0045] A material layer (not shown) used to address the lattice structure differences and lattice constant mismatch between the fixed layer 15 and the magnetic correction layer 17 may be located between the fixed layer 15 and the magnetic correction layer 17. For example, the material layer may be amorphous and may include metals, metal nitrides, or metal oxides.

[0046] The first uniform-thickness doped selector layer 122 and the second uniform-thickness doped selector layer 125 can be used to control access to the variable resistor layer 123. For this purpose, the first uniform-thickness doped selector layer 122 and the second uniform-thickness doped selector layer 125 can have characteristics for regulating current flow according to the amplitude of the applied voltage or current; that is, for blocking or substantially limiting the current flowing through the memory cell 120 when the amplitude of the applied voltage is less than a predetermined threshold, and for allowing a sudden increase in the current flowing through the memory cell 120 when the amplitude of the applied voltage is equal to or greater than the threshold. The first uniform-thickness doped selector layer 122 and the second uniform-thickness doped selector layer 125 can include metal-insulator transition (MIT) materials such as NbO2, TiO2, VO2, WO2, or others, and mixed ion-electron conduction (MIEC) materials such as ZrO2 (Y2O3), Bi2O3-BaO, (La2O3). X (CeO2) 1-X Alternatively, the bidirectional threshold switch (OTS) material includes chalcogenide materials such as Ge2Sb2Te5, As2Te3, As2, As2Se3, or others, or tunneling insulating materials such as silicon oxide, silicon nitride, metal oxide, or others. The thickness of the tunneling insulating layer is small enough to allow electrons to tunnel under a given voltage or current. The first uniform-thickness doped selector layer 122 and the second uniform-thickness doped selector layer 125 may comprise a single-layer or multi-layer structure.

[0047] In one embodiment, the first uniform-thickness doped selector layer 122 and the second uniform-thickness doped selector layer 125 can be configured to perform threshold switching operation. In this patent document, the term "threshold switching operation" can be used to indicate turning the first uniform-thickness doped selector layer 122 and the second uniform-thickness doped selector layer 125 on or off when an external voltage having a voltage value related to a threshold voltage is applied to them. The absolute value of this external voltage can be controlled to gradually increase or decrease. When the absolute value of the external voltage applied to the first uniform-thickness doped selector layer 122 and the second uniform-thickness doped selector layer 125 increases, the first uniform-thickness doped selector layer 122 and the second uniform-thickness doped selector layer 125 can be turned on or become conductive; when the absolute value of the external voltage is greater than the first threshold voltage, once turned on, the increase in the external voltage causes a non-linear increase in the operating current. When the absolute value of the external voltage applied to the first uniform-thickness doped selector layer 122 and the second uniform-thickness doped selector layer 125 decreases after the first uniform-thickness doped selector layer 122 and the second uniform-thickness doped selector layer 125 are turned on, the operating current flowing through the first uniform-thickness doped selector layer 122 and the second uniform-thickness doped selector layer 125, or the operating current between the two, decreases non-linearly until the applied voltage value reaches the second threshold voltage. If the voltage value is below the second threshold voltage, the first uniform-thickness doped selector layer 122 and the second uniform-thickness doped selector layer 125 can be turned off (i.e., non-conductive). Therefore, the first uniform-thickness doped selector layer 122 and the second uniform-thickness doped selector layer 125 performing threshold switching operation can have non-storage operation characteristics.

[0048] In some embodiments, the first uniform-thickness doped selector layer 122 and the second uniform-thickness doped selector layer 125 may include a dielectric material having incorporated dopants. The first uniform-thickness doped selector layer 122 and the second uniform-thickness doped selector layer 125 may include oxides with dopants, nitrides with dopants, or oxynitrides with dopants, or combinations thereof, such as silicon oxide, tungsten oxide, titanium oxide, vanadium oxide, chromium oxide, platinum oxide, aluminum oxide, copper oxide, zinc oxide, nickel oxide, cobalt oxide, lead oxide, manganese oxide, niobium oxide, hafnium oxide, silicon nitride, tungsten nitride, titanium nitride, vanadium nitride, chromium nitride, platinum nitride, aluminum nitride, copper nitride, zinc nitride, nickel nitride, cobalt nitride, lead nitride, manganese nitride, niobium nitride, hafnium nitride, silicon oxynitride, tungsten oxynitride, titanium oxynitride, vanadium oxynitride, chromium oxynitride, platinum oxynitride, aluminum oxynitride, copper oxynitride, zinc oxynitride, nickel oxynitride, cobalt oxynitride, lead oxynitride, manganese oxynitride, niobium oxynitride, or hafnium oxynitride, or combinations thereof. The dopants incorporated into the first uniform-thickness doped selector layer 122 and the second uniform-thickness doped selector layer 125 may include n-type or p-type dopants and may be incorporated or bonded, for example, by an ion implantation process. Examples of dopants may include one or more of boron (B), nitrogen (N), carbon (C), phosphorus (P), arsenic (As), aluminum (Al), silicon (Si), and germanium (Ge).

[0049] Typically, doped selectors are formed by depositing a dielectric layer as the selector substrate, bonding or incorporating dopants into the dielectric layer via ion implantation, and then patterning the doped dielectric layer. In this case, a separate dielectric layer must be formed to create the selector, increasing the overall height of the memory, which may lead to insufficient hard mask margin during subsequent patterning processes. Consequently, etch damage to the doped selector may occur during the patterning process.

[0050] To overcome such problems, in embodiments of the disclosed technology, a portion of the lower electrode contact and / or a portion of the upper electrode contact can be converted into a dielectric layer by introducing oxygen and / or nitrogen into a portion of the lower electrode contact and / or a portion of the upper electrode contact, instead of forming separate dielectric layers for the first uniform thickness doped selector layer 122 and the second uniform thickness doped selector layer 125. The first uniform thickness doped selector layer 122 and the second uniform thickness doped selector layer 125 comprising doped dielectric material are then formed by introducing or implanting dopants into or into the dielectric layer, for example, by an ion implantation process.

[0051] The first uniform-thickness doped selector layer 122 and the second uniform-thickness doped selector layer 125 may include dielectric materials and dopants.

[0052] The first uniform thickness doped selector layer 122 may include a first portion 122-1 and a second portion 122-2. The first portion 122-1 may be disposed between the first lower electrode contact 121-1 and the second lower electrode contact 121-2, and the second portion 122-2 may be disposed between the dielectric layer 102-1 and the dielectric layer 102-2.

[0053] In some embodiments, the first part 122-1 and the second part 122-2 may have different dielectric materials from each other.

[0054] The second uniform-thickness doped selector layer 125 may include a first portion 125-1 and a second portion 125-2. The first portion 125-1 may be disposed between the first upper electrode contact 124-1 and the second upper electrode contact 124-2, and the second portion 125-2 may be disposed between the dielectric layer 104-1 and the dielectric layer 104-2.

[0055] In some embodiments, the first part 125-1 and the second part 125-2 may have different dielectric materials from each other.

[0056] In some embodiments, the first portion 122-1 of the first uniform thickness doped selector layer 122 and the first portion 125-1 of the second uniform thickness doped selector layer 125 may include the same dielectric material and dopant.

[0057] In some embodiments, the second portion 122-2 of the first uniform thickness doped selector layer 122 and the second portion 125-2 of the second uniform thickness doped selector layer 125 may include the same dielectric material and dopant.

[0058] The distance from the lower surface of the first lower electrode contact 121-1 to the lower surface of the first portion 122-1 can be the same as or different from the distance from the upper surface of the second lower electrode contact 121-2 to the upper surface of the first portion 122-1. The distance from the lower surface of the dielectric layer 102-1 to the lower surface of the second portion 122-2 can be the same as or different from the distance from the upper surface of the dielectric layer 102-2 to the upper surface of the second portion 122-2.

[0059] The distance from the lower surface of the first upper electrode contact 124-1 to the lower surface of the first portion 125-1 can be the same as or different from the distance from the upper surface of the second upper electrode contact 124-2 to the upper surface of the first portion 125-1. The distance from the lower surface of the dielectric layer 104-1 to the lower surface of the second portion 125-2 can be the same as or different from the distance from the upper surface of the dielectric layer 104-2 to the upper surface of the second portion 125-2.

[0060] In some embodiments, separate dielectric layers are not formed for forming the first uniform-thickness doped selector layer 122 and the second uniform-thickness doped selector layer 125. Therefore, the overall height of the memory cell 120 is not increased, thereby improving hard mask margin and preventing etch damage during the patterning process of the first uniform-thickness doped selector layer 122 and the second uniform-thickness doped selector layer 125.

[0061] Reference Figures 2A to 2G , Figures 3A to 3D as well as Figures 4A to 4D The formation of the first uniform-thickness doped selector layer 122 and the second uniform-thickness doped selector layer 125 is described in detail.

[0062] In some embodiments, the first uniform-thickness doped selector layer 122 and the second uniform-thickness doped selector layer 125 can perform threshold switching operations by doping regions formed in the material layers used for the first uniform-thickness doped selector layer 122 and the second uniform-thickness doped selector layer 125. Therefore, the size of the threshold switching operation region can be controlled by the distribution region of the dopant. The dopant can form charge carrier trapping sites in the material layers used for the first uniform-thickness doped selector layer 122 and the second uniform-thickness doped selector layer 125. Based on an external voltage applied to the first uniform-thickness doped selector layer 122 and the second uniform-thickness doped selector layer 125, these trapping sites can capture charge carriers moving within the first uniform-thickness doped selector layer 122 and the second uniform-thickness doped selector layer 125. The trapping sites thus provide threshold switching characteristics and are used to perform threshold switching operations.

[0063] In some embodiments, each of the memory cells 120 may include a first lower electrode contact 121-1, a first uniform-thickness doped selector layer 122, a second lower electrode contact 121-2, a variable resistor layer 123, a first upper electrode contact 124-1, a second uniform-thickness doped selector layer 125, and a second upper electrode contact 124-2, stacked sequentially. However, the memory cells 120 may have different structures. In some embodiments, at least one of the first uniform-thickness doped selector layer 122 or the second uniform-thickness doped selector layer 125 may be omitted. In some embodiments, besides... Figure 1B As shown in layers 121 to 125, storage cell 120 may further include one or more layers (not shown) for enhancing the characteristics of storage cell 120 or improving the manufacturing process.

[0064] In some embodiments, adjacent memory cells of the plurality of memory cells 120 may be spaced apart from each other at a predetermined interval, and trenches may exist between the plurality of memory cells 120. The height-to-width ratio (e.g., aspect ratio) of the trenches between adjacent memory cells 120 ranges from 1:1 to 40:1, from 10:1 to 40:1, from 10:1 to 20:1, from 5:1 to 10:1, from 10:1 to 15:1, from 1:1 to 25:1, from 1:1 to 30:1, from 1:1 to 35:1, or from 1:1 to 45:1.

[0065] In some embodiments, the trenches may have sidewalls that are substantially perpendicular to the upper surface of the substrate 100. In some embodiments, adjacent trenches may be spaced apart from each other by equal or similar distances.

[0066] In some embodiments, in addition to the first wire 110, the memory cell 120 and the second wire 130, the semiconductor device may also include other layers.

[0067] Although one cross-point structure has been described, two or more cross-point structures can be stacked in a vertical direction perpendicular to the top surface of the substrate 100.

[0068] Reference Figures 2A to 2G This describes a method for manufacturing semiconductor devices.

[0069] refer to Figure 2A The first conductive line 210 can be formed over a substrate 200 with a predetermined structure. The first conductive line 210 can be formed by forming a first interlayer dielectric layer 201 with trenches for forming the first conductive line 210 over the substrate 200, forming a conductive layer for the first conductive line 210, and etching the conductive layer using a linear mask pattern extending in a first direction.

[0070] The lower electrode contact 221 can be formed above the first conductor 210. The lower electrode layer 221 can be formed by forming a second interlayer dielectric layer 202 with holes on the structure in which the first conductor 210 is formed, forming a material layer for the lower electrode layer 221 in the holes, and performing a planarization process such as chemical mechanical planarization (CMP).

[0071] The lower electrode contact 221 may include a material capable of forming a dielectric material, for example, by bonding or doping with oxygen, nitrogen, or a combination of oxygen and nitrogen through an ion implantation process. For example, the lower electrode contact 221 may include tungsten (W), titanium (Ti), tantalum (Ta), vanadium (V), chromium (Cr), platinum (Pt), aluminum (Al), copper (Cu), zinc (Zn), nickel (Ni), cobalt (Co), lead (Pb), manganese (Mn), niobium (Nb), tungsten nitride (WN), tungsten silicide (WSi), titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), silicon tantalum nitride (TaSiN), or tantalum aluminum nitride (TaAlN), or combinations thereof.

[0072] refer to Figure 2B A first ion implantation process can be performed on a portion of the lower electrode contact 221 and a portion of the second interlayer dielectric layer 202 to incorporate oxygen, nitrogen, or a combination thereof into the portion of the lower electrode contact 221 and the portion of the second interlayer dielectric layer 202. The portion of the lower electrode contact 221 may be a portion spaced apart from the upper and lower surfaces of the lower electrode contact 221. Similarly, a portion of the second interlayer dielectric layer 202 may be a portion spaced apart from the upper and lower surfaces of the second interlayer dielectric layer 202. That is, the first ion implantation process can be performed by targeting locations spaced apart from the upper and lower surfaces of the lower electrode contact 221 and the upper and lower surfaces of the second interlayer dielectric layer 202 to incorporate oxygen, nitrogen, or a combination thereof into a given portion of the lower electrode contact 221 and a given portion of the second interlayer dielectric layer 202 in a direction perpendicular to the surfaces of the layers. The first ion implantation process can be a process of converting the portion of the lower electrode contact 221 and the portion of the second interlayer dielectric layer 202 into a dielectric layer by oxidation, nitridation, or nitrooxidation. Since the second interlayer dielectric layer 202 is initially formed of a dielectric material, it can maintain its dielectric properties even after oxygen and / or nitrogen are introduced through the first ion implantation process.

[0073] In the first ion implantation process, a first uniform-thickness doped selector layer can be considered (see...). Figure 2C The position and thickness of the reference mark 222 are used to adjust the projection range (Rp).

[0074] A first material layer 222A can be formed in the lower electrode contact 221 using a first ion implantation process, and a second material layer 222B can be formed in the second interlayer dielectric layer 202. The lower electrode contact 221 below the first material layer 222A and the lower electrode contact 221 above the first material layer 222A can be referred to as the first lower electrode contact 221-1 and the second lower electrode contact 221-2, respectively. The first lower electrode contact 221-1 and the second lower electrode contact 221-2 can have the same thickness or different thicknesses. The second interlayer dielectric layer 202 below the second material layer 222B and the second interlayer dielectric layer 202 above the second material layer 222B can be referred to as the first portion 202-1 and the second portion 202-2 of the second interlayer dielectric layer 202, respectively. The first portion 202-1 and the second portion 202-2 can have the same thickness or different thicknesses.

[0075] Each of the first material layer 222A and the second material layer 222B may include a dielectric material. In some embodiments, the first material layer 222A and the second material layer 222B may include dielectric materials that are different from each other.

[0076] refer to Figure 2C The first uniform-thickness doped selector layer 222 can be formed by incorporating dopants through a second ion implantation process on the first material layer 222A and the second material layer 222B.

[0077] The first uniform-thickness doped selector layer 222 may include a first portion 222-1 between the first lower electrode contact 221-1 and the second lower electrode contact 221-2, and a second portion 222-2 between the first portion 202-1 and the second portion 202-2 of the second interlayer dielectric layer 202. That is, the first uniform-thickness doped selector layer 222 may be uniformly doped between the first lower electrode contact 221-1 and the second lower electrode contact 221-2, and between the first portion 202-1 and the second portion 202-2 of the second interlayer dielectric layer 202.

[0078] The dopant produced by the second ion implantation process may include one or more of boron (B), nitrogen (N), carbon (C), phosphorus (P), arsenic (As), aluminum (Al), silicon (Si), and germanium (Ge).

[0079] The first uniform-thickness doped selector layer 222 may be located between the first portion 202-1 and the second portion 202-2 of the second interlayer dielectric layer 202 and between the first lower electrode contact 221-1 and the second lower electrode contact 221-2 in the form of uniform-thickness doping.

[0080] refer to Figure 2DA variable resistance layer 223 and an upper electrode contact 224 can be formed above the second lower electrode contact 221-2.

[0081] The variable resistor layer 223 can be used in Figure 2C A material layer for the variable resistance layer 223 is formed on the structure and the material layer is patterned to form it. Then, a third interlayer dielectric layer 203 can be formed.

[0082] The upper electrode contact 224 can be formed by forming a fourth interlayer dielectric layer 204 with holes above the variable resistance layer 223 and the third interlayer dielectric layer 203, forming a material layer for the upper electrode contact 224 in the holes, and performing a planarization process such as chemical mechanical planarization (CMP).

[0083] The upper electrode contact 224 may include a material capable of forming a dielectric material, for example, by doping with oxygen, nitrogen, or a combination thereof through an ion implantation process. For example, the upper electrode contact 224 may include tungsten (W), titanium (Ti), tantalum (ta), vanadium (V), chromium (Cr), platinum (Pt), aluminum (Al), copper (Cu), zinc (Zn), nickel (Ni), cobalt (Co), lead (Pb), manganese (Mn), niobium (Nb), tungsten nitride (WN), tungsten silicide (WSi), titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), silicon tantalum nitride (TaSiN), or tantalum aluminum nitride (TaAlN), or combinations thereof.

[0084] refer to Figure 2EA third ion implantation process can be performed on a portion of the upper electrode contact 224 and a portion of the fourth interlayer dielectric layer 204 to incorporate oxygen, nitrogen, or a combination thereof into the portion of the upper electrode contact 224 and the fourth interlayer dielectric layer 204. The portion of the upper electrode contact 224 may be a portion spaced apart from the upper and lower surfaces of the upper electrode contact 224. Similarly, the portion of the fourth interlayer dielectric layer 204 may be a portion spaced apart from the upper and lower surfaces of the fourth interlayer dielectric layer 204. That is, the third ion implantation process can be performed by targeting positions spaced apart from the upper and lower surfaces of the upper electrode contact 224 and the upper and lower surfaces of the fourth interlayer dielectric layer 204 to incorporate oxygen, nitrogen, or a combination thereof into a given portion of the upper electrode contact 224 and the fourth interlayer dielectric layer 204 in a direction perpendicular to the surface of the layers. The third ion implantation process can be a process that transforms the portion of the upper electrode contact 224 and the portion of the fourth interlayer dielectric layer 204 into a dielectric layer through oxidation, nitriding, or nitrogen oxidation. Since the fourth interlayer dielectric layer 204 is initially formed of a dielectric material, it can maintain its dielectric properties even after oxygen and / or nitrogen are introduced through the third ion implantation process.

[0085] In the third ion implantation process, a second uniform-thickness doped selector layer (e.g.) can be considered. Figure 2F The position and thickness of the 225) are used to adjust the projection range (Rp).

[0086] A first material layer 225A can be formed in the upper electrode contact 224 using a third ion implantation process, and a second material layer 225B can be formed in the fourth interlayer dielectric layer 204. The upper electrode contact 224 below the first material layer 225A and the upper electrode contact 224 above the first material layer 225A can be referred to as the first upper electrode contact 224-1 and the second upper electrode contact 224-2, respectively. The first upper electrode contact 224-1 and the second upper electrode contact 224-2 can have the same thickness or different thicknesses. The fourth interlayer dielectric layer 204 below the second material layer 225B and the fourth interlayer dielectric layer 204 above the second material layer 225B can be referred to as the first portion 204-1 and the second portion 204-2 of the fourth interlayer dielectric layer 204. The first portion 204-1 and the second portion 204-2 can have the same thickness or different thicknesses.

[0087] Each of the first material layer 225A and the second material layer 225B may include a dielectric material. In some embodiments, the first material layer 225A and the second material layer 225B may include dielectric materials that are different from each other.

[0088] refer to Figure 2F The second uniform-thickness doped selector layer 225 can be formed by incorporating dopants through a fourth ion implantation process on the first material layer 225A and the second material layer 225B.

[0089] The second uniform thickness doped selector layer 225 may include a first portion 225-1 between the first upper electrode contact 224-1 and the second upper electrode contact 224-2, and a second portion 225-2 between the first portion 204-1 and the second portion 204-2 of the fourth interlayer dielectric layer 204.

[0090] The dopants used in the fourth ion implantation process may include one or more of boron (B), nitrogen (N), carbon (C), phosphorus (P), arsenic (As), aluminum (Al), silicon (Si), and germanium (Ge).

[0091] The second part of the doped selector layer 225 can be located between the first part 204-1 and the second part 204-2 and between the first upper electrode contact 224-1 and the second upper electrode contact 224-2 in the form of uniform thickness doping.

[0092] In some embodiments, the first portion 225-1 of the second uniform-thickness doped selector layer 225 and the first portion 222-1 of the first uniform-thickness doped selector layer 222 can be formed of the same material. In some embodiments, the second portion 225-2 of the second uniform-thickness doped selector layer 225 and the second portion 222-2 of the first uniform-thickness doped selector layer 222 can be formed of the same material. In this case, since the first uniform-thickness doped selector layer 222 and the second uniform-thickness doped selector layer 225 can have the same operating characteristics, the device operating conditions can be the same.

[0093] refer to Figure 2G A second conductor 230 can be formed above the second upper electrode contact 224-2 and the second portion 204-2 of the fourth interlayer dielectric layer 204.

[0094] The second conductor 230 can be formed by forming a conductive layer for the second conductor 230 over the second upper electrode contact 224-2 and the second portion 204-2, and by etching the conductive layer using a linear mask pattern extending in the second direction.

[0095] The semiconductor device comprising a first conductive line 210, a memory cell 220, and a second conductive line 230 can be formed using the process described above. The memory cell 220 may include a first lower electrode contact 221-1, a first uniform-thickness doped selector layer 222, a second lower electrode contact 221-2, a variable resistor layer 223, a first upper electrode contact 224-1, a second uniform-thickness doped selector layer 225, and a second upper electrode contact 224-2, which are stacked sequentially.

[0096] Memory cell 220 may include a first uniform-thickness doped selector layer 222 and a second uniform-thickness doped selector layer 225. In some embodiments, the first uniform-thickness doped selector layer 222 and the second uniform-thickness doped selector layer 225 may be formed of the same material as each other, thereby having the same operating characteristics and device operating conditions. With two uniform-thickness doped selector layers 222 and 225, bit cell operations at the corresponding addresses can be preserved even if either uniform-thickness doped selector layer 222 or 225 is not operational.

[0097] According to the semiconductor device described above, the first uniform-thickness doped selector layer 222 and the second uniform-thickness doped selector layer 225 can be formed by converting a portion of the lower electrode contact 221 and a portion of the upper electrode contact 224 into dielectric layers instead of forming additional dielectric layers for the first uniform-thickness doped selector layer 222 and the second uniform-thickness doped selector layer 225, and then introducing dopant into said portions. Therefore, the height of the memory cell 220 does not need to be increased, thereby improving the hard mask margin and preventing etch damage during the patterning process of the first uniform-thickness doped selector layer 222 and the second uniform-thickness doped selector layer 225.

[0098] Figure 2G The substrate 200, first conductive line 210, first lower electrode contact 221-1, first uniform thickness doped selector layer 222, second lower electrode contact 221-2, variable resistor layer 223, first upper electrode contact 224-1, second uniform thickness doped selector layer 225, second upper electrode contact 224-2, and second conductive line 230 shown can correspond to the substrate 100, first conductive line 110, first lower electrode contact 121-1, first uniform thickness doped selector layer 122, second lower electrode contact 121-2, variable resistor layer 123, first upper electrode contact 124-1, second uniform thickness doped selector layer 125, second upper electrode contact 124-2, and second conductive line 130.

[0099] In some embodiments, the semiconductor device may include: a first conductor configured to electrically connect two or more circuit elements in the semiconductor device; a second conductor configured to electrically connect two or more circuit elements in the semiconductor device and disposed above and spaced apart from the first conductor; a variable resistance layer disposed above the first conductor and below the second conductor; at least one of a first dielectric layer and a second dielectric layer, the first dielectric layer including a first through-hole disposed between the first conductor and the variable resistance layer, the second dielectric layer including a second through-hole disposed between the variable resistance layer and the second conductor; at least one of a first contact and a second contact, the first contact being configured to include a conductive material filling the first through-hole, the second contact being configured to include a conductive material filling the second through-hole, the first contact including a first contact portion and a second contact portion spaced apart from each other, and the second contact including a third contact portion and a fourth contact portion spaced apart from each other; and at least one of a first uniform-thickness doped selector layer and a second uniform-thickness doped selector layer. The first uniform-thickness doped selector layer may include: a first selector element portion located between a first contact portion and a second contact portion; and a second selector element portion disposed in the first dielectric layer and spaced apart from the upper surface and the lower surface of the first dielectric layer; and the second uniform-thickness doped selector layer may include: a third selector element portion located between a third contact portion and a fourth contact portion; and a fourth selector element portion disposed in the second dielectric layer and spaced apart from the upper surface and the lower surface of the second dielectric layer. Here, the first dielectric layer may include a second interlayer dielectric layer 202, and the second dielectric layer may include a fourth interlayer dielectric layer 204.

[0100] The aforementioned semiconductor device may include a first uniform-thickness doped selector layer 222 and a second uniform-thickness doped selector layer 225. However, the semiconductor device may include either the first uniform-thickness doped selector layer 222 or the second uniform-thickness doped selector layer 225. This will be referred to... Figures 3A to 3D and Figures 4A to 3D Detailed description.

[0101] Figures 3A to 3D This is a cross-sectional view illustrating another example method of manufacturing a semiconductor device based on certain embodiments of the technology disclosed herein.

[0102] Figures 3A to 3D The semiconductor device shown is similar to Figures 2A to 2G The semiconductor device shown includes only one uniformly thick doped selector layer (see [link]). Figure 3C (Ref. 322). Figures 3A to 3D The implementation shown will focus on the above. Figures 2A to 2G The differences between the embodiments shown are described.

[0103] refer to Figure 3A A first conductive line 310, a first interlayer dielectric layer 301, a lower electrode contact 321, and a second interlayer dielectric layer 302 can be formed on a substrate 300 with a predetermined structure.

[0104] refer to Figure 3B A first ion implantation process can be performed on a portion of the lower electrode contact 321 spaced apart from the upper and lower surfaces, and on a portion of the second interlayer dielectric layer 302 spaced apart from the upper and lower surfaces, to incorporate oxygen, nitrogen, or a combination thereof into the portions of the lower electrode contact 321 and the second interlayer dielectric layer 302. The first ion implantation process can be a process that transforms the portions of the lower electrode contact 321 and the second interlayer dielectric layer 302 into dielectric layers through oxidation, nitriding, or nitrogen oxidation. Since the second dielectric layer 302 is initially formed of a dielectric material, it retains its dielectric properties even after oxygen and / or nitrogen are introduced through the first ion implantation process.

[0105] In the first ion implantation process, a uniformly thick doped selector layer can be considered for formation in subsequent processes (see [link]). Figure 3C The position and thickness of the reference mark 322) are adjusted to adjust the projected range (Rp).

[0106] A first material layer 322A can be formed in the lower electrode contact 321 using a first ion implantation process, and a second material layer 322B can be formed in the second interlayer dielectric layer 302. The first material layer 322A and the second material layer 322B may include a dielectric material. In some embodiments, the first material layer 322A and the second material layer 322B may include different dielectric materials. The lower electrode contact 321 below the first material layer 322A and the lower electrode contact 321 above the first material layer 322A are respectively referred to as the first lower electrode contact 321-1 and the second lower electrode contact 321-2. The first lower electrode contact 321-1 and the second lower electrode contact 321-2 may have the same thickness or different thicknesses. The second interlayer dielectric layer 302 below the second material layer 322B and the second interlayer dielectric layer 302 above the second material layer 322B may be respectively referred to as the first portion 302-1 and the second portion 302-2 of the second interlayer dielectric layer 302. Part 302-1 and Part 302-2 may have the same thickness or different thicknesses.

[0107] refer to Figure 3C A uniform-thickness doped selector layer 322 can be formed by incorporating dopants through a second ion implantation process on the first material layer 322A and the second material layer 322B.

[0108] The uniform-thickness doped selector layer 322 may include: a first portion 322-1, which is located between the first lower electrode contact 321-1 and the second lower electrode contact 321-2; and a second portion 322-2, which is located between the first portion 302-1 and the second portion 302-2 of the second interlayer dielectric layer 302. That is, the uniform-thickness doped selector layer 322 may be located in a uniform-thickness doped manner between the first lower electrode contact 321-1 and the second lower electrode contact 321-2 and between the first portion 302-1 and the second portion 302-2 of the second interlayer dielectric layer 302.

[0109] refer to Figure 3D A variable resistance layer 323 can be formed above the second lower electrode contact 321-2. The variable resistance layer 323 can be formed by... Figure 3C A material layer for the variable resistance layer 323 is formed on the structure and the material layer is patterned to form the structure. Therefore, a memory cell 320 can be formed, which includes a first lower contact 321-1, a uniform-thickness doped selector layer 322, a second lower contact 321-2, and a variable resistance layer 323. Then, a third interlayer dielectric layer 303 can be formed.

[0110] Then, a second conductor 330 can be formed above the variable resistance layer 323 and the third interlayer dielectric layer 303.

[0111] The second conductor 230 can be formed by forming a conductive layer for the second conductor 230 over the variable resistance layer 323 and the third interlayer dielectric layer 303, and by etching the conductive layer using a linear mask pattern extending in the second direction.

[0112] The semiconductor device comprising a first conductive line 310, a memory cell 320, and a second conductive line 330 can be formed using the process described above. The memory cell 320 may include a first lower electrode contact 321-1, a uniform-thickness doped selector layer 322, a second lower electrode contact 321-2, and a variable resistance layer 323, which are stacked sequentially.

[0113] Figure 3D The substrate 300, first conductive line 310, first lower electrode contact 321-1, uniform thickness doped selector layer 322, second lower electrode contact 321-2, variable resistor layer 323, and second conductive line 330 shown can respectively correspond to Figure 1B The substrate 100, first conductive line 110, first lower electrode contact 121-1, first uniform-thickness doped selector layer 122, second lower electrode contact 121-2, variable resistor layer 123, and second conductive line 130 shown correspond to respectively Figure 2GThe substrate 200, first conductive line 210, first lower electrode contact 221-1, uniform thickness doped selector layer 222, second lower electrode contact 221-2, variable resistance layer 223, and second conductive line 230 are shown.

[0114] Figures 4A to 4D This is a cross-sectional view illustrating yet another example of a method for manufacturing a semiconductor device based on certain embodiments of the present disclosure.

[0115] Figure 4A The semiconductor device shown in the 4D diagram is similar to Figures 2A to 2G The semiconductor device shown includes only one uniformly thick doped selector layer (see [link]). Figure 4C (Ref. 425). Figures 4A to 4D The embodiments shown will focus on the above. Figures 2A to 2G The differences between the embodiments shown are described.

[0116] refer to Figure 4A A first conductive line 410, a first interlayer dielectric layer 401, a variable resistor layer 423, a second interlayer dielectric layer 403, an upper electrode contact 424, and a third interlayer dielectric layer 404 can be formed above a substrate 400 in which a predetermined structure is formed.

[0117] refer to Figure 4B A first ion implantation process can be performed on a portion spaced apart from the upper and lower surfaces of the upper electrode contact 424 and a portion spaced apart from the upper and lower surfaces of the third interlayer dielectric layer 404 to incorporate oxygen, nitrogen, or a combination thereof into said portions of the upper electrode contact 424 and the third interlayer dielectric layer 404. The first ion implantation process can be a process for converting a portion of the upper electrode contact and a portion of the third interlayer dielectric layer 404 into a dielectric layer by oxidation, nitridation, or nitrogen oxidation. Since the third interlayer dielectric layer 404 is initially formed of a dielectric material, it can retain its dielectric properties even after oxygen and / or nitrogen are introduced through the first ion implantation process.

[0118] In the first ion implantation process, a first uniform-thickness doped selector layer can be considered for formation in subsequent processes (see [link]). Figure 4C The position and thickness of the reference mark 425 are used to adjust the projected range (Rp).

[0119] A first material layer 425A can be formed in the upper electrode contact 424 using a first ion implantation process, and a second material layer 425B can be formed in the third interlayer dielectric layer 404. The upper electrode contact 424 below the first material layer 425A and the upper electrode contact 424 above the first material layer 425A can be referred to as the first upper electrode contact 424-1 and the second upper electrode contact 424-2, respectively. The third interlayer dielectric layer 404 below the second material layer 425B and the third interlayer dielectric layer 404 above the second material layer 425B can be referred to as the first portion 404-1 and the second portion 404-2 of the third interlayer dielectric layer 404, respectively. The first material layer 425A and the second material layer 425B can include dielectric materials. In some embodiments, the first material layer 425A and the second material layer 425B can include dielectric materials that are different from each other.

[0120] refer to Figure 4C A uniform-thickness doped selector layer 425 can be formed by incorporating dopants through a second ion implantation process on the first material layer 425A and the second material layer 425B.

[0121] The uniform-thickness doped selector layer 425 may include: a first portion 425-1, which is located between the first upper electrode contact 424-1 and the second upper electrode contact 424-2; and a second portion 425-2, which is located between the first portion 404-1 and the second portion 404-2 of the third interlayer dielectric layer 404. That is, the uniform-thickness doped selector layer 425 may be located in a uniform-thickness doped manner between the first upper electrode contact 424-1 and the second upper electrode contact 424-2 and between the first portion 404-1 and the second portion 404-2 of the third interlayer dielectric layer 404.

[0122] Therefore, a memory cell 420 can be formed, which includes a variable resistance layer 423, a first upper contact 424-1, a uniform thickness doped selector layer 425, and a second upper contact 424-2.

[0123] refer to Figure 4D A second conductor 330 can be formed above the second upper electrode contact 424-2 and the second portion 404-2 of the third interlayer dielectric layer 404.

[0124] The semiconductor device comprising a first conductive line 410, a memory cell 420, and a second conductive line 430 can be formed using the process described above. The memory cell 420 may include a variable resistor layer 423, a first upper contact 424-1, a uniform-thickness doped selector layer 425, and a second upper contact 424-2, which are stacked sequentially.

[0125] The substrate 400, the first conductive line 410, the variable resistor layer 423, the first upper electrode contact 424-1, the uniform thickness doped selector layer 425, the second upper electrode contact 424-2, and the second conductive line 430 can respectively correspond to Figure 1B The substrate 100, first conductive line 110, first upper electrode contact 124-1, second uniform-thickness doped selector layer 125, second upper electrode contact 124-2, and second conductive line 130 shown correspond to respectively Figure 2G The substrate 200, first conductive line 210, resistive layer 223, first upper electrode contact 224-1, second uniform thickness doped selector layer 225, second upper electrode contact 224-2, and second conductive line 230 are shown.

[0126] While this patent document contains numerous details, it should not be construed as a limitation on any scope of disclosure or potentially claimed protection, but rather as a description of features that may be specific to particular embodiments of a particular disclosure. Certain features described in the context of different embodiments in this patent document may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments. Furthermore, although features may be described above as functioning in a particular combination, or even initially claimed to be so, in certain circumstances one or more features from a claimed combination may be removed from said combination, and the claimed combination may involve sub-combinations or variations thereof.

[0127] Similarly, although the operations are depicted in a specific order in the accompanying drawings, it should not be construed as requiring these operations to be performed in the specific order shown or in sequential order, or as requiring all the operations shown to achieve the desired result. Furthermore, the separation of various system components in the embodiments described in this patent document should not be construed as requiring such separation in all embodiments.

[0128] Only a few embodiments and examples have been described. Improvements, modifications, and other embodiments of the disclosed embodiments can be made based on the description and illustrations in this patent document.

Claims

1. A semiconductor device, comprising: First conductor; The second conductor is positioned above the first conductor and spaced apart from it; A variable resistance layer is disposed above the first conductor and below the second conductor; At least one of a first dielectric layer or a second dielectric layer, wherein the first dielectric layer includes a first through-hole disposed between the first conductor and the variable resistor layer, and the second dielectric layer includes a second through-hole disposed between the variable resistor layer and the second conductor; At least one of a first contact or a second contact, wherein the first contact is configured to include a conductive material filling the first through-hole and includes a first contact portion and a second contact portion spaced apart from each other; and the second contact is configured to include a conductive material filling the second through-hole and includes a third contact portion and a fourth contact portion spaced apart from each other; and At least one of a first doped selector layer or a second doped selector layer, wherein each of the first doped selector layer and the second doped selector layer comprises a dielectric material and a dopant, wherein the first doped selector layer comprises: a first selector portion between the first contact portion and the second contact portion, and a second selector portion disposed in the first dielectric layer and spaced apart from the upper surface and the lower surface of the first dielectric layer; the second doped selector layer comprises: a third selector portion between the third contact portion and the fourth contact portion, and a fourth selector portion disposed in the second dielectric layer and spaced apart from the upper surface and the lower surface of the second dielectric layer.

2. The semiconductor device of claim 1, wherein the first selection element portion and the second selection element portion of the first doped selector layer comprise dielectric materials that are different from each other.

3. The semiconductor device of claim 1, wherein the third selection element portion and the fourth selection element portion of the second doped selector layer comprise dielectric materials that are different from each other.

4. The semiconductor device of claim 1, wherein the first selection element portion and the third selection element portion comprise the same dielectric material and dopant.

5. The semiconductor device of claim 1, wherein the second selection element portion and the fourth selection element portion comprise the same dielectric material and dopant.

6. The semiconductor device of claim 1, wherein, Specifically, the first contact, the second contact, the first selection element portion, and the third selection element portion comprise two or more of the following: tungsten (W), titanium (Ti), tantalum (Ta), vanadium (V), chromium (Cr), platinum (Pt), aluminum (Al), copper (Cu), zinc (Zn), nickel (Ni), cobalt (Co), lead (Pb), manganese (Mn), niobium (Nb), tungsten nitride (WN), tungsten silicide (WSi), titanium nitride (TiN), titanium silicon nitride (TiSiN), aluminum titanium nitride (TiAlN), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), or aluminum tantalum nitride (TaAlN), or a combination of two or more of the following: tungsten (W), titanium (Ti), tantalum (Ta), vanadium (V), chromium (Cr), platinum (Pt), aluminum (Al), copper (Cu), zinc (Zn), nickel (Ni), cobalt (Co), lead (Pb), manganese (Mn), niobium (Nb), tungsten nitride (WN), tungsten silicide (WSi), titanium nitride (TiN), titanium silicon nitride (TiSiN), aluminum titanium nitride (TiAlN), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), or aluminum tantalum nitride (TaAlN).

7. The semiconductor device according to claim 1, wherein the dopant comprises one or more of boron (B), nitrogen (N), carbon (C), phosphorus (P), arsenic (As), aluminum (Al), silicon (Si), and germanium (Ge).

8. The semiconductor device of claim 1, wherein the distance from the upper surface of the first dielectric layer and the upper surface of the first contact to the upper surface of the first doped selector layer is the same as or different from the distance from the lower surface of the first dielectric layer and the lower surface of the first contact to the lower surface of the first doped selector layer.

9. The semiconductor device of claim 1, wherein the distance from the upper surface of the second dielectric layer and the upper surface of the second contact to the upper surface of the second doped selector layer is the same as or different from the distance from the lower surface of the second dielectric layer and the lower surface of the second contact to the lower surface of the second doped selector layer.

10. A method for manufacturing a semiconductor device includes: A first conductive line is formed above the substrate; A variable resistance layer is formed above the first conductor; A second conductor is formed above the variable resistance layer; A first dielectric layer is formed, the first dielectric layer including a through hole, the through hole being between the first conductor and the variable resistance layer, between the variable resistance layer and the second conductor, or both between the first conductor and the variable resistance layer and between the variable resistance layer and the second conductor; A contact is formed in the through hole; Perform a first ion implantation process to form a first sub-dielectric layer in the contact and form a second sub-dielectric layer in the first dielectric layer, by converting a portion of the contact into the first sub-dielectric layer and a portion of the first dielectric layer into the second sub-dielectric layer, such that the first sub-dielectric layer is spaced apart from the upper and lower surfaces of the contact and the second sub-dielectric layer is spaced apart from the upper and lower surfaces of the first dielectric layer; as well as A second ion implantation is performed to implant dopants into the first sub-dielectric layer and the second sub-dielectric layer to form a doped selector layer. The doped selector layer includes: a first portion comprising the first sub-dielectric layer and the dopant; The second part includes the second sub-dielectric layer and the dopant.

11. The method of claim 10, wherein the contact comprises a material capable of forming a dielectric material via the first ion implantation process using oxygen, nitrogen, or a combination of oxygen and nitrogen.

12. The method of claim 10, wherein the dopant doped by the second ion implantation process comprises one or more of boron (B), nitrogen (N), carbon (C), phosphorus (P), arsenic (As), aluminum (Al), silicon (Si), and germanium (Ge).

13. The method of claim 10, wherein the doped selector layer comprises a dielectric material and the dopant.

14. The method of claim 10, wherein the first sub-dielectric layer and the second sub-dielectric layer comprise dielectric materials that are different from each other.

15. The method of claim 10, wherein the first dielectric layer and the second sub-dielectric layer comprise the same dielectric material or different dielectric materials.

16. The method of claim 10, wherein the doped selector layer comprises a first doped selector layer formed between the first conductor and the variable resistance layer, and a second doped selector layer formed between the variable resistance layer and the second conductor, and The first portion of the first doped selector layer and the first portion of the second doped selector layer comprise the same material as each other, and the second portion of the first doped selector layer and the second portion of the second doped selector layer comprise the same material as each other.

17. The method of claim 10, wherein the contact and the first portion of the doped selector layer comprise two or more of the following: tungsten (W), titanium (Ti), tantalum (Ta), vanadium (V), chromium (Cr), platinum (Pt), aluminum (Al), copper (Cu), zinc (Zn), nickel (Ni), cobalt (Co), lead (Pb), manganese (Mn), niobium (Nb), tungsten nitride (WN), tungsten silicide (WSi), titanium nitride (TiN), titanium silicon nitride (TiSiN), aluminum titanium nitride (TiAlN), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), or aluminum tantalum nitride (TaAlN), or a combination of two or more of the following: tungsten (W), titanium (Ti), tantalum (Ta), vanadium (V), chromium (Cr), platinum (Pt), aluminum (Al), copper (Cu), zinc (Zn), nickel (Ni), cobalt (Co), lead (Pb), manganese (Mn), niobium (Nb), tungsten nitride (WN), tungsten silicide (WSi), titanium nitride (TiN), titanium silicon nitride (TiSiN), aluminum titanium nitride (TiAlN), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), or aluminum tantalum nitride (TaAlN).

18. The method of claim 10, wherein the distance from the upper surface of the first dielectric layer and the upper surface of the contact to the upper surface of the doped selector layer is the same as or different from the distance from the lower surface of the first dielectric layer and the lower surface of the contact to the lower surface of the doped selector layer.

Images