Three-dimensional memory devices and methods for forming the same

Abstract

In some aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes an array of NAND memory strings, a first peripheral circuit of the array of NAND memory strings including a first transistor, a polysilicon layer between the array of NAND memory strings and the first peripheral circuit, and a first semiconductor layer in contact with the first transistor. The polysilicon layer is in contact with a source of the array of NAND memory strings. The second semiconductor structure includes a second peripheral circuit of the array of NAND memory strings including a second transistor, and a second semiconductor layer in contact with the second transistor. The second semiconductor layer is between the bonding interface and the second semiconductor layer. The polysilicon layer is between the first semiconductor layer and the second semiconductor layer.

Description

BACKGROUND

[0001] The present disclosure relates to memory devices and methods of manufacturing the same.

[0002] Planar memory cells are scaled to smaller sizes by improving process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of memory cells approaches a lower limit, planar processes and manufacturing technology become challenging and costly. As a result, the memory density of planar memory cells approaches an upper limit.

[0003] Three-dimensional (3D) memory architectures can address the density limitations in planar memory cells. 3D memory architectures include a memory array and a peripheral circuit to facilitate operation of the memory array. SUMMARY

[0004] In one aspect, a 3D memory device includes a first semiconductor structure, a second semiconductor structure, and a bonded interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes an array of NAND memory strings, a first peripheral circuit of the array of NAND memory strings including a first transistor, a polysilicon layer between the array of NAND memory strings and the first peripheral circuit, and a first semiconductor layer in contact with the first transistor. The polysilicon layer is in contact with a source of the array of NAND memory strings. The second semiconductor structure includes a second peripheral circuit of the array of NAND memory strings including a second transistor, and a second semiconductor layer in contact with the second transistor. The second semiconductor layer is between the bonded interface and the second semiconductor layer. The polysilicon layer is between the first semiconductor layer and the second semiconductor layer.

[0005] In another aspect, a system includes a memory device configured to store data. The memory device includes a first semiconductor structure, a second semiconductor structure, and a bonded interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes an array of NAND memory strings, a first peripheral circuit of the array of NAND memory strings including a first transistor, a polysilicon layer between the array of NAND memory strings and the first peripheral circuit, and a first semiconductor layer in contact with the first transistor. The polysilicon layer is in contact with a source of the array of NAND memory strings. The second semiconductor structure includes a second peripheral circuit of the array of NAND memory strings including a second transistor, and a second semiconductor layer in contact with the second transistor. The second semiconductor layer is between the bonded interface and the second semiconductor layer. The polysilicon layer is between the first semiconductor layer and the second semiconductor layer. The system further includes a memory controller coupled to the memory device and configured to control the array of memory cells through the first peripheral circuit and the second peripheral circuit.

[0006] In yet another aspect, a method for forming a 3D memory device is disclosed. A first transistor is formed on a first substrate. A polysilicon layer is formed over the first transistor on the first substrate. An array of NAND memory strings is formed on the polysilicon layer. A second transistor is formed on a second substrate. The first substrate and the second substrate are bonded in a face-to-face manner. BRIEF DESCRIPTION OF DRAWINGS

[0007] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate aspects of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and to enable a person skilled in the relevant art to make and use the present disclosure.

[0008] Figure 1A A schematic diagram of a cross-section of a 3D memory device is shown in accordance with some aspects of the present disclosure.

[0009] Figure 1B A schematic diagram of a cross-section of another 3D memory device is shown in accordance with some aspects of the present disclosure.

[0010] Figure 2 A schematic circuit diagram of a memory device including a peripheral circuit is shown in accordance with some aspects of the present disclosure.

[0011] Figure 3 A block diagram of a memory device including an array of memory cells and a peripheral circuit is shown in accordance with some aspects of the present disclosure.

[0012] Figure 4A A block diagram of a peripheral circuit provided with various voltages is shown in accordance with some aspects of the present disclosure.

[0013] Figure 4B A schematic diagram of a peripheral circuit provided with various voltages arranged in separate semiconductor structures is shown in accordance with some aspects of the present disclosure.

[0014] Figure 5A And 5B Perspective and side views of a planar transistor are shown in accordance with some aspects of the present disclosure.

[0015] Figure 6A And 6B Perspective and side views of a 3D transistor are shown in accordance with some aspects of the present disclosure.

[0016] Figure 7 A circuit diagram of a word line driver and page buffer is shown in accordance with some aspects of the present disclosure.

[0017] Figure 8A side view of a NAND memory string in a 3D memory device is shown in accordance with some aspects of the disclosure.

[0018] Figure 9A and 9B A schematic diagram of a cross-section of a 3D memory device having two stacked semiconductor structures is shown in accordance with various aspects of the disclosure.

[0019] Figure 10 A schematic diagram of a cross-section of a 3D memory device in Figure 9A and 9B is shown in accordance with various aspects of the disclosure.

[0020] Figure 11A and 11B A side view of various examples of a 3D memory device in Figure 10 is shown in accordance with various aspects of the disclosure.

[0021] Figure 12A-12G A flow diagram of a method for forming a 3D memory device in Figure 10 is shown in accordance with some aspects of the disclosure.

[0022] Figure 13A and 13B Another manufacturing process for forming a 3D memory device in Figure 10 is shown in accordance with some aspects of the disclosure.

[0023] Figure 14 A flow diagram of a method for forming a 3D memory device in Figure 10 is shown in accordance with some aspects of the disclosure.

[0024] Figure 15A and 15B A schematic diagram of a cross-section of a 3D memory device in Figure 9A and 9B is shown in accordance with various aspects of the disclosure.

[0025] Figure 16A and 16B A side view of various examples of a 3D memory device in Figure 15A and 15B is shown in accordance with various aspects of the disclosure.

[0026] Figures 17A-17H A manufacturing process for forming a 3D memory device in Figure 15A and 15B is shown in accordance with some aspects of the disclosure.

[0027] Figures 18A-18FAnother manufacturing process for forming a 3D memory device in Figure 15A and 15B is shown.

[0028] Figure 19 A flowchart of a method for forming a 3D memory device in Figure 15A and 15B is shown.

[0029] Figure 20 A flowchart of a method for forming a 3D memory device in Figure 15A and 15B is shown.

[0030] Figure 21A and 21B A schematic diagram of a cross-section of a 3D memory device having two stacked semiconductor structures according to various aspects of the present disclosure is shown.

[0031] Figure 22A and 22B A schematic diagram of a cross-section of a 3D memory device in Figure 21A and 21B is shown.

[0032] Figure 23A and 23B A side view of various examples of a 3D memory device in Figure 22A and 22B is shown.

[0033] Figures 24A-24F A manufacturing process for forming a 3D memory device in Figure 22A and 22B is shown.

[0034] Figure 25A-25G Another manufacturing process for forming a 3D memory device in Figure 22A and 22B is shown.

[0035] Figure 26 A flowchart of a method for forming a 3D memory device in Figure 22A and 22B is shown.

[0036] Figure 27 A flowchart of a method for forming a 3D memory device in Figure 22A and 22Ba flowchart of another method of forming a 3D memory device in

[0037] Figure 28A and 28B shows a schematic diagram of a cross-section of a 3D memory device in accordance with some aspects of the present disclosure. Figure 21A and 21B shows a schematic diagram of a cross-section of a 3D memory device in accordance with some aspects of the present disclosure.

[0038] Figure 29A and 29B shows a side view of various examples of a 3D memory device in accordance with various aspects of the present disclosure. Figure 28A and 28B shows a side view of various examples of a 3D memory device in accordance with various aspects of the present disclosure.

[0039] Figure 30A-30G shows a flowchart of a method of forming a 3D memory device in accordance with some aspects of the present disclosure. Figure 28A and 28B shows a flowchart of a method of forming a 3D memory device in accordance with some aspects of the present disclosure.

[0040] Figures 31A to 31H shows a flowchart of another method of forming a 3D memory device in accordance with some aspects of the present disclosure. Figure 28A and 28B shows a flowchart of another method of forming a 3D memory device in accordance with some aspects of the present disclosure.

[0041] Figure 32 shows a flowchart of a method of forming a 3D memory device in accordance with some aspects of the present disclosure. Figure 28A and 28B shows a flowchart of a method of forming a 3D memory device in accordance with some aspects of the present disclosure.

[0042] Figure 33 shows a flowchart of another method of forming a 3D memory device in accordance with some aspects of the present disclosure. Figure 28A and 28B shows a flowchart of another method of forming a 3D memory device in accordance with some aspects of the present disclosure.

[0043] Figures 34A-34D shows a flowchart of a method of forming a 3D memory device in accordance with some aspects of the present disclosure.

[0044] Figures 35A-35D shows a flowchart of another method of forming a 3D memory device in accordance with some aspects of the present disclosure.

[0045] Figure 36 shows a block diagram of an exemplary system having a memory device in accordance with some aspects of the present disclosure.

[0046] Figure 37A shows a diagram of an exemplary memory card having a memory device in accordance with some aspects of the present disclosure.

[0047] Figure 37BA diagram illustrating an exemplary solid state drive (SSD) with memory devices is shown in accordance with some aspects of the present disclosure.

[0048] The present disclosure will be illustrated by way of example with reference to the accompanying drawings. DETAILED DESCRIPTION

[0049] While specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. Other configurations and arrangements can be employed without departing from the scope of the present disclosure. Additionally, the present disclosure is likewise applicable to various other applications. The functions and structures described in this disclosure can be combined, adjusted, and modified in ways that are not specifically shown in the drawings, such that these combinations, adjustments, and modifications are within the scope of the present disclosure.

[0050] Generally, terminology can be understood at least in part from usage in context. For example, the term “one or more” as used herein, depending at least in part upon context, can be used to describe any feature, structure, or characteristic in the singular or can be used to describe combinations of features, structures or characteristics. Similarly, terms such as “a” and “the” are intended to be interpreted in accordance with their context and are likewise open to be used in a singular or plural sense, depending at least in part on how the iteration is used

[0051] It should be readily understood that the terms “on,” “over,” and “above,” in the present disclosure, are to be interpreted in the broadest relative terms consistent with their context, such that “on” means not only “directly on” but also includes the meaning of “on” with intervening features or layers therebetween, and “over” or “above” means not only “over” or “above” but also can include the meaning of “over” or “above” without intervening features or layers therebetween (i.e., directly over).

[0052] Further, to facilitate description, spatially relative terms— such as “beneath,” “below,” “lower,” “above,” “upper,” and the like— can be used herein for describing elemental and feature relationships when the apparatus is illustrated in the drawings and / or as used in the text. Spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to the orientations shown in the drawings. The apparatus can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0053] As used herein, the term "layer" refers to a portion of material that includes a region having a thickness. A layer can extend over an entire underlying or overlying structure, or can have an area less than the area of the underlying or overlying structure. Further, a layer can be a region of uniform or non-uniform thickness that is less than the thickness of a continuous structure. For example, a layer can be between any pair of lateral planes between a top surface and a bottom surface of a continuous structure or at the top and bottom surfaces. A layer can extend laterally, vertically, and / or along a tapered surface. A substrate can be a layer, wherein one or more layers can be included therein, and / or one or more layers can be provided thereon, over and / or under. A layer can include multiple layers. For example, an interconnect layer can include one or more conductor and contact layers (in which interconnect lines and / or vertical interconnect access (via) contacts are formed) and one or more dielectric layers.

[0054] As 3D memory devices (e.g., 3D NAND flash memory devices) have developed, more stacked layers (e.g., more word lines and the resulting more memory cells) have required more peripheral circuitry (and components forming the peripheral circuitry, e.g., transistors) for operating the 3D memory devices. For example, the number and / or size of page buffers have needed to increase to match the increased number of memory cells. In another example, the number of string drivers in a word line driver is proportional to the number of word lines in a 3D NAND flash memory. Thus, the ever-increasing number of word lines has also increased the area occupied by the word line drivers, as well as the complexity of the metal routing, and sometimes even the number of metal layers. Further, in 3D memory devices in which some of the peripheral circuitry is fabricated under the memory cell array, sometimes referred to as a "peripheral under cell" (PUC) architecture or a "complementary metal-oxide-semiconductor (CMOS) under array" (CuA) architecture, the ever-increasing area of the peripheral circuitry has made it a bottleneck for reducing the overall chip size, as the memory cell array can be scaled up vertically by increasing the number of levels rather than increasing the planar size.

[0055] Accordingly, it is desirable to reduce the planar area occupied by the peripheral circuitry of a 3D memory device as the number of peripheral circuitry and its transistors increases. However, scaling down the transistor size of the peripheral circuitry following the advanced CMOS technology node trend for logic devices would result in significant cost increase and higher leakage current, which is undesirable for memory devices. Further, because 3D NAND flash memory devices require relatively high voltages (e.g., higher than 5V) in certain memory operations (e.g., program and erase), unlike logic devices, which can lower their operating voltage as the CMOS technology node advances, the voltage provided to the memory peripheral circuitry cannot be lowered. Thus, scaling down the memory peripheral circuitry size by following the trend of advancing the CMOS technology node, as ordinary logic devices, becomes infeasible.

[0056] To address one or more of the concerns described above, the present disclosure introduces various solutions in which the peripheral circuits of a memory device are disposed in different planes (levels, tiers) in a vertical direction, i.e., stacked on top of each other, to reduce the planar chip size of the peripheral circuits and the overall chip size of the memory device. In some embodiments, the memory cell arrays (e.g., NAND memory strings), the memory peripheral circuits provided with a relatively high voltage (e.g., higher than 3.3V), and the memory peripheral circuits provided with a relatively low voltage (e.g., lower than 2V) are disposed in different planes in a vertical direction, i.e., stacked on top of each other, to further reduce the chip size. The 3D memory device architecture and fabrication process disclosed herein can be easily scaled vertically to stack more peripheral circuits in different planes to further reduce the chip size. In addition, the 3D memory device architecture and fabrication process disclosed herein can be compatible with the PUC / CuA architecture and process. In some embodiments, as opposed to a single crystalline silicon substrate, the memory cell arrays (e.g., NAND memory strings) can be formed on a deposited polysilicon (also referred to as poly) layer (e.g., in contact with a poly source plate), which is suitable for certain designs of the channel structure in “floating gate” type of NAND memory strings or “charge trapping” type of NAND memory strings, e.g., suitable for gate induced drain leakage (GIDL) erase operations.

[0057] Based on different performance requirements, e.g., the voltage applied to the transistors of the peripheral circuits, which affects the size of the transistors (e.g., gate dielectric thickness), the size of the substrate in which the transistors are formed (e.g., substrate thickness), and the thermal budget (e.g., interconnect material), the peripheral circuits can be separated into different planes in a vertical direction. Thus, the peripheral circuits with different size requirements (e.g., gate dielectric thickness and substrate thickness) and thermal budget can be fabricated in different processes to reduce the design and process constraints between each other, thereby improving the device performance and fabrication complexity.

[0058] According to some aspects of the disclosure, arrays of memory cells with different performance and size requirements and various peripheral circuits can be fabricated on different substrates in parallel, and then stacked on top of each other using various bonding techniques such as hybrid bonding, transfer bonding, etc. As a result, the fabrication cycle of the memory device can be further reduced. Moreover, since the thermal budget of different devices becomes independent of each other, interconnect materials such as copper, which have desirable electrical performance but have low thermal budget, can be used to interconnect the memory cells and transistors of the peripheral circuits, further improving the device performance. The bonding techniques can also introduce additional benefits. In some embodiments, hybrid bonding in a face-to-face manner enables millions of parallel short interconnects between the bonded semiconductor structures to increase the throughput and input / output (I / O) speed of the memory device. In some embodiments, transfer bonding reuses a single wafer to transfer its thin semiconductor layer onto a different memory device for forming transistors thereon, which can reduce the cost of the memory device.

[0059] The 3D memory device architecture and fabrication process disclosed in the present disclosure also has the flexibility to allow various device pad-out schemes to meet the different needs and different designs of the array of memory cells. In some embodiments, the pad-out interconnect layer is formed from the side of the semiconductor structure that has the peripheral circuits to shorten the interconnect distance between the pad-out interconnect layer and the transistors of the peripheral circuits, reducing the parasitic capacitance from the interconnects and improving the electrical performance. In some embodiments, the pad-out interconnect layer is formed on a thinned substrate to enable layer-to-layer vias (LLVs, e.g., sub-micron) for pad-out interconnects with high I / O throughput and low fabrication complexity.

[0060] Figure 1A A schematic diagram of a cross-section of a 3D memory device 100 is shown, according to some aspects of the disclosure. The 3D memory device 100 represents an example of a bonded chip. In some embodiments, the components of the 3D memory device 100 (e.g., the array of memory cells and the peripheral circuits) are formed separately and in parallel on different substrates and then bonded to form the bonded chip (a process referred to herein as a “parallel process”). In some embodiments, a transfer bonding is used to attach a semiconductor layer (e.g., single crystalline silicon) onto another semiconductor structure, and then some components of the 3D memory device 100 (e.g., some of the peripheral circuits) are formed on the attached semiconductor layer (a process referred to herein as a “serial process”).

[0061] Note that, in some embodiments, the 3D memory device 100 is formed using a parallel process. In some embodiments, the 3D memory device 100 is formed using a serial process. Figure 1AThe x- and y-axes are added to further illustrate the spatial relationship of components of the semiconductor device. A substrate of a semiconductor device (e.g., 3D memory device 100) includes two lateral surfaces (e.g., top and bottom surfaces) that extend laterally in the x-direction (lateral direction or width direction). As used herein, one component (e.g., layer or device) of a semiconductor device is determined to be “on,” “above,” or “below” another component (e.g., layer or device) relative to the substrate of the semiconductor device in the y-direction when the substrate is positioned in the lowest plane of the semiconductor device in the y-direction (vertical direction or thickness direction). The same concept is applied throughout the present disclosure for describing spatial relationships.

[0062] 3D memory device 100 can include a first semiconductor structure 102 that includes an array of memory cells (also referred to herein as a “memory cell array”). In some embodiments, the memory cell array includes a NAND flash memory cell array. For ease of description, a NAND flash memory cell array can be used as an example to describe a memory cell array in the present disclosure. However, it should be understood that the memory cell array is not limited to a NAND flash memory cell array, and can include any other suitable type of memory cell array, such as a NOR flash memory cell array, a phase change memory (PCM) cell array, a resistive memory cell array, a magnetic memory cell array, a spin transfer torque (STT) memory cell array, just to name a few examples.

[0063] The first semiconductor structure 102 can be a NAND flash memory device in which memory cells are provided in the form of an array of 3D NAND memory strings and / or an array of two-dimensional (2D) NAND memory cells. The NAND memory cells can be organized into pages or fingers that are then organized into blocks, with each NAND memory cell coupled to a separate line called a bit line (BL). All cells in a NAND memory cell that have the same vertical position can be coupled by a control gate via a word line (WL). In some embodiments, a memory plane contains a certain number of blocks that are coupled by the same bit line. The first semiconductor structure 102 can include one or more memory planes, while the peripheral circuitry required to perform all read / program (write) / erase operations can be included in the second semiconductor structure 104 and the first semiconductor structure 102.

[0064] In some embodiments, the NAND memory cell array is a 2D NAND memory cell array, each of which includes a floating-gate transistor. According to some embodiments, the 2D NAND memory cell array includes multiple 2D NAND memory strings, each of which includes multiple memory cells (similar to NAND gates) connected in series and two select transistors. According to some embodiments, each 2D NAND memory string is arranged in the same plane on the substrate (i.e., a flat two-dimensional (2D) surface herein, which differs from the term "memory plane" in this disclosure). In some embodiments, the NAND memory cell array is a 3D NAND memory string array, each of which extends vertically above the substrate through a stacked layer structure (e.g., a memory stack) (in 3D). Depending on the 3D NAND technology (e.g., the number of layers / levels in the memory stack), a 3D NAND memory string typically includes a certain number of memory cells, each of which includes a floating-gate transistor or a charge-trapping transistor.

[0065] Consistent with the scope of this disclosure, the first semiconductor structure 102 may further include a polysilicon layer 106 on which a memory cell array is formed. In some embodiments, the memory cell array includes an array of NAND memory strings, and the polysilicon layer 106 is in contact with the source of the NAND memory strings. That is, the polysilicon layer 106 can serve as a common source plate for multiple NAND memory strings. As described in detail below, the polysilicon layer 106 can be formed in the first semiconductor structure 102 using one or more thin-film deposition processes (including, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof compatible with PUC / CuA processes). It should be understood that in some examples, the polysilicon layer 106 may typically be a semiconductor layer not limited to polysilicon.

[0066] like Figure 1A As shown, the first semiconductor structure 102 may further include some of the peripheral circuitry of the memory cell array, and the memory cell array and peripheral circuitry in the first semiconductor structure 102 may be separated in the vertical direction by a polysilicon layer 106. That is, the polysilicon layer 106 may be vertically disposed between the memory cell array and the peripheral circuitry in the first semiconductor structure 102. In some embodiments, the peripheral circuitry is disposed below the polysilicon layer 106 and the memory cell array formed thereon. Depending on the thickness of the polysilicon layer 106, interconnects (e.g., submicron-level interlayer vias (ILVs) or micron-level or tens of micron-level through-substrate vias (TSVs)) may be formed through the polysilicon layer 106 to form direct, short-distance (e.g., submicron to tens of micron-level) electrical connections between the memory cell array and the peripheral circuitry in the first semiconductor structure 102.

[0067] As shown in Figure 1A , the 3D memory device 100 can also include a second semiconductor structure 104 that includes some of the peripheral circuitry of the memory cell array of the first semiconductor structure 102. That is, the peripheral circuitry of the memory cell array can be split into at least two semiconductor structures (e.g., 102 and 104 in Figure 1A ). The peripheral circuitry (also referred to as control and sense circuitry) can include any suitable digital, analog, and / or mixed-signal circuitry for facilitating operation of the memory cell array. For example, the peripheral circuitry can include one or more of a page buffer, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), I / O circuitry, charge pumps, voltage sources or generators, current or voltage references, any portion of the above-mentioned functional circuitry (e.g., sub-circuits), or any active or passive components of the circuitry (e.g., transistors, diodes, resistors, or capacitors). The peripheral circuitry in the first semiconductor structure 102 and the second semiconductor structure 104 can use CMOS technology, for example, which can be implemented with a logic process in any suitable technology node.

[0068] As shown in Figure 1A , according to some embodiments, the first semiconductor structure 102 and the second semiconductor structure 104 are stacked on top of each other in different planes. As a result, the memory cell array in the first semiconductor structure 102, the peripheral circuitry in the first semiconductor structure 102, and the peripheral circuitry in the second semiconductor structure 104 can be stacked on top of each other in different planes to reduce the planar size of the 3D memory device 100, as compared to a memory device in which all of the peripheral circuitry is disposed in the same plane.

[0069] As shown in Figure 1A , the 3D memory device 100 further includes a bonding interface 103 vertically between the first semiconductor structure 102 and the second semiconductor structure 104. The bonding interface 103 can be an interface between the two semiconductor structures formed by any suitable bonding technique as described in detail below, such as hybrid bonding, anodic bonding, fusion bonding, transfer bonding, adhesive bonding, eutectic bonding, to name a few.

[0070] It should be appreciated that the relative positions of the stacked first semiconductor structure 102 and the stacked second semiconductor structure 104 are not limited and can vary in different examples. Figure 1B A schematic diagram showing a cross-section of another exemplary 3D memory device 101 is shown according to some embodiments. Unlike the 3D memory device 100 in Figure 1A , in which the memory cell array in the first semiconductor structure is vertically between the peripheral circuitry in the first semiconductor structure 102 and the peripheral circuitry in the second semiconductor structure 104, in the 3D memory device 101, the memory cell array in the first semiconductor structure 102 is vertically between the peripheral circuitry in the first semiconductor structure 102 and the peripheral circuitry in the second semiconductor structure 104. Figure 1B In 3D memory device 101, the peripheral circuit in first semiconductor structure 102 is vertically between the memory cell array in first semiconductor structure 102 and the peripheral circuit in second semiconductor structure. That is, second semiconductor structure 102 can be bonded to first semiconductor structure 102 on either side thereof, e.g., on the side on which the memory cell array is formed in 3D memory device 100, or on the side on which the peripheral circuit is formed in 3D memory device 101. Figure 1A In 3D memory device 100, the side on which the memory cell array is formed, or in 3D memory device 101, the side on which the peripheral circuit is formed. Figure 1B In 3D memory device 101, the side on which the peripheral circuit is formed. As a result, in contrast to 3D memory device 100 in which bonding interface 103 is formed vertically between second semiconductor structure 104 and the memory cell array of first semiconductor structure 102, bonding interface 105 is formed vertically between second semiconductor structure 104 and the peripheral circuit of first semiconductor structure 102. Like bonding interface 103, bonding interface 105 can be the interface between the two semiconductor structures formed by any suitable bonding technique as described in detail below, such as hybrid bonding, anodic bonding, fusion bonding, transfer bonding, adhesive bonding, eutectic bonding, to name a few.

[0071] As described in detail below, in some embodiments, first semiconductor structure 102 and second semiconductor structure 104 can be fabricated separately (and in some embodiments, in parallel) by parallel processes, such that the thermal budget of fabricating one of first semiconductor structure 102 and second semiconductor structure 104 does not limit the process of fabricating the other. Moreover, a large number of interconnects (e.g., bonding contacts and / or ILVs / TSVs) can be formed across bonding interface 103 or 105 to make direct, short distance (e.g., micron or sub-micron level) electrical connections between semiconductor structures 102 and 104, as opposed to long distance (e.g., millimeter or centimeter level) chip-to-chip data buses on a circuit board (e.g., printed circuit board (PCB)), thereby eliminating chip interface delays and enabling high speed I / O throughput at reduced power consumption. Data transfer between the memory cell array and the different peripheral circuit in different semiconductor structures 102 and 104 can be performed through the interconnects (e.g., bonding contacts and / or ILVs / TSVs) across bonding interface 103 or 105 and through polysilicon layer 106. By vertically integrating first semiconductor structure 102 and second semiconductor structure 104, and vertically separating the memory cell array and the peripheral circuit in first semiconductor structure 102 into different planes, chip size can be reduced, and memory cell density can be increased.

[0072] Figure 2A schematic circuit diagram of a memory device 200 including a peripheral circuit is shown in accordance with some aspects of the present disclosure. The memory device 200 can include a memory cell array 201 and a peripheral circuit 202 coupled to the memory cell array 201. The 3D memory devices 100 and 101 can be examples of memory devices 200 in which at least two portions of the memory cell array 201 and the peripheral circuit 202 can be included in different stacked semiconductor structures 102 and 104. The memory cell array 201 can be a NAND flash memory cell array in which memory cells 206 are provided in the form of an array of NAND memory strings 208, each extending vertically above a substrate (not shown). In some implementations, each NAND memory string 208 includes a plurality of memory cells 206 coupled in series and stacked vertically. Each memory cell 206 can hold a continuous analog value, such as a voltage or charge, depending on the number of electrons captured within a region of the memory cell 206. Each memory cell 206 can be a floating gate type of memory cell including a floating gate transistor, or a charge trap type of memory cell including a charge trap transistor.

[0073] In some implementations, each memory cell 206 is a single-level cell (SLC) having two possible memory states and thus can store one bit of data. For example, a first memory state "0" can correspond to a first voltage range, while a second memory state "1" can correspond to a second voltage range. In some implementations, each memory cell 206 is a multi-level cell (MLC) capable of storing more than a single bit of data in more than four memory states. For example, an MLC can store two bits per cell, three bits per cell (also referred to as a triple-level cell (TLC)), or four bits per cell (also referred to as a quad-level cell (QLC)). Each MLC can be programmed to take on a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed to take on one of three possible programmed levels from an erased state by writing one of three possible nominal storage values to the cell. A fourth nominal storage value can be used for the erased state.

[0074] As Figure 2As shown in FIG. 1, each NAND memory string 208 can include a source select gate (SSG) transistor 210 at its source end and a drain select gate (DSG) transistor 212 at its drain end. The SSG transistor 210 and the DSG transistor 212 can be configured to activate the selected NAND memory string 208 (column of the array) during read and program operations. In some embodiments, the SSG transistors 210 of the NAND memory strings 208 in the same block 204 are coupled to ground through the same source line (SL) 214 (e.g., common SL). According to some embodiments, the DSG transistor 212 of each NAND memory string 208 is coupled to a respective bit line 216 from which data can be read or programmed via an output bus (not shown). In some embodiments, each NAND memory string 208 is configured to be selected or not selected by applying a select voltage (e.g., above the threshold voltage of the DSG transistor 212) or a non-select voltage (e.g., 0 V) to the respective DSG transistor 212 via one or more DSG lines 213 and / or by applying a select voltage (e.g., above the threshold voltage of the SSG transistor 210) or a non-select voltage (e.g., 0 V) to the respective SSG transistor 210 via one or more SSG lines 215.

[0075] As Figure 2 As shown in FIG. 1, the NAND memory strings 208 can be organized into a plurality of blocks 204, each of which can have a common source line 214. In some embodiments, each block 204 is the basic unit of data for erase operations, i.e., all memory cells 206 on the same block 204 are erased simultaneously. The memory cells 206 of adjacent NAND memory strings 208 can be coupled by word lines 218, which select which row of memory cells 206 is affected by read and program operations. In some embodiments, each word line 218 is coupled to a page 220 of memory cells 206, which is the basic unit of data for program and read operations. The size in bits of a page 220 can correspond to the number of NAND memory strings 208 in a block 204 that are coupled by a word line 218. Each word line 218 can include a plurality of control gates (gate electrodes) at each memory cell 206 in the respective page 220 and a gate line that couples the control gates.

[0076] Figure 8 A side view of a NAND memory string 208 in a 3D memory device is shown in accordance with some aspects of the present disclosure. As Figure 8 As shown in FIG. 1, the NAND memory strings 208 can be organized into a plurality of blocks 204, each of which can have a common source line 214. In some embodiments, each block 204 is the basic unit of data for erase operations, i.e., all memory cells 206 on the same block 204 are erased simultaneously. The memory cells 206 of adjacent NAND memory strings 208 can be coupled by word lines 218, which select which row of memory cells 206 is affected by read and program operations. In some embodiments, each word line 218 is coupled to a page 220 of memory cells 206, which is the basic unit of data for program and read operations. The size in bits of a page 220 can correspond to the number of NAND memory strings 208 in a block 204 that are coupled by a word line 218. Each word line 218 can include a plurality of control gates (gate electrodes) at each memory cell 206 in the respective page 220 and a gate line that couples the control gates. Figure 1A and 1BAn example of polysilicon layer 106 is shown. The memory stack layer 804 may include interleaved gate conductive layers 806 and dielectric layers 808. The number of pairs of gate conductive layers 806 and dielectric layers 808 in the memory stack layer 804 determines the number of memory cells 206 in the memory cell array 201. The gate conductive layer 806 may include a conductive material, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicides, or any combination thereof. In some embodiments, each gate conductive layer 806 includes a metal layer, such as a tungsten layer. In some embodiments, each gate conductive layer 806 includes a doped polysilicon layer. Each gate conductive layer 806 may include a control gate surrounding a memory cell, a gate of a DSG transistor 212 or a gate of an SSG transistor 210, and may extend laterally as a DSG line 213 at the top of the memory stack 804, an SSG line 215 at the bottom of the memory stack 804, or a word line 218 between the DSG line 213 and the SSG line 215.

[0077] like Figure 8 As shown, the NAND memory string 208 includes a channel structure 812 extending vertically through a memory stack layer 804. In some embodiments, the channel structure 812 includes channel holes filled with one or more semiconductor materials (e.g., as a semiconductor channel 820) and one or more dielectric materials (e.g., as a memory film 818). In some embodiments, the semiconductor channel 820 includes silicon, such as polysilicon. In some embodiments, the memory film 818 is a composite dielectric layer including a tunneling layer 826, a storage layer 824 (also referred to as a "charge trap / storage layer"), and a barrier layer 822. The channel structure 812 may have a cylindrical shape (e.g., columnar). According to some embodiments, the semiconductor channel 820, tunneling layer 826, storage layer 824, and barrier layer 822 are arranged radially from the center of the column toward the outer surface in this order. The tunneling layer 826 may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer 824 may include silicon nitride, silicon oxynitride, silicon, or any combination thereof. The barrier layer 822 may comprise silicon oxide, silicon oxynitride, a high-k dielectric, or any combination thereof. In one example, the memory film 818 may comprise a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO). The channel structure 812 may also include a channel plug 816 on the drain terminal of the NAND memory string 208. The channel plug 816 may comprise polysilicon and contact the semiconductor channel 820.

[0078] In some embodiments, the polysilicon layer 805 contacts the semiconductor channel 820 of the channel structure 812 at the source end of the NAND memory string 208. A portion of the memory film 818 of the channel structure 812 at the source end can be removed to expose the semiconductor channel 820, thereby contacting the polysilicon layer 805. In some embodiments, the portion of the semiconductor channel 820 at the source end of the NAND memory string 208 is doped to form a doped region 832 in contact with the polysilicon layer 805. It should be understood that in some examples, the polysilicon layer 805 can be doped with the same dopant as the doped region 832, and the dopant can diffuse to portions of the semiconductor channel 820 to form the doped region 832. In some embodiments, the polysilicon layer 805 comprises N-type doped polysilicon to enable GILD erase operations.

[0079] like Figure 8 As shown, according to some embodiments, the slot structure 828 does not include any conductors (e.g., source contacts) and therefore is not used as part of the source line 214. Instead, source contacts (not shown) may be formed on the opposite side of the polysilicon layer 805 relative to the channel structure 812, such that the source contacts and portions of the polysilicon layer 805 can be used as portions of the source line 214 coupled to the source of the NAND memory string 208, for example, for applying an erase voltage to the source of the NAND memory string 208 during an erase operation.

[0080] Return to reference Figure 2 The peripheral circuitry 202 can be coupled to the memory cell array 201 via bit line 216, word line 218, source line 214, SSG line 215, and DSG line 213. As described above, the peripheral circuitry 202 can include any suitable circuitry for facilitating the operation of the memory cell array 201 by applying and sensing voltage and / or current signals traveling to and from each target memory cell 206 via bit line 216 through word line 218, source line 214, SSG line 215, and DSG line 213. The peripheral circuitry 202 can include various types of peripheral circuitry formed using MOS technology. For example, Figure 3 Some exemplary peripheral circuitry 202 is shown, including a page buffer 304, a column decoder / bit line driver 306, a row decoder / word line driver 308, a voltage generator 310, control logic 312, a register 314, an interface (I / F) 316, and a data bus 318. It should be understood that additional peripheral circuitry 202 may also be included in some examples.

[0081] The page buffer 304 can be configured to buffer data read from or programmed to the memory cell array 201 according to control signals of the control logic 312. In one example, the page buffer 304 can store a page of program data (write data) to program into a page 220 of the memory cell array 201. In another example, the page buffer 304 also performs a program verify operation to ensure that the data has been properly programmed into the memory cells 206 coupled to the selected word line 218.

[0082] The row decoder / word line driver 308 can be configured to be controlled by the control logic 312 and select a block 204 of the memory cell array 201 and a word line 218 of the selected block 204. The row decoder / word line driver 308 can be further configured to drive the memory cell array 201. For example, the row decoder / word line driver 308 can use a word line voltage generated from the voltage generator 310 to drive the memory cells 206 coupled to the selected word line 218.

[0083] The column decoder / bit line driver 306 can be configured to be controlled by the control logic 312 and select one or more 3D NAND memory strings 208 by applying a bit line voltage generated from the voltage generator 310. For example, the column decoder / bit line driver 306 can apply a column signal for selecting a set of N data bits from the page buffer 304 to be output in a read operation.

[0084] The control logic 312 can be coupled to each of the peripheral circuits 202 and configured to control the operation of the peripheral circuits 202. The registers 314 can be coupled to the control logic 312 and include status registers, command registers, and address registers for storing status information, command operation codes (OP codes), and command addresses for controlling the operation of each of the peripheral circuits 202.

[0085] The interface 316 can be coupled to the control logic 312 and configured to interface the memory cell array 201 with a memory controller (not shown). In some implementations, the interface 316 acts as a control buffer to buffer and relay control commands received from the memory controller and / or a host (not shown) to the control logic 312 and buffer and relay status information received from the control logic 312 to the memory controller and / or the host. The interface 316 can also be coupled to the page buffer 304 and the column decoder / bit line driver 306 via a data bus 318 and act as an I / O interface and data buffer to buffer and relay program data received from the memory controller and / or the host to the page buffer 304 and buffer and relay read data from the page buffer 304 to the memory controller and / or the host. In some implementations, the interface 316 and the data bus 318 are part of the I / O circuit of the peripheral circuits 202.

[0086] The voltage generator 310 can be configured to be controlled by the control logic 312 and to generate word line voltages (e.g., read voltages, program voltages, pass voltages, local voltages, and verify voltages) and bit line voltages to be provided to the memory cell array 201. In some implementations, the voltage generator 310 is part of a voltage source that provides various levels of voltages for different peripheral circuits 202, as described in detail below. Consistent with the scope of the disclosure, in some implementations, the voltages provided by the voltage generator 310 to, for example, the row decoder / word line driver 308, the column decoder / bit line driver 306, and the page buffer 304 are higher than certain levels sufficient to perform memory operations. For example, the voltages provided to page buffer circuits in the page buffer 304 and / or logic circuits in the control logic 312 can be between 2 V and 3.3 V, such as 3.3 V, and the voltages provided to driver circuits in the row decoder / word line driver 308 and / or the column decoder / bit line driver 306 can be between 5 V and 30 V.

[0087] Unlike logic devices (e.g., microprocessors), memory devices (e.g., 3D NAND flash memory) need to provide a wide range of voltages to different memory peripheral circuits. For example, Figure 4A A block diagram of peripheral circuits provided with various voltages is shown in accordance with some aspects of the disclosure. In some implementations, a memory device (e.g., the memory device 200) includes a low-low voltage (LLV) source 401, a low voltage (LV) source 403, and a high voltage (HV) source 405, each of which is configured to provide a voltage at a respective level (Vddl, Vdd2, or Vdd3). For example, Vdd3 > Vdd2 > Vddl. Each voltage source 401, 403, or 405 can receive a voltage input at an appropriate level from an external power source (e.g., a battery). Each voltage source 401, 403, or 405 can also include a voltage converter and / or a voltage regulator to convert the external voltage input to the respective level (Vddl, Vdd2, or Vdd3) and to maintain the voltage at the respective level (Vddl, Vdd2, or Vdd3) and output the voltage through a corresponding power rail. In some implementations, the voltage generator 310 of the memory device 200 is part of the voltage sources 401, 403, and 405.

[0088] In some implementations, the LLV source 401 is configured to provide a voltage below 2V, such as between 0.9V and 2V (e.g., 0.9V, 0.95V, 1V, 1.05V, 1.1V, 1.15V, 1.2V, 1.25V, 1.3V, 1.35V, 1.4V, 1.45V, 1.5V, 1.55V, 1.6V, 1.65V, 1.7V, 1.75V, 1.8V, 1.85V, 1.9V, 1.95V, any range bounded below by any of these values, or in any range bounded by any two of these values). In one example, the voltage is 1.2V. In some implementations, the LV source 403 is configured to provide a voltage between 2V and 3.3V (e.g., 2V, 2.1V, 2.2V, 2.3V, 2.4V, 2.5V, 2.6V, 2.7V, 2.8V, 2.9V, 3V, 3.1V, 3.2V, 3.3V, any range bounded below by any of these values, or in any range bounded by any two of these values). In one example, the voltage is 3.3V. In some implementations, the HV source 405 is configured to provide a voltage greater than 3.3V, such as between 5V and 30V (e.g., 5V, 6V, 7V, 8V, 9V, 10V, 11V, 12V, 13V, 14V, 15V, 16V, 17V, 18V, 19V, 20V, 21V, 22V, 23V, 24V, 25V, 26V, 27V, 28V, 29V, 30V, any range bounded below by any of these values, or in any range bounded by any two of these values). It should be understood that the voltage ranges described above with respect to the HV source 405, the LV source 403, and the LLV source 401 are for illustrative purposes and are not limiting, and the HV source 405, the LV source 403, and the LLV source 401 can provide any other suitable voltage range.

[0089] Based on suitable voltage levels (Vddl, Vdd2, or Vdd3) of the memory peripheral circuitry (e.g., peripheral circuitry 202), it can be classified as LLV circuitry 402, LV circuitry 404, and HV circuitry 406, which can be coupled to LLV source 401, LV source 403, and HV source 405, respectively. In some embodiments, HV circuitry 406 includes one or more drive circuits coupled to a memory cell array (e.g., memory cell array 201) through word lines, bit lines, SSG lines, DSG lines, source lines, etc., and configured to drive the memory cell array by applying voltages at suitable levels to the word lines, bit lines, SSG lines, DSG lines, source lines, etc., when performing memory operations (e.g., read, program, or erase). In one example, HV circuitry 406 can include word line drive circuitry (e.g., in row decoder / word line driver 308) coupled to word lines and applying program voltages (Vprog) or pass voltages (Vpass) in a range of, for example, 5V and 30V to the word lines during program operations. In another example, HV circuitry 406 can include bit line drive circuitry (e.g., in column decoder / bit line driver 306) coupled to bit lines and applying erase voltages (Veras) in a range of, for example, 5V and 30V to the bit lines during erase operations. In some embodiments, LV circuitry 404 includes page buffer circuitry (e.g., in latches of page buffer 304) and is configured to buffer data read from or programmed to the memory cell array. For example, a voltage of, for example, 3.3V can be provided to the page buffer by LV source 403. LV circuitry 404 can also include logic circuitry (e.g., in control logic 312). In some embodiments, LLV circuitry 402 includes I / O circuitry (e.g., in interface 316 and / or data bus 318) configured to interface the memory cell array with a memory controller. For example, a voltage of, for example, 1.2V can be provided to the I / O circuitry by LLV source 401.

[0090] As described above, to reduce the total area occupied by the memory peripheral circuitry, the peripheral circuitry 202 can be formed in different planes separately based on different performance requirements (e.g., voltages applied). For example, Figure 4BA schematic diagram of peripheral circuits provided with various voltages arranged in separate semiconductor structures is shown in accordance with some aspects of the present disclosure. In some implementations, due to the significant difference in voltages of the LLV circuits 402 and the HV circuits 406 and the resulting difference in device sizes, e.g., different substrate thickness and different gate dielectric thickness, they are separated, e.g., in semiconductor structures 408 and 410, respectively. In one example, the thickness of the semiconductor layer (e.g., substrate or thinned substrate) in which the HV circuits 406 are formed in semiconductor structure 410 can be greater than the thickness of the semiconductor layer (e.g., substrate or thinned substrate) in which the LLV circuits 402 are formed in semiconductor structure 408. In another example, the thickness of the gate dielectric of the transistors forming the HV circuits 406 can be greater than the thickness of the gate dielectric of the transistors forming the LLV circuits 402. For example, the difference in thickness can be at least 5 times. It can be appreciated that the stacked LLV circuits 402 and HV circuits 406 in different planes can be formed in two semiconductor structures 408 or 410 separated by a bonding interface (e.g., in Figure 1A and 1B .

[0091] The LV circuits 404 can be formed in semiconductor structure 408 or 410, or in another semiconductor, i.e., in the same plane as the LLV circuits 402 or the HV circuits 406, or in a different plane from the LLV circuits 402 and the HV circuits 406. As Figure 4BAs shown, in some embodiments, some of the LV circuits 404 are formed in the semiconductor structure 408, i.e., in the same plane as the LLV circuits 402, while some of the LV circuits 404 are formed in the semiconductor structure 410, i.e., in the same plane as the HV circuits 406. That is, the LV circuits 404 can also be separated into different planes. For example, when the same voltage is applied to the LV circuits 404 in the different semiconductor structures 408 and 410, the thickness of the gate dielectric of the transistors forming the LV circuits 404 in the semiconductor structure 408 can be the same as the thickness of the gate dielectric of the transistors forming the LV circuits 404 in the semiconductor structure 410. In some embodiments, the same voltage is applied to the LV circuits 404 in the semiconductor structure 408 and the LV circuits 404 in the semiconductor structure 410, such that the voltage applied to the HV circuits 406 in the semiconductor structure 410 is higher than the voltage applied to the LV circuits 404 in either semiconductor structure 408 or 410, which is in turn higher than the voltage applied to the LLV circuits 402 in the semiconductor structure 408. Moreover, according to some embodiments, because the voltage applied to the LV circuits 404 is between the voltage applied to the HV circuits 406 and the voltage applied to the LLV circuits 402, the thickness of the gate dielectric of the transistors forming the LV circuits 404 is between the thickness of the gate dielectric of the transistors forming the HV circuits 406 and the thickness of the gate dielectric of the transistors forming the LLV circuits 402. For example, the thickness of the gate dielectric of the transistors forming the LV circuits 404 can be greater than the thickness of the gate dielectric of the transistors forming the LLV circuits 402, but less than the thickness of the gate dielectric of the transistors forming the HV circuits 406.

[0092] Based on different performance requirements (e.g., associated with different applied voltages), the peripheral circuits 202 can be separated into at least two stacked semiconductor structures 408 and 410 in different planes. In some embodiments, the I / O circuits in the interface 316 and / or the data bus 318 (as LLV circuits 402) and the logic circuits in the control logic 312 (as part of the LV circuits) are disposed in the semiconductor structure 408, while the page buffer circuits in the page buffer 304 and the driver circuits in the row decoder / word line drivers 308 and the column decoder / bit line drivers 306 are disposed in the semiconductor structure 410. For example, Figure 7 A circuit diagram of the word line drivers 308 and the page buffer 304 is shown, in accordance with some aspects of the present disclosure.

[0093] In some implementations, the page buffer 304 includes a plurality of page buffer circuits 702, each coupled to one NAND memory string 208 via a respective bit line 216. That is, the memory device 200 can include bit lines 216 coupled to the NAND memory strings 208, respectively, and the page buffer 304 can include page buffer circuits 702 coupled to the bit lines 216 and the NAND memory strings 208, respectively. Each page buffer circuit 702 can include one or more latches, switches, power sources, nodes (e.g., data nodes and I / O nodes), current mirrors, verification logic, sensing circuits, etc. In some implementations, each page buffer circuit 702 is configured to store sense data corresponding to read data received from the respective bit line 216 and output the stored sense data at a read operation; each page buffer circuit 702 is also configured to store program data and output the stored program data to the respective bit line 216 at a program operation.

[0094] In some implementations, the word line driver 308 includes a plurality of string drivers 704 (also referred to as drive circuits) coupled to the word lines 218, respectively. The word line driver 308 can also include a plurality of local word lines 706 (LWLs) coupled to the string drivers 704, respectively. Each string driver 704 can include a gate coupled to a decoder (not shown), a source / drain coupled to a respective local word line 706, and another source / drain coupled to a respective word line 218. In some memory operations, the decoder can select certain string drivers 704, for example, by applying a voltage signal greater than a threshold voltage of the string drivers 704 and applying a voltage (e.g., a program voltage, a pass voltage, or an erase voltage) to each local word line 706, such that the voltage is applied to the respective word line 218 by each selected string driver 704. Conversely, the decoder can also deselect certain string drivers 704, for example, by applying a voltage signal less than a threshold voltage of the string drivers 704, such that each deselected string driver 704 floats the respective word line 218 during the memory operation.

[0095] In some implementations, the page buffer circuits 702 include portions of the LV circuit 404 disposed in the semiconductor structures 408 and / or 410. In one example, since the number of page buffer circuits 702 increases as the number of bits increases, which can occupy a large area for memory devices with a large number of memory cells, the page buffer circuits 702 can be the semiconductor structures 408 and 410. In some implementations, the string drivers 704 include portions of the HV circuit 406 disposed in the semiconductor structure 410.

[0096] Consistent with the scope of this disclosure, each peripheral circuit 202 may include multiple transistors as its basic building blocks. The transistors may be 2D (also known as planar transistors) or 3D (3D transistors) metal-oxide-semiconductor field-effect transistors (MOSFETs). For example, Figure 5A and 5B Perspective and side views of a planar transistor 500 according to some aspects of this disclosure are shown respectively. Figure 6A and 6B Perspective and side views of a 3D transistor 600 according to some aspects of this disclosure are shown respectively. Figure 5B It shows Figure 5A A side view of the cross-section of the planar transistor 500 in the BB plane. Figure 6B It shows Figure 6A A side view of the 3D transistor 600 in the BB plane cross-section.

[0097] like Figure 5A and 5B As shown, the planar transistor 500 may be a MOSFET on a substrate 502, which may include silicon (e.g., single-crystal silicon, c-Si), silicon-germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable semiconductor material. Trench isolation 503, such as shallow trench isolation (STI), may be formed in the substrate 502 and between adjacent planar transistors 500 to reduce current leakage. Trench isolation 503 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric (e.g., aluminum oxide, hafnium oxide, zirconium oxide, etc.). In some embodiments, the high-k dielectric material includes any dielectric material having a dielectric constant or k value higher than that of silicon nitride (k>7). In some embodiments, trench isolation 503 includes silicon oxide.

[0098] like Figure 5A and 5B As shown, the planar transistor 500 may further include a gate structure 508 on the substrate 502. In some embodiments, the gate structure 508 is on the top surface of the substrate 502. Figure 5BAs shown, the gate structure 508 may include a gate dielectric 507 on and in contact with the top surface of the substrate 502. The gate structure 508 may also include a gate electrode 509 on and in contact with the gate dielectric 507. The gate dielectric 507 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. In some embodiments, the gate dielectric 507 includes silicon oxide, i.e., a gate oxide. The gate electrode 509 may include any suitable conductive material, such as polysilicon, a metal (e.g., W, Cu, Al, etc.), a metal compound (e.g., TiN, TaN, etc.), or a silicide. In some embodiments, the gate electrode 509 includes doped polysilicon, i.e., gate polysilicon.

[0099] like Figure 5A As shown, the planar transistor 500 may further include a pair of source and drain electrodes 506 in the substrate 502. The source and drain electrodes 506 may be doped with any suitable P-type dopant, such as boron (B) or gallium (Ga), or any suitable N-type dopant, such as phosphorus (P) or arsenic (As). In the planar view, the source and drain electrodes 506 may be separated by a gate structure 508. That is, according to some embodiments, in the planar view, the gate structure 508 is formed between the source and drain electrodes 506. When the gate voltage applied to the gate electrode 509 of the gate structure 508 is higher than the threshold voltage of the planar transistor 500, a channel of the planar transistor 500 in the substrate 502 may be laterally formed between the source and drain electrodes 506 under the gate structure 508. Figure 5A and 5B As shown, the gate structure 508 can be above and contact the top surface of the portion (active region) of the substrate 502 in which a channel can be formed. That is, according to some embodiments, the gate structure 508 contacts only one side of the active region, i.e., in the plane of the top surface of the substrate 502. It should be understood that, although Figure 5A and 5B The planar transistor 500 may include additional components such as wells and spacers, though not shown in the diagram.

[0100] like Figure 6A and 6BAs shown, the 3D transistor 600 may be a MOSFET on a substrate 602, which may include silicon (e.g., monocrystalline silicon, c-Si), SiGe, GaAs, Ge, silicon-on-insulator (SOI), or any other suitable material. In some embodiments, the substrate 602 comprises monocrystalline silicon. Trench isolation 603, such as STI, may be formed in the substrate 602 and between adjacent 3D transistors 600 to reduce current leakage. The trench isolation 603 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric (e.g., aluminum oxide, hafnium oxide, zirconium oxide, etc.). In some embodiments, the trench isolation 603 comprises silicon oxide.

[0101] like Figure 6A and 6B As shown, unlike the planar transistor 500, the 3D transistor 600 may also include a 3D semiconductor body 604 above the substrate 602. That is, in some embodiments, the 3D semiconductor body 604 extends at least partially above the top surface of the substrate 602 to expose not only the top surface of the 3D semiconductor body 604 but also both side surfaces. Figure 6A and 6B As shown, for example, the 3D semiconductor body 604 can be a 3D structure, also referred to as a "fin," to expose its three sides. According to some embodiments, the 3D semiconductor body 604 is formed from a substrate 602 and therefore has the same semiconductor material as the substrate 602. In some embodiments, the 3D semiconductor body 604 comprises monocrystalline silicon. Since a channel can be formed in the 3D semiconductor body 604 opposite to the substrate 602, the 3D semiconductor body 604 can be considered as the active region of the 3D transistor 600.

[0102] like Figure 6A and 6B As shown, the 3D transistor 600 may further include a gate structure 608 on the substrate 602. Unlike the planar transistor 500, where the gate structure 508 contacts only one side of the active region, i.e., in a plane on the top surface of the substrate 502, the gate structure 608 of the 3D transistor 600 can contact multiple sides of the active region, i.e., in multiple planes on the top surface and sides of the 3D semiconductor body 604. That is, the active region of the 3D transistor 600, i.e., the 3D semiconductor body 604, can be at least partially surrounded by the gate structure 608.

[0103] The gate structure 608 may include a gate dielectric 607 over the 3D semiconductor body 604, for example, contacting the top surface and two sides of the 3D semiconductor body 604. The gate structure 608 may also include a gate electrode 609 over and in contact with the gate dielectric 607. The gate dielectric 607 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. In some embodiments, the gate dielectric 607 includes silicon oxide, i.e., a gate oxide. The gate electrode 609 may include any suitable conductive material, such as polysilicon, a metal (e.g., W, Cu, Al, etc.), a metal compound (e.g., TiN, TaN, etc.), or a silicide. In some embodiments, the gate electrode 609 includes doped polysilicon, i.e., gate polysilicon.

[0104] like Figure 6A As shown, the 3D transistor 600 may further include a pair of source and drain electrodes 606 within the 3D semiconductor body 604. The source and drain electrodes 606 may be doped with any suitable P-type dopant, such as B or Ga, or any suitable N-type dopant, such as P or Ar. In a planar view, the source and drain electrodes 606 may be separated by a gate structure 608. That is, according to some embodiments, in a planar view, the gate structure 608 is formed between the source and drain electrodes 606. As a result, when the gate voltage applied to the gate electrode 609 of the gate structure 608 is higher than the threshold voltage of the 3D transistor 600, multiple channels of the 3D transistor 600 can be formed laterally between the source and drain electrodes 606 surrounded by the gate structure 608. Unlike the planar transistor 500, in which only a single channel can be formed on the top surface of the substrate 502, multiple channels can be formed on the top surface and sides of the 3D semiconductor body 604 in the 3D transistor 600. In some implementations, the 3D transistor 600 includes a multi-gate transistor. It should be understood that, although in Figure 6A and 6B Not shown, but the 3D transistor 600 may include additional components such as wells, spacers, and stress sources (also called strain elements) at the source and drain 606.

[0105] It should also be understood that Figure 6A and 6B An example of a 3D transistor that can be used in memory peripheral circuitry is shown, and any other suitable 3D multi-gate transistor can also be used in memory peripheral circuitry, including, for example, full-ring gate (GAA) silicon-free (SON) transistors, multi-gate independent FETs (MIGET), tri-gate FETs, ΠE gate FETs and ΩΩT gate FETs, quad-gate FETs, cylindrical FETs or multi-bridge / stacked nanowire FETs.

[0106] Whether planar transistor 500 or 3D transistor 600, each transistor of the memory peripheral circuit can include a gate dielectric (e.g., gate dielectric 507 and 607) having a thickness T (gate dielectric thickness, e.g., as shown in Figure 5B and 6B . The gate dielectric thickness T of a transistor can be designed to accommodate the voltage applied to the transistor. For example, referring back to Figure 4A and 4B , the gate dielectric thickness of a transistor in HV circuit 406 (e.g., a driver circuit such as string driver 704) can be greater than the gate dielectric thickness of a transistor in LV circuit 404 (e.g., page buffer circuit 702 or logic circuit in control logic 312), which in turn can be greater than the gate dielectric thickness of a transistor in LLV circuit 402 (e.g., I / O circuit in interface 316 and data bus 318). In some embodiments, the difference between the gate dielectric thickness of a transistor in HV circuit 406 and the dielectric thickness of a transistor in LLV circuit 402 is at least 5 times, e.g., between 5 times and 50 times. For example, the gate dielectric thickness of a transistor in HV circuit 406 can be at least 5 times greater than the gate dielectric thickness of a transistor in LLV circuit 402.

[0107] In some implementations, the dielectric thickness of the transistors in the LLV circuit 402 is between 2 nm and 4 nm (e.g., 2 nm, 2.1 nm, 2.2 nm, 2.3 nm, 2.4 nm, 2.5 nm, 2.6 nm, 2.7 nm, 2.8 nm, 2.9 nm, 3 nm, 3.1 nm, 3.2 nm, 3.3 nm, 3.4 nm, 3.5 nm, 3.6 nm, 3.7 nm, 3.8 nm, 3.9 nm, 4 nm, any range bounded by a lower limit of any of these values, or in any range defined by any two of these values). It will be appreciated that this thickness can be commensurate with the range of LLV voltages applied to the LLV circuit 402, such as less than 2 V (e.g., 1.2 V), as described in detail above. In some implementations, the dielectric thickness of the transistors in the LV circuit 404 is between 4 nm and 10 nm (e.g., 4 nm, 4.5 nm, 5 nm, 5.5 nm, 6 nm, 6.5 nm, 7 nm, 7.5 nm, 8 nm, 8.5 nm, 9 nm, 9.5 nm, 10 nm, any range bounded by a lower limit of any of these values, or in any range defined by any two of these values). It will be appreciated that this thickness can be commensurate with the range of LV voltages applied to the LV circuit 404, such as between 2 V and 3.3 V (e.g., 3.3 V), as described in detail above. In some implementations, the dielectric thickness of the transistors in the HV circuit 406 is between 20 nm and 100 nm (e.g., 20 nm, 21 nm, 22 nm, 23 nm, 24 nm, 25 nm, 26 nm, 27 nm, 28 nm, 29 nm, 30 nm, 31 nm, 32 nm, 33 nm, 34 nm, 35 nm, 36 nm, 37 nm, 38 nm, 39 nm, 40 nm, 45 nm, 50 nm, 55 nm, 60 nm, 65 nm, 70 nm, 75 nm, 80 nm, 85 nm, 90 nm, 95 nm, 100 nm, any range bounded by a lower limit of any of these values, or in any range defined by any two of these values). It will be appreciated that this thickness can be commensurate with the range of HV voltages applied to the HV circuit 406, such as greater than 3.3 V (e.g., between 5 V and 30 V), as described in detail above.

[0108] Figure 9A and 9B FIGS. 9A and 9B show schematic diagrams of cross-sections of 3D memory devices 900 and 901 having two stacked semiconductor structures, in accordance with various aspects of the present disclosure. The 3D memory devices 900 and 901 can be Figure 1AAn example of a 3D memory device 100 is provided, wherein the memory array cells of the first semiconductor structure 102 are vertically disposed between the peripheral circuits of the first semiconductor structure 102 and the peripheral circuits of the second semiconductor structure 104. That is, the two separate portions of the peripheral circuits can be disposed on opposite sides of the 3D memory device 900 or 901 in the vertical direction, respectively. For example... Figure 9A and 9B As shown, according to some embodiments, a second semiconductor structure 104, including some of the peripheral circuitry, is bonded to a first semiconductor structure 102 on one side having a memory cell array to form a bonding interface 103 between the second semiconductor structure 104 and the memory cell array of the first semiconductor structure 102.

[0109] In addition, such as Figure 9A and 9B As shown, the 3D memory device 900 or 901 may further include a pad-out interconnect layer 902 for pad-out destinations, i.e., for interconnecting with external devices using contact pads on which bonding wires can be soldered. Figure 9A In one example shown, a second semiconductor structure 104, including some of the peripheral circuitry on one side of the 3D memory device 900, may include a pad-out interconnect layer 902. Figure 9B In another example shown, the first semiconductor structure 102, including some of the memory cell array and peripheral circuitry on the other side of the 3D memory device 901, may include a pad-out interconnect layer 902, allowing the 3D memory device 901 to be led out from the pads on the other peripheral circuitry side. In either example, the 3D memory device 900 or 901 may be led out from the peripheral circuitry side pads to reduce the interconnect distance between the contact pads and the peripheral circuitry, thereby reducing parasitic capacitance from the interconnect and improving the electrical performance of the 3D memory device 900 or 901.

[0110] Figure 10 Some aspects of this disclosure are shown. Figure 9A and 9B A schematic diagram of a cross-section of the 3D memory device 1000. Figure 9A and 9B Examples of 3D memory devices 900 and 901. (See example...) Figure 10 As shown, the 3D memory device 1000 may include a stacked first semiconductor structure 102 and a second semiconductor structure 104. In some embodiments, the first semiconductor structure 102 includes a semiconductor layer 1002, a polysilicon layer 106, a bonding layer 1008, a memory cell array vertically disposed between the polysilicon layer 106 and the bonding layer 1008, and some of peripheral circuitry vertically disposed between the semiconductor layer 1002 and the polysilicon layer 106.

[0111] The array of memory cells can include an array of NAND memory strings (e.g., the NAND memory strings 208 disclosed herein), and the sources of the array of NAND memory strings can be in contact with the polysilicon layer 106 (e.g., as shown in FIG. 8B). The polysilicon layer 106 can be a deposited polysilicon layer (e.g., N-type doped, P-type doped, or undoped) suitable for channel structures in “floating gate” type NAND memory strings or “charge trapping” type NAND memory strings suitable for GIDL erase operations, for example. The polysilicon layer 106 can be a deposited polysilicon layer (e.g., N-type doped, P-type doped, or undoped) suitable for channel structures in “floating gate” type NAND memory strings or “charge trapping” type NAND memory strings suitable for GIDL erase operations, for example. Figure 8 The array of memory cells can include an array of NAND memory strings (e.g., the NAND memory strings 208 disclosed herein), and the sources of the array of NAND memory strings can be in contact with the polysilicon layer 106 (e.g., as shown in FIG. 8B). The polysilicon layer 106 can be a deposited polysilicon layer (e.g., N-type doped, P-type doped, or undoped) suitable for channel structures in “floating gate” type NAND memory strings or “charge trapping” type NAND memory strings suitable for GIDL erase operations, for example. The polysilicon layer 106 can be a deposited polysilicon layer (e.g., N-type doped, P-type doped, or undoped) suitable for channel structures in “floating gate” type NAND memory strings or “charge trapping” type NAND memory strings suitable for GIDL erase operations, for example. Figure 8 The bonding layer 1008 can include conductive bonding contacts (not shown) and a dielectric that electrically isolates the bonding contacts, which can be used for hybrid bonding as described in detail below, for example. The bonding layer 1008 can be a deposited layer of a conductive material (e.g., a metal or a metal alloy) that is suitable for forming a conductive bonding contact. The bonding layer 1008 can be a deposited layer of a dielectric material (e.g., an oxide, a nitride, a high-k dielectric, or a combination thereof) that is suitable for forming an electrically isolating dielectric. The bonding layer 1008 can be a deposited layer of a conductive material (e.g., a metal or a metal alloy) that is suitable for forming a conductive bonding contact and a deposited layer of a dielectric material (e.g., an oxide, a nitride, a high-k dielectric, or a combination thereof) that is suitable for forming an electrically isolating dielectric. The bonding layer 1008 can be a deposited layer of a conductive material (e.g., a metal or a metal alloy) that is suitable for forming a conductive bonding contact and a deposited layer of a dielectric material (e.g., an oxide, a nitride, a high-k dielectric, or a combination thereof) that is suitable for forming an electrically isolating dielectric.

[0112] In some embodiments, the peripheral circuitry in the first semiconductor structure 102 is in contact with the semiconductor layer 1002 but not in contact with the polysilicon layer 106. That is, the transistors (e.g., the planar transistors 500 and the 3D transistors 600) of the peripheral circuitry can be in contact with the semiconductor layer 1004. The semiconductor layer 1002 can include a semiconductor material, such as single crystalline silicon (e.g., a silicon substrate or a thinned silicon substrate). It will be appreciated that, unlike the polysilicon layer 106 in the first semiconductor structure 102, the semiconductor layer 1002 on which the transistors are formed can include single crystalline silicon, rather than polysilicon, due to the superior carrier mobility of single crystalline silicon that is desirable for the performance of the transistors. Through-via contacts (e.g., ILV / TSVs) through the polysilicon layer 106 can form a direct, short distance (e.g., sub-micron or micron level) electrical connection between the array of memory cells in the first semiconductor structure 102 and the peripheral circuitry.

[0113] In some embodiments, the second semiconductor structure 104 includes the semiconductor layer 1004, the bonding layer 1010, and some of the peripheral circuitry of the array of memory cells vertically between the semiconductor layer 1004 and the bonding layer 1010. The transistors (e.g., the planar transistors 500 and the 3D transistors 600) of the peripheral circuitry can be in contact with the semiconductor layer 1004. Similar to the semiconductor layer 1002, the semiconductor layer 1004 can include a semiconductor material, such as single crystalline silicon (e.g., a silicon substrate or a thinned silicon substrate). It will be appreciated that, unlike the polysilicon layer 106 in the first semiconductor structure 102, the semiconductor layer 1004 on which the transistors are formed can include single crystalline silicon, rather than polysilicon, due to the superior carrier mobility of single crystalline silicon that is desirable for the performance of the transistors.

[0114] Similar to the bonding layer 1008 in the first semiconductor structure 102, the bonding layer 1010 may further include a dielectric material for conductive bonding contacts (not shown) and electrically isolating bonding contacts. According to some embodiments, a bonding interface 103 is perpendicularly positioned between and in contact with the bonding layers 1008 and 1010, respectively. That is, the bonding layers 1008 and 1010 can be disposed on opposite sides of the bonding interface 103, and the bonding contacts of the bonding layer 1008 can contact the bonding contacts of the bonding layer 1010 at the bonding interface 103. As a result, unlike through-contacts (e.g., ILV / TSV), a large number (e.g., millions) of bonding contacts spanning the bonding interface 103 can provide direct, short-distance (e.g., micrometer-scale) electrical connections between adjacent semiconductor structures 102 and 104.

[0115] like Figure 10 As shown, according to some embodiments, since the first semiconductor structure 102 and the second semiconductor structure 104 are bonded face-to-face (e.g., in...), Figure 10 In this configuration, semiconductor layer 1002 is disposed on the bottom side of the first semiconductor structure 102, while semiconductor layer 1004 is disposed on the top side of the second semiconductor structure 104. Therefore, the transistors of the peripheral circuits in the first semiconductor structure 102 and the second semiconductor structure 104 are disposed facing each other. Furthermore, within the first semiconductor structure 102, since polysilicon layer 106 is perpendicularly positioned between the memory cell array and the peripheral circuits, and the memory cell array and the peripheral circuits are formed on polysilicon layer 106 and semiconductor layer 1002 respectively, the memory cell array and the peripheral circuits face the same direction (e.g., in...). Figure 10 (in the positive y-direction). It should be understood that, for ease of explanation, Figure 9A and 9B The pads in the 902 interconnect layer are brought out from the pads. Figure 10 The 3D memory device 1000 is omitted in the above description and may be included in the above description. Figure 9A and 9B In the 3D memory device 1000.

[0116] As described above, the first semiconductor structure 102 and the second semiconductor structure 104 may have peripheral circuitry, which includes transistors to which different voltages are applied. For example, the second semiconductor structure 104 may include... Figure 4B An example of semiconductor structure 408 for LLV circuit 402 (and LV circuit 404 in some examples), and the first semiconductor structure 102 may include Figure 4Bone example of the semiconductor structure 410 of the HV circuit 406 (and the LV circuit 404 in some examples) in the HV circuit 406 (and the LLV circuit 402 in some examples) in the second semiconductor structure 104. Thus, in some implementations, the semiconductor layers 1002 and 1004 in the first semiconductor structure 102 and the second semiconductor structure 104 have different thicknesses to accommodate the transistors to which different voltages are applied. In one example, the first semiconductor structure 102 can include the HV circuit 406, and the second semiconductor structure 104 can include the LLV circuit 402, and the thickness of the semiconductor layer 1002 in the first semiconductor structure 102 can be greater than the thickness of the semiconductor layer 1004 in the second semiconductor structure 104. Further, in some implementations, the gate dielectric of the transistors in the first semiconductor structure 102 and the second semiconductor structure 104 also have different thicknesses to accommodate the different voltages applied. In one example, the first semiconductor structure 102 can include the HV circuit 406, and the second semiconductor structure 104 can include the LLV circuit 402, and the thickness of the gate dielectric of the transistors in the first semiconductor structure 102 can be greater (e.g., at least 5 times) than the thickness of the gate dielectric of the transistors in the second semiconductor structure 104. The thicker gate dielectric can withstand the higher operating voltage applied to the transistors in the first semiconductor structure 102 compared to the transistors in the second semiconductor structure 104 to avoid breakdown during high voltage operation.

[0117] Figure 11A and 11B shows various examples of a 3D memory device 1100 in accordance with various aspects of the present disclosure. Figure 10 shows a side view of various examples of a 3D memory device 1000 in Figure 11A As shown, as one example of the 3D memory device 1000 in Figure 10 in accordance with some implementations, the 3D memory device 1100 is a bonded chip including the first semiconductor structure 102 and the second semiconductor structure 104 stacked on top of each other in different planes in a vertical direction (e.g., the y-direction) in Figure 11A in accordance with some implementations, the first semiconductor structure 102 and the second semiconductor structure 104 are bonded at a bonding interface 103 therebetween.

[0118] As shown, as one example of the 3D memory device 1000 in Figure 11AAs shown, the first semiconductor structure 102 can include a semiconductor layer 1002 having a semiconductor material. In some embodiments, the semiconductor layer 1002 is a silicon substrate having single-crystal silicon. The first semiconductor structure 102 can also include a device layer 1102 over and in contact with the semiconductor layer 1002. In some embodiments, the device layer 1102 includes a first peripheral circuit 1104 and a second peripheral circuit 1106. The first peripheral circuit 1104 can include HV circuitry 406, such as drive circuitry (e.g., string drivers 704 in row decoders / word line drivers 308 and drivers in column decoders / bit line drivers 306), and the second peripheral circuit 1106 can include LV circuitry 404, such as page buffer circuitry (e.g., page buffer circuitry 702 in page buffers 304) and logic circuitry (e.g., in control logic 312). In some embodiments, the first peripheral circuit 1104 includes a plurality of transistors 1108 in contact with the semiconductor layer 1002, and the second peripheral circuit 1106 includes a plurality of transistors 1110 in contact with the semiconductor layer 1002. The transistors 1108 and 1110 can include any of the transistors disclosed herein, such as planar transistor 500 and 3D transistor 600. As described in detail above with respect to transistors 500 and 600, in some embodiments, each transistor 1108 or 1110 includes a gate dielectric, and due to the voltage applied to the transistors 1108 being higher than the voltage of the transistors 1110, the thickness of the gate dielectric of the transistors 1108 (e.g., in HV circuitry 406) is greater than the thickness of the gate dielectric of the transistors 1110 (e.g., in LV circuitry 404). Trench isolation (e.g., STI) and doped regions (e.g., wells, sources, and drains of transistors 1108 and 1110) can also be formed on or in the semiconductor layer 1002.

[0119] In some embodiments, the first semiconductor structure 102 further includes an interconnect layer 1112 over the device layer 1102 to transmit electrical signals to and from the peripheral circuits 1106 and 1104. As shown, the interconnect layer 1112 includes a plurality of conductive lines 1114 and a plurality of vias 1116. The conductive lines 1114 can be formed of any suitable conductive material, such as copper, and can be formed by any suitable process, such as damascene processing. The vias 1116 can be formed of any suitable conductive material, such as tungsten, and can be formed by any suitable process, such as sputtering. In some embodiments, the conductive lines 1114 and vias 1116 are formed by a damascene process, such as a copper damascene process. In some embodiments, the conductive lines 1114 and vias 1116 are formed by a sputtering process, such as a tungsten sputtering process. Figure 11AAs shown, interconnect layer 1112 may be vertically positioned between polysilicon layer 106 and device layer 1102 (including transistors 1108 and 1110 of peripheral circuits 1104 and 1106). Interconnect layer 1112 may include multiple interconnects (also referred to herein as “contacts”), including lateral lines and vias. As used herein, the term “interconnect” may broadly include any suitable type of interconnect, such as mid-process (MEOL) interconnects and back-end process (BEOL) interconnects. Interconnects in interconnect layer 1112 may be coupled to transistors 1108 and 1110 of peripheral circuits 1104 and 1106 in device layer 1102. Interconnect layer 1112 may also include one or more interlayer dielectric (ILD) layers (also referred to as “intermetallic dielectric (IMD) layers”) in which lateral lines and vias may be formed. That is, interconnect layer 1112 may include lateral lines and vias in multiple ILD layers. In some embodiments, devices in device layer 1102 are coupled to each other via interconnects in interconnect layer 1112. For example, peripheral circuit 1104 can be coupled to peripheral circuit 1106 via interconnect layer 1112. Interconnects in interconnect layer 1112 may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. The ILD layer in interconnect layer 1112 may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low dielectric constant (low k) dielectrics, or any combination thereof. In some embodiments, interconnects in interconnect layer 1112 include W, which has a relatively high thermal budget (compatible with high-temperature processes) and good quality (fewer defects, such as voids) among conductive metallic materials.

[0120] like Figure 11A As shown, the first semiconductor structure may further include a polysilicon layer 106 above and in contact with the interconnect layer 1112. According to some embodiments, the polysilicon layer 106 is a doped polysilicon layer on the interconnect layer 1112, as described in detail below with respect to the manufacturing process. It should be understood that in some examples, trench isolation and doped regions (not shown) may also be formed in the polysilicon layer 106.

[0121] like Figure 11A As shown, the first semiconductor structure 102 may further include an array of memory cells, such as an array of NAND memory strings 208 above and in contact with the polysilicon layer 106. The sources of the NAND memory strings 208 may be in contact with the polysilicon layer 106. In some embodiments, the polysilicon layer 106 is perpendicularly positioned between the NAND memory strings 208 and the device layer 1102, which includes transistors 1108 and 1110. In some embodiments, each NAND memory string 208 is a "charge-trapping" type NAND memory string, which includes any suitable channel structure disclosed herein, such as those described above. Figure 8The channel structure 812 is described in detail. In some embodiments, the NAND memory string 208 is a "floating gate" type NAND memory string, and the polysilicon layer 106 is the source plate of the floating gate type NAND memory string.

[0122] According to some implementations, each NAND memory string 208 extends vertically through multiple pairs of layers, each comprising a conductive layer and a dielectric layer. The stacked and interleaved conductive and dielectric layers are also referred to herein as a stacked layer structure, for example, memory stack 1127. Memory stack 1127 may be... Figure 8 Examples of memory stack layer 804 include conductive layers and dielectric layers in memory stack layer 1127, which may be examples of gate conductive layer 806 and dielectric layer 808 in memory stack layer 804, respectively. According to some embodiments, the staggered conductive and dielectric layers in memory stack layer 1127 alternate in the vertical direction. Each conductive layer may include a gate electrode (gate line) surrounded by an adhesive layer and a gate dielectric layer. The gate electrode of the conductive layer may extend laterally as a word line, terminating at one or more stepped structures in memory stack layer 1127.

[0123] like Figure 11A As shown, the first semiconductor structure 102 may further include an interconnect layer 1128 above and in contact with the NAND memory string 208, for transmitting electrical signals to and from the NAND memory string 208. In some embodiments, the memory stack layer 1127 and the NAND memory string 208 are perpendicularly positioned between the interconnect layer 1128 and the polysilicon layer 106. The interconnect layer 1128 may include multiple interconnects, such as MEOL interconnects and BEOL interconnects. In some embodiments, the interconnects in the interconnect layer 1128 may also include local interconnects, such as bit line contacts and word line contacts. The interconnect layer 1128 may also include one or more ILD layers in which lateral lines and vias may be formed. The interconnects in the interconnect layer 1128 may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. The ILD layers in the interconnect layer 1128 may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0124] like Figure 11AAs shown, the first semiconductor structure 102 may further include one or more contacts 1124 extending vertically through the polysilicon layer 106. In some embodiments, the contacts 1124 couple interconnects in the interconnect layer 1128 to interconnects in the interconnect layer 1112 to provide electrical connection between the NAND memory string 208 and transistors 1108 and 1110 through the polysilicon layer 106. The contacts 1124 may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. In some embodiments, the contacts 1124 include W. In some embodiments, the contacts 1124 include vias surrounded by dielectric spacers (e.g., having silicon oxide) to electrically isolate the vias from the polysilicon layer 106. Depending on the thickness of the polysilicon layer 106, the contact 1124 can be an ILV with a depth (in the vertical direction) in the submicron range (e.g., between 10 nm and 1 μm), or a TSV with a depth (in the vertical direction) in the micron range or tens of micron range (e.g., between 1 μm and 100 μm).

[0125] like Figure 11A As shown, the first semiconductor structure 102 may further include a bonding layer 1008 at the bonding interface 103, located above and in contact with the interconnect layer 1128. The bonding layer 1008 may include a dielectric material comprising a plurality of bonding contacts and electrically isolating bonding contacts. The bonding contacts may comprise conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. In some embodiments, the bonding contacts of the bonding layer 1008 comprise Cu. The remaining region of the bonding layer 1008 may be formed of a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. The bonding contacts in the bonding layer 1008 and the surrounding dielectric material can be used for hybrid bonding (also known as “metal / dielectric hybrid bonding”), a direct bonding technique (e.g., forming a bond between surfaces without using an intermediate layer, such as solder or adhesive), and can simultaneously achieve metal-to-metal (e.g., Cu-Cu) bonding and dielectric-to-dielectric (e.g., SiO2-SiO2) bonding.

[0126] like Figure 11AAs shown, the second semiconductor structure 104 can be bonded face-to-face to the top of the first semiconductor structure 102 at the bonding interface 103. The second semiconductor structure 104 may also include a bonding layer 1010 at the bonding interface 103, for example, on the opposite side of the bonding interface 103 relative to the bonding layer 1008 in the first semiconductor structure 102. The bonding layer 1010 may include a dielectric material of a plurality of bonding contacts and electrically isolating bonding contacts. The bonding contacts may include a conductive material, such as Cu. The remaining region of the bonding layer 1010 may be formed of a dielectric material such as silicon oxide. The bonding contacts in the bonding layer 1010 and the surrounding dielectric material may be used for hybrid bonding. In some embodiments, the bonding interface 103 is the location where the bonding layers 1008 and 1010 meet and bond. In fact, the bonding interface 103 can be a layer with a specific thickness, including the top surface of the bonding layer 1008 of the first semiconductor structure 102 and the bottom surface of the bonding layer 1010 of the second semiconductor structure 104.

[0127] like Figure 11A As shown, the second semiconductor structure 104 may further include an interconnect layer 1126 above the bonding layer 1010 for transmitting electrical signals. The interconnect layer 1126 may include multiple interconnects, such as MEOL interconnects and BEOL interconnects. The interconnect layer 1126 may also include one or more ILD layers, in which lateral lines and vias may be formed. The interconnects in the interconnect layer 1126 may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. The ILD layers in the interconnect layer 1126 may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. In some embodiments, the interconnects in the interconnect layer 1126 include Cu, which has a relatively low resistivity (better electrical performance) among conductive metal materials. As described below regarding the manufacturing process, although Cu has a relatively low thermal budget (incompatible with high-temperature processes), interconnects with Cu interconnect layers 1126 can become feasible because the fabrication of interconnect layer 1126 can be performed after the high-temperature process of forming device layer 1114 in second semiconductor structure 104, and separately from the high-temperature process of forming first semiconductor structure 102.

[0128] like Figure 11AAs shown, the second semiconductor structure 104 can include a device layer 1114 over and in contact with the interconnect layer 1126. In some embodiments, the interconnect layer 1126 is vertically between the bonding interface 103 and the device layer 1114. In some embodiments, the device layer 1114 includes a third peripheral circuit 1116 and a fourth peripheral circuit 1118. The third peripheral circuit 1116 can include the LLV circuit 402, e.g., I / O circuitry (e.g., in the interface 316 and the data bus 318), and the fourth peripheral circuit 1118 can include the LV circuit 404, e.g., page buffer circuitry (e.g., the page buffer circuitry 702 in the page buffer 304) and logic circuitry (e.g., in the control logic 312). In some embodiments, the third peripheral circuit 1116 includes a plurality of transistors 1120, and the fourth peripheral circuit 1118 also includes a plurality of transistors 1122. The transistors 1120 and 1122 can include any of the transistors disclosed herein, e.g., the planar transistor 500 and the 3D transistor 600. As described in detail above with respect to the transistors 500 and 600, in some embodiments, each transistor 1120 or 1122 includes a gate dielectric, and due to the voltage applied to the transistor 1120 being lower than the voltage applied to the transistor 1122, the thickness of the gate dielectric of the transistor 1120 (e.g., in the LLV circuit 402) is less than the thickness of the gate dielectric of the transistor 1122 (e.g., in the LV circuit 404).

[0129] Further, the different voltages applied to the different transistors 1120, 1122, 1108, and 1110 in the second semiconductor structure 104 and the first semiconductor structure 102 can result in a difference in device size between the second semiconductor structure 104 and the first semiconductor structure 102. In some embodiments, due to the voltage applied to the transistor 1108 being higher than the voltage applied to the transistor 1120, the thickness of the gate dielectric of the transistor 1108 (e.g., in the HV circuit 406) is greater than the thickness of the gate dielectric of the transistor 1120 (e.g., in the LLV circuit 402). In some embodiments, due to the voltage applied to the transistor 1122 and the transistor 1110 being the same, the thickness of the gate dielectric of the transistor 1122 (e.g., in the LV circuit 404) is the same as the thickness of the gate dielectric of the transistor 1110 (e.g., in the LV circuit 404). In some embodiments, due to the voltage applied to the transistor 1108 being higher than the voltage applied to the transistor 1120, the thickness of the semiconductor layer 1002 in which the transistor 1108 (e.g., in the HV circuit 406) is formed is greater than the thickness of the semiconductor layer 1004 in which the transistor 1120 (e.g., in the LLV circuit 402) is formed.

[0130] As Figure 11AAs shown, the second semiconductor structure 104 may further include a semiconductor layer 1004 having a semiconductor material. In some embodiments, the semiconductor layer 1004 is a thinned silicon substrate having single-crystal silicon, on which transistors 1120 and 1122 may be formed. The semiconductor layer 1004 may be disposed above and in contact with transistors 1120 and 1122 of the peripheral circuits 1116 and 1118 in the device layer 1114. In some embodiments, transistors 1120 and 1122 are disposed vertically between the bonding interface 103 and the semiconductor layer 1004. Trench isolation (e.g., STI) and doped regions (e.g., the well, source, and drain of transistors 1120 and 1122) may also be formed on or in the semiconductor layer 1004.

[0131] like Figure 11A As shown, the second semiconductor structure 104 may further include a pad-out interconnect layer 902 above and in contact with the semiconductor layer 1004. In some embodiments, the semiconductor layer 1004 is vertically disposed between the pad-out interconnect layer 902 and transistors 1120 and 1122. The pad-out interconnect layer 902 may include interconnects in one or more ILD layers, for example, contact pads 1132. The pad-out interconnect layer 902 and interconnect layer 1126 may be formed on opposite sides of the semiconductor layer 1004. In some embodiments, for example, for pad-out purposes, the interconnects in the pad-out interconnect layer 902 may transmit electrical signals between the 3D memory 1100 and external devices.

[0132] like Figure 11A As shown, the second semiconductor structure 104 may further include one or more contacts 1130 extending vertically through the semiconductor layer 1004. In some embodiments, the contacts 1130 couple interconnects in the interconnect layer 1126 to contact pads 1132 in the interconnect layer 902 for electrical connection through the semiconductor layer 1004. The contacts 1130 may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. In some embodiments, the contacts 1130 include W. In some embodiments, the contacts 1130 include vias surrounded by dielectric spacers (e.g., having silicon oxide) to electrically isolate the vias from the semiconductor layer 1004. Depending on the thickness of the semiconductor layer 1004, the contacts 1130 may be ILVs with depths in the submicron range (e.g., between 10 nm and 10 μm) or TSVs with depths in the micron or tens of micron ranges (e.g., between 1 μm and 100 μm).

[0133] As a result, the peripheral circuits 1104, 1106, 1116, and 1118 in the first semiconductor structure 102 and the second semiconductor structure 104 can be coupled to the NAND memory string 208 in the first semiconductor structure 102 through various interconnect structures, including interconnect layers 1112, 1126, and 1128, bonding layers 1008 and 1010, and contact 1124. Furthermore, the peripheral circuits 1104, 1106, 1116, and 1118 in the 3D memory device 1100 and the NAND memory string 208 can be further coupled to external devices through contact 1130 and pads leading out from the interconnect layer 902.

[0134] It should also be understood that the pad leads of 3D memory devices are not limited to those from sources such as... Figure 11A The second semiconductor structure 104 of the peripheral circuit 1116 shown (corresponding to) Figure 9A ), and can come from a first semiconductor structure 102 having peripheral circuitry 1104 (corresponding to Figure 9B For example, such as Figure 11B As shown, the 3D memory device 1101 may include a pad-out interconnect layer 902 in a first semiconductor structure 102. The pad-out interconnect layer 902 may contact the semiconductor layer 1002 of the first semiconductor structure 102, on which transistors 1108 of peripheral circuitry 1104 are formed. In some embodiments, the first semiconductor structure 102 further includes one or more contacts 1134 extending vertically through the semiconductor layer 1002. In some embodiments, the contacts 1134 couple interconnects in the interconnect layer 1112 of the first semiconductor structure 102 to contact pads 1132 in the pad-out interconnect layer 902 for electrical connection through the semiconductor layer 1002. The contacts 1134 may include a conductive material, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. In some embodiments, the contacts 1134 include W. In some embodiments, the contacts 1134 include vias surrounded by dielectric spacers (e.g., having silicon oxide) to electrically isolate the vias from the semiconductor layer 1002. Depending on the thickness of the semiconductor layer 1002, the contact 1134 can be an ILV with a thickness in the submicron range (e.g., between 10 nm and 10 μm), or a TSV with a depth in the micron or tens of micron range (e.g., between 1 μm and 100 μm). It should be understood that, for ease of description, details of identical components (e.g., materials, manufacturing processes, functions, etc.) in both 3D memory devices 1100 and 1101 will not be repeated.

[0135] Figure 12A-12G This disclosure illustrates some aspects of the formation of Figure 10 The manufacturing process of 3D memory devices. Figure 13A and 13BThis disclosure illustrates some aspects of the formation of Figure 10 Another manufacturing process for 3D memory devices. Figure 14 This disclosure illustrates some aspects of the formation of Figure 10 The flowchart of the method 1400 for 3D memory devices. Figure 12A-12G Examples of 3D memory devices shown in 13A, 13B and 14 include Figure 11A and 11B The 3D memory devices 1100 and 1101 shown are described together. Figure 12A-12G 13A, 13B, and 14. It should be understood that the operations shown in method 1400 are not exhaustive, and other operations may be performed before, after, or between any of the operations shown. Furthermore, some operations may be performed simultaneously, or in conjunction with... Figure 14 The different execution orders shown.

[0136] refer to Figure 14 Method 1400 begins with operation 1402, wherein a first transistor is formed on a first substrate. The first substrate may be a silicon substrate having monocrystalline silicon. Figure 12A As shown, a plurality of transistors 1204 and 1206 are formed on a silicon substrate 1202. Transistors 1204 and 1206 can be formed by a variety of processes, including but not limited to photolithography, dry / wet etching, thin film deposition, thermal growth, implantation, chemical mechanical polishing (CMP), and any other suitable processes. In some embodiments, doped regions are formed in the silicon substrate 1202 by ion implantation and / or thermal diffusion, which serve, for example, as the well and source / drain regions of transistors 1204 and 1206. In some embodiments, isolation regions (e.g., STI) are also formed in the silicon substrate 1202 by wet / dry etching and thin film deposition. In some embodiments, the thickness of the gate dielectric of transistor 1204 differs from the thickness of the gate dielectric of transistor 1206, for example, by depositing a thicker silicon oxide film in a region of transistor 1204 than in a region of transistor 1206, or by etching back a portion of the silicon oxide film deposited in a region of transistor 1206. It should be understood that the details of fabricating transistors 1204 and 1206 may depend on the type of transistor (e.g., Figure 5A , 5B The variations are due to the planar transistor 500 or 3D transistor 600 in 6A and 6B, and therefore will not be elaborated further for the sake of description.

[0137] In some embodiments, an interconnect layer 1208 is formed over the transistors on the first substrate. The interconnect layer may include multiple interconnects within one or more ILD layers. Figure 12AAs shown, an interconnect layer 1208 can be formed over transistors 1204 and 1206. The interconnect layer 1208 may include MEOL and / or BEOL interconnects in a plurality of ILD layers for electrical connection to transistors 1204 and 1206. In some embodiments, the interconnect layer 1208 includes a plurality of ILD layers and interconnects formed therein using a plurality of processes. For example, the interconnects in the interconnect layer 1208 may include conductive materials deposited by one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof). The fabrication process forming the interconnects may also include photolithography, CMP, wet / dry etching, or any other suitable process. The ILD layers may include dielectric materials deposited by one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, or any combination thereof). Figure 12A The ILD layer and interconnects shown can be collectively referred to as interconnect layer 1208. In some embodiments, the interconnects in interconnect layer 1208 include W, which has a relatively high thermal budget in a conductive metallic material to withstand subsequent high-temperature processes.

[0138] Method 1400 proceeds to operation 1404, such as... Figure 14 As shown, a polysilicon layer is formed above the first transistor. Figure 12A As shown, a polysilicon layer 1211 is formed over the interconnect layer 1208 and transistors 1204 and 1206 on the first silicon substrate 1202. The polysilicon layer 1211 can be formed by depositing polysilicon on the interconnect layer 1208 using one or more thin-film deposition processes (including but not limited to CVD, PVD, ALD, or any combination thereof). In some embodiments, the polysilicon layer 1211 is doped with P-type or N-type dopant using an in-situ doping process during the deposition process or an ion implantation / diffusion process after the deposition process.

[0139] Method 1400 proceeds to operation 1406, such as... Figure 14 As shown, an array of NAND memory strings is formed on a polysilicon layer. In some embodiments, a memory stack layer is formed on the polysilicon layer to form the array of NAND memory strings. Figure 12CAs shown, a stacked layer structure, such as a memory stacked layer 1226 comprising staggered conductive and dielectric layers, is formed on a polysilicon layer 1211. To form the memory stacked layer 1226, in some embodiments, a dielectric stacked layer (not shown) comprising staggered sacrificial layers (not shown) and dielectric layers is formed on the polysilicon layer 1211. In some embodiments, each sacrificial layer comprises a silicon nitride layer, and each dielectric layer comprises a silicon oxide layer. The staggered sacrificial and dielectric layers can be formed by one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, or any combination thereof). The memory stacked layer 1226 can then be formed by a gate replacement process, for example, by replacing the sacrificial layers with conductive layers using a wet / dry etching process that selectively etches the dielectric layers, and filling the resulting trenches with conductive layers. In some embodiments, each conductive layer comprises a metal layer, such as a W layer. It should be understood that, in some examples, the memory stack 1226 can be formed by alternately depositing conductive layers (e.g., doped polysilicon layers) and dielectric layers (e.g., silicon oxide layers) without a gate replacement process. In some embodiments, a pad oxide layer comprising silicon oxide is formed between the memory stack 1226 and the polysilicon layer 1211.

[0140] like Figure 12C As shown, a NAND memory string 1228 is formed above a polysilicon layer 1211, with each string extending vertically through a memory stack layer 1226 to contact the polysilicon layer 1211. In some embodiments, the fabrication process for forming the NAND memory string 1228 includes forming channel vias through the memory stack layer 1226 (or dielectric stack layer) and into the polysilicon layer 1211 using dry etching and / or wet etching (e.g., deep reactive ion etching (DRIE)), followed by filling the channel vias with multiple layers (e.g., memory films (e.g., tunneling layers, storage layers, and barrier layers) and semiconductor layers) using thin-film deposition processes (e.g., ALD, CVD, PVD, or any combination thereof). It should be understood that the details of fabricating the NAND memory string 1228 can depend on the type of channel structure of the NAND memory string 1228 (e.g., Figure 8 The channel structure (812) varies, and therefore will not be elaborated further for ease of description.

[0141] In some implementations, an interconnect layer is formed above an array of NAND memory strings. The interconnect layer may include a plurality of interconnects within one or more ILD layers. Figure 12CAs shown, an interconnect layer 1230 is formed over the memory stack layer 1226 and the NAND memory string 1228. The interconnect layer 1230 may include interconnects of MEOL and / or BEOL in a plurality of ILD layers for electrical connection to the NAND memory string 1228. In some embodiments, the interconnect layer 1230 includes a plurality of ILD layers and interconnects formed therein using a plurality of processes. For example, the interconnects in the interconnect layer 1230 may include conductive materials deposited by one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof). The fabrication processes forming the interconnects may also include photolithography, CMP, wet / dry etching, or any other suitable process. The ILD layers may include dielectric materials deposited by one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, or any combination thereof). Figure 12D The ILD layer and interconnect shown can be collectively referred to as interconnect layer 1230.

[0142] In some implementations, contacts are formed through the polysilicon layer. For example... Figure 12C As shown, one or more contacts 1224 are formed, each extending vertically through the polysilicon layer 1211. The contacts 1224 can couple interconnects in interconnect layers 1230 and 1208. The contacts 1224 can be formed by first patterning contact holes through the polysilicon layer 1211 using a patterning process (e.g., photolithography and dry / wet etching of the dielectric material in the dielectric layer). The contact holes can be filled with a conductor (e.g., W or Cu). In some embodiments, filling the contact holes includes depositing a spacer (e.g., a silicon oxide layer) before depositing the conductor.

[0143] In some implementations, a first bonding layer is formed over the interconnect layer. The first bonding layer may include a plurality of first bonding contacts. For example... Figure 12C As shown, a bonding layer 1232 is formed over the interconnect layer 1230. The bonding layer 1232 may include a plurality of bonding contacts surrounded by a dielectric. In some embodiments, a dielectric layer is deposited on the top surface of the interconnect layer 1230 by one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, or any combination thereof). Then, by patterning contact holes through the dielectric layer first by using a patterning process (e.g., photolithography and dry / wet etching of the dielectric material in the dielectric layer), bonding contacts that penetrate the dielectric layer and contact the interconnects in the interconnect layer 1230 can be formed. The contact holes may be filled with a conductor (e.g., Cu). In some embodiments, filling the contact holes includes depositing an adhesive layer, a barrier layer, and / or a seed layer prior to depositing the conductor.

[0144] Method 1400 proceeds to operation 1408, such as... Figure 14As shown, a second transistor is formed on a second substrate. The second substrate can be a silicon substrate with single crystalline silicon. As Figure 12D As shown, a plurality of transistors 1214 and 1216 are formed on a silicon substrate 1210 with single crystalline silicon. The transistors 1214 and 1216 can be formed by a variety of processes, including but not limited to photolithography, dry / wet etching, thin film deposition, thermal growth, implantation, CMP, and any other suitable processes. In some embodiments, doped regions are formed in the silicon substrate 1210 by ion implantation and / or thermal diffusion, which serve as, for example, well and source / drain regions for the transistors 1214 and 1216. In some embodiments, isolation regions (e.g., STI) are also formed in the silicon substrate 1210 by wet / dry etching and thin film deposition. In some embodiments, the thickness of the gate dielectric of the transistor 1214 is different from the thickness of the gate dielectric of the transistor 1216, for example, by depositing a thicker silicon oxide film in the region of the transistor 1214 than in the region of the transistor 1216, or by etching back a portion of the silicon oxide film deposited in the region of the transistor 1216. It should be appreciated that the details of fabricating the transistors 1214 and 1216 can vary depending on the type of transistors (e.g., planar or 3D), and thus are not elaborated further for ease of description. Figure 5A 、 5B , the planar transistor 500 or the 3D transistor 600 in FIGS. 6A and 6B) and thus are not elaborated further for ease of description.

[0145] In some embodiments, an interconnect layer 1220 is formed over the transistors on the second substrate. The interconnect layer can include a plurality of interconnects in one or more ILD layers. As Figure 12D As shown, an interconnect layer 1220 can be formed over the transistors 1214 and 1216. The interconnect layer 1220 can include interconnects of MEOL and / or BEOL in a plurality of ILD layers to electrically connect with the transistors 1214 and 1216. In some embodiments, the interconnect layer 1220 includes a plurality of ILD layers and interconnects formed therein by a plurality of processes. For example, the interconnects in the interconnect layer 1220 can include conductive materials deposited by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. The fabrication processes to form the interconnects can also include photolithography, CMP, wet / dry etching, or any other suitable processes. The ILD layers can include dielectric materials deposited by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. Figure 12CThe ILD layers and interconnects shown in FIG. 12A can be collectively referred to as interconnect layers 1220. Unlike the interconnect layers 1208, in some embodiments, the interconnects in the interconnect layers 1220 comprise Cu, which has a relatively low resistivity among conductive metal materials. It should be appreciated that although Cu has a relatively low thermal budget (not compatible with high temperature processes), it becomes feasible to use Cu as the conductive material for the interconnects in the interconnect layers 1220 because there are no high temperature processes after the fabrication of the interconnect layers 1220.

[0146] In some embodiments, a second bonding layer is formed over the interconnect layers. The second bonding layer can include a plurality of second bonding contacts. As Figure 12D shown in FIG. 12A, a bonding layer 1222 is formed over the interconnect layers 1220. The bonding layer 1222 can include a plurality of bonding contacts surrounded by a dielectric. In some embodiments, a dielectric layer is deposited on the top surface of the interconnect layers 1220 by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. Then, by first patterning contact holes through the dielectric layer using a patterning process (e.g., photolithography and dry / wet etching of the dielectric material in the dielectric layer), bonding contacts can be formed through the dielectric layer and in contact with the interconnect contacts in the interconnect layers 1220. The contact holes can be filled with a conductor (e.g., Cu). In some embodiments, filling the contact holes includes depositing an adhesion (glue) layer, a barrier layer, and / or a seed layer before depositing the conductor.

[0147] The method 1400 proceeds to operation 1410, as Figure 14 shown, where the first substrate and the second substrate are bonded in a face-to-face manner. After bonding the first and second substrates, the first bonding contacts in the first bonding layer can be in contact with the second bonding contacts in the second bonding layer at the bonding interface. The bonding can include hybrid bonding.

[0148] As Figure 12E shown, the silicon substrate 1210 and the components (e.g., transistors 1214 and 1216) formed thereon are flipped upside down. The downward facing bonding layer 1222 is bonded with the upward facing bonding layer 1232, i.e., in a face-to-face manner, thereby forming a bonding interface 1212. That is, the silicon substrate 1210 and the components formed thereon can be bonded with the silicon substrate 1202 and the components formed thereon in a face-to-face manner, such that the bonding contacts in the bonding layer 1232 are in contact with the bonding contacts in the bonding layer 1222 at the bonding interface 1212. In some embodiments, a treatment process, such as a plasma treatment, a wet treatment, and / or a thermal treatment, is applied to the bonding surfaces before the bonding. Although Figure 12EAs not shown, but it should be understood that in some examples, the silicon substrate 1202 and the components formed thereon (e.g., transistors 1204, 1206, memory stack 1226, and NAND memory string 1228) can be flipped upside down, and the downside bonding layer 1232 can be bonded to the upside bonding layer 1222, i.e., bonded face to face, thereby also forming the bonding interface 1212.

[0149] As a result of bonding (e.g., hybrid bonding), the bonding contacts on opposite sides of bonding interface 1212 can be mixed with each other. After bonding, according to some embodiments, the bonding contacts in bonding layer 1232 and bonding layer 1222 are aligned and in contact with each other, such that the memory stack layer 1226 and NAND memory string 1228 formed therethrough, as well as transistors 1204 and 1206, can be coupled to transistors 1214 and 1216 through the bonding contacts bonded on bonding interface 1212.

[0150] like Figure 14 As shown, method 1400 proceeds to operation 1412, in which the first substrate or the second substrate is thinned. In some embodiments, such as Figure 12F As shown, silicon substrate 1210 ( Figure 12E The silicon substrate 1210 is thinned to form a semiconductor layer 1234 having monocrystalline silicon. The thinning can be achieved by processes including, but not limited to, wafer grinding, dry etching, wet etching, CMP, any other suitable process, or any combination thereof. In some embodiments, such as... Figure 13A As shown, silicon substrate 1202 ( Figure 12E The silicon substrate 1202 can be thinned to form a semiconductor layer 1302 having monocrystalline silicon (as shown in the diagram). Similarly, the silicon substrate 1202 can be thinned by processes including but not limited to wafer grinding, dry etching, wet etching, CMP, any other suitable process or any combination thereof.

[0151] like Figure 14 As shown, method 1400 proceeds to operation 1414, in which a pad-out interconnect layer is formed. The pad-out interconnect layer can be formed on a thinned second substrate or on a thinned first substrate.

[0152] In some implementations, such as Figure 12GAs shown, a pad-out interconnect layer 1236 is formed on the semiconductor layer 1234 (thinned silicon substrate 1210). The pad-out interconnect layer 1236 can include interconnects formed in one or more ILD layers, such as contact pads 1238. The contact pads 1238 can include a conductive material, including but not limited to W, Co, Cu, Al, doped silicon, silicide, or any combination thereof. The ILD layers can include a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. In some embodiments, after bonding and thinning, contacts 1235 are formed that extend vertically through the semiconductor layer 1234, such as by wet / dry etching, followed by deposition of a dielectric material as a spacer and a conductive material as a conductor. The contacts 1235 can couple the contact pads 1238 in the pad-out interconnect layer 1236 to interconnects in the interconnect layer 1220. It will be appreciated that in some examples, the contacts 1235 can be formed in the silicon substrate 1210 prior to thinning (formation of the semiconductor layer 1234) and exposed from the backside of the silicon substrate 1210 (where thinning occurs) after thinning. Figure 12D As shown, a pad-out interconnect layer 1306 is formed on the semiconductor layer 1302 (thinned silicon substrate 1202). The pad-out interconnect layer 1306 can include interconnects formed in one or more ILD layers, such as contact pads 1308. The contact pads 1308 can include a conductive material, including but not limited to W, Co, Cu, Al, doped silicon, silicide, or any combination thereof. The ILD layers can include a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. In some embodiments, after bonding and thinning, contacts 1304 are formed that extend vertically through the semiconductor layer 1302, such as by wet / dry etching, followed by deposition of a dielectric material as a spacer and a conductive material as a conductor. The contacts 1304 can couple the contact pads 1308 in the pad-out interconnect layer 1306 to interconnects in the interconnect layer 1208. It will be appreciated that in some examples, the contacts 1304 can be formed in the silicon substrate 1202 prior to thinning (formation of the semiconductor layer 1234) and exposed from the backside of the silicon substrate 1202 (where thinning occurs) after thinning.

[0153] In some embodiments, as shown in FIGS. 12A and 12B, a semiconductor layer 1202 is formed on a silicon substrate 1200. The semiconductor layer 1202 can include a semiconductor material, such as silicon, germanium, silicon- germanium, silicon-carbide, gallium-arsenide, or any combination thereof. The semiconductor layer 1202 can be formed by epitaxy, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or any combination thereof. In some embodiments, the semiconductor layer 1202 can be formed by a process that includes a chemical-mechanical polishing (CMP) step, such as a CMP step to planarize the semiconductor layer 1202. In some embodiments, the semiconductor layer 1202 can be formed by a process that includes a CMP step to planarize the semiconductor layer 1202 and a CMP step to planarize the silicon substrate 1200. In some embodiments, the semiconductor layer 1202 can be formed by a process that includes a CMP step to planarize the semiconductor layer 1202 and a CMP step to planarize the silicon substrate 1200, and a CMP step to planarize the semiconductor layer 1202 and the silicon substrate 1200. Figure 13B As shown, a pad-out interconnect layer 1236 is formed on the semiconductor layer 1234 (thinned silicon substrate 1210). The pad-out interconnect layer 1236 can include interconnects formed in one or more ILD layers, such as contact pads 1238. The contact pads 1238 can include a conductive material, including but not limited to W, Co, Cu, Al, doped silicon, silicide, or any combination thereof. The ILD layers can include a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. In some embodiments, after bonding and thinning, contacts 1235 are formed that extend vertically through the semiconductor layer 1234, such as by wet / dry etching, followed by deposition of a dielectric material as a spacer and a conductive material as a conductor. The contacts 1235 can couple the contact pads 1238 in the pad-out interconnect layer 1236 to interconnects in the interconnect layer 1220. It will be appreciated that in some examples, the contacts 1235 can be formed in the silicon substrate 1210 prior to thinning (formation of the semiconductor layer 1234) and exposed from the backside of the silicon substrate 1210 (where thinning occurs) after thinning.

[0154] Figure 15A and 15B FIGS. 15A and 15B show schematic diagrams of cross-sections of 3D memory devices in accordance with various aspects of the present disclosure. The 3D memory devices 1500 and 1501 can be Figure 9A and 9B FIGS. 15A and 15B show schematic diagrams of cross-sections of 3D memory devices in accordance with various aspects of the present disclosure. The 3D memory devices 1500 and 1501 can be Figure 9A and 9BExamples of 3D memory devices 900 and 901. (See example...) Figure 15A As shown, the 3D memory device 1500 may include a stacked first semiconductor structure 102 and a second semiconductor structure 104. In some embodiments, the first semiconductor structure 102 includes a semiconductor layer 1002, a polysilicon layer 106, a bonding layer 1008, a memory cell array vertically disposed between the polysilicon layer 106 and the bonding layer 1008, and some peripheral circuitry vertically disposed between the semiconductor layer 1002 and the polysilicon layer 106.

[0155] The memory cell array may include an array of NAND memory strings (e.g., NAND memory string 208 disclosed herein), and the source of the array of NAND memory strings may be in contact with the polysilicon layer 106 (e.g., as shown in the image). Figure 8 (As shown in the diagram). The polysilicon layer 106 may be a deposited polysilicon layer (e.g., N-type doped, P-type doped, or undoped), suitable for channel structures in "floating gate" type NAND memory strings or, for example, "charge trap" type NAND memory strings suitable for GIDL erase operations (e.g., as shown in the diagram). Figure 8 Certain designs of the channel structure 812 in the middle. The bonding layer 1008 may include a dielectric of conductive bonding contacts (not shown) and electrically isolating bonding contacts, which can be used for hybrid bonding, for example, as described in detail below.

[0156] In some embodiments, peripheral circuitry in the first semiconductor structure 102 contacts the semiconductor layer 1002 but not the polysilicon layer 106. That is, transistors of the peripheral circuitry (e.g., planar transistors 500 and 3D transistors 600) may contact the semiconductor layer 1002. The semiconductor layer 1002 may comprise a semiconductor material, such as monocrystalline silicon (e.g., a silicon substrate or a thinned silicon substrate). It should be understood that in some examples, unlike the polysilicon layer 106 in the first semiconductor structure 102, the semiconductor layer 1002 on which transistors are formed may comprise monocrystalline silicon, but not polycrystalline silicon, due to the superior carrier mobility of monocrystalline silicon desired for transistor performance. Through-contacts (e.g., ILV / TSV) through the polysilicon layer 106 may form direct, short-distance (e.g., submicron or micron-scale) electrical connections between the memory cell array in the first semiconductor structure 102 and the peripheral circuitry.

[0157] In some embodiments, the second semiconductor structure 104 includes a semiconductor layer 1004, a bonding layer 1010, and some of the peripheral circuitry of the memory cell array. The semiconductor layer 1004 can be vertically between the peripheral circuitry and the bonding layer 1010. Transistors (e.g., planar transistors 500 and 3D transistors 600) of the peripheral circuitry can be in contact with the semiconductor layer 1004. Similar to the semiconductor layer 1002, the semiconductor layer 1004 can include a semiconductor material, such as single crystalline silicon (e.g., a silicon substrate or a thinned silicon substrate). It should be appreciated that, in some examples, unlike the polysilicon layer 106 in the first semiconductor structure 102, the semiconductor layer 1004 on which the transistors are formed can include single crystalline silicon, rather than polysilicon, due to the superior carrier mobility of single crystalline silicon that is desirable for the performance of the transistors. The peripheral circuitry and the bonding layer 1010 can be formed on opposite sides of the semiconductor layer 1004, such that the semiconductor layer 1004 is disposed vertically between the peripheral circuitry and the bonding layer 1010. In some embodiments, the transistors of the peripheral circuitry are formed on a front side of the semiconductor layer 1004, and the bonding contacts of the bonding layer 1010 are formed on a back side of the semiconductor layer 1004.

[0158] Similar to the bonding layer 1008 in the first semiconductor structure 102, the bonding layer 1010 can also include electrically conductive bonding contacts (not shown) and a dielectric that electrically isolates the bonding contacts. According to some embodiments, the bonding interface 103 is vertically between and in contact with the bonding layers 1008 and 1010, respectively. That is, the bonding layers 1008 and 1010 can be disposed on opposite sides of the bonding interface 103, and the bonding contacts of the bonding layer 1008 can be in contact with the bonding contacts of the bonding layer 1010 at the bonding interface 103. As a result, a large number (e.g., millions) of bonding contacts across the bonding interface 103, through-via contacts (e.g., ILV / TSVs) through the semiconductor layer 1004, can make direct, short distance (e.g., micron-level) electrical connections between the adjacent semiconductor structures 102 and 104.

[0159] It should be appreciated that, in some examples, the first semiconductor structure 102 and the second semiconductor structure 104 can not include the bonding layers 1008 and 1010, respectively, disposed on opposite sides of the bonding interface 103, as shown in FIG. 1A. For example, the bonding interface 103 can be a single layer of a dielectric that electrically isolates the bonding contacts of the first semiconductor structure 102 and the second semiconductor structure 104. Figure 15A Figure 15B ​In some embodiments, the semiconductor layer 1004 in the second semiconductor structure 104 of the 3D memory device 1501 can be a monocrystalline silicon layer transferred from a silicon substrate or an SOI substrate and attached to a top surface of the first semiconductor structure 102 by transfer bonding, and the bonding interface 103 between the first semiconductor structure 102 and the second semiconductor structure 104 can be created by the transfer bonding, as opposed to hybrid bonding. Through-via contacts (e.g., ILV / TSVs) vertically through the semiconductor layer 1004 between the first semiconductor structure 102 and the second semiconductor structure 104 can make direct, short-distance (e.g., sub-micron) electrical connections between the adjacent semiconductor structures 102 and 104.

[0160] As shown in FIGS. 1A and IB, the first semiconductor structure 102 and the second semiconductor structure 104 can be bonded in a face-to-back manner (e.g., with the semiconductor layer 1002 on the bottom side of the first semiconductor structure 102 and the semiconductor layer 1004 on the top side of the second semiconductor structure 104) in some embodiments. Figure 15A 15B As shown in FIGS. 1A and IB, the first semiconductor structure 102 and the second semiconductor structure 104 can be bonded in a face-to-back manner (e.g., with the semiconductor layer 1002 on the bottom side of the first semiconductor structure 102 and the semiconductor layer 1004 on the top side of the second semiconductor structure 104) in some embodiments. Figure 15A 15B As shown in FIGS. 1A and IB, the first semiconductor structure 102 and the second semiconductor structure 104 can be bonded in a face-to-back manner (e.g., with the semiconductor layer 1002 on the bottom side of the first semiconductor structure 102 and the semiconductor layer 1004 on the top side of the second semiconductor structure 104) in some embodiments. Figure 15A 15B As shown in FIGS. 1A and IB, the first semiconductor structure 102 and the second semiconductor structure 104 can be bonded in a face-to-back manner (e.g., with the semiconductor layer 1002 on the bottom side of the first semiconductor structure 102 and the semiconductor layer 1004 on the top side of the second semiconductor structure 104) in some embodiments. Figure 15A 15B As shown in FIGS. 1A and IB, the first semiconductor structure 102 and the second semiconductor structure 104 can be bonded in a face-to-back manner (e.g., with the semiconductor layer 1002 on the bottom side of the first semiconductor structure 102 and the semiconductor layer 1004 on the top side of the second semiconductor structure 104) in some embodiments. Figure 9A Figure 9B As shown in FIGS. 1A and IB, the first semiconductor structure 102 and the second semiconductor structure 104 can be bonded in a face-to-back manner (e.g., with the semiconductor layer 1002 on the bottom side of the first semiconductor structure 102 and the semiconductor layer 1004 on the top side of the second semiconductor structure 104) in some embodiments. Figure 15A Figure 15B As shown in FIGS. 1A and IB, the first semiconductor structure 102 and the second semiconductor structure 104 can be bonded in a face-to-back manner (e.g., with the semiconductor layer 1002 on the bottom side of the first semiconductor structure 102 and the semiconductor layer 1004 on the top side of the second semiconductor structure 104) in some embodiments. Figure 9A Figure 9B As shown in FIGS. 1A and IB, the first semiconductor structure 102 and the second semiconductor structure 104 can be bonded in a face-to-back manner (e.g., with the semiconductor layer 1002 on the bottom side of the first semiconductor structure 102 and the semiconductor layer 1004 on the top side of the second semiconductor structure 104) in some embodiments.

[0161] As shown in FIGS. 1A and IB, the first semiconductor structure 102 and the second semiconductor structure 104 can be bonded in a face-to-back manner (e.g., with the semiconductor layer 1002 on the bottom side of the first semiconductor structure 102 and the semiconductor layer 1004 on the top side of the second semiconductor structure 104) in some embodiments. Figure 4B Figure 4B ​​​​​​​​one example, the first semiconductor structure 102 can include the HV circuit 406, the second semiconductor structure 104 can include the LLV circuit 402, and the thickness of the semiconductor layer 1002 in the first semiconductor structure 102 can be greater than the thickness of the semiconductor layer 1004 in the second semiconductor structure 104. Further, in some implementations, the gate dielectric of the transistors in the first semiconductor structure 102 and the second semiconductor structure 104 also have different thicknesses to accommodate the different voltages applied. In one example, the first semiconductor structure 102 can include the HV circuit 406, the second semiconductor structure 104 can include the LLV circuit 402, and the thickness of the gate dielectric of the transistors in the first semiconductor structure 102 can be greater (e.g., at least 5 times) than the thickness of the gate dielectric of the transistors in the second semiconductor structure 104.

[0162] Figure 16A and 16B FIG. 16 shows a side view of various examples of 3D memory devices 1600 and 1601 in accordance with various aspects of the present disclosure. Figure 15A and 15B FIG. 16 shows a side view of various examples of 3D memory devices 1600 and 1601 in accordance with various aspects of the present disclosure. Figure 16A As shown, as one example of 3D memory devices 1500 and 1501 in Figure 15A and 15B As shown, as one example of 3D memory devices 1500 and 1501 in Figure 16A According to some implementations, the first semiconductor structure 102 and the second semiconductor structure 104 are bonded at a bonding interface 103 therebetween.

[0163] As shown, as one example of 3D memory devices 1500 and 1501 in Figure 16AAs shown, the first semiconductor structure 102 can include a semiconductor layer 1002 having a semiconductor material. In some embodiments, the semiconductor layer 1002 is a silicon substrate having single-crystal silicon. The first semiconductor structure 102 can also include a device layer 1602 over and in contact with the semiconductor layer 1002. In some embodiments, the device layer 1602 includes a first peripheral circuit 1604 and a second peripheral circuit 1606. The first peripheral circuit 1604 can include HV circuitry 406, such as drive circuitry (e.g., string drivers 704 in row decoders / word line drivers 308 and drivers in column decoders / bit line drivers 306), and the second peripheral circuit 1606 can include LV circuitry 404, such as page buffer circuitry (e.g., page buffer circuitry 702 in page buffers 304) and logic circuitry (e.g., in control logic 312). In some embodiments, the first peripheral circuit 1604 includes a plurality of transistors 1608 in contact with the semiconductor layer 1002, and the second peripheral circuit 1606 includes a plurality of transistors 1610 in contact with the semiconductor layer 1002. The transistors 1608 and 1610 can include any of the transistors disclosed herein, such as planar transistor 500 and 3D transistor 600. As described in detail above with respect to transistors 500 and 600, in some embodiments, each transistor 1608 or 1610 includes a gate dielectric, and because the voltage applied to the transistors 1608 is higher than the voltage applied to the transistors 1610, the thickness of the gate dielectric of the transistors 1608 (e.g., in HV circuitry 406) is greater than the thickness of the gate dielectric of the transistors 1610 (e.g., in LV circuitry 404). Trench isolation (e.g., STI) and doped regions (e.g., wells, sources, and drains of transistors 1608 and 1610) can also be formed on or in the semiconductor layer 1002.

[0164] In some embodiments, the first semiconductor structure 102 also includes an interconnect layer 1612 over the device layer 1102 to transmit electrical signals to and from the peripheral circuits 1106 and 1104. As shown, the interconnect layer 1612 includes a plurality of conductive lines 1614 and a plurality of vias 1616. The conductive lines 1614 can be formed of any suitable conductive material, such as copper, and can be formed by any suitable process, such as damascene processing. The vias 1616 can be formed of any suitable conductive material, such as tungsten, and can be formed by any suitable process, such as sputtering. Figure 16AAs shown, interconnect layer 1612 may be perpendicularly positioned between polysilicon layer 106 and device layer 1602 (including transistors 1608 and 1610 of peripheral circuits 1604 and 1606). Interconnect layer 1612 may include multiple interconnects, such as MEOL interconnects and BEOL interconnects. Interconnects in interconnect layer 1612 may be coupled to transistors 1608 and 1610 of peripheral circuits 1604 and 1606 in device layer 1602. Interconnect layer 1612 may also include one or more ILD layers in which lateral lines and vias may be formed. That is, interconnect layer 1612 may include lateral lines and vias in multiple ILD layers. In some embodiments, devices in device layer 1602 are coupled to each other through interconnects in interconnect layer 1612. For example, peripheral circuit 1604 may be coupled to peripheral circuit 1606 through interconnect layer 1612. Interconnects in interconnect layer 1612 may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. The ILD layer in interconnect layer 1612 may include a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low dielectric constant (low k) dielectric, or any combination thereof. In some embodiments, the interconnects in interconnect layer 1612 include W, which has a relatively high thermal budget (compatible with high-temperature processes) and good quality (fewer defects, such as voids) in a conductive metallic material.

[0165] like Figure 16A As shown, the first semiconductor structure may further include a polysilicon layer 106 above and in contact with the interconnect layer 1612. According to some embodiments, the polysilicon layer 106 is a doped polysilicon layer on the interconnect layer 1612, as described in detail below with respect to the manufacturing process. It should be understood that in some examples, trench isolation and doped regions (not shown) may also be formed in the polysilicon layer 106.

[0166] like Figure 16A As shown, the first semiconductor structure 102 may further include an array of memory cells, such as an array of NAND memory strings 208 above and in contact with the polysilicon layer 106. The sources of the NAND memory strings 208 may be in contact with the polysilicon layer 106. In some embodiments, the polysilicon layer 106 is perpendicularly positioned between the NAND memory strings 208 and the device layer 1602, which includes transistors 1608 and 1610. In some embodiments, each NAND memory string 208 is a "charge-trapping" type NAND memory string, which includes any suitable channel structure disclosed herein, such as those described above. Figure 8 The channel structure 812 is described in detail. In some embodiments, the NAND memory string 208 is a "floating gate" type NAND memory string, and the polysilicon layer 106 is the source plate of the floating gate type NAND memory string.

[0167] According to some implementations, each NAND memory string 208 extends vertically through multiple pairs, each including a conductive layer and a dielectric layer. The stacked and interleaved conductive and dielectric layers are also referred to herein as a stacked layer structure, for example, memory stack 1627. Memory stack 1627 may be... Figure 8 Examples of memory stack layer 804 include the conductive layer and dielectric layer in memory stack layer 1627, which may be examples of gate conductive layer 806 and dielectric layer 808 in memory stack layer 804, respectively. According to some embodiments, the staggered conductive and dielectric layers in memory stack layer 1627 alternate in the vertical direction. Each conductive layer may include a gate electrode (gate line) surrounded by an adhesive layer and a gate dielectric layer. The gate electrode of the conductive layer may extend laterally as a word line, terminating at one or more stepped structures in memory stack layer 1627.

[0168] like Figure 16A As shown, the first semiconductor structure 102 may further include an interconnect layer 1628 above and in contact with the NAND memory string 208, for transmitting electrical signals to and from the NAND memory string 208. In some embodiments, the memory stack layer 1627 and the NAND memory string 208 are perpendicularly positioned between the interconnect layer 1628 and the polysilicon layer 106. The interconnect layer 1628 may include multiple interconnects, such as MEOL interconnects and BEOL interconnects. In some embodiments, the interconnects in the interconnect layer 1628 may also include local interconnects, such as bit line contacts and word line contacts. The interconnect layer 1628 may also include one or more ILD layers in which lateral lines and vias may be formed. The interconnects in the interconnect layer 1628 may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. The ILD layers in the interconnect layer 1628 may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0169] like Figure 16AAs shown, the first semiconductor structure 102 may further include one or more contacts 1624 extending vertically through the polysilicon layer 106. In some embodiments, the contacts 1624 couple interconnects in the interconnect layer 1628 to interconnects in the interconnect layer 1612 to provide electrical connection between the NAND memory string 208 and transistors 1608 and 1610 through the polysilicon layer 106. The contacts 1624 may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. In some embodiments, the contacts 1624 include W. In some embodiments, the contacts 1624 include vias surrounded by dielectric spacers (e.g., having silicon oxide) to electrically isolate the vias from the polysilicon layer 106. Depending on the thickness of the polysilicon layer 106, the contact 1624 can be an ILV with a depth (in the vertical direction) in the submicron range (e.g., between 10 nm and 10 μm), or a TSV with a depth (in the vertical direction) in the micron range or tens of micron range (e.g., between 1 μm and 100 μm).

[0170] like Figure 16A As shown, the first semiconductor structure 102 may further include a bonding layer 1008 at the bonding interface 103, located above and in contact with the interconnect layer 1628. The bonding layer 1008 may include a dielectric material comprising a plurality of bonding contacts and electrically isolating bonding contacts. The bonding contacts may comprise conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. In some embodiments, the bonding contacts of the bonding layer 1008 comprise Cu. The remaining region of the bonding layer 1008 may be formed of a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. The bonding contacts in the bonding layer 1008 and the surrounding dielectric material may be used for hybrid bonding (also known as “metal / dielectric hybrid bonding”), a direct bonding technique (e.g., forming a bond between surfaces without using an intermediate layer, such as solder or adhesive), and may simultaneously achieve metal-to-metal (e.g., Cu-Cu) bonding and dielectric-to-dielectric (e.g., SiO2-SiO2) bonding.

[0171] like Figure 16AAs shown, the second semiconductor structure 104 can be bonded in a back-to-back fashion on top of the first semiconductor structure 102 at the bonding interface 103. The second semiconductor structure 104 can also include a bonding layer 1010 at the bonding interface 103, for example, on the opposite side of the bonding interface 103 relative to the bonding layer 1008 in the first semiconductor structure 102. The bonding layer 1010 can include a plurality of bonding contacts and a dielectric that electrically isolates the bonding contacts. The bonding contacts can include a conductive material, for example, Cu. The remaining areas of the bonding layer 1010 can be formed of a dielectric material, such as silicon oxide. The bonding contacts in the bonding layer 1010 and the surrounding dielectric can be used for hybrid bonding. In some embodiments, the bonding interface 103 is where the bonding layers 1008 and 1010 meet and bond. In effect, the bonding interface 103 can be a layer of a particular thickness that includes a top surface of the bonding layer 1008 of the first semiconductor structure 102 and a bottom surface of the bonding layer 1010 of the second semiconductor structure 104.

[0172] As Figure 16AAs shown, the second semiconductor structure 104 can also include a semiconductor layer 1004 having a semiconductor material. A bonding layer 1010 can be formed on a backside of the semiconductor layer 1004 and disposed vertically between the semiconductor layer 1004 and the bonding interface 103. In some embodiments, the semiconductor layer 1004 is a thinned silicon substrate having single crystalline silicon. The second semiconductor structure 104 can also include a device layer 1614 over and in contact with the semiconductor layer 1004. In some embodiments, the device layer 1614 includes a third peripheral circuit 1616 and a fourth peripheral circuit 1618 over and in contact with the semiconductor layer 1004. In some embodiments, the semiconductor layer 1004 is disposed vertically between the bonding interface 103 and the device layer 1614 having the peripheral circuits 1616 and 1618. The third peripheral circuit 1616 can include the LLV circuit 402, e.g., I / O circuits (e.g., in the interface 316 and the data bus 318), and the fourth peripheral circuit 1618 can include the LV circuit 404, e.g., page buffer circuits (e.g., the page buffer circuits 702 in the page buffer 304) and logic circuits (e.g., in the control logic 312). In some embodiments, the third peripheral circuit 1616 includes a plurality of transistors 1620 and the fourth peripheral circuit 1618 also includes a plurality of transistors 1622. The transistors 1620 and 1622 can include any of the transistors disclosed herein, e.g., the planar transistor 500 and the 3D transistor 600. As described in detail above with respect to the transistors 500 and 600, in some embodiments, each of the transistors 1620 or 1622 includes a gate dielectric and the thickness of the gate dielectric of the transistors 1620 (e.g., in the LLV circuit 402) is less than the thickness of the gate dielectric of the transistors 1622 (e.g., in the LV circuit 404) due to the voltage applied to the transistors 1620 being lower than the voltage applied to the transistors 1622.

[0173] Furthermore, different voltages applied to the different transistors 1620, 1622, 1608, and 1610 in the second semiconductor structure 104 and the first semiconductor structure 102 can lead to differences in device dimensions between the second semiconductor structure 104 and the first semiconductor structure 102. In some embodiments, because the voltage applied to transistor 1608 is higher than the voltage applied to transistor 1620, the thickness of the gate dielectric of transistor 1608 (e.g., in HV circuit 406) is greater than the thickness of the gate dielectric of transistor 1620 (e.g., in LLV circuit 402). In some embodiments, because the voltages applied to transistors 1622 and 1610 are the same, the thickness of the gate dielectric of transistor 1622 (e.g., in LV circuit 404) is the same as the thickness of the gate dielectric of transistor 1610 (e.g., in LV circuit 404). In some embodiments, since the voltage applied to transistor 1608 is higher than the voltage applied to transistor 1620, the thickness of semiconductor layer 1002 in which transistor 1608 is formed (e.g., in HV circuit 406) is greater than the thickness of semiconductor layer 1004 in which transistor 1620 is formed (e.g., in LLV circuit 402).

[0174] like Figure 16A As shown, the second semiconductor structure 104 may further include an interconnect layer 1626 that is above and in contact with device layer 1614, transmitting electrical signals from transistors 1620 and 1622 in peripheral circuits 1616 and 1618. Interconnect layer 1626 may include multiple interconnects, such as MEOL interconnects and BEOL interconnects. Interconnect layer 1626 may also include one or more ILD layers, in which lateral lines and vias may be formed. Interconnects in interconnect layer 1626 may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. ILD layers in interconnect layer 1626 may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. In some embodiments, interconnects in interconnect layer 1626 include Cu, which has a relatively low resistivity (better electrical performance) among conductive metal materials. As described below regarding the manufacturing process, although Cu has a relatively low thermal budget (incompatible with high-temperature processes), interconnects with Cu interconnect layers 1626 can become feasible because the fabrication of interconnect layer 1626 can be performed after the high-temperature process of forming device layer 1614 in second semiconductor structure 104, and separately from the high-temperature process of forming first semiconductor structure 102.

[0175] like Figure 16AAs shown, the second semiconductor structure 104 may further include one or more contacts 1630 extending vertically through the semiconductor layer 1004. In some embodiments, contacts 1630, in conjunction with bonding contacts spanning the bonding interface 103, couple interconnects in interconnect layer 1626 to interconnects in interconnect layer 1628 to provide electrical connections between NAND memory string 208 and transistors 1620 and 1622 through the semiconductor layer 1004. Contacts 1630 may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. In some embodiments, contacts 1630 include Cu. In some embodiments, contacts 1630 include vias surrounded by dielectric spacers (e.g., having silicon oxide) to electrically isolate the vias from the semiconductor layer 1004. Depending on the thickness of the semiconductor layer 1004, the contact 1630 can be an ILV with a depth in the submicron range (e.g., between 10 nm and 1 μm), or a TSV with a depth in the micron range or tens of micron range (e.g., between 1 μm and 100 μm).

[0176] like Figure 16A As shown, the second semiconductor structure 104 may further include an interconnect layer 1626 and a pad-out interconnect layer 902 above transistors 1620 and 1622. In some embodiments, transistors 1620 and 1622 are vertically disposed between the pad-out interconnect layer 902 and the semiconductor layer 1004. The pad-out interconnect layer 902 may include interconnects in one or more ILD layers, such as contact pads 1632. The pad-out interconnect layer 902 and the interconnect layer 1626 may be formed on the same side of the semiconductor layer 1004. In some embodiments, for example, for pad-out purposes, the interconnects in the pad-out interconnect layer 902 may transmit electrical signals between the 3D memory device 1600 and external devices.

[0177] As a result, the peripheral circuits 1604, 1606, 1616, and 1618 in the first semiconductor structure 102 and the second semiconductor structure 104 can be coupled to the NAND memory string 208 in the first semiconductor structure 102 through various interconnect structures, including interconnect layers 1612, 1626, and 1628, bonding layers 1008 and 1010, and contacts 1624 and 1630. Furthermore, the peripheral circuits 1604, 1606, 1616, and 1618 and the NAND memory string 208 in the 3D memory device 1600 can be further coupled to external devices through the contact 1630 and pads leading out from the interconnect layer 902.

[0178] It should be understood that the pad leads of 3D memory devices are not limited to those from sources with, for example, Figure 16A The second semiconductor structure 104 of the peripheral circuit 1616 shown (corresponding to) Figure 9A), and can be from the first semiconductor structure 102 (corresponding to Figure 9B ) with the peripheral circuit 1604. For example, as shown in Figure 16B , the 3D memory device 1601 can include a pad-out interconnect layer 902 in the first semiconductor structure 102. The pad-out interconnect layer 902 can be in contact with the semiconductor layer 1002 of the first semiconductor structure 102 on which transistors 1608 of the peripheral circuit 1604 are formed. In some embodiments, the first semiconductor structure 102 further includes one or more contacts 1634 extending vertically through the semiconductor layer 1002. In some embodiments, the contacts 1634 couple interconnects in the interconnect layer 1612 in the first semiconductor structure 102 to contact pads 1632 in the pad-out interconnect layer 902 for electrical connection through the semiconductor layer 1002. The contacts 1634 can include a conductive material including, but not limited to, W, Co, Cu, Al, silicide, or any combination thereof. In some embodiments, the contacts 1634 include W. In some embodiments, the contacts 1634 include vias surrounded by a dielectric spacer (e.g., with silicon oxide) to electrically isolate the vias from the semiconductor layer 1002. Depending on the thickness of the semiconductor layer 1002, the contacts 1634 can be ILVs with a thickness in the sub-micron scale (e.g., between 10 nm and 1 pm), or TSVs with a depth in the micron scale or tens of micron scale (e.g., between 1 pm and 100 pm).

[0179] As shown in Figure 16B , the second semiconductor structure 104 can also include a passivation layer 1650 in place of the pad-out interconnect layer 902 in Figure 16A to protect and package the 3D memory device 1601 from the side of the second semiconductor structure 104 that does not have the pad-out interconnect layer 902. The passivation layer 1650 can include a dielectric material such as silicon nitride and / or silicon oxide. In some embodiments, the second semiconductor structure 104 in the 3D memory device 1601 further includes an operational / carrier substrate 1651 in contact with the passivation layer 1650 as a base substrate for the 3D memory device 1601 to provide support. It should be appreciated that in some examples, the passivation layer 1650 can be omitted or combined with the operational substrate 1651 as a single layer for support and protection.

[0180] It should also be appreciated that in some examples, the first semiconductor structure 102 and the second semiconductor structure 104 of the 3D memory device 1601 can not include the bonding layers 1008 and 1010, respectively, as shown in Figure 16BThe bonding interface 103 can be produced by a transfer bonding process, and the semiconductor layer 1004 can be a monocrystalline silicon layer transferred and attached to a top surface of the first semiconductor structure 102 by transfer bonding from a silicon substrate or an SOI substrate, as described in detail below with respect to the fabrication process. In some embodiments, a dielectric layer (e.g., a silicon oxide layer) is formed vertically between the bonding interface 103 and the semiconductor layer 1004 and / or between the bonding interface 105 and the interconnect layer 1628 to facilitate transfer bonding of the semiconductor layer 1004 onto the interconnect layer 1628. Thus, it should be understood that in some examples, the bonding interface 103 can include a surface of the dielectric layer(s). It should also be understood that details of the same components (e.g., materials, fabrication processes, functions, and so on) in both 3D memory devices 1600 and 1601 are not repeated for ease of description.

[0181] Figures 17A-17H A flow diagram illustrating a method 1900 for forming a 3D memory device in Figure 15A and 15B is shown. Figure 19 A flow diagram illustrating a method 1900 for forming a 3D memory device in Figure 15A and 15B is shown. Figures 17A-17H Examples of the 3D memory devices shown in Figure 16A The 3D memory device 1600 shown in Figures 17A-17H and 19 will be described together. It should be understood that the operations shown in the method 1900 are not exhaustive and that other operations can also be performed before, after, or between any of the shown operations. Furthermore, some operations can be performed concurrently, or in a different order than shown in Figure 19 .

[0182] Referring to Figure 19 , the method 1900 begins at operation 1902, where a first transistor is formed on a first substrate. The first substrate can be a silicon substrate having monocrystalline silicon. As Figure 17AAs shown, a plurality of transistors 1704 and 1706 are formed on a silicon substrate 1702. Transistors 1704 and 1706 can be formed by a variety of processes, including but not limited to photolithography, dry / wet etching, thin film deposition, thermal growth, implantation, CMP, and any other suitable process. In some embodiments, doped regions are formed in the silicon substrate 1702 by ion implantation and / or thermal diffusion, which serve, for example, as the well and source / drain regions of transistors 1704 and 1706. In some embodiments, isolation regions (e.g., STI) are also formed in the silicon substrate 1702 by wet / dry etching and thin film deposition. In some embodiments, the thickness of the gate dielectric of transistor 1704 differs from the thickness of the gate dielectric of transistor 1706, for example, by depositing a thicker silicon oxide film in the region of transistor 1704 than in the region of transistor 1706, or by etching back a portion of the silicon oxide film deposited in the region of transistor 1706. It should be understood that the details of fabricating transistors 1704 and 1706 may depend on the type of transistor (e.g., Figure 5A , 5B The variations are due to the planar transistor 500 or 3D transistor 600 in 6A and 6B, and therefore will not be elaborated further for the sake of description.

[0183] In some embodiments, an interconnect layer 1708 is formed over the transistors on the first substrate. The interconnect layer may include multiple interconnects within one or more ILD layers. For example... Figure 17A As shown, an interconnect layer 1708 can be formed over transistors 1704 and 1706. Interconnect layer 1708 may include MEOL and / or BEOL interconnects in a plurality of ILD layers for electrical connection to transistors 1704 and 1706. In some embodiments, interconnect layer 1708 includes a plurality of ILD layers and interconnects formed therein using a plurality of processes. For example, interconnects in interconnect layer 1708 may include conductive materials deposited by one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof). The fabrication process forming the interconnects may also include photolithography, CMP, wet / dry etching, or any other suitable process. The ILD layers may include dielectric materials deposited by one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, or any combination thereof). Figure 17A The ILD layer and interconnects shown can be collectively referred to as interconnect layer 1708. In some embodiments, the interconnects in interconnect layer 1708 include W, which has a relatively high thermal budget in a conductive metallic material to withstand subsequent high-temperature processes.

[0184] Method 1900 proceeds to operation 1904, such as... Figure 19 As shown, a polysilicon layer is formed above the first transistor. Figure 17BAs shown, a polysilicon layer 1711 is formed over the interconnect layer 1708 and transistors 1704 and 1706 on the first silicon substrate 1702. The polysilicon layer 1711 can be formed by depositing polysilicon on the interconnect layer 1708 using one or more thin-film deposition processes (including but not limited to CVD, PVD, ALD, or any combination thereof). In some embodiments, the polysilicon layer 1711 is doped with P-type or N-type dopants using an in-situ doping process during the deposition process or an ion implantation / diffusion process after the deposition process.

[0185] Method 1900 proceeds to operation 1906, such as... Figure 19 As shown, an array of NAND memory strings is formed on a polysilicon layer. In some embodiments, a memory stack layer is formed on the polysilicon layer to form the array of NAND memory strings. Figure 17C As shown, a stacked layer structure, such as a memory stacked layer 1726 comprising staggered conductive and dielectric layers, is formed on a polysilicon layer 1716. To form the memory stacked layer 1726, in some embodiments, a dielectric stacked layer (not shown) comprising staggered sacrificial layers (not shown) and dielectric layers is formed on the polysilicon layer 1716. In some embodiments, each sacrificial layer comprises a silicon nitride layer, and each dielectric layer comprises a silicon oxide layer. The staggered sacrificial and dielectric layers can be formed by one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, or any combination thereof). The memory stacked layer 1726 can then be formed by a gate replacement process, for example, by replacing the sacrificial layers with conductive layers using a wet / dry etching process that selectively etches the dielectric layers, and filling the resulting trenches with conductive layers. In some embodiments, each conductive layer comprises a metal layer, such as a W layer. It should be understood that, in some examples, the memory stack 1726 can be formed by alternately depositing conductive layers (e.g., doped polysilicon layers) and dielectric layers (e.g., silicon oxide layers) without a gate replacement process. In some embodiments, a pad oxide layer comprising silicon oxide is formed between the memory stack 1726 and the polysilicon layer 1716.

[0186] like Figure 17CAs shown, NAND memory strings 1728 are formed over polysilicon layer 1716, with each extending vertically through memory stack layers 1726 to contact polysilicon layer 1711. In some embodiments, the fabrication process to form NAND memory strings 1728 includes forming channel holes through memory stack layers 1726 (or dielectric stack layers) and into polysilicon layer 1716 using dry etching and / or wet etching (e.g., DRIE), followed by filling the channel holes with a plurality of layers (e.g., memory films (e.g., tunneling, storage, and blocking layers) and semiconductor layers) using thin film deposition processes (e.g., ALD, CVD, PVD, or any combination thereof). It should be appreciated that the details of fabricating NAND memory strings 1728 can vary depending on the type of channel structure of NAND memory strings 1728 (e.g., channel structure 812 in FIG. 8), and thus, for ease of description, the details are not elaborated on again. Figure 8

[0187] In some embodiments, an interconnect layer is formed over the array of NAND memory strings. The interconnect layer can include a first plurality of interconnects in one or more ILD layers. As shown in Figure 17C As shown in FIG. 17, an interconnect layer 1730 is formed over memory stack layers 1726 and NAND memory strings 1728. Interconnect layer 1730 can include interconnects of MEOL and / or BEOL in a plurality of ILD layers to electrically connect with NAND memory strings 1728. In some embodiments, interconnect layer 1730 includes a plurality of ILD layers and interconnects formed therein with a plurality of processes. For example, the interconnects in interconnect layer 1730 can include conductive materials deposited by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. The fabrication processes to form the interconnects can also include photolithography, CMP, wet / dry etching, or any other suitable processes. The ILD layers can include dielectric materials deposited by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. Figure 17D The ILD layers and interconnects shown in FIG. 17 can be collectively referred to as interconnect layer 1730.

[0188] In some embodiments, contacts are formed through the polysilicon layer. As shown in Figure 17C ​As shown, one or more contacts 1724 are formed that each extend vertically through the polysilicon layer 1711. The contacts 1724 can couple interconnects in the interconnect layers 1730 and 1708. The contacts 1724 can be formed by first patterning contact holes through the polysilicon layer 1711 using a patterning process (e.g., photolithography and dry / wet etching of dielectric material in the dielectric layer). The contact holes can be filled with a conductor (e.g., W or Cu). In some embodiments, filling the contact holes includes depositing a spacer (e.g., a silicon oxide layer) before depositing the conductor.

[0189] In some embodiments, a first bonding layer is formed over the interconnect layer. The first bonding layer can include a plurality of first bonding contacts. As Figure 17C As shown, a bonding layer 1732 is formed over the interconnect layer 1730. The bonding layer 1732 can include a plurality of bonding contacts surrounded by a dielectric. In some embodiments, a dielectric layer is deposited on the top surface of the interconnect layer 1730 by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. Bonding contacts through the dielectric layer and to interconnects in the interconnect layer 1730 can then be formed by first patterning contact holes through the dielectric layer using a patterning process (e.g., photolithography and dry / wet etching of dielectric material in the dielectric layer). The contact holes can be filled with a conductor (e.g., Cu). In some embodiments, filling the contact holes includes depositing an adhesion (glue) layer, a barrier layer, and / or a seed layer before depositing the conductor.

[0190] The method 1900 proceeds to operation 1908, as Figure 19 As shown, a second transistor is formed on the front side of the second substrate. The second substrate can be a silicon substrate with single-crystal silicon. As Figure 17DAs shown, a plurality of transistors 1714 and 1716 are formed on the front side of a silicon substrate 1710 with single crystalline silicon. The transistors 1714 and 1716 can be formed by a variety of processes, including but not limited to photolithography, dry / wet etching, thin film deposition, thermal growth, implantation, CMP, and any other suitable processes. In some embodiments, doped regions are formed in the silicon substrate 1710 by ion implantation and / or thermal diffusion, which serve as, for example, well and source / drain regions for the transistors 1719 and 1716. In some embodiments, isolation regions (e.g., STI) are also formed in the silicon substrate 1710 by wet / dry etching and thin film deposition. In some embodiments, the thickness of the gate dielectric of the transistors 1714 is different from the thickness of the gate dielectric of the transistors 1716, for example, by depositing a thicker silicon oxide film in the region of the transistors 1714 than in the region of the transistors 1716, or by etching back a portion of the silicon oxide film deposited in the region of the transistors 1716. It should be appreciated that the details of fabricating the transistors 1714 and 1716 can vary depending on the type of transistors (e.g., planar transistors 500 or 3D transistors 600 in FIGS. 6A and 6B), and thus are not elaborated on for ease of description. Figure 5A , 5B , 6A and 6B) are not elaborated on for ease of description.

[0191] In some embodiments, an interconnect layer 1720 is formed over the transistors on the second substrate. The interconnect layer can include a plurality of interconnects in one or more ILD layers. As Figure 17D shown, an interconnect layer 1720 can be formed over the transistors 1719 and 1716. The interconnect layer 1720 can include interconnects of MEOL and / or BEOL in a plurality of ILD layers to electrically connect with the transistors 1714 and 1716. In some embodiments, the interconnect layer 1720 includes a plurality of ILD layers and interconnects formed therein with a plurality of processes. For example, the interconnects in the interconnect layer 1720 can include a conductive material deposited by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. The fabrication processes to form the interconnects can also include photolithography, CMP, wet / dry etching, or any other suitable processes. The ILD layers can include a dielectric material deposited by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. Figure 17D The ILD layers and interconnects shown in FIG. 17B can be collectively referred to as the interconnect layer 1720. Unlike the interconnect layer 1708, in some embodiments, the interconnects in the interconnect layer 1720 include Cu, which has a relatively low resistivity among conductive metallic materials. It should be appreciated that although Cu has a relatively low thermal budget (not compatible with high temperature processes), it becomes feasible to use Cu as the conductive material for the interconnects in the interconnect layer 1720 because there are no more high temperature processes after the fabrication of the interconnect layer 1720.

[0192] In some embodiments, a contact is formed through the thinned second substrate. As shown, Figure 17D a contact 1718 is formed extending vertically from a front side of the silicon substrate 1710 into the silicon substrate 1710. The contact 1718 can be coupled to an interconnect in the interconnect layer 1720. The contact 1718 can be formed by first patterning a contact hole in the silicon substrate 1710 using a patterning process (e.g., photolithography and dry / wet etching of a dielectric material in a dielectric layer). The contact hole can be filled with a conductor (e.g., Cu). In some embodiments, filling the contact hole includes depositing a spacer (e.g., a silicon oxide layer) prior to depositing the conductor.

[0193] In some embodiments, the second substrate is thinned. As shown, Figure 17E the silicon substrate 1710 (as shown in Figure 17D is thinned to be a semiconductor layer 1709 having single crystalline silicon. The silicon substrate 1710 can be thinned by processes including, but not limited to, wafer grinding, dry etching, wet etching, CMP, any other suitable process, or any combination thereof. For example, by controlling the duration of the CMP process, the thickness of the semiconductor layer 1709 can be controlled to expose the contact 1718 from a back side of the thinned silicon substrate 1710. It should be appreciated that in some examples, in contrast to being in the silicon substrate 1710 prior to thinning, after thinning, the contact 1718 can be formed through the semiconductor layer 1709 from a back side thereof. In some embodiments, prior to thinning, a passivation layer 1721 is formed on the interconnect layer 1720 by depositing a dielectric material such as silicon nitride on the interconnect layer 1720 using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. Then, prior to thinning, the handle substrate 1701 can be attached to the passivation layer 1721, for example, using adhesive bonding, to allow for subsequent back side processing of the silicon substrate 1710 such as thinning, contact formation, and bonding.

[0194] In some embodiments, a second bonding layer is formed on a back side of the thinned second substrate. The second bonding layer can include a plurality of second bonding contacts. As shown, FIG. 17FAs shown, a bonding layer 1722 is formed on the back side of semiconductor layer 1709 (i.e., thinned silicon substrate 1710). Bonding layer 1722 may include a plurality of bonding contacts surrounded by a dielectric. In some embodiments, a dielectric layer is deposited on the back side of semiconductor layer 1709 (opposite to the front side where transistors 1714 and 1716 are formed) by one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, or any combination thereof). Then, by patterning contact holes through the dielectric layer first using a patterning process (e.g., photolithography and dry / wet etching of the dielectric material in the dielectric layer), bonding contacts that penetrate the dielectric layer and contact contacts 1718 on the back side of the thinned silicon substrate 1710 can be formed. The contact holes may be filled with a conductor (e.g., Cu). In some embodiments, filling the contact holes includes depositing an adhesive layer, a barrier layer, and / or a seed layer prior to depositing the conductor.

[0195] Method 1900 proceeds to operation 1910, such as... FIG. 19 As shown, a first substrate and a second substrate are bonded together in a face-to-back manner. After bonding the first and second substrates, a first bonding contact in the first bonding layer can contact a second bonding contact in the second bonding layer at the bonding interface. Bonding may include hybrid bonding.

[0196] like FIG. 17G As shown, the silicon substrate 1702 and components formed thereon (e.g., transistors 1704 and 1706 and NAND memory string 1728), and the thinned silicon substrate 1710 (i.e., semiconductor layer 1709) and components formed thereon (e.g., transistors 1714 and 1716) are bonded in a face-to-face manner with the bonding layer 1732 facing upward on the front side of the silicon substrate 1702 and the bonding layer 1722 facing downward on the back side of the thinned silicon substrate 1710, thereby forming a bonding interface 1712. That is, the silicon substrate 1702 and the components formed thereon can be bonded to the thinned silicon substrate 1710 and the components formed thereon in a face-to-back manner, such that the bonding contacts in the bonding layer 1732 and the bonding contacts in the bonding layer 1722 contact at the bonding interface 1712. In some embodiments, a processing technique, such as plasma treatment, wet treatment, and / or heat treatment, is applied to the bonding surfaces prior to bonding. As a result of bonding (e.g., hybrid bonding), the bonding contacts on opposite sides of the bonding interface 1712 can be mixed with each other. After bonding, according to some embodiments, the bonding contacts in the bonding layer 1732 and the bonding contacts in the bonding layer 1722 are aligned and contacted with each other, such that the memory stack layer 1726 and the NAND memory string 1728 formed therethrough, as well as transistors 1704 and 1706, can be coupled to transistors 1714 and 1716 across the bonding interface 1712 via the bonded bonding contacts.

[0197] Method 1900 proceeds to optional operation 1912, such as... FIG. 19 As shown, the first substrate is thinned. FIG. 17H As shown, silicon substrate 1702 (as shown) FIG. 17G The silicon substrate 1702 (as shown) is thinned to become a semiconductor layer 1703 having monocrystalline silicon. The silicon substrate 1702 can be thinned by processes including but not limited to wafer grinding, dry etching, wet etching, CMP, any other suitable process or any combination thereof.

[0198] Method 1900 proceeds to operation 1914, such as... FIG. 19 As shown, an interconnect layer with pads is formed. The interconnect layer with pads is formed on a thinned first substrate. FIG. 17H As shown, a pad-out interconnect layer 1736 is formed on a semiconductor layer 1703 (a thinned silicon substrate 1702). The pad-out interconnect layer 1736 may include interconnects formed in one or more ILD layers, such as contact pads 1938. Contact pads 1738 may include conductive materials, including but not limited to W, Co, Cu, Al, doped silicon, silicides, or any combination thereof. The ILD layers may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. In some embodiments, after bonding and thinning, contacts 1734 extending vertically through the semiconductor layer 1703 are formed, for example by wet / dry etching, followed by deposition of a dielectric material as a spacer and a conductive material as a conductor. Contacts 1734 may couple the contact pads 1738 in the pad-out interconnect layer 1736 to the interconnects in the interconnect layer 1708. It should be understood that in some examples, contacts 1734 may be thinned (e.g., FIG. 17G As shown, the semiconductor layer 1703 was formed in the silicon substrate 1702 before thinning and is exposed from the back side of the silicon substrate 1702 (at the location where thinning occurs) after thinning.

[0199] In some implementations, after operation 1910, optional operation 1912 is skipped, and method 1900 proceeds to operation 1914, such as... FIG. 19 As shown, an interconnect layer with pads is formed. An interconnect layer with pads can be formed above the second transistor. Although FIG. 17G Although not shown, it should be understood that in some examples, after removing the operating substrate 1701 and the passivation layer 1721, a pad-out interconnect layer with contact pads may be formed over the interconnect layer 1720 and transistors 1716 and 1714.

[0200] FIG. 18A-18F This disclosure illustrates some aspects of the formation of FIG. 15A and15B Another manufacturing process for 3D memory devices. FIG. 20 This disclosure illustrates some aspects of the formation of FIG. 15A and 15B A flowchart of another method for 3D memory devices in 2000. FIG. 18A-18F Examples of 3D memory devices shown in Figure 20 include FIG. 16B The 3D memory device 1601 shown is described together. FIG. 18A-18F And 20. It should be understood that the operations shown in method 2000 are not exhaustive, and other operations may be performed before, after, or between any of the operations shown. Furthermore, some operations may be performed simultaneously, or in conjunction with... FIG. 20 The different execution orders shown.

[0201] refer to FIG. 20 Method 2000 begins with operation 2002, in which a first transistor is formed on a first substrate. The first substrate may be a silicon substrate having monocrystalline silicon. FIG. 18A As shown, a plurality of transistors 1804 and 1806 are formed on a silicon substrate 1802. Transistors 1804 and 1806 can be formed by a variety of processes, including but not limited to photolithography, dry / wet etching, thin film deposition, thermal growth, implantation, CMP, and any other suitable process. In some embodiments, doped regions are formed in the silicon substrate 1802 by ion implantation and / or thermal diffusion, which serve, for example, as the well and source / drain regions of transistors 1804 and 1806. In some embodiments, isolation regions (e.g., STI) are also formed in the silicon substrate 1802 by wet / dry etching and thin film deposition. In some embodiments, the thickness of the gate dielectric of transistor 1804 differs from the thickness of the gate dielectric of transistor 1806, for example, by depositing a thicker silicon oxide film in the region of transistor 1804 than in the region of transistor 1806, or by etching back a portion of the silicon oxide film deposited in the region of transistor 1806. It should be understood that the details of fabricating transistors 1804 and 1806 may depend on the type of transistor (e.g., FIG. 5A , 5B The variations are due to the planar transistor 500 or 3D transistor 600 in 6A and 6B, and therefore will not be elaborated further for the sake of description.

[0202] In some embodiments, an interconnect layer 1808 is formed over the transistors on the first substrate. The interconnect layer may include multiple interconnects within one or more ILD layers. FIG. 18AAs shown, an interconnect layer 1808 can be formed over transistors 1804 and 1806. Interconnect layer 1808 may include MEOL and / or BEOL interconnects in a plurality of ILD layers for electrical connection to transistors 1804 and 1806. In some embodiments, interconnect layer 1808 includes a plurality of ILD layers and interconnects formed therein using a plurality of processes. For example, interconnects in interconnect layer 1808 may include conductive materials deposited by one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof). The fabrication process forming the interconnects may also include photolithography, CMP, wet / dry etching, or any other suitable process. The ILD layers may include dielectric materials deposited by one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, or any combination thereof). FIG. 18A The ILD layer and interconnects shown can be collectively referred to as interconnect layer 1808. In some embodiments, the interconnects in interconnect layer 1808 include W, which has a relatively high thermal budget in a conductive metallic material to withstand subsequent high-temperature processes.

[0203] Method 2000 proceeds to operation 2004, such as... FIG. 20 As shown, a polysilicon layer is formed above the first transistor. FIG. 18B As shown, a polysilicon layer 1811 is formed over the interconnect layer 1808 and transistors 1804 and 1806 on the first silicon substrate 1802. The polysilicon layer 1811 can be formed by depositing polysilicon on the interconnect layer 1808 using one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, or any combination thereof). In some embodiments, the polysilicon layer 1811 is doped with P-type or N-type dopants using an in-situ doping process during the deposition process or an ion implantation / diffusion process after the deposition process.

[0204] Method 2000 proceeds to operation 2006, such as... FIG. 20 As shown, an array of NAND memory strings is formed on a polysilicon layer. In some embodiments, a memory stack layer is formed on the polysilicon layer to form the array of NAND memory strings. FIG. 18CAs shown, a stacked layer structure, such as a memory stacked layer 1826 comprising staggered conductive and dielectric layers, is formed on a polysilicon layer 1816. To form the memory stacked layer 1826, in some embodiments, a dielectric stacked layer (not shown) comprising staggered sacrificial layers (not shown) and dielectric layers is formed on the polysilicon layer 1816. In some embodiments, each sacrificial layer comprises a silicon nitride layer, and each dielectric layer comprises a silicon oxide layer. The staggered sacrificial and dielectric layers can be formed by one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, or any combination thereof). The memory stacked layer 1826 can then be formed by a gate replacement process, for example, by replacing the sacrificial layers with conductive layers using a wet / dry etching process that selectively etches the dielectric layers, and filling the resulting trenches with conductive layers. In some embodiments, each conductive layer comprises a metal layer, such as a W layer. It should be understood that, in some examples, the memory stack 1826 can be formed by alternately depositing conductive layers (e.g., doped polysilicon layers) and dielectric layers (e.g., silicon oxide layers) without a gate replacement process. In some embodiments, a pad oxide layer comprising silicon oxide is formed between the memory stack 1826 and the polysilicon layer 1816.

[0205] like FIG. 18C As shown, a NAND memory string 1828 is formed above a polysilicon layer 1816, with each string extending vertically through the memory stack layer 1826 to contact the polysilicon layer 1811. In some embodiments, the fabrication process for forming the NAND memory string 1828 includes forming channel vias through the memory stack layer 1826 (or dielectric stack layer) and into the polysilicon layer 1816 using dry etching and / or wet etching (e.g., DRIE), followed by filling the channel vias with multiple layers (e.g., memory films (e.g., tunneling layers, storage layers, and barrier layers) and semiconductor layers) using thin-film deposition processes (e.g., ALD, CVD, PVD, or any combination thereof). It should be understood that the details of fabricating the NAND memory string 1828 can depend on the type of channel structure of the NAND memory string 1828 (e.g., FIG. 8 The channel structure (812) varies, and therefore will not be elaborated further for ease of description.

[0206] In some implementations, an interconnect layer is formed above an array of NAND memory strings. The interconnect layer may include a plurality of interconnects within one or more ILD layers. FIG. 18CAs shown, an interconnect layer 1830 is formed over the memory stack layer 1826 and the NAND memory string 1828. The interconnect layer 1830 may include interconnects of MEOL and / or BEOL in a plurality of ILD layers for electrical connection to the NAND memory string 1828. In some embodiments, the interconnect layer 1830 includes a plurality of ILD layers and interconnects formed therein using a plurality of processes. For example, the interconnects in the interconnect layer 1830 may include conductive materials deposited by one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof). The fabrication processes forming the interconnects may also include photolithography, CMP, wet / dry etching, or any other suitable process. The ILD layers may include dielectric materials deposited by one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, or any combination thereof). FIG. 18C The ILD layer and interconnect shown can be collectively referred to as interconnect layer 1830.

[0207] In some implementations, contacts are formed through the polysilicon layer. For example... FIG. 18C As shown, one or more contacts 1817 are formed, each extending vertically through the polysilicon layer 1811. The contacts 1817 can couple interconnects in interconnect layers 1830 and 1808. The contacts 1817 can be formed by first patterning contact holes through the polysilicon layer 1811 using a patterning process (e.g., photolithography and dry / wet etching of the dielectric material in the dielectric layer). The contact holes can be filled with a conductor (e.g., W or Cu). In some embodiments, filling the contact holes includes depositing a spacer (e.g., a silicon oxide layer) before depositing the conductor.

[0208] Method 2000 proceeds to Operation 2008, such as... FIG. 20 As shown, a semiconductor layer is formed over a NAND memory string array. The semiconductor layer may include monocrystalline silicon. In some embodiments, to form the semiconductor layer, another substrate is bonded to the first substrate face-to-face, and the other substrate is thinned to leave the semiconductor layer. Bonding may include transfer bonding. The other substrate may be a silicon substrate having monocrystalline silicon.

[0209] like FIG. 18D As shown, a semiconductor layer 1810, such as a single-crystal silicon layer, is formed over the interconnect layer 1830 and the NAND memory string 1828. The semiconductor layer 1810 may be attached over the interconnect layer 1830 to form a bonding interface 1812 perpendicularly between the semiconductor layer 1810 and the interconnect layer 1830. In some embodiments, to form the semiconductor layer 1810, transfer bonding is used to bond another silicon substrate face-to-face. FIG. 18D(Not shown in the diagram) and a silicon substrate 1802 (with components formed on the silicon substrate 1802, such as NAND memory strings 1828 and transistors 1804 and 1806, facing the other silicon substrate), thereby forming a bonding interface 1812. The other silicon substrate can then be thinned using any suitable process to leave a semiconductor layer 1810 attached above the interconnect layer 1830.

[0210] FIG. 34A-34D A manufacturing process for transfer bonding according to some aspects of this disclosure is illustrated. For example... FIG. 34A As shown, a functional layer 3404 can be formed on a base substrate 3402. The functional layer 3404 may include a device layer, an interconnect layer, and / or any suitable layer disclosed herein, such as… FIG. 18C The transistors 1804 and 1806, polysilicon layer 106, memory stack layer 1826, NAND memory string 1828, and interconnect layers 1808 and 1830 are included. A transfer substrate 3406 is provided, such as a silicon substrate having monocrystalline silicon. In some embodiments, the transfer substrate 3406 is a monocrystalline silicon substrate. FIG. 34B As shown, the transfer substrate 3406 and the base substrate 3402 (and the functional layer 3404 formed thereon) can be bonded face-to-face using any suitable substrate / wafer bonding process, including, for example, anodic bonding and fusion (direct) bonding, thereby forming a bonding interface 3410 between the transfer substrate 3406 and the base substrate 3402. In one example, fusion bonding can be performed between silicon and silicon, silicon and silicon oxide, or silicon oxide and silicon oxide layers using pressure and heat. In another example, anodic bonding can be performed between a silicon oxide layer (in an ionomer glass) and a silicon layer using voltage, pressure, and heat. It should be understood that, depending on the bonding process, a dielectric layer (e.g., a silicon oxide layer) can be formed on one or both sides of the bonding interface 3410. For example, silicon oxide layers can be formed on both the top surfaces of the transfer substrate 3406 and the functional layer 3404 to allow for fusion-bonded SiO2-SiO2 bonding; or, a silicon oxide layer can be formed only on the functional layer 3404 to allow for anodic bonding or fusion-bonded SiO2-Si bonding. In some embodiments where the silicon oxide layer is formed on the transfer substrate 3406 (e.g., FIG. 34B As shown, the transfer substrate 3406 can be flipped upside down so that the silicon oxide layer on the transfer substrate 3406 faces downward toward the base substrate 3402 before bonding.

[0211] like FIG. 34C As shown, for example, ion implantation can be used to form a cleavage layer 3412 in the transfer substrate 3406. In some embodiments, for example, by controlling the energy of the ion implantation process, a light element such as hydrogen ions is implanted into the transfer substrate 3406 to a desired depth to form the cleavage layer 3412.FIG. 34D As shown, the transfer substrate 3406 can be thinned to leave only the semiconductor layer 3414 perpendicularly between the dicing layer 3412 and the bonding interface 3410. In some embodiments, the transfer substrate 3406 is separated at the dicing layer 3412 by applying mechanical force to the transfer substrate 3406, i.e., peeling the remaining portion of the transfer substrate 3406 from the semiconductor layer 3414. It should be understood that the transfer substrate 3406 can be separated at the dicing layer 3412 by any suitable means, not limited to mechanical force alone, such as thermal, acoustic, etc., or any combination thereof. As a result, the semiconductor layer 3414 can be transferred from the transfer substrate 3406 and bonded to the base substrate 3402 (and the functional layer 3404) using a transfer bonding process. In some embodiments, a planarization process, such as chemical mechanical polishing (CMP), is performed on the semiconductor layer 3412 to polish and smooth the top surface of the semiconductor layer 3412 and adjust the thickness of the semiconductor layer 3412. Therefore, the semiconductor layer 3414 can have the same material as the transfer substrate 3406, such as single-crystal silicon. The thickness of the semiconductor layer 3414 can be determined by the depth of the dicing layer 3412, for example, by adjusting the implantation energy, and / or by a planarization process. Furthermore, the remaining portion of the transfer substrate 3406 can be reused in the same manner to form semiconductor layers bonded to other base substrates, thereby reducing the material cost of the transfer bonding process.

[0212] FIG. 35A-35D Another manufacturing process for transfer bonding based on some aspects of this disclosure is illustrated. For example... FIG. 35A As shown, a functional layer 3404 can be formed on a base substrate 3402. The functional layer 3404 may include a device layer, an interconnect layer, and / or any suitable layer disclosed herein, such as… FIG. 18C The transistors 1804 and 1806, polysilicon layer 106, memory stack layer 1826, NAND memory string 1828, and interconnect layers 1808 and 1830 are included. The SOI substrate 3502, including the base / operation layer 3504, buried oxide layer (BOx) 3506, and device layer 3508, can be flipped to face the base substrate 3402. (As shown...) FIG. 35BAs shown, the SOI substrate 3502 and the base substrate 3402 (and functional layer 3404 formed thereon) can be bonded in a face-to-face manner using any suitable substrate / wafer bonding process, including, for example, anodic bonding and fusion (direct) bonding, thereby forming a bonding interface 3512 between the SOI substrate 3502 and the base substrate 3402. In one example, fusion bonding can be performed between layers of silicon and silicon, silicon and silicon oxide, or silicon oxide and silicon oxide with pressure and heat. In another example, anodic bonding can be performed between a silicon oxide layer (in ion glass) and a silicon layer with voltage, pressure, and heat. It should be appreciated that a dielectric layer (e.g., a silicon oxide layer) can be formed on one or both sides of the bonding interface 3512 depending on the bonding process. For example, a silicon oxide layer can be formed on both the SOI substrate 3502 and the top surface of the functional layer 3404 to allow SiO2-SiO2 bonding using fusion bonding. Alternatively, a silicon oxide layer can be formed only on the functional layer 3404 to allow SiO2-Si bonding using anodic bonding or fusion bonding.

[0213] As shown in FIG. 35C and 35D the SOI substrate 3502 can be thinned by sequentially removing the base / operational layer 3504 and the buried oxide layer 3506, for example, using wet / dry etching and / or CMP processes (as shown in FIG. 35B ), leaving only the device layer 3508 (as a semiconductor layer) at the bonding interface 3512. As a result, the device layer 3508 can be transferred from the SOI substrate 3502 and bonded onto the base substrate 3402 (and functional layer 3404) as a semiconductor layer using another transfer bonding process. Thus, the transferred semiconductor layer can have the same material as the device layer 3508, e.g., single-crystal silicon. The thickness of the semiconductor layer can be the same as the thickness of the device layer 3508. It should be appreciated that in some examples, the device layer 3508 can be further thinned using wet / dry etching and / or CMP processes such that the transferred semiconductor layer can be thinner than the device layer 3508.

[0214] Referring back to FIG. 20 , the method 2000 proceeds to operation 2010, where a second transistor is formed on the semiconductor layer. As shown in FIG. 18EAs shown, a plurality of transistors 1814 and 1816 are formed on the semiconductor layer 1810 with single crystalline silicon. The transistors 1814 and 1816 can be formed by a variety of processes, including but not limited to photolithography, dry / wet etching, thin film deposition, thermal growth, implantation, CMP, and any other suitable processes. In some embodiments, doped regions are formed in the semiconductor layer 1810 by ion implantation and / or thermal diffusion, which are used as, for example, the well and source / drain regions of the transistors 1814 and 1816. In some embodiments, isolation regions (e.g., STI) are also formed in the semiconductor layer 1810 by wet / dry etching and thin film deposition. In some embodiments, the thickness of the gate dielectric of the transistors 1814 is different from the thickness of the gate dielectric of the transistors 1816, for example, by depositing a thicker silicon oxide film in the region of the transistors 1814 than in the region of the transistors 1816, or by etching back a portion of the silicon oxide film deposited in the region of the transistors 1816. It should be appreciated that the details of fabricating the transistors 1814 and 1816 can vary depending on the type of transistors (e.g., planar transistors 500 or 3D transistors 600 in FIGS. 6A and 6B), and thus are not elaborated further for ease of description. FIG. 5A 5B

[0215] In some embodiments, an interconnect layer is formed over the transistors on the second substrate. The interconnect layer can include a plurality of interconnects in one or more ILD layers. As FIG. 18E shown, an interconnect layer 1820 can be formed over the transistors 1820 and 1816. The interconnect layer 1820 can include interconnects of MEOL and / or BEOL in a plurality of ILD layers to electrically connect with the transistors 1814 and 1816. In some embodiments, the interconnect layer 1820 includes a plurality of ILD layers and interconnects formed therein with a plurality of processes. For example, the interconnects in the interconnect layer 1820 can include conductive materials deposited by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. The fabrication processes to form the interconnects can also include photolithography, CMP, wet / dry etching, or any other suitable processes. The ILD layers can include dielectric materials deposited by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. FIG. 17D The ILD layers and interconnects shown in FIG. 18B can be collectively referred to as the interconnect layer 1820. Unlike the interconnect layer 1808, in some embodiments, the interconnects in the interconnect layer 1820 include Cu, which has a relatively low resistivity among conductive metallic materials. It should be appreciated that although Cu has a relatively low thermal budget (not compatible with high temperature processes), it becomes feasible to use Cu as the conductive material for the interconnects in the interconnect layer 1820 because there are no more high temperature processes after the fabrication of the interconnect layer 1820.​​

[0216] In some embodiments, contacts are formed perpendicularly through the semiconductor layer. Contact 1818 may extend perpendicularly through the semiconductor layer 1810 from the front side. Contact 1818 may be coupled to an interconnect in interconnect layer 1820. Contact 1818 may further extend through a dielectric layer (if present) on the back side of semiconductor layer 1810 to align and contact an interconnect in interconnect layer 1830 at bonding interface 1812. Thus, contact 1818 couples the interconnect in interconnect layer 1820 through semiconductor layer 1810 and across bonding interface 1812 to the interconnect in interconnect layer 1830. Contact 1818 may be formed by first patterning contact holes in semiconductor layer 1810 using a patterning process (e.g., photolithography and dry / wet etching of the dielectric material in the dielectric layer). Contact holes may be filled with a conductor (e.g., W or Cu). In some embodiments, filling contact holes includes depositing a spacer (e.g., a silicon oxide layer) before depositing a conductor.

[0217] Method 2000 skips optional operation 2012 and proceeds to operation 2014, as follows. FIG. 20 As shown, an interconnect layer with pads is formed therein. An interconnect layer with pads can also be formed above the second transistor. (As shown...) FIG. 18F As shown, a pad-lead interconnect layer 1836 is formed above the interconnect layer 1820 on the semiconductor layer 1810 and above transistors 1814 and 1816. The pad-lead interconnect layer 1836 may include interconnects formed in one or more ILD layers, such as contact pads 1838. Contact pads 1838 may include conductive materials, including but not limited to W, Co, Cu, Al, doped silicon, silicides, or any combination thereof. The ILD layer may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0218] In some embodiments, in order to form pads to lead out interconnect layers on the first substrate, after operation 2010, method 2000 proceeds to optional operation 2012, such as... FIG. 20 As shown, the first substrate is thinned. It should be understood that, although not shown, in some examples, processes including, but not limited to, wafer grinding, dry etching, wet etching, CMP, any other suitable process, or any combination thereof, can be used to thin the silicon substrate 1802. FIG. 18EThe semiconductor layer with single crystal silicon is formed (as shown in FIG. 1A). After thinning, contacts can be formed extending vertically through the thinned silicon substrate 1802, for example, by wet / dry etching, followed by deposition of a dielectric material as a spacer and a conductive material as a conductor. It should be appreciated that in some examples, the contacts can be formed in the silicon substrate 1802 prior to thinning and exposed from the backside of the silicon substrate 1802 (where thinning occurs) after thinning.

[0219] The method 2000 proceeds to operation 2014, as FIG. 20 shown, where a pad-out interconnect layer is formed. The pad-out interconnect layer can be formed on the thinned first substrate. It should be appreciated that although not shown, in some examples, a pad-out interconnect layer with contact pads can be formed on the thinned silicon substrate 1802.

[0220] FIG. 21A and 21B schematics of cross-sections of 3D memory devices 2100 and 2101 with two stacked semiconductor structures, in accordance with various aspects of the present disclosure. The 3D memory devices 2100 and 2101 can be examples of the 3D memory device 101 in FIG. 1A, where the peripheral circuit of the first semiconductor structure 102 is disposed vertically between the memory cell array of the first semiconductor structure 102 and the peripheral circuit of the second semiconductor structure 104. That is, two separate portions of the peripheral circuit can be disposed adjacently in the vertical direction. As FIG. 1B schematics of cross-sections of 3D memory devices 2100 and 2101 with two stacked semiconductor structures, in accordance with various aspects of the present disclosure. The 3D memory devices 2100 and 2101 can be examples of the 3D memory device 101 in FIG. 1A, where the peripheral circuit of the first semiconductor structure 102 is disposed vertically between the memory cell array of the first semiconductor structure 102 and the peripheral circuit of the second semiconductor structure 104. That is, two separate portions of the peripheral circuit can be disposed adjacently in the vertical direction. As FIG. 21A and 21B shown, according to some implementations, the second semiconductor structure 104 including some of the peripheral circuit is bonded to the first semiconductor structure 102 on a side with the peripheral circuit to form a bonding interface 105 between the peripheral circuit of the second semiconductor structure 104 and the first semiconductor structure 102.

[0221] Further, as FIG. 21A and 21B shown, the 3D memory device 2100 or 2101 can also include a pad-out interconnect layer 902 for pad-out purposes, that is, to interconnect with external devices using contact pads on which bond wires can be soldered. In FIG. 21B one example shown, the second semiconductor structure 104 including some of the peripheral circuit on a side of the 3D memory device 2101 can include the pad-out interconnect layer 902, such that the 3D memory device 2101 can be pad-out from the peripheral circuit side to reduce the interconnect distance between the contact pads and the peripheral circuit, thereby reducing the parasitic capacitance from the interconnect and improving the electrical performance of the 3D memory device 2101. In FIG. 21AIn another example shown in FIG. 2, the first semiconductor structure 102 including a memory cell array and some peripheral circuits on another side of the 3D memory device 2100 can include a pad-out interconnect layer 902 such that the 3D memory device 901 can be pad-out from the memory cell array side.

[0222] FIG. 22A and 22B shows a schematic diagram of a cross-section of a 3D memory device in accordance with common aspects of the present disclosure. FIG. 21A and 21B shows a schematic diagram of a cross-section of a 3D memory device in accordance with common aspects of the present disclosure. FIG. 21A and 21B shows a schematic diagram of a cross-section of a 3D memory device in accordance with common aspects of the present disclosure. FIG. 22A In some embodiments, the first semiconductor structure 102 includes a semiconductor layer 1002, a bonding layer 1014, a memory cell array, some of the peripheral circuits vertically between the semiconductor layer 1002 and the polysilicon layer 106, and the polysilicon layer 106 vertically between the memory cell array and the peripheral circuits.

[0223] The memory cell array can include an array of NAND memory strings (e.g., the NAND memory string 208 disclosed herein), and the sources of the array of NAND memory strings can be in contact with the polysilicon layer 106 (e.g., as shown in FIG. 8B). The polysilicon layer 106 can be a deposited polysilicon layer (e.g., N-type doped, P-type doped, or undoped) suitable for certain designs of channel structures in “floating gate” type NAND memory strings or “charge trapping” type NAND memory strings suitable for GIDL erase operations, for example (e.g., the channel structure 812 in FIG. 8B). FIG. 8 FIG. 8 The through-via contacts (e.g., ILV / TSVs) through the polysilicon layer 106 can make direct, short distance (e.g., sub-micron or micron level) electrical connections between the memory cell array and the peripheral circuits in the first semiconductor structure 102. The bonding layer 1014 can include conductive bonding contacts (not shown) and a dielectric electrically isolating the bonding contacts, which can be used for hybrid bonding as described in detail below, for example.

[0224] ​In some embodiments, the peripheral circuitry in the first semiconductor structure 102 is in contact with the semiconductor layer 1002, but not the polysilicon layer 106. That is, the transistors (e.g., planar transistors 500 and 3D transistors 600) of the peripheral circuitry can be in contact with the semiconductor layer 1002. The semiconductor layer 1002 can include a semiconductor material, such as single crystalline silicon (e.g., a silicon substrate or a thinned silicon substrate). It should be appreciated that, unlike the polysilicon layer 106 in the first semiconductor structure 102, the semiconductor layer 1002 on which the transistors are formed can include single crystalline silicon, rather than polysilicon, due to the superior carrier mobility of single crystalline silicon that is desirable for the performance of the transistors. The peripheral circuitry and the bonding layer 1014 can be formed on opposite sides of the semiconductor layer 1002, such that the semiconductor layer 1002 is disposed vertically between the peripheral circuitry and the bonding layer 1014. In some embodiments, the transistors of the peripheral circuitry are formed on the front side of the semiconductor layer 1002, and the bonding contacts of the bonding layer 1014 are formed on the back side of the semiconductor layer 1002.

[0225] In some embodiments, the second semiconductor structure 104 includes a semiconductor layer 1004, a bonding layer 1012, and some of the peripheral circuitry of the array of memory cells vertically between the semiconductor layer 1004 and the bonding layer 1012. The transistors (e.g., planar transistors 500 and 3D transistors 600) of the peripheral circuitry can be in contact with the semiconductor layer 1004. Similar to the semiconductor layer 1002, the semiconductor layer 1004 can include a semiconductor material, such as single crystalline silicon (e.g., a silicon substrate or a thinned silicon substrate). It should be appreciated that, unlike the polysilicon layer 106 in the first semiconductor structure 102, the semiconductor layer 1004 on which the transistors are formed can include single crystalline silicon, rather than polysilicon, due to the superior carrier mobility of single crystalline silicon that is desirable for the performance of the transistors.

[0226] Similar to the bonding layer 1014 in the first semiconductor structure 102, the bonding layer 1012 can also include electrically conductive bonding contacts (not shown) and a dielectric that electrically isolates the bonding contacts. According to some embodiments, the bonding interface 105 is vertically between and in contact with the bonding layers 1012 and 1014, respectively. That is, the bonding layers 1012 and 1014 can be disposed on opposite sides of the bonding interface 105, and the bonding contacts of the bonding layer 1012 can be in contact with the bonding contacts of the bonding layer 1014 at the bonding interface 105. As a result, a large number (e.g., millions) of bonding contacts across the bonding interface 105, in combination with the through- substrate contacts (e.g., ILVs / TSVs) through the semiconductor layer 1002, can enable direct, short distance (e.g., micron-scale) electrical connections between adjacent semiconductor structures 102 and 104.

[0227] It should be appreciated that in some examples, the first semiconductor structure 102 and the second semiconductor structure 104 can not include the bonding layers 1014 and 1012 disposed on opposite sides of the bonding interface 105, respectively, as shown in FIG. 22A In FIG. 22B , the semiconductor layer 1002 in the first semiconductor structure 102 of the 3D memory device 2201 can be a single-crystalline silicon layer transferred from a silicon substrate or an SOI substrate by transfer bonding and attached to a top surface of the second semiconductor structure 104, and in contrast to hybrid bonding, the bonding interface 105 between the first semiconductor structure 102 and the second semiconductor structure 104 can be generated by the transfer bonding. A through via (e.g., ILV / TSV) vertically passing through the semiconductor layer 1002 between the first semiconductor structure 102 and the second semiconductor structure 104 can make a direct short distance (e.g., sub-micron level) electrical connection between the adjacent semiconductor structures 102 and 104.

[0228] As shown in FIG. 22A and 22B , according to some embodiments, since the first semiconductor structure 102 and the second semiconductor structure 104 are bonded in a back-to-back manner (e.g., the semiconductor layer 1002 and 1004 are disposed on the bottom side of the first semiconductor structure 102 and the second semiconductor structure 104, respectively, in FIG. 22A and 22B ), the transistors of the peripheral circuit in the first semiconductor structure 102 and the second semiconductor structure 104 are disposed to face the same direction (e.g., the positive y-direction in FIG. 12A and 12B ). Further, within the first semiconductor structure 102, since the polysilicon layer 106 is vertically between the memory cell array and the peripheral circuit, and the memory cell array and the peripheral circuit are formed on the polysilicon layer 106 and the semiconductor layer 1002, respectively, the memory cell array and the peripheral circuit face the same direction (e.g., in the positive y-direction in FIG. 22A and 22B ). It should be appreciated that for ease of illustration, the pad-out interconnect layer 902 in FIG. 21A and 21B is omitted from the 3D memory devices 2200 and 2201 in FIG. 22A and 22B , and can be included in the 3D memory devices 2200 and 2201 as described above with respect to FIG. 21A and 21B .

[0229] As described above, the first semiconductor structure 102 and the second semiconductor structure 104 can have a peripheral circuit with transistors applied with different voltages. For example, the first semiconductor structure 102 can be a logic circuitry including FIG. 4BAn example of semiconductor structure 408 for LLV circuit 402 (and LV circuit 404 in some examples), and the second semiconductor structure 104 may include FIG. 4B An example of semiconductor structure 410 for HV circuit 406 (and LLV circuit 404 in some examples), and vice versa. Therefore, in some embodiments, semiconductor layers 1002 and 1004 in the first semiconductor structure 102 and the second semiconductor structure 104 have different thicknesses to accommodate transistors to which different voltages are applied. In one example, the second semiconductor structure 104 may include HV circuit 406, the first semiconductor structure 102 may include LLV circuit 402, and the thickness of semiconductor layer 1002 in the first semiconductor structure 102 may be less than the thickness of semiconductor layer 1004 in the second semiconductor structure 104. Furthermore, in some embodiments, the gate dielectrics of the transistors in the first semiconductor structure 102 and the second semiconductor structure 104 also have different thicknesses to accommodate the different applied voltages. In one example, the second semiconductor structure 104 may include HV circuit 406, the first semiconductor structure 102 may include LLV circuit 402, and the thickness of the gate dielectric of the transistor in the second semiconductor structure 104 may be greater than (e.g., at least 5 times) the thickness of the gate dielectric of the transistor in the first semiconductor structure 102.

[0230] FIG. 23A and 23B The various aspects of this disclosure are shown. FIG. 22A and 22B Side views of various examples of 3D memory devices 2200 and 2201. FIG. 23A As shown, as FIG. 22A and 22B An example of 3D memory devices 2200 and 2201, according to some embodiments, 3D memory device 2300 is a bonded chip including a first semiconductor structure 102 and a second semiconductor structure 104, which in the vertical direction (e.g., FIG. 23A The first semiconductor structure 102 and the second semiconductor structure 104 are stacked on different planes in the y-direction. According to some embodiments, the first semiconductor structure 102 and the second semiconductor structure 104 are bonded at the bonding interface 105 therebetween.

[0231] like FIG. 23AAs shown, the second semiconductor structure 104 can include a semiconductor layer 1004 having a semiconductor material. In some embodiments, the semiconductor layer 1004 is a silicon substrate having single-crystal silicon. The second semiconductor structure 104 can also include a device layer 2302 over and in contact with the semiconductor layer 1004. In some embodiments, the device layer 2302 includes a first peripheral circuit 2304 and a second peripheral circuit 2306. The first peripheral circuit 2304 can include HV circuitry 406, such as drive circuitry (e.g., string drivers 704 in row decoders / word line drivers 308 and drivers in column decoders / bit line drivers 306), and the second peripheral circuit 2306 can include LV circuitry 404, such as page buffer circuitry (e.g., page buffer circuitry 702 in page buffers 304) and logic circuitry (e.g., in control logic 312). In some embodiments, the first peripheral circuit 2304 includes a plurality of transistors 2308 in contact with the semiconductor layer 1004, and the second peripheral circuit 2306 includes a plurality of transistors 2310 in contact with the semiconductor layer 1004. The transistors 2308 and 2310 can include any of the transistors disclosed herein, such as planar transistor 500 and 3D transistor 600. As described in detail above with respect to transistors 500 and 600, in some embodiments, each transistor 2308 or 2310 includes a gate dielectric, and due to the voltage applied to the transistors 2308 being higher than the voltage of the transistors 2310, the thickness of the gate dielectric of the transistors 2308 (e.g., in HV circuitry 406) is greater than the thickness of the gate dielectric of the transistors 2310 (e.g., in LV circuitry 404). Trench isolation (e.g., STI) and doped regions (e.g., wells, sources, and drains of transistors 2308 and 2310) can also be formed on or in the semiconductor layer 1004.

[0232] In some embodiments, the second semiconductor structure 104 also includes an interconnect layer 2312 over the device layer 2302 to transmit electrical signals to and from the peripheral circuits 2306 and 2304. As shown, the interconnect layer 2312 includes a plurality of conductive lines 2314 and a plurality of vias 2316. The conductive lines 2314 can be formed of any of the conductive materials disclosed herein, such as copper. The vias 2316 can be formed of any of the conductive materials disclosed herein, such as tungsten. In some embodiments, the conductive lines 2314 and vias 2316 are formed by a damascene process. FIG. 23AAs shown, interconnect layer 2312 may be vertically positioned between bonding interface 105 and device layer 2302 (including transistors 2308 and 2310 of peripheral circuits 2304 and 2306). Interconnect layer 2312 may include multiple interconnects, such as MEOL interconnects and BEOL interconnects. Interconnects in interconnect layer 2312 may be coupled to transistors 2308 and 2310 of peripheral circuits 2304 and 2306 in device layer 2302. Interconnect layer 2312 may also include one or more ILD layers, in which lateral lines and vias may be formed. That is, interconnect layer 2312 may include lateral lines and vias in multiple ILD layers. In some embodiments, devices in device layer 2302 are coupled to each other through interconnects in interconnect layer 2312. For example, peripheral circuit 2304 may be coupled to peripheral circuit 2306 through interconnect layer 2312. Interconnects in interconnect layer 2312 may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. The ILD layer in interconnect layer 2312 may include a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof. In some embodiments, the interconnects in interconnect layer 2312 include W, which has a relatively high thermal budget (compatible with high-temperature processes) and good quality (fewer defects, such as voids) in a conductive metallic material.

[0233] like FIG. 23A As shown, the first semiconductor structure 102 can be bonded to the top of the second semiconductor structure 104 at the bonding interface 105 in a back-to-back manner. The first semiconductor structure 102 may also include a semiconductor layer 1002 having a semiconductor material. In some embodiments, the bonding interface 105 is the location where the semiconductor layer 1002 of the first semiconductor structure 102 and the interconnect layer 2312 of the second semiconductor structure 104 meet and bond. In practice, the bonding interface 105 may be a layer of a specific thickness, comprising the top surface of the interconnect layer 2312 of the second semiconductor structure 104 and the bottom surface of the semiconductor layer 1002 of the first semiconductor structure 102. The bonding interface 105 may be generated by a transfer bonding process, and the semiconductor layer 1002 may be a single-crystal silicon layer transferred from a silicon substrate or SOI substrate and attached to the top surface of the first semiconductor structure 102 by transfer bonding, as described in detail below regarding the manufacturing process. In some embodiments, a dielectric layer (e.g., a silicon oxide layer) is vertically formed between the bonding interface 105 and the semiconductor layer 1002 and / or between the bonding interface 105 and the interconnect layer 2312 to facilitate transfer bonding from the semiconductor layer 1002 to the interconnect layer 2312. Therefore, it should be understood that in some examples, the bonding interface 105 may include the surface of one or more dielectric layers.

[0234] like FIG. 23AAs shown, the first semiconductor structure 102 can also include a device layer 2314 over and in contact with the semiconductor layer 1002. In some embodiments, the device layer 2314 includes a third peripheral circuit 2316 and a fourth peripheral circuit 2318 over and in contact with the semiconductor layer 1002. In some embodiments, the semiconductor layer 1002 is disposed vertically between the bonding interface 105 and the device layer 2314 having the peripheral circuits 2316 and 2318. The third peripheral circuit 2316 can include the LLV circuit 402, such as I / O circuitry (e.g., in the interface 316 and the data bus 318), and the fourth peripheral circuit 2318 can include the LV circuit 404, such as page buffer circuitry (e.g., the page buffer circuitry 702 in the page buffer 304) and logic circuitry (e.g., in the control logic 312). In some embodiments, the third peripheral circuit 2316 includes a plurality of transistors 2320, and the fourth peripheral circuit 2318 also includes a plurality of transistors 2322. The transistors 2320 and 2322 can include any of the transistors disclosed herein, such as the planar transistor 500 and the 3D transistor 600. As described in detail above with respect to the transistors 500 and 600, in some embodiments, each of the transistors 2320 or 2322 includes a gate dielectric, and the thickness of the gate dielectric of the transistors 2320 (e.g., in the LLV circuit 402) is less than the thickness of the gate dielectric of the transistors 2322 (e.g., in the LV circuit 404) due to the voltage applied to the transistors 2320 being lower than the voltage applied to the transistors 2322.

[0235] Furthermore, different voltages applied to different transistors 2320, 2322, 2308, and 2310 in the first semiconductor structure 102 and the second semiconductor structure 104 can result in a difference in device size between the first semiconductor structure 102 and the second semiconductor structure 104. In some embodiments, the thickness of the gate dielectric of the transistors 2308 (e.g., in the HV circuit 406) is greater than the thickness of the gate dielectric of the transistors 2320 (e.g., in the LLV circuit 402) due to the voltage applied to the transistors 2308 being higher than the voltage applied to the transistors 2320. In some embodiments, the thickness of the gate dielectric of the transistors 2322 (e.g., in the LV circuit 404) is the same as the thickness of the gate dielectric of the transistors 2310 (e.g., in the LV circuit 404) due to the voltage applied to the transistors 2322 being the same as the voltage applied to the transistors 2310. In some embodiments, the thickness of the semiconductor layer 1004 in which the transistors 2308 are formed (e.g., in the HV circuit 406) is greater than the thickness of the semiconductor layer 1002 in which the transistors 2320 are formed (e.g., in the LLV circuit 402) due to the voltage applied to the transistors 2308 being higher than the voltage applied to the transistors 2320.

[0236] As FIG. 23A shown in FIG. 35, the first semiconductor structure 102 can also include an interconnect layer 2326 over and in contact with the device layer 2314 to transport electrical signals to and from the transistors 2320 and 2322 of the peripheral circuits 2316 and 2318. The interconnect layer 2326 can include a plurality of interconnects, such as MEOL interconnects and BEOL interconnects. The interconnect layer 2326 can also include one or more ILD layers in which lateral lines and vias can be formed. The interconnects in the interconnect layer 2326 can include a conductive material, including but not limited to W, Co, Cu, Al, silicide, or any combination thereof. The ILD layers in the interconnect layer 2326 can include a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof. In some embodiments, the interconnects in the interconnect layer 2326 include W, which has a relatively high thermal budget (compatible with high temperature processes) and good quality (fewer defects, such as voids) among conductive metal materials.

[0237] As FIG. 23A shown in FIG. 35, the first semiconductor structure 102 can also include one or more contacts 2330 extending vertically through the semiconductor layer 1002. In some embodiments, the contacts 2330 further extend through a dielectric layer (if any) on the backside of the semiconductor layer 1002 to contact interconnects of the interconnect layer 2312 at the bonding interface 105. The contacts 2330 can thus couple interconnects in the interconnect layer 2326 to interconnects in the interconnect layer 2312 for electrical connection through the semiconductor layer 1004 and across the bonding interface 105 between the first semiconductor structure 102 and the second semiconductor structure 104. The contacts 2330 can include a conductive material, including but not limited to W, Co, Cu, Al, silicide, or any combination thereof. In some embodiments, the contacts 2330 include W. In some embodiments, the contacts 2330 include vias surrounded by a dielectric spacer (e.g., with silicon oxide) to electrically isolate the vias from the semiconductor layer 1002. Depending on the thickness of the semiconductor layer 1002, the contacts 2330 can be ILVs with a sub-micron depth (e.g., between 10 nm and 1 pm), or TSVs with a micron or tens-of-micron depth (e.g., between 1 pm and 100 pm).

[0238] As FIG. 23A shown in FIG. 35, the first semiconductor structure can also include a polysilicon layer 106 over and in contact with the interconnect layer 2326. According to some embodiments, the polysilicon layer 106 is a doped polysilicon layer on the interconnect layer 2326, as described in detail below with respect to the fabrication process. It should be appreciated that in some examples, trench isolation and doped regions (not shown) can also be formed in the polysilicon layer 106.

[0239] As FIG. 8As shown, the first semiconductor structure 102 may further include an array of memory cells, such as an array of NAND memory strings 208 above and in contact with the polysilicon layer 106. The sources of the NAND memory strings 208 may be in contact with the polysilicon layer 106. In some embodiments, the polysilicon layer 106 is perpendicular between the NAND memory strings 208 and a device layer 2314 including transistors 2320 and 2322. In some embodiments, each NAND memory string 208 is a "charge-trapping" type NAND memory string, which includes any suitable channel structure disclosed herein, such as those described above relative to... FIG. 8 The channel structure 812 is described in detail. In some embodiments, the NAND memory string 208 is a "floating gate" type NAND memory string, and the polysilicon layer 106 is the source plate of the floating gate type NAND memory string.

[0240] According to some implementations, each NAND memory string 208 extends vertically through multiple pairs of layers, each comprising a conductive layer and a dielectric layer. The stacked and interleaved conductive and dielectric layers are also referred to herein as a stacked layer structure, for example, a memory stack 2327. The memory stack 2327 may be... FIG. 23A Examples of memory stack layer 804 include conductive layers and dielectric layers in memory stack layer 2327, which may be examples of gate conductive layer 806 and dielectric layer 808 in memory stack layer 804, respectively. According to some embodiments, the staggered conductive and dielectric layers in memory stack layer 2327 alternate in the vertical direction. Each conductive layer may include a gate electrode (gate line) surrounded by an adhesive layer and a gate dielectric layer. The gate electrode of the conductive layer may extend laterally as a word line, terminating at one or more stepped structures in memory stack layer 2327.

[0241] like FIG. 23A As shown, the first semiconductor structure 102 may further include an interconnect layer 2328 above and in contact with the NAND memory string 208, for transmitting electrical signals to and from the NAND memory string 208. In some embodiments, the memory stack layer 2327 and the NAND memory string 208 are perpendicularly positioned between the interconnect layer 2328 and the polysilicon layer 106. The interconnect layer 2328 may include multiple interconnects, such as MEOL interconnects and BEOL interconnects. In some embodiments, the interconnects in the interconnect layer 2328 may also include local interconnects, such as bit line contacts and word line contacts. The interconnect layer 2328 may also include one or more ILD layers in which lateral lines and vias can be formed. The interconnects in the interconnect layer 2328 may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. The ILD layers in the interconnect layer 2328 may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0242] like FIG. 23A As shown, the first semiconductor structure 102 may further include one or more contacts 2324 extending vertically through the polysilicon layer 106. In some embodiments, the contacts 2324 couple interconnects in interconnect layer 2328 to interconnects in interconnect layer 2326 to make electrical connections between NAND memory string 208 and transistors 2320 and 2322 through the polysilicon layer 106. The contacts 2324 may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. In some embodiments, the contacts 2324 include W or Cu. In some embodiments, the contacts 2324 include vias surrounded by dielectric spacers (e.g., having silicon oxide) to electrically isolate the vias from the polysilicon layer 106. Depending on the thickness of the polysilicon layer 106, the contacts 2324 may be ILVs with depths in the submicron range (e.g., between 10 nm and 1 μm) or TSVs with depths in the micron or tens of micron ranges (e.g., between 1 μm and 100 μm).

[0243] like FIG. 23A As shown, the first semiconductor structure 102 may further include an interconnect layer 2328 and a pad-out interconnect layer 902 above the NAND memory string 208. In some embodiments, the NAND memory string 208 is vertically disposed between the pad-out interconnect layer 902 and the polysilicon layer 106. The pad-out interconnect layer 902 may include interconnects in one or more ILD layers, such as contact pads 2332. In some embodiments, for example, for pad-out purposes, the interconnects in the pad-out interconnect layer 902 may transmit electrical signals between the 3D memory device 2300 and external devices.

[0244] As a result, the peripheral circuits 2304, 2306, 2316, and 2318 in the second semiconductor structure 104 and the first semiconductor structure 102 can be coupled to the NAND memory string 208 in the first semiconductor structure 102 through various interconnect structures, including interconnect layers 2312, 2326, and 2328 and contacts 2324 and 2330. Furthermore, the peripheral circuits 2304, 2306, 2316, and 2318 in the 3D memory device 2300 and the NAND memory string 208 can be further coupled to external devices through the contact 2330 and pads leading out from the interconnect layer 902.

[0245] It should be understood that the pad leads of 3D memory devices are not limited to those from, for example... FIG. 21A The first semiconductor structure 102 shown has a NAND memory string 208 and peripheral circuitry 2316 (corresponding to...) FIG. 21B ), and can come from a second semiconductor structure 104 having peripheral circuitry 2304 (corresponding toFIG. 23B For example, such as FIG. 23B As shown, the 3D memory device 2301 may include a pad-out interconnect layer 902 in a second semiconductor structure 104. The pad-out interconnect layer 902 may contact the semiconductor layer 1004 of the second semiconductor structure 104, on which transistors 2308 of peripheral circuitry 2304 are formed. In some embodiments, the second semiconductor structure 104 further includes one or more contacts 2334 extending vertically through the semiconductor layer 1004. In some embodiments, the contacts 2334 couple interconnects in the interconnect layer 2312 of the second semiconductor structure 104 to contact pads 2332 in the pad-out interconnect layer 902 for electrical connection through the semiconductor layer 1004. The contacts 2334 may include a conductive material, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. In some embodiments, the contacts 2334 include W. In some embodiments, the contacts 2334 include vias surrounded by dielectric spacers (e.g., having silicon oxide) to electrically isolate the vias from the semiconductor layer 1004. Depending on the thickness of the semiconductor layer 1004, the contact 2334 can be an ILV with a thickness in the submicron range (e.g., between 10 nm and 1 μm), or a TSV with a depth in the micron range or tens of micron range (e.g., between 1 μm and 100 μm).

[0246] like FIG. 23A As shown, the first semiconductor structure 102 may further include a passivation layer 2350, which replaces... FIG. 23B The first semiconductor structure 102 has pads leading out from the interconnect layer 902 to protect and encapsulate the 3D memory device 2301 from the side of the first semiconductor structure 102 without pads. The passivation layer 2350 may include a dielectric material such as silicon nitride and / or silicon oxide. In some embodiments, the first semiconductor structure 102 in the 3D memory device 2301 also includes an operational / carrier substrate 2351 in contact with the passivation layer 2350, serving as a base substrate for support of the 3D memory device 2301. It should be understood that in some examples, the passivation layer 2350 may be omitted or combined with the operational substrate 2351 as a single layer for support and protection.

[0247] It should also be understood that, in some examples, the first semiconductor structure 102 and the second semiconductor structure 104 of the 3D memory device 2301 may also include bonding layers 1012 and 1014 at the bonding interface 105 (on opposite sides of the bonding interface 105), such as FIG. 24A-24FAs shown. That is, in contrast to transfer bonding, the bonding interface 105 can be generated by hybrid bonding. A bonding layer 1012 can be disposed between the bonding interface 105 and the interconnect layer 2312, and a bonding layer 1014 can be disposed between the bonding interface 105 and the semiconductor layer 1002. In some embodiments, the bonding layer 1014 is formed on the back side of the semiconductor layer 1002 (e.g., a thinned silicon substrate) opposite to the front side on which the device layer 2314 is formed. In practice, the bonding interface 105 can be a layer of a specific thickness, comprising the top surface of the bonding layer 1012 of the second semiconductor structure 104 and the bottom surface of the bonding layer 1014 of the first semiconductor structure 102.

[0248] Bonding layers 1012 and 1014 may include a dielectric material comprising multiple bonding contacts and electrically isolating bonding contacts. The bonding contacts may comprise conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. In some embodiments, the bonding contacts of bonding layers 1012 and 1014 comprise Cu. The remaining regions of bonding layers 1012 and 1014 may be formed of a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. The bonding contacts and surrounding dielectric in bonding layers 1012 and 1014 can be used for hybrid bonding (also known as “metal / dielectric hybrid bonding”), a direct bonding technique (e.g., forming a bond between surfaces without using an intermediate layer, such as solder or adhesive), and can simultaneously achieve metal-to-metal (e.g., Cu-Cu) bonding and dielectric-to-dielectric (e.g., SiO2-SiO2) bonding.

[0249] FIG. 22A This disclosure illustrates some aspects of the formation of FIG. 26 and 22B The manufacturing process of 3D memory devices. FIG. 22A This disclosure illustrates some aspects of the formation of FIG. 24A-24F and 22B The flowchart of the method 2600 for 3D memory devices. FIG. 23A Examples of 3D memory devices shown in Figure 26 include: FIG. 24A-24F The 3D memory device 2300 shown is described together. FIG. 26 And 26. It should be understood that the operations shown in method 2600 are not exhaustive, and other operations may be performed before, after, or between any of the operations shown. Furthermore, some operations may be performed simultaneously, or in conjunction with... FIG. 26 The different execution orders shown.

[0250] refer to FIG. 24AMethod 2600 begins at operation 2602, where a first transistor is formed on a first substrate. The first substrate can be a silicon substrate having single-crystal silicon. As shown in FIGS. 6A and 6B, a planar transistor 500 or a 3D transistor 600 can be formed on a silicon substrate 2402. The transistors 500 and 600 can be formed by a variety of processes, including but not limited to photolithography, dry / wet etching, thin film deposition, thermal growth, implantation, CMP, and any other suitable processes. In some embodiments, doped regions are formed in the silicon substrate 2402 by ion implantation and / or thermal diffusion, which are used as, for example, well and source / drain regions for the transistors 500 and 600. In some embodiments, isolation regions (e.g., STI) are also formed in the silicon substrate 2402 by wet / dry etching and thin film deposition. In some embodiments, the thickness of the gate dielectric of the transistors 500 is different from the thickness of the gate dielectric of the transistors 600, for example, by depositing a thicker silicon oxide film in the region of the transistors 500 than in the region of the transistors 600, or by etching back a portion of the silicon oxide film deposited in the region of the transistors 600. It should be understood that the details of fabricating the transistors 500 and 600 can vary depending on the type of transistors (e.g., NMOS, PMOS, or CMOS), and thus are not elaborated further for ease of description. FIG. 5A As shown in FIGS. 6A and 6B, a planar transistor 500 or a 3D transistor 600 can be formed on a silicon substrate 2402. The transistors 500 and 600 can be formed by a variety of processes, including but not limited to photolithography, dry / wet etching, thin film deposition, thermal growth, implantation, CMP, and any other suitable processes. In some embodiments, doped regions are formed in the silicon substrate 2402 by ion implantation and / or thermal diffusion, which are used as, for example, well and source / drain regions for the transistors 500 and 600. In some embodiments, isolation regions (e.g., STI) are also formed in the silicon substrate 2402 by wet / dry etching and thin film deposition. In some embodiments, the thickness of the gate dielectric of the transistors 500 is different from the thickness of the gate dielectric of the transistors 600, for example, by depositing a thicker silicon oxide film in the region of the transistors 500 than in the region of the transistors 600, or by etching back a portion of the silicon oxide film deposited in the region of the transistors 600. It should be understood that the details of fabricating the transistors 500 and 600 can vary depending on the type of transistors (e.g., NMOS, PMOS, or CMOS), and thus are not elaborated further for ease of description. FIG. 24A , 5B As shown in FIGS. 6A and 6B, a planar transistor 500 or a 3D transistor 600 can be formed on a silicon substrate 2402. The transistors 500 and 600 can be formed by a variety of processes, including but not limited to photolithography, dry / wet etching, thin film deposition, thermal growth, implantation, CMP, and any other suitable processes. In some embodiments, doped regions are formed in the silicon substrate 2402 by ion implantation and / or thermal diffusion, which are used as, for example, well and source / drain regions for the transistors 500 and 600. In some embodiments, isolation regions (e.g., STI) are also formed in the silicon substrate 2402 by wet / dry etching and thin film deposition. In some embodiments, the thickness of the gate dielectric of the transistors 500 is different from the thickness of the gate dielectric of the transistors 600, for example, by depositing a thicker silicon oxide film in the region of the transistors 500 than in the region of the transistors 600, or by etching back a portion of the silicon oxide film deposited in the region of the transistors 600. It should be understood that the details of fabricating the transistors 500 and 600 can vary depending on the type of transistors (e.g., NMOS, PMOS, or CMOS), and thus are not elaborated further for ease of description.

[0251] In some embodiments, an interconnect layer 2408 is formed over the transistors on the first substrate. The interconnect layer can include a plurality of interconnects in one or more ILD layers. As shown in FIGS. 6A and 6B, an interconnect layer 2408 can be formed over the transistors 500 and 600. The interconnect layer 2408 can include MEOL and / or BEOL interconnects in a plurality of ILD layers to electrically connect with the transistors 500 and 600. In some embodiments, the interconnect layer 2408 includes a plurality of ILD layers and interconnects formed therein by a plurality of processes. For example, the interconnects in the interconnect layer 2408 can include a conductive material deposited by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. The fabrication processes to form the interconnects can also include photolithography, CMP, wet / dry etching, or any other suitable processes. The ILD layers can include a dielectric material deposited by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. FIG. 24A As shown in FIGS. 6A and 6B, a planar transistor 500 or a 3D transistor 600 can be formed on a silicon substrate 2402. The transistors 500 and 600 can be formed by a variety of processes, including but not limited to photolithography, dry / wet etching, thin film deposition, thermal growth, implantation, CMP, and any other suitable processes. In some embodiments, doped regions are formed in the silicon substrate 2402 by ion implantation and / or thermal diffusion, which are used as, for example, well and source / drain regions for the transistors 500 and 600. In some embodiments, isolation regions (e.g., STI) are also formed in the silicon substrate 2402 by wet / dry etching and thin film deposition. In some embodiments, the thickness of the gate dielectric of the transistors 500 is different from the thickness of the gate dielectric of the transistors 600, for example, by depositing a thicker silicon oxide film in the region of the transistors 500 than in the region of the transistors 600, or by etching back a portion of the silicon oxide film deposited in the region of the transistors 600. It should be understood that the details of fabricating the transistors 500 and 600 can vary depending on the type of transistors (e.g., NMOS, PMOS, or CMOS), and thus are not elaborated further for ease of description. FIG. 26 The ILD layers and interconnects shown in FIGS. 6A and 6B can be collectively referred to as the interconnect layer 2408. In some embodiments, the interconnects in the interconnect layer 2408 include W, which has a relatively high thermal budget among conductive metal materials to withstand later high-temperature processes.

[0252] Method 2600 proceeds to operation 2604, as FIG. 24B illustrated, where a semiconductor layer is formed over the first transistor. The semiconductor layer can include single crystal silicon. In some embodiments, to form the semiconductor layer, another substrate is bonded to the first substrate in a face-to-face manner, and the other substrate is thinned to leave the semiconductor layer. The bonding can include transfer bonding. The other substrate can be a silicon substrate having single crystal silicon.

[0253] As FIG. 24B illustrated, a semiconductor layer 2410, such as a single crystal silicon layer, is formed over the interconnect layer 2408 and the transistors 2404 and 2406. The semiconductor layer 2410 can be attached over the interconnect layer 2408 to form a bonding interface 2412 vertically between the semiconductor layer 2410 and the interconnect layer 2408. In some embodiments, a dielectric layer(s) (e.g., a silicon oxide layer) is formed between the bonding interface 2412 and the semiconductor layer 2410 and / or between the bonding interface 2412 and the interconnect layer 2408 to facilitate transfer bonding of the semiconductor layer 2410. In some embodiments, to form the semiconductor layer 2410, transfer bonding is used to bond another silicon substrate (not shown in FIG. 24B) to the silicon substrate 2402 in a face-to-face manner (with the components formed on the silicon substrate 2402, such as the transistors 2404 and 2406, facing the other silicon substrate), thereby forming the bonding interface 2412. The other silicon substrate can then be thinned using any suitable process to leave the semiconductor layer 2410 attached over the interconnect layer 2408. Details of various transfer bonding processes are described above with reference to FIG. 34A-34D and FIG. 35A-35D and FIG. 24C are not repeated for the sake of brevity of the description.

[0254] Method 2600 proceeds to operation 2606, where a second transistor is formed on the semiconductor layer. As FIG. 5AAs shown, a plurality of transistors 2414 and 2416 are formed on a semiconductor layer 2410 having single crystalline silicon. The transistors 2414 and 2416 can be formed by a variety of processes, including but not limited to photolithography, dry / wet etching, thin film deposition, thermal growth, implantation, CMP, and any other suitable processes. In some embodiments, doped regions are formed in the semiconductor layer 2410 by ion implantation and / or thermal diffusion, which are used as, for example, the well and source / drain regions of the transistors 2414 and 2416. In some embodiments, isolation regions (e.g., STI) are also formed in the semiconductor layer 2410 by wet / dry etching and thin film deposition. In some embodiments, the thickness of the gate dielectric of the transistors 2414 is different from the thickness of the gate dielectric of the transistors 2416, for example, by depositing a thicker silicon oxide film in the region of the transistors 2414 than in the region of the transistors 2416, or by etching back a portion of the silicon oxide film deposited in the region of the transistors 2416. It should be appreciated that the details of fabricating the transistors 2414 and 2416 can vary depending on the type of transistors (e.g., planar transistors 500 or 3D transistors 600 in FIGS. 6A and 6B), and thus are not elaborated further for ease of description. FIG. 24C 5B

[0255] In some embodiments, an interconnect layer is formed over the transistors. The interconnect layer can include a plurality of interconnects in one or more ILD layers. As FIG. 24C As shown, an interconnect layer 2420 can be formed over the transistors 2414 and 2416. The interconnect layer 2420 can include MEOL and / or BEOL interconnects in a plurality of ILD layers to electrically connect with the transistors 2414 and 2416. In some embodiments, the interconnect layer 2420 includes a plurality of ILD layers and interconnects formed therein with a plurality of processes. For example, the interconnects in the interconnect layer 2420 can include a conductive material deposited by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. The fabrication processes to form the interconnects can also include photolithography, CMP, wet / dry etching, or any other suitable processes. The ILD layers can include a dielectric material deposited by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. FIG. 26 The ILD layers and interconnects shown in FIG. 24B can be collectively referred to as the interconnect layer 2420. In some embodiments, the interconnects in the interconnect layer 2420 include W, which has a relatively high thermal budget among conductive metal materials to withstand later high temperature processes.

[0256] ​​In some embodiments, a contact is formed through the semiconductor layer. The contact 2418 can extend vertically from the front side of the semiconductor layer 2410 through the semiconductor layer. The contact 2418 can be coupled to an interconnect in the interconnect layer 2420. The contact 2418 can further extend through a dielectric layer (if any) on the back side of the semiconductor layer 2410 to align with and contact an interconnect in the interconnect layer 2408 at the bonding interface 2412. Thus, the contact 2418 couples an interconnect in the interconnect layer 2408 with an interconnect in the interconnect layer 2420 through the semiconductor layer 2410 and across the bonding interface 2412. The contact 2418 can be formed by first patterning a contact hole in the semiconductor layer 2410 using a patterning process (e.g., photolithography and dry / wet etching of the dielectric material in the dielectric layer). The contact hole can be filled with a conductor (e.g., W). In some embodiments, filling the contact hole includes depositing a spacer (e.g., a silicon oxide layer) prior to depositing the conductor.

[0257] The method 2600 proceeds to operation 2608, where a polysilicon layer is formed over the second transistor. As shown in FIG. 24D As shown in FIG. 26 The polysilicon layer 2411 can be formed by depositing polysilicon on the interconnect layer 2420 using one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. In some embodiments, the polysilicon layer 2411 is doped with P-type or N-type dopants using an in-situ doping process during the deposition process or during an ion implantation / diffusion process after the deposition process.

[0258] The method 2600 proceeds to operation 2010, where an array of NAND memory strings is formed on the polysilicon layer. In some embodiments, to form the array of NAND memory strings, a memory stack is formed on the polysilicon layer. As shown in FIG. 24E As shown in FIG. 24E To form the memory stack 2426, in some embodiments, a dielectric stack (not shown) including alternating sacrificial layers (not shown) and dielectric layers is formed on the polysilicon layer 2411.

[0259] In some embodiments, each sacrificial layer comprises a silicon nitride layer, and each dielectric layer comprises a silicon oxide layer. The staggered sacrificial and dielectric layers can be formed using one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, or any combination thereof). The memory stack 2426 can then be formed using a gate replacement process, for example, by replacing the sacrificial layers with conductive layers using a wet / dry etching process selectively applied to the dielectric layers, and filling the resulting trenches with the conductive layers. In some embodiments, each conductive layer comprises a metal layer, such as a W layer. It should be understood that in some examples, the memory stack 2426 can be formed by alternately depositing conductive layers (e.g., doped polysilicon layers) and dielectric layers (e.g., silicon oxide layers) without a gate replacement process.

[0260] In some embodiments, a pad oxide layer comprising silicon oxide is formed between the memory stack layer 2426 and the polysilicon layer 2411.

[0261] like FIG. 8 As shown, a NAND memory string 2428 is formed over a polysilicon layer 2411, with each string extending vertically through a memory stack layer 2426 to contact the polysilicon layer 2411. In some embodiments, the fabrication process for forming the NAND memory string 2428 includes forming channel vias through the memory stack layer 2426 (or dielectric stack layer) and into the polysilicon layer 2411 using dry etching and / or wet etching (e.g., DRIE), followed by filling the channel vias with multiple layers (e.g., memory films (e.g., tunneling layers, storage layers, and barrier layers) and semiconductor layers) using thin-film deposition processes (e.g., ALD, CVD, PVD, or any combination thereof). It should be understood that the details of fabricating the NAND memory string 2428 can depend on the type of channel structure of the NAND memory string 2428 (e.g., FIG. 24E The channel structure (812) varies, and therefore will not be elaborated further for ease of description.

[0262] In some implementations, an interconnect layer is formed above an array of NAND memory strings. The interconnect layer may include a plurality of interconnects within one or more ILD layers. FIG. 24EAs shown, an interconnect layer 2430 is formed over the memory stack layer 2426 and the NAND memory string 2428. The interconnect layer 2430 may include interconnects of MEOL and / or BEOL in a plurality of ILD layers for electrical connection to the NAND memory string 2428. In some embodiments, the interconnect layer 2430 includes a plurality of ILD layers and interconnects formed therein using a plurality of processes. For example, the interconnects in the interconnect layer 2430 may include conductive materials deposited by one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof). The fabrication processes forming the interconnects may also include photolithography, CMP, wet / dry etching, or any other suitable process. The ILD layers may include dielectric materials deposited by one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, or any combination thereof). FIG. 24E The ILD layer and interconnect shown can be collectively referred to as interconnect layer 2430.

[0263] In some implementations, contacts are formed through the polysilicon layer. For example... FIG. 26 As shown, one or more contacts 2417 are formed, each extending vertically through the polysilicon layer 2411. The contacts 2417 can couple interconnects in interconnect layers 2430 and 2408. The contacts 2417 can be formed by first patterning contact holes through the polysilicon layer 2411 using a patterning process (e.g., photolithography and dry / wet etching of the dielectric material in the dielectric layer). The contact holes can be filled with a conductor (e.g., W or Cu). In some embodiments, filling the contact holes includes depositing a spacer (e.g., a silicon oxide layer) before depositing the conductor.

[0264] Method 2600 skips optional operation 2612 and proceeds to operation 2614, such as... FIG. 24F As shown, an interconnect layer with pads is formed. This interconnect layer can be formed above the array of NAND memory strings. FIG. 26 As shown, a pad-lead interconnect layer 2436 is formed above the interconnect layer 2430 and the NAND memory string 2428 on the polysilicon layer 2411. The pad-lead interconnect layer 2436 may include interconnects formed in one or more ILD layers, such as contact pads 2438. The contact pads 2438 may include conductive materials, including but not limited to W, Co, Cu, Al, doped silicon, silicides, or any combination thereof. The ILD layer may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0265] In some embodiments, in order to form pads to lead out interconnect layers on the first substrate, after operation 2610, method 2600 proceeds to optional operation 2612, such as... FIG. 24Eshown, where the first substrate is thinned. It should be appreciated that although not shown, in some examples, the silicon substrate 2402 (shown in FIG. 24B) can be thinned using processes including, but not limited to, wafer grinding, dry etching, wet etching, CMP, any other suitable process, or any combination thereof. FIG. 26 After thinning, contacts can be formed extending vertically through the thinned silicon substrate 2402, for example, by wet / dry etching, followed by deposition of a dielectric material as a spacer and a conductive material as a conductor. It should be appreciated that in some examples, the contacts can be formed in the silicon substrate 2402 prior to thinning and exposed from the backside of the silicon substrate 2402 (where thinning occurs) after thinning.

[0266] The method 2600 proceeds to operation 2614, as FIG. 25A-25G shown, where a pad-out interconnect layer is formed. The pad-out interconnect layer can be formed on the thinned first substrate. It should be appreciated that although not shown, in some examples, a pad-out interconnect layer with contact pads can be formed on the thinned silicon substrate 2402.

[0267] FIG. 22A Another manufacturing process for forming a 3D memory device in FIG. 27 and 22B in accordance with some aspects of the disclosure is shown. FIG. 22A Another method 2700 for forming a 3D memory device in FIG. 25A-25G and 22B in accordance with some aspects of the disclosure is shown. FIG. 23B Examples of the 3D memory devices shown in FIG. 25A-25G include the 3D memory device 2301 shown in FIG. 23A. The FIG. 27 and 27 will be described together. It should be appreciated that the operations shown in the method 2700 are not exhaustive and that other operations can also be performed before, after, or in between any of the shown operations. Furthermore, some operations can be performed concurrently, or in a different order than shown in FIG. 27 .

[0268] Referring to FIG. 25A , the method 2700 begins at operation 2702, where a first transistor is formed on a frontside of a first substrate. The first substrate can be a silicon substrate having single crystalline silicon. As FIG. 5AAs shown, a plurality of transistors 2514 and 2516 are formed on the front side of the silicon substrate 2510. The transistors 2514 and 2516 can be formed by a variety of processes, including but not limited to photolithography, dry / wet etching, thin film deposition, thermal growth, implantation, CMP, and any other suitable processes. In some embodiments, doped regions are formed in the silicon substrate 2510 by ion implantation and / or thermal diffusion, which are used as, for example, well and source / drain regions for the transistors 2514 and 2516. In some embodiments, isolation regions (e.g., STI) are also formed in the silicon substrate 2510 by wet / dry etching and thin film deposition. In some embodiments, the thickness of the gate dielectric of the transistors 2514 is different from the thickness of the gate dielectric of the transistors 2516, for example, by depositing a thicker silicon oxide film in the region of the transistors 2514 than in the region of the transistors 2516, or by etching back a portion of the silicon oxide film deposited in the region of the transistors 2516. It should be appreciated that the details of fabricating the transistors 2514 and 2516 can vary depending on the type of transistors (e.g., planar transistors 500 or 3D transistors 600 in FIGS. 6A and 6B), and thus are not elaborated further for ease of description. FIG. 25A , 5B , 6A and 6B), and thus are not elaborated further for ease of description.

[0269] In some embodiments, an interconnect layer 2520 is formed over the transistors on the first substrate. The interconnect layer can include a plurality of interconnects in one or more ILD layers. As FIG. 25A shown, the interconnect layer 2520 can be formed over the transistors 2514 and 2516. The interconnect layer 2520 can include MEOL and / or BEOL interconnects in a plurality of ILD layers to electrically connect with the transistors 2514 and 2516. In some embodiments, the interconnect layer 2520 includes a plurality of ILD layers and interconnects formed therein with a plurality of processes. For example, the interconnects in the interconnect layer 2520 can include a conductive material deposited by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. The fabrication processes to form the interconnects can also include photolithography, CMP, wet / dry etching, or any other suitable processes. The ILD layers can include a dielectric material deposited by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. FIG. 25A The ILD layers and interconnects shown in FIG. 25B can be collectively referred to as the interconnect layer 2520. In some embodiments, the interconnects in the interconnect layer 2520 include W, which has a relatively high thermal budget among conductive metal materials to withstand later high temperature processes.

[0270] In some embodiments, contacts are formed through the thinned first substrate. As FIG. 27As shown, contacts 2518 are formed extending vertically from the front side of silicon substrate 2510 into silicon substrate 2510. Contacts 2518 can be coupled to interconnects in interconnect layer 2520. Contacts 2518 can be formed by first patterning contact holes in silicon substrate 2510 using a patterning process (e.g., photolithography and dry / wet etching of dielectric material in dielectric layer). Contact holes can be filled with a conductor (e.g., Cu). In some embodiments, filling contact holes includes depositing a spacer (e.g., silicon oxide layer) before depositing a conductor.

[0271] Method 2700 proceeds to operation 2704, such as... FIG. 25B As shown, a polysilicon layer is formed above the first transistor. FIG. 27 As shown, a polysilicon layer 2511 is formed over the interconnect layer 2520 and transistors 2514 and 2516 on the first silicon substrate 2510. The polysilicon layer 2511 can be formed by depositing polysilicon on the interconnect layer 2520 using one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, or any combination thereof). In some embodiments, the polysilicon layer 2511 is doped with a P-type or N-type dopant using an in-situ doping process during or after the deposition process, or during an ion implantation / diffusion process.

[0272] Method 2700 proceeds to operation 2706, such as... FIG. 25C As shown, an array of NAND memory strings is formed on a polysilicon layer. In some embodiments, a memory stack layer is formed on the polysilicon layer to form the array of NAND memory strings. FIG. 25C As shown, a stacked layer structure is formed on the polysilicon layer 2511, such as a memory stacked layer 2526 including staggered conductive and dielectric layers. In order to form the memory stacked layer 2526, in some embodiments, a dielectric stacked layer (not shown) including staggered sacrificial layers (not shown) and dielectric layers is formed on the polysilicon layer 2511.

[0273] In some embodiments, each sacrificial layer includes a silicon nitride layer, and each dielectric layer includes a silicon oxide layer. The staggered sacrificial and dielectric layers can be formed by one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, or any combination thereof). The memory stack 2526 can then be formed by a gate replacement process, for example, by replacing the sacrificial layers with a conductive layer using a wet / dry etching process with a sacrificial layer selective for the dielectric layers, and filling the resulting trenches with the conductive layer.

[0274] In some implementations, each conductive layer includes a metal layer, such as a W layer. It should be understood that in some examples, the memory stack layer 2526 can be formed by alternately depositing conductive layers (e.g., doped polysilicon layers) and dielectric layers (e.g., silicon oxide layers) without a gate replacement process.

[0275] In some embodiments, a pad oxide layer comprising silicon oxide is formed between the memory stack layer 2526 and the polysilicon layer 2511.

[0276] like FIG. 8 As shown, a NAND memory string 2528 is formed over a polysilicon layer 2511, with each string extending vertically through a memory stack layer 2526 to contact the polysilicon layer 2511. In some embodiments, the fabrication process for forming the NAND memory string 2528 includes forming channel vias through the memory stack layer 2526 (or dielectric stack layer) and into the polysilicon layer 2511 using dry etching and / or wet etching (e.g., DRIE), followed by filling the channel vias with multiple layers (e.g., memory films (e.g., tunneling layers, storage layers, and barrier layers) and semiconductor layers) using thin-film deposition processes (e.g., ALD, CVD, PVD, or any combination thereof). It should be understood that the details of fabricating the NAND memory string 2528 can depend on the type of channel structure of the NAND memory string 2528 (e.g., FIG. 25C The channel structure (812) varies, and therefore will not be elaborated further for ease of description.

[0277] In some implementations, an interconnect layer is formed above an array of NAND memory strings. The interconnect layer may include a plurality of interconnects within one or more ILD layers. FIG. 25C As shown, an interconnect layer 2530 is formed over the memory stack layer 2526 and the NAND memory string 2528. The interconnect layer 2530 may include interconnects of MEOL and / or BEOL in a plurality of ILD layers for electrical connection to the NAND memory string 2528. In some embodiments, the interconnect layer 2530 includes a plurality of ILD layers and interconnects formed therein using a plurality of processes. For example, the interconnects in the interconnect layer 2530 may include conductive materials deposited by one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof). The fabrication processes forming the interconnects may also include photolithography, CMP, wet / dry etching, or any other suitable process. The ILD layers may include dielectric materials deposited by one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, or any combination thereof). FIG. 25C The ILD layer and interconnect shown can be collectively referred to as interconnect layer 2530.

[0278] In some embodiments, contacts are formed through the polysilicon layer. As shown in FIG. 25E one or more contacts 2517 are formed that each extend vertically through the polysilicon layer 2511. The contacts 2517 can couple interconnects in the interconnect layers 2530 and 2508. The contacts 2517 can be formed by first patterning contact holes through the polysilicon layer 2511 using a patterning process (e.g., photolithography and dry / wet etching of dielectric material in a dielectric layer). The contact holes can be filled with a conductor (e.g., W or Cu). In some embodiments, filling the contact holes includes depositing a spacer (e.g., a silicon oxide layer) prior to depositing the conductor.

[0279] In some embodiments, the first substrate is thinned. As shown in FIG. 25C the silicon substrate 2510 (as shown in FIG. 25E ) is thinned to be a semiconductor layer 2509 having single crystalline silicon. The silicon substrate 2510 can be thinned by processes including, but not limited to, wafer grinding, dry etching, wet etching, CMP, any other suitable process, or any combination thereof. For example, by controlling the duration of the CMP process, the thickness of the semiconductor layer 2509 can be controlled to expose the contacts 2518 from the backside of the thinned silicon substrate 2510. It should be appreciated that in some examples, in contrast to being in the silicon substrate 2510 prior to thinning, the contacts 2518 can be formed through the semiconductor layer 2509 from the backside thereof after thinning. In some embodiments, prior to thinning, a passivation layer 2523 is formed on the interconnect layer 2530 by depositing a dielectric material such as silicon nitride on the interconnect layer 2530 using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. Then, prior to thinning, the handle substrate 2501 can be attached to the passivation layer 2523, e.g., using adhesive bonding, to allow for subsequent backside processing of the silicon substrate 2510 such as thinning, contact formation, and bonding.

[0280] In some embodiments, a first bonding layer is formed on the backside of the thinned first substrate. The first bonding layer can include a plurality of first bonding contacts. As shown in FIG. 27As shown, a bonding layer 2522 is formed on the backside of the semiconductor layer 2509 (i.e., the thinned silicon substrate 2510). The bonding layer 2522 can include a plurality of bonding contacts surrounded by a dielectric. In some embodiments, a dielectric layer is deposited on the backside of the semiconductor layer 2509 (opposite the frontside on which the transistors 2514 and 2516 are formed) by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. Then, by first patterning contact holes through the dielectric layer using a patterning process (e.g., photolithography and dry / wet etching of the dielectric material in the dielectric layer), bonding contacts can be formed through the dielectric layer and into contact with the contacts 2518 on the backside of the thinned silicon substrate 2510. The contact holes can be filled with a conductor (e.g., Cu). In some embodiments, filling the contact holes includes depositing an adhesion (glue) layer, a barrier layer, and / or a seed layer prior to depositing the conductor.

[0281] The method 2700 proceeds to operation 2708, as FIG. 25D shown, where a second transistor is formed on a second substrate. The second substrate can be a silicon substrate having single crystalline silicon. As FIG. 5A shown, a plurality of transistors 2504 and 2506 are formed on a silicon substrate 2502 having single crystalline silicon. The transistors 2504 and 2506 can be formed by a variety of processes, including but not limited to photolithography, dry / wet etching, thin film deposition, thermal growth, implantation, CMP, and any other suitable processes. In some embodiments, doped regions are formed in the silicon substrate 2502 by ion implantation and / or thermal diffusion, which are used as, for example, well and source / drain regions for the transistors 2504 and 2506. In some embodiments, isolation regions (e.g., STI) are also formed in the silicon substrate 2502 by wet / dry etching and thin film deposition. In some embodiments, the thickness of the gate dielectric of the transistor 2504 is different from the thickness of the gate dielectric of the transistor 2506, for example, by depositing a thicker silicon oxide film in the region of the transistor 2504 than in the region of the transistor 2506, or by etching back a portion of the silicon oxide film deposited in the region of the transistor 2506. It should be appreciated that the details of fabricating the transistors 2504 and 2506 can vary depending on the type of transistors (e.g., planar transistors 500 or 3D transistors 600 in FIGS. 6A and 6B), and thus, are not elaborated on again for ease of description. FIG. 25D 5B , 6A and 6B), and thus, are not elaborated on again for ease of description.

[0282] In some embodiments, an interconnect layer is formed over the transistors on the second substrate. The interconnect layer can include a plurality of interconnects in one or more ILD layers. As FIG. 25D ​As shown, an interconnect layer 2508 can be formed over transistors 2504 and 2506. Interconnect layer 2508 can include interconnects of MEOL and / or BEOL in multiple ILD layers to electrically connect with transistors 2504 and 2506. In some embodiments, interconnect layer 2508 includes multiple ILD layers and interconnects formed therein with multiple processes. For example, the interconnects in interconnect layer 2508 can include conductive materials deposited by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. The manufacturing processes to form the interconnects can also include photolithography, CMP, wet / dry etching, or any other suitable processes. The ILD layers can include dielectric materials deposited by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. FIG. 25D The ILD layers and interconnects shown therein can be collectively referred to as interconnect layer 2520. Unlike interconnect layer 2520, in some embodiments, the interconnects in interconnect layer 2508 include Cu, which has a relatively low resistivity among conductive metallic materials. It should be appreciated that although Cu has a relatively low thermal budget (not compatible with high temperature processes), it becomes feasible to use Cu as the conductive material for the interconnects in interconnect layer 2508 because there are no more high temperature processes after the fabrication of interconnect layer 2508.

[0283] In some embodiments, a second bonding layer is formed over the interconnect layer. The second bonding layer can include a plurality of second bonding contacts. As FIG. 27 As shown, a bonding layer 2521 is formed over interconnect layer 2508. Bonding layer 2521 can include a plurality of bonding contacts surrounded by a dielectric. In some embodiments, a dielectric layer is deposited on the top surface of interconnect layer 2508 by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. Bonding contacts through the dielectric layer and to the interconnects in interconnect layer 2508 can then be formed by first patterning contact holes through the dielectric layer using a patterning process (e.g., photolithography and dry / wet etching of the dielectric material in the dielectric layer). The contact holes can be filled with a conductor (e.g., Cu). In some embodiments, filling the contact holes includes depositing an adhesion (glue) layer, a barrier layer, and / or a seed layer before depositing the conductor.

[0284] Method 2700 proceeds to operation 2710, as FIG. 25F shown, where the first substrate and the second substrate are bonded in a face-to-back manner. After bonding the first and second substrates, the first bonding contacts in the first bonding layer can be in contact with the second bonding contacts in the second bonding layer at the bonding interface. The bonding can include hybrid bonding.

[0285] As FIG. 27As shown, the thinned silicon substrate 2510 (i.e., semiconductor layer 2509) and components formed thereon (e.g., transistors 2514 and 2516 and NAND memory string 2528) are bonded to the silicon substrate 2502 and components formed thereon (e.g., transistors 2504 and 2506) in a face-to-face manner, with the bonding layer 2521 facing upward on the front side of the silicon substrate 2502 and the bonding layer 2522 facing downward on the back side of the thinned silicon substrate 2510, thereby forming a bonding interface 2524. That is, the thinned silicon substrate 2510 and components formed thereon can be bonded to the silicon substrate 2502 and components formed thereon in a back-to-face manner, such that the bonding contacts in the bonding layer 2521 and the bonding contacts in the bonding layer 2522 contact at the bonding interface 2524. In some embodiments, a processing technique, such as plasma treatment, wet treatment, and / or heat treatment, is applied to the bonding surfaces prior to bonding. As a result of bonding (e.g., hybrid bonding), the bonding contacts on opposite sides of the bonding interface 2524 can be mixed with each other. After bonding, according to some embodiments, the bonding contacts in the bonding layer 2521 and the bonding contacts in the bonding layer 2522 are aligned and contacted with each other, such that the memory stack layer 2526 and the NAND memory string 2528 formed therethrough, as well as transistors 2514 and 2516, can be coupled to transistors 2504 and 2506 across the bonding interface 2524 via the bonded bonding contacts.

[0286] Method 2700 proceeds to optional operation 2712, such as... FIG. 25F As shown, the second substrate is thinned. FIG. 25E As shown, silicon substrate 2502 ( FIG. 27 The silicon substrate 2502 (as shown) is thinned to become a semiconductor layer 2503 having monocrystalline silicon. The silicon substrate 2502 can be thinned by processes including but not limited to wafer grinding, dry etching, wet etching, CMP, any other suitable process or any combination thereof.

[0287] Method 2700 proceeds to operation 2714, such as... FIG. 25F As shown, a pad-out interconnect layer is formed therein. The pad-out interconnect layer can be formed on a thinned second substrate. As... FIG. 25FAs shown, a pad-out interconnect layer 2536 is formed on a semiconductor layer 2503 (thinned silicon substrate 2502). The pad-out interconnect layer 2536 may include interconnects formed in one or more ILD layers, such as contact pads 2538. Contact pads 2538 may include conductive materials, including but not limited to W, Co, Cu, Al, doped silicon, silicides, or any combination thereof. The ILD layers may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. In some embodiments, after bonding and thinning, contacts 2534 extending vertically through the semiconductor layer 2503 are formed, for example by wet / dry etching, followed by deposition of a dielectric material as a spacer and a conductive material as a conductor. Contacts 2534 can couple the contact pads 2538 in the pad-out interconnect layer 2536 to the interconnects in the interconnect layer 2508. It should be understood that in some examples, contacts 2534 may be formed before thinning (e.g., FIG. 27 The semiconductor layer 2503 shown is formed in the silicon substrate 2502 and exposed from the back side of the silicon substrate 2502 (at the location where the thinning occurs) after thinning.

[0288] In some implementations, after operation 2710, optional operation 2712 is skipped, and method 2700 proceeds to operation 2714, such as... FIG. 25F As shown, an interconnect layer with pads is formed. This interconnect layer can be formed above the array of NAND memory strings. Although in FIG. 28A Although not shown, it should be understood that in some examples, after removing the operating substrate 2501 and the passivation layer 2523, a pad-out interconnect layer with contact pads may be formed over the interconnect layer 2530 and the NAND memory string 2528.

[0289] FIG. 21A and 28B Some aspects of this disclosure are shown. FIG. 21A and 21B A schematic diagram of a cross-section of the 3D memory devices shown. The 3D memory devices 2800 and 2801 can be... FIG. 28A and 21B Examples of 3D memory devices 2100 and 2101. (See example...) FIG. 8 As shown, the 3D memory device 2800 may include a stacked first semiconductor structure 102 and a second semiconductor structure 104. In some embodiments, the first semiconductor structure 102 includes a semiconductor layer 1002, a bonding layer 1014, a memory cell array, some peripheral circuitry in peripheral circuitry vertically between the semiconductor layer 1002 and the polysilicon layer 106, and the polysilicon layer 106 vertically between the memory cell array and the peripheral circuitry.

[0290] The array of memory cells can include an array of NAND memory strings (e.g., the NAND memory strings 208 disclosed herein), and the sources of the array of NAND memory strings can be in contact with the polysilicon layer 106 (e.g., as shown in FIG. 8B). The polysilicon layer 106 can be a deposited polysilicon layer (e.g., N-type doped, P-type doped, or undoped) suitable for channel structures in “floating gate” type NAND memory strings or “charge trapping” type NAND memory strings suitable for GIDL erase operations, for example. The polysilicon layer 106 can be a deposited polysilicon layer (e.g., N-type doped, P-type doped, or undoped) suitable for channel structures in “floating gate” type NAND memory strings or “charge trapping” type NAND memory strings suitable for GIDL erase operations, for example. FIG. 8 The array of memory cells can include an array of NAND memory strings (e.g., the NAND memory strings 208 disclosed herein), and the sources of the array of NAND memory strings can be in contact with the polysilicon layer 106 (e.g., as shown in FIG. 8B). The polysilicon layer 106 can be a deposited polysilicon layer (e.g., N-type doped, P-type doped, or undoped) suitable for channel structures in “floating gate” type NAND memory strings or “charge trapping” type NAND memory strings suitable for GIDL erase operations, for example. The polysilicon layer 106 can be a deposited polysilicon layer (e.g., N-type doped, P-type doped, or undoped) suitable for channel structures in “floating gate” type NAND memory strings or “charge trapping” type NAND memory strings suitable for GIDL erase operations, for example. FIG. 28A The array of memory cells can include an array of NAND memory strings (e.g., the NAND memory strings 208 disclosed herein), and the sources of the array of NAND memory strings can be in contact with the polysilicon layer 106 (e.g., as shown in FIG. 8B). The polysilicon layer 106 can be a deposited polysilicon layer (e.g., N-type doped, P-type doped, or undoped) suitable for channel structures in “floating gate” type NAND memory strings or “charge trapping” type NAND memory strings suitable for GIDL erase operations, for example. The polysilicon layer 106 can be a deposited polysilicon layer (e.g., N-type doped, P-type doped, or undoped) suitable for channel structures in “floating gate” type NAND memory strings or “charge trapping” type NAND memory strings suitable for GIDL erase operations, for example.

[0291] In some embodiments, the peripheral circuitry in the first semiconductor structure 102 is in contact with the semiconductor layer 1002 but not in contact with the polysilicon layer 106. That is, the transistors (e.g., the planar transistors 500 and the 3D transistors 600) of the peripheral circuitry can be in contact with the semiconductor layer 1002. The semiconductor layer 1002 can include a semiconductor material such as single crystalline silicon (e.g., a silicon substrate or a thinned silicon substrate). It will be appreciated that, unlike the polysilicon layer 106 in the first semiconductor structure 102, the semiconductor layer 1002 on which the transistors are formed can include single crystalline silicon rather than polysilicon in some examples due to the superior carrier mobility of single crystalline silicon that is desirable for the performance of the transistors. The peripheral circuitry and the bonding layer 1014 can be formed on opposite sides of the semiconductor layer 1002 such that the semiconductor layer 1002 is disposed vertically between the peripheral circuitry and the bonding layer 1014. In some embodiments, the transistors of the peripheral circuitry are formed on the front side of the semiconductor layer 1002 and the bonding contacts of the bonding layer 1014 are formed on the back side of the semiconductor layer 1002.

[0292] In some embodiments, the second semiconductor structure 104 includes the bonding layer 1012, some of the peripheral circuits of the array of memory cells, and the semiconductor layer 1004 vertically between the peripheral circuits and the bonding layer 1012. The transistors (e.g., planar transistors 500 and 3D transistors 600) of the peripheral circuits can be in contact with the front side of the semiconductor layer 1004. Similar to the semiconductor layer 1002, the semiconductor layer 1004 can include a semiconductor material such as single crystalline silicon (e.g., a silicon substrate or a thinned silicon substrate). It should be appreciated that, in some examples, unlike the polysilicon layer 106 in the first semiconductor structure 102, the semiconductor layer 1004 on which the transistors are formed can include single crystalline silicon, rather than polysilicon, due to the superior carrier mobility of single crystalline silicon that is desirable for the performance of the transistors. The peripheral circuits and the bonding layer 1012 can be formed on opposite sides of the semiconductor layer 1004, such that the semiconductor layer 1004 is disposed vertically between the peripheral circuits and the bonding layer 1012. In some embodiments, the transistors of the peripheral circuits are formed on the front side of the semiconductor layer 1004, and the bonding contacts of the bonding layer 1012 are formed on the back side of the semiconductor layer 1004.

[0293] Similar to the bonding layer 1014 in the first semiconductor structure 102, the bonding layer 1012 can also include electrically conductive bonding contacts (not shown) and a dielectric that electrically isolates the bonding contacts. According to some embodiments, the bonding interface 105 is vertically between and in contact with the bonding layers 1012 and 1014, respectively. That is, the bonding layers 1012 and 1014 can be disposed on opposite sides of the bonding interface 105, and the bonding contacts of the bonding layer 1012 can be in contact with the bonding contacts of the bonding layer 1014 at the bonding interface 105. As a result, a large number (e.g., millions) of bonding contacts across the bonding interface 105 in combination with through contacts (e.g., ILV / TSVs) through the semiconductor layers 1002 and 1004 can enable direct, short distance (e.g., micron-level) electrical connections between adjacent semiconductor structures 102 and 104.

[0294] It should be appreciated that, in some examples, the first semiconductor structure 102 and the second semiconductor structure 104 can not include the bonding layers 1014 and 1012, respectively, as shown disposed on opposite sides of the bonding interface 105. In some examples, the first semiconductor structure 102 and the second semiconductor structure 104 can not include the bonding layers 1014 and 1012, respectively, as shown disposed on opposite sides of the bonding interface 105. FIG. 28B FIG. 28A ​In the 3D memory device 2801, the semiconductor layer 1004 in the second semiconductor structure 104 can be a single-crystal silicon layer transferred from a silicon substrate or SOI substrate and attached to the bottom surface of the first semiconductor structure 102 by transfer bonding. Conversely, unlike hybrid bonding, the bonding interface 105 between the first semiconductor structure 102 and the second semiconductor structure 104 can be generated by transfer bonding. Through-contacts (e.g., ILV / TSV) perpendicularly passing between the first semiconductor structure 102 and the second semiconductor structure 104 through the semiconductor layers 1002 and 1004 can provide direct, short-distance (e.g., submicron-level) electrical connections between adjacent semiconductor structures 102 and 104.

[0295] like FIG. 28A and 28B As shown, according to some embodiments, since the first semiconductor structure 102 and the second semiconductor structure 104 are bonded back-to-back (e.g., in...), FIG. 28A and 28B In this configuration, semiconductor layer 1002 is disposed on the bottom side of the first semiconductor structure 102, while semiconductor layer 1004 is disposed on the top side of the second semiconductor structure 104....

Claims

1. A three-dimensional (3D) memory device, comprising: A first semiconductor structure, the first semiconductor structure comprising: NAND memory string array; The first peripheral circuit of the NAND memory string array includes a first transistor; A polysilicon layer, the polysilicon layer being located between the NAND memory string array and the first peripheral circuit, the polysilicon layer being in contact with the source of the NAND memory string array; and A first semiconductor layer, wherein the first semiconductor layer is in contact with the first transistor; A second semiconductor structure, the second semiconductor structure comprising: The second peripheral circuit of the NAND memory string array, the second peripheral circuit including a second transistor; and A second semiconductor layer, which is in contact with the second transistor; and a bonding interface, which is located between the first semiconductor structure and the second semiconductor structure. Wherein, the second transistor is located between the bonding interface and the second semiconductor layer; and The polycrystalline silicon layer is located between the first semiconductor layer and the second semiconductor layer.

2. The 3D memory device according to claim 1, wherein, The first peripheral circuit is located between the first semiconductor layer and the polysilicon layer.

3. The 3D memory device according to claim 1 or 2, wherein, Each of the first semiconductor layer and the second semiconductor layer comprises monocrystalline silicon.

4. The 3D memory device according to any one of claims 1-3, wherein, The thickness of the first semiconductor layer is greater than the thickness of the second semiconductor layer.

5. The 3D memory device according to any one of claims 1-4, wherein, The first transistor includes a first gate dielectric; The second transistor includes a second gate dielectric; and The thickness of the first gate dielectric is greater than the thickness of the second gate dielectric.

6. The 3D memory device according to claim 5, wherein, The difference between the thicknesses of the first gate dielectric and the second gate dielectric is at least 5 times.

7. The 3D memory device according to claim 5 or 6, wherein, The first semiconductor structure further includes a third peripheral circuit for the NAND memory string array, the third peripheral circuit including a third transistor, the third transistor including a third gate dielectric; and The second semiconductor structure further includes a fourth peripheral circuit of the NAND memory string array, the fourth peripheral circuit including a fourth transistor including a fourth gate dielectric.

8. The 3D memory device according to claim 7, wherein, The third gate dielectric and the fourth gate dielectric have the same thickness.

9. The 3D memory device according to claim 8, wherein, The thickness of the third gate dielectric and the fourth gate dielectric is between the thickness of the first gate dielectric and the second gate dielectric.

10. The 3D memory device according to any one of claims 7-9, wherein, The third and fourth peripheral circuits include at least one of a page buffer circuit or a logic circuit.

11. The 3D memory device according to any one of claims 1-10, wherein, The first semiconductor structure further includes a first interconnect layer between the polysilicon layer and the first peripheral circuit, the first interconnect layer including a first interconnect coupled to the first transistor; and The second semiconductor structure further includes a second interconnect layer between the bonding interface and the second peripheral circuit, the second interconnect layer including a second interconnect coupled to the second transistor.

12. The 3D memory device according to claim 11, wherein, The first interconnect comprises tungsten, and the second interconnect comprises copper.

13. The 3D memory device according to claim 11 or 12, wherein, The first semiconductor structure further includes: A third interconnect layer, the third interconnect layer being between the bonding interface and the NAND memory string array, the third interconnect layer including a third interconnect coupled to the NAND memory string array; and The contact passes through the polysilicon layer and couples the third interconnect to the first interconnect.

14. The 3D memory device according to any one of claims 1-13, wherein, The first semiconductor structure further includes a first pad leading to an interconnect layer in contact with the first semiconductor layer, or The second semiconductor structure also includes a second pad lead-out interconnect layer that contacts the second semiconductor layer.

15. The 3D memory device according to any one of claims 1-14, wherein, The first peripheral circuit includes a driving circuit, and the second peripheral circuit includes an input / output (I / O) circuit.

16. The 3D memory device according to any one of claims 1-15, further comprising: A first voltage source, the first voltage source being coupled to the first peripheral circuit and configured to provide a first voltage to the first peripheral circuit; as well as A second voltage source, coupled to the second peripheral circuit and configured to provide a second voltage to the second peripheral circuit. Wherein, the first voltage is greater than the second voltage.

17. The 3D memory device according to any one of claims 1-16, wherein, The first semiconductor structure further includes a first bonding layer, such that the NAND memory string array is located between the first bonding layer and the polysilicon layer, and the first bonding layer includes a first bonding contact; The second semiconductor structure further includes a second bonding layer, such that the second transistor is located between the second bonding layer and the second semiconductor layer, the second bonding layer including second bonding contacts; and The first bonding contact contacts the second bonding contact at the bonding interface.

18. The 3D memory device according to any one of claims 1-17, wherein, The first transistor is formed on the first semiconductor layer, and the second transistor is formed on the second semiconductor layer.

19. A system comprising: A memory device configured to store data, and the memory device comprising: A first semiconductor structure, the first semiconductor structure comprising: NAND memory string array; The first peripheral circuit of the NAND memory string array includes a first transistor; A polysilicon layer, the polysilicon layer being between the NAND memory string array and the first transistor, the polysilicon layer being in contact with the source of the NAND memory string array; and A first semiconductor layer, wherein the first semiconductor layer is in contact with the first transistor; A second semiconductor structure, the second semiconductor structure comprising: The second peripheral circuit of the NAND memory string array, the second peripheral circuit including a second transistor; and A second semiconductor layer, the second semiconductor layer being in contact with the second transistor; and A bonding interface is located between the first semiconductor structure and the second semiconductor structure, wherein the second transistor is located between the bonding interface and the second semiconductor layer, and the polysilicon layer is located between the first semiconductor layer and the second semiconductor layer; and A memory controller coupled to the memory device and configured to control the NAND memory string array via the first peripheral circuitry and the second peripheral circuitry.

20. A method for forming a three-dimensional (3D) memory device, comprising: A first transistor is formed on a first substrate; A polycrystalline silicon layer is formed above the first transistor on the first substrate; A NAND memory string array is formed on the polysilicon layer, wherein the polysilicon layer is between the NAND memory string array and the first transistor; A second transistor is formed on a second substrate; and The first substrate and the second substrate are bonded face-to-face. The polycrystalline silicon layer is located between the first substrate and the second substrate.

21. The method of claim 20, further comprising: After bonding the first substrate and the second substrate, the second substrate is thinned; as well as An interconnect layer with pads is formed on the thinned second substrate.

22. The method of claim 20, further comprising: After bonding the first substrate and the second substrate, the first substrate is thinned; as well as An interconnect layer with pads is formed on the thinned first substrate.

23. The method according to any one of claims 20-22, wherein, Bonding the first substrate and the second substrate includes hybrid bonding.

24. The method according to any one of claims 20-23, further comprising: A first bonding layer is formed over the NAND memory string array, the first bonding layer including a first bonding contact; as well as A second bonding layer is formed above the second transistor, the second bonding layer including second bonding contacts. After the first substrate and the second substrate are bonded, the first bonding contact contacts the second bonding contact at the bonding interface.

25. The method according to any one of claims 20-24, further comprising forming contacts through the polysilicon layer.

26. The method according to any one of claims 20-25, wherein, Forming the first transistor includes forming a first gate dielectric; Forming the second transistor includes forming a second gate dielectric; and The thickness of the first gate dielectric is greater than the thickness of the second gate dielectric.

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