Three-dimensional memory devices and methods for forming the same

Abstract

In some aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes an array of NAND memory strings, a first peripheral circuit of the array of NAND memory strings including a first transistor, a polysilicon layer between the array of NAND memory strings and the first peripheral circuit, and a first semiconductor layer in contact with the first transistor. The polysilicon layer is in contact with a source of the array of NAND memory strings. The second semiconductor structure includes a second peripheral circuit of the array of NAND memory strings including a second transistor, and a second semiconductor layer in contact with the second transistor. The second semiconductor layer is between the bonding interface and the second peripheral circuit. The polysilicon layer is between the first semiconductor layer and the second semiconductor layer.

Description

Background Technology

[0001] This disclosure relates to memory devices and methods of manufacturing the same.

[0002] Planar memory cells can be scaled to smaller sizes by improving process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of memory cells approaches its lower limit, planar processes and manufacturing technologies become challenging and costly. As a result, the memory density of planar memory cells is approaching its upper limit.

[0003] Three-dimensional (3D) memory architectures can address the density limitations of planar memory cells. A 3D memory architecture includes a memory array and peripheral circuitry to facilitate the operation of the memory array. Summary of the Invention

[0004] In one aspect, a 3D memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first and second semiconductor structures. The first semiconductor structure includes a NAND flash memory string array, a first peripheral circuit of the NAND flash memory string array including a first transistor, a polysilicon layer between the NAND flash memory string array and the first peripheral circuit, and a first semiconductor layer in contact with the first transistor. The polysilicon layer is in source contact with the NAND flash memory string array. The second semiconductor structure includes a second peripheral circuit of the NAND flash memory string array and a second semiconductor layer in contact with a second transistor, the second peripheral circuit including the second transistor. The second semiconductor layer is located between the bonding interface and the second peripheral circuit. The polysilicon layer is located between the first and second semiconductor layers.

[0005] In another aspect, a system includes a memory device configured to store data. The memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first and second semiconductor structures. The first semiconductor structure includes a NAND flash memory string array, first peripheral circuitry of the NAND flash memory string array including a first transistor, a polysilicon layer between the NAND flash memory string array and the first peripheral circuitry, and a first semiconductor layer in contact with the first transistor. The polysilicon layer is in source contact with the NAND flash memory string array. The second semiconductor structure includes a second peripheral circuitry of the NAND flash memory string array and a second semiconductor layer in contact with a second transistor, the second peripheral circuitry including the second transistor. The second semiconductor layer is located between the bonding interface and the second peripheral circuitry. The polysilicon layer is located between the first and second semiconductor layers. The system also includes a memory controller coupled to the memory device and configured to control the memory cell array via the first and second peripheral circuitry.

[0006] In another aspect, a method for forming a 3D memory device is disclosed. A first transistor is formed on a first substrate. A polysilicon layer is formed over the first transistor on the first substrate. A NAND memory string array is formed on the polysilicon layer. A second transistor is formed on the front side of a second substrate. The first and second substrates are bonded together in a face-to-back manner.

[0007] In another aspect, a method for forming a 3D memory device is disclosed. A first transistor is formed on a first substrate. A polysilicon layer is formed over the first transistor on the first substrate. A NAND memory string array is formed on the polysilicon layer. A semiconductor layer is formed over the NAND memory string array. The semiconductor layer comprises monocrystalline silicon. A second transistor is formed on the semiconductor layer. Attached Figure Description

[0008] The accompanying drawings, which are incorporated herein and form part of the specification, illustrate various aspects of this disclosure and, together with the specification, further serve to explain the principles of this disclosure and enable those skilled in the art to make and use this disclosure.

[0009] Figure 1A A schematic diagram of a cross-section of a 3D memory device according to some aspects of this disclosure is shown.

[0010] Figure 1B A schematic cross-sectional view of another 3D memory device according to some aspects of this disclosure is shown.

[0011] Figure 2 A schematic circuit diagram of a memory device including peripheral circuitry is shown, according to some aspects of this disclosure.

[0012] Figure 3 A block diagram of a memory device including a memory cell array and peripheral circuitry, according to some aspects of this disclosure, is shown.

[0013] Figure 4A Block diagrams of peripheral circuits provided with various voltages according to some aspects of this disclosure are shown.

[0014] Figure 4B A schematic diagram is shown of peripheral circuitry provided with various voltages in a separate semiconductor structure, arranged according to some aspects of this disclosure.

[0015] Figure 5A and 5B Perspective and side views of a planar transistor according to some aspects of this disclosure are shown respectively.

[0016] Figure 6A and 6BPerspective and side views of 3D transistors according to some aspects of this disclosure are shown respectively.

[0017] Figure 7 Circuit diagrams of word line drivers and page buffers according to some aspects of this disclosure are shown.

[0018] Figure 8 A side view of a NAND memory string in a 3D memory device according to some aspects of this disclosure is shown.

[0019] Figure 9A and 9B A schematic cross-sectional view of a 3D memory device having two stacked semiconductor structures is shown, according to various aspects of this disclosure.

[0020] Figure 10 The various aspects of this disclosure are shown. Figure 9A and 9B A schematic diagram of the cross-section of a 3D memory device.

[0021] Figure 11A and 11B The various aspects of this disclosure are shown. Figure 10 Side view of various examples of 3D memory devices.

[0022] Figure 12A-12G This disclosure illustrates some aspects of the formation of Figure 10 The manufacturing process of 3D memory devices.

[0023] Figure 13A and 13B This disclosure illustrates some aspects of the formation of Figure 10 Another manufacturing process for 3D memory devices.

[0024] Figure 14 This disclosure illustrates some aspects of the formation of Figure 10 A flowchart of a method for developing 3D memory devices.

[0025] Figure 15A and 15B The various aspects of this disclosure are shown. Figure 9A and 9B A schematic diagram of the cross-section of a 3D memory device.

[0026] Figure 16A and 16B The various aspects of this disclosure are shown. Figure 15A and 15B Side views of various examples of 3D memory devices.

[0027] Figures 17A-17H This disclosure illustrates some aspects of the formation of Figure 15A and 15B The manufacturing process of 3D memory devices.

[0028] Figures 18A-18F This disclosure illustrates some aspects of the formation of Figure 15A and 15B Another manufacturing process for 3D memory devices.

[0029] Figure 19 This disclosure illustrates some aspects of the formation of Figure 15A and 15B A flowchart of a method for developing 3D memory devices.

[0030] Figure 20 This disclosure illustrates some aspects of the formation of Figure 15A and 15B A flowchart of a method for developing 3D memory devices.

[0031] Figure 21A and 21B A schematic cross-sectional view of a 3D memory device having two stacked semiconductor structures is shown, according to various aspects of this disclosure.

[0032] Figure 22A and 22B Some aspects of this disclosure are shown. Figure 21A and 21B A schematic diagram of the cross-section of a 3D memory device.

[0033] Figure 23A and 23B The various aspects of this disclosure are shown. Figure 22A and 22B Side views of various examples of 3D memory devices.

[0034] Figures 24A-24F This disclosure illustrates some aspects of the formation of Figure 22A and 22B The manufacturing process of 3D memory devices.

[0035] Figure 25A-25G This disclosure illustrates some aspects of the formation of Figure 22A and 22B Another manufacturing process for 3D memory devices.

[0036] Figure 26 This disclosure illustrates some aspects of the formation of Figure 22A and22B A flowchart of a method for developing 3D memory devices.

[0037] Figure 27 This disclosure illustrates some aspects of the formation of Figure 22A and 22B A flowchart of another method for 3D memory devices.

[0038] Figure 28A and 28B Some aspects of this disclosure are shown. Figure 21A and 21B A schematic diagram of the cross-section of a 3D memory device.

[0039] Figure 29A and 29B The various aspects of this disclosure are shown. Figure 28A and 28B Side views of various examples of 3D memory devices.

[0040] Figure 30A-30G This disclosure illustrates some aspects of the formation of Figure 28A and 28B The manufacturing process of 3D memory devices.

[0041] Figures 31A to 31H This disclosure illustrates some aspects of the formation of Figure 28A and 28B Another manufacturing process for 3D memory devices.

[0042] Figure 32 This disclosure illustrates some aspects of the formation of Figure 28A and 28B A flowchart of a method for developing 3D memory devices.

[0043] Figure 33 This disclosure illustrates some aspects of the formation of Figure 28A and 28B A flowchart of another method for 3D memory devices.

[0044] Figures 34A-34D The manufacturing process of transfer bonding according to some aspects of this disclosure is illustrated.

[0045] Figures 35A-35D Another manufacturing process for transfer bonding based on some aspects of this disclosure is shown.

[0046] Figure 36 A block diagram of an exemplary system having a memory device is shown, according to some aspects of this disclosure.

[0047] Figure 37A A diagram of an exemplary memory card having a memory device is shown, according to some aspects of this disclosure.

[0048] Figure 37B A diagram of an exemplary solid-state drive (SSD) having a memory device is shown, according to some aspects of this disclosure.

[0049] The contents of this disclosure will be explained with reference to the accompanying drawings. Detailed Implementation

[0050] Although specific configurations and arrangements have been discussed, it should be understood that this is for illustrative purposes only. Therefore, other configurations and arrangements may be used without departing from the scope of this disclosure. Furthermore, this disclosure can be used in a variety of other applications. The functional and structural features described in this disclosure may be combined, adjusted, and modified with each other in a manner not specifically shown in the accompanying drawings, such combinations, adjustments, and modifications being within the scope of this disclosure.

[0051] Generally, terms can be understood at least partly from their usage in context. For example, the term "one or more," as used herein, depends at least partly on the context and can be used to describe any feature, structure, or characteristic in a singular sense, or to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a" or "described" can also be understood, at least partly on the context, to express either a singular or plural usage. Furthermore, the term "based on" can be understood to not necessarily convey an exclusive set of factors, but rather to allow for the presence of other factors that are not necessarily explicitly described, which also depends at least partly on the context.

[0052] It should be readily understood that the meanings of “on,” “above,” and “on top of” in this disclosure should be interpreted in the broadest possible sense, such that “on” means not only “directly on” but also includes “on” with intermediate features or layers, and that “above” or “on top of” means not only “above” or “on top of” but also includes “above” or “on top of” without intermediate features or layers (i.e., directly on).

[0053] Furthermore, for ease of description, spatially relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or feature and another, as shown in the figures. In addition to the orientations shown in the figures, the spatially relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatially relative descriptive terms used herein may be interpreted accordingly.

[0054] As used herein, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entire lower or upper layer structure, or may have a range smaller than that of the lower or upper layer structure. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any pair of lateral planes at the top and bottom surfaces. A layer may extend laterally, vertically, and / or along a tapered surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (where interconnect lines and / or vertical interconnect access (via) contacts are formed) and one or more dielectric layers.

[0055] As 3D memory devices (e.g., 3D NAND flash memory devices) evolve, the increasing number of stacked layers (e.g., more word lines and consequently more memory cells) necessitates more peripheral circuitry (and components forming this peripheral circuitry, such as transistors) to operate the 3D memory devices. For example, the number and / or size of page buffers need to increase to match the increased number of memory cells. In another example, the number of string drivers in the word line drivers is proportional to the number of word lines in the 3D NAND flash memory. Therefore, the increasing number of word lines also increases the area occupied by the word line drivers, as well as the complexity of the metal wiring, and sometimes even the number of metal layers. Furthermore, in some 3D memory devices where peripheral circuitry is fabricated under the memory cell array, sometimes referred to as a "peripheral under cell" (PUC) architecture or an "under-array complementary metal-oxide-semiconductor (CMOS) (CuA)" architecture, the increasing peripheral circuitry area becomes a bottleneck for reducing the overall chip size, as the memory cell array can be vertically scaled up by increasing the number of layers rather than increasing the planar size.

[0056] Therefore, it is desirable to reduce the planar area occupied by the peripheral circuitry of 3D memory devices as the number of peripheral circuits and their transistors increases. However, scaling down the transistor size of peripheral circuitry in line with the advanced CMOS technology nodes used in logic devices would result in a significant increase in cost and higher leakage current, which is undesirable for memory devices. Furthermore, because 3D NAND flash memory devices require relatively high voltages (e.g., above 5V) for certain memory operations (e.g., programming and erasing), unlike logic devices which can reduce their operating voltage with advancements in CMOS technology nodes, the voltage supplied to the memory peripheral circuitry cannot be reduced. Therefore, scaling down the size of memory peripheral circuitry by following the development trends of CMOS technology nodes (as with conventional logic devices) becomes impractical.

[0057] To address one or more of the aforementioned problems, this disclosure describes various solutions in which the peripheral circuitry of the memory device is arranged in different planes (levels, layers) in the vertical direction, i.e., stacked on top of each other, to reduce the planar chip size of the peripheral circuitry and the overall chip size of the memory device. In some embodiments, memory cell arrays (e.g., NAND memory strings), memory peripheral circuitry supplied with relatively high voltages (e.g., above 3.3V), and memory peripheral circuitry supplied with relatively low voltages (e.g., below 2V) are arranged in different planes in the vertical direction, i.e., stacked on top of each other, to further reduce the chip size. The 3D memory device architecture and manufacturing process disclosed in this disclosure can be easily vertically scaled up to stack more peripheral circuitry in different planes to further reduce the chip size. Furthermore, the 3D memory device architecture and manufacturing process disclosed herein are compatible with PUC / CuA architectures and processes. In some implementations, instead of a single-crystal silicon substrate, a memory cell array (e.g., a NAND memory string) can be formed on a deposited polycrystalline silicon (also known as polysilicon) layer (e.g., in contact with a polycrystalline silicon source plate). This is suitable for certain designs of the channel structure in "floating gate" type NAND memory strings or "charge trap" type NAND memory strings, for example, suitable for gate-induced drain leakage (GIDL) erase operations.

[0058] Based on different performance requirements, such as the voltage applied to the transistors in the peripheral circuitry (which affects the transistor dimensions (e.g., gate dielectric thickness), the dimensions of the substrate in which the transistors are formed (e.g., substrate thickness), and the thermal budget (e.g., interconnect material)), the peripheral circuitry can be separated into different planes in the vertical direction. Therefore, peripheral circuitry with different dimensional requirements (e.g., gate dielectric thickness and substrate thickness) and thermal budgets can be manufactured using different processes to reduce design and process constraints between them, thereby improving device performance and manufacturing complexity.

[0059] According to some aspects of this disclosure, arrays of memory cells and various peripheral circuits with different performance and size requirements can be fabricated in parallel on different substrates, and then stacked on top of each other using various bonding techniques such as hybrid bonding and transfer bonding. As a result, the manufacturing cycle of memory devices can be further reduced. Furthermore, since the thermal budgets of different devices become independent of each other, interconnect materials with desired electrical properties but low thermal budgets, such as copper, can be used to interconnect transistors of memory cells and peripheral circuits, thereby further improving device performance. Bonding techniques can also introduce additional benefits. In some embodiments, hybrid bonding in a face-to-face manner achieves millions of parallel short interconnects between bonded semiconductor structures to increase the throughput and input / output (I / O) speed of memory devices. In some embodiments, transfer bonding reuses a single wafer to transfer its thin semiconductor layer onto different memory devices for forming transistors thereon, which can reduce the cost of memory devices.

[0060] The 3D memory device architecture and manufacturing process disclosed in this disclosure also offer flexibility, allowing for various device pad lead-out schemes to meet the diverse needs and designs of memory cell arrays. In some embodiments, the pad lead-out interconnect layer is formed from the side of the semiconductor structure with peripheral circuitry to shorten the interconnect distance between the pad lead-out interconnect layer and the transistors of the peripheral circuitry, thereby reducing parasitic capacitance from the interconnect and improving electrical performance. In some embodiments, the pad lead-out interconnect layer is formed on a thinned substrate to enable interlayer vias (LLVs, e.g., submicron scale) for pad lead-out interconnects with high I / O throughput and low manufacturing complexity.

[0061] Figure 1A A schematic cross-sectional view of a 3D memory device 100 according to some aspects of this disclosure is shown. The 3D memory device 100 represents an example of a bonded chip. In some embodiments, components of the 3D memory device 100 (e.g., memory cell arrays and peripheral circuitry) are individually and in parallel formed on different substrates and then bonded to form a bonded chip (a process referred to herein as a "parallel process"). In some embodiments, a semiconductor layer (e.g., single-crystal silicon) is attached to another semiconductor structure using transfer bonding, and then some components of the 3D memory device 100 (e.g., some peripheral circuitry) are formed on the attached semiconductor layer (a process referred to herein as a "serial process").

[0062] Note that in Figure 1AAn x-axis and a y-axis have been added to further illustrate the spatial relationships of the components of a semiconductor device. The substrate of a semiconductor device (e.g., a 3D memory device 100) includes two lateral surfaces (e.g., a top surface and a bottom surface) extending laterally in the x-direction (lateral or width direction). As used herein, when the substrate is positioned in the y-direction (vertical or thickness direction) within the lowest plane of the semiconductor device, the y-direction relative to the substrate of the semiconductor device determines whether one component (e.g., a layer or device) of the semiconductor device is “on,” “above,” or “below” another component (e.g., a layer or device). The same concepts used to describe spatial relationships are applied throughout this disclosure.

[0063] 3D memory device 100 may include a first semiconductor structure 102 comprising an array of memory cells (also referred to herein as a "memory cell array"). In some embodiments, the memory cell array includes a NAND flash memory cell array. For ease of description, a NAND flash memory cell array may be used as an example to describe the memory cell array in this disclosure. However, it should be understood that the memory cell array is not limited to NAND flash memory cell arrays and may include any other suitable type of memory cell array, such as a NOR flash memory cell array, a phase-change memory (PCM) cell array, a resistive memory cell array, a magnetic memory cell array, a spin-transfer torque (STT) memory cell array, to name just a few examples.

[0064] The first semiconductor structure 102 may be a NAND flash memory device, wherein memory cells are provided in the form of an array of 3D NAND memory strings and / or an array of two-dimensional (2D) NAND memory cells. NAND memory cells may be organized into pages or fingers, which are then organized into blocks, wherein each NAND memory cell is coupled to a separate line called a bit line (BL). All cells in the NAND memory cell having the same vertical position may be coupled by word lines (WL) via control gates. In some embodiments, a memory plane comprises a number of blocks coupled via the same bit line. The first semiconductor structure 102 may include one or more memory planes, while the peripheral circuitry required to perform all read / program (write) / erase operations may be included in the second semiconductor structure 104 and the first semiconductor structure 102.

[0065] In some embodiments, the NAND memory cell array is a 2D NAND memory cell array, each of which includes a floating-gate transistor. According to some embodiments, the 2D NAND memory cell array includes multiple 2D NAND memory strings, each of which includes multiple memory cells (similar to NAND gates) connected in series and two select transistors. According to some embodiments, each 2D NAND memory string is arranged in the same plane on the substrate (i.e., a flat two-dimensional (2D) surface herein, which differs from the term "memory plane" in this disclosure). In some embodiments, the NAND memory cell array is a 3D NAND memory string array, each of which extends vertically above the substrate through a stacked layer structure (e.g., a memory stack) (in 3D). Depending on the 3D NAND technology (e.g., the number of layers / levels in the memory stack), a 3D NAND memory string typically includes a certain number of memory cells, each of which includes a floating-gate transistor or a charge-trapping transistor.

[0066] Consistent with the scope of this disclosure, the first semiconductor structure 102 may further include a polysilicon layer 106 on which a memory cell array is formed. In some embodiments, the memory cell array includes an array of NAND memory strings, and the polysilicon layer 106 is in contact with the source of the NAND memory strings. That is, the polysilicon layer 106 can serve as a common source plate for multiple NAND memory strings. As described in detail below, the polysilicon layer 106 can be formed in the first semiconductor structure 102 using one or more thin-film deposition processes (including, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof compatible with PUC / CuA processes). It should be understood that in some examples, the polysilicon layer 106 may typically be a semiconductor layer not limited to polysilicon.

[0067] like Figure 1A As shown, the first semiconductor structure 102 may further include some of the peripheral circuitry of the memory cell array, and the memory cell array and peripheral circuitry in the first semiconductor structure 102 may be separated in the vertical direction by a polysilicon layer 106. That is, the polysilicon layer 106 may be vertically disposed between the memory cell array and the peripheral circuitry in the first semiconductor structure 102. In some embodiments, the peripheral circuitry is disposed below the polysilicon layer 106 and the memory cell array formed thereon. Depending on the thickness of the polysilicon layer 106, interconnects (e.g., submicron-level interlayer vias (ILVs) or micron-level or tens of micron-level through-substrate vias (TSVs)) may be formed through the polysilicon layer 106 to form direct, short-distance (e.g., submicron to tens of micron-level) electrical connections between the memory cell array and the peripheral circuitry in the first semiconductor structure 102.

[0068] like Figure 1A As shown, the 3D memory device 100 may further include a second semiconductor structure 104, which includes some of the peripheral circuitry of the memory cell array of the first semiconductor structure 102. That is, the peripheral circuitry of the memory cell array may be divided into at least two semiconductor structures (e.g., Figure 1A (Referring to 102 and 104 in the original text). Peripheral circuitry (also known as control and sensing circuitry) may include any suitable digital, analog, and / or mixed-signal circuitry used to facilitate the operation of the memory cell array. For example, peripheral circuitry may include page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), I / O circuitry, charge pumps, voltage sources or generators, current or voltage references, any portion of the aforementioned functional circuitry (e.g., sub-circuits), or one or more of any active or passive components of the circuitry (e.g., transistors, diodes, resistors, or capacitors). The peripheral circuitry in the first semiconductor structure 102 and the second semiconductor structure 104 may be implemented using CMOS technology, for example, using logic processes at any suitable technology node.

[0069] like Figure 1A As shown, according to some embodiments, the first semiconductor structure 102 and the second semiconductor structure 104 are stacked on top of each other in different planes. As a result, compared to a memory device in which all peripheral circuits are disposed in the same plane, the memory cell array in the first semiconductor structure 102, the peripheral circuits in the first semiconductor structure 102, and the peripheral circuits in the second semiconductor structure 104 can be stacked on top of each other in different planes to reduce the planar size of the 3D memory device 100.

[0070] like Figure 1A As shown, the 3D memory device 100 further includes a bonding interface 103 perpendicularly between the first semiconductor structure 102 and the second semiconductor structure 104. The bonding interface 103 can be an interface between two semiconductor structures formed by any suitable bonding technique described in detail below, such as hybrid bonding, anodic bonding, fused bonding, transfer bonding, binder bonding, eutectic bonding, to name just a few.

[0071] It should be understood that the relative positions of the stacked first semiconductor structure 102 and the stacked second semiconductor structure 104 are not limited and can vary in different examples. Figure 1B A schematic cross-sectional view of another exemplary 3D memory device 101 according to some embodiments is shown. Figure 1A The 3D memory device 100 differs from the others, wherein the memory cell array in the first semiconductor structure is vertically positioned between the peripheral circuitry in the first semiconductor structure 102 and the peripheral circuitry in the second semiconductor structure 104. Figure 1B In the 3D memory device 101, the peripheral circuitry in the first semiconductor structure 102 is perpendicularly positioned between the memory cell array in the first semiconductor structure 102 and the peripheral circuitry in the second semiconductor structure. That is, the second semiconductor structure 102 can be bonded to the first semiconductor structure 102 on either side, for example, in… Figure 1A In the 3D memory device 100, on one side where a memory cell array is formed, or in Figure 1B In the 3D memory device 101, a peripheral circuit is formed on one side. As a result, unlike the 3D memory device 100 in which a bonding interface 103 is formed perpendicularly between the memory cell arrays of the second semiconductor structure 104 and the first semiconductor structure 102, a bonding interface 105 is formed perpendicularly between the peripheral circuits of the second semiconductor structure 104 and the first semiconductor structure 102. Similar to the bonding interface 103, the bonding interface 105 can be an interface between two semiconductor structures formed by any suitable bonding technique described in detail below, such as hybrid bonding, anodic bonding, fused bonding, transfer bonding, adhesive bonding, eutectic bonding, to name just a few.

[0072] As described in detail below, in some embodiments, the first semiconductor structure 102 and the second semiconductor structure 104 can be fabricated separately (and in some embodiments in parallel) via parallel processes, such that the thermal budget for fabricating one of the first semiconductor structure 102 and the second semiconductor structure 104 does not limit the process for fabricating the other. Furthermore, a large number of interconnects (e.g., bonding contacts and / or ILV / TSVs) can be formed across bonding interfaces 103 or 105 to provide direct, short-distance (e.g., micrometer or submicrometer) electrical connections between semiconductor structures 102 and 104, as opposed to long-distance (e.g., millimeter or centimeter) chip-to-chip data buses on a circuit board (e.g., a printed circuit board (PCB)), thereby eliminating chip interface latency and achieving high-speed I / O throughput with reduced power consumption. Data transfer between memory cell arrays and different peripheral circuits in the different semiconductor structures 102 and 104 can be performed via interconnects (e.g., bonding contacts and / or ILV / TSVs) across bonding interfaces 103 or 105 and through the polysilicon layer 106. By vertically integrating the first semiconductor structure 102 and the second semiconductor structure 104, and by vertically separating the memory cell array and peripheral circuitry into different planes in the first semiconductor structure 102, the chip size can be reduced and the memory cell density can be increased.

[0073] Figure 2A schematic circuit diagram of a memory device 200 including peripheral circuitry according to some aspects of this disclosure is shown. The memory device 200 may include a memory cell array 201 and peripheral circuitry 202 coupled to the memory cell array 201. 3D memory devices 100 and 101 may be examples of memory devices 200 in which at least two portions of the memory cell array 201 and peripheral circuitry 202 may be included in different stacked semiconductor structures 102 and 104. The memory cell array 201 may be a NAND flash memory cell array, wherein memory cells 206 are provided in the form of an array of NAND memory strings 208, each NAND memory string extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 208 includes a plurality of memory cells 206 coupled in series and stacked vertically. Each memory cell 206 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of the memory cell 206. Each memory cell 206 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0074] In some implementations, each memory cell 206 is a single-level cell (SLC) having two possible memory states and thus capable of storing one bit of data. For example, a first memory state "0" may correspond to a first voltage range, and a second memory state "1" may correspond to a second voltage range. In some implementations, each memory cell 206 is a multi-level cell (MLC) capable of storing more than a single data bit in more than four memory states. For example, an MLC may store two bits per cell, three bits per cell (also known as a three-level cell (TLC)), or four bits per cell (also known as a four-level cell (QLC)). Each MLC can be programmed to take a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed to take one of three possible programming levels from the erase state by writing one of the three possible nominal storage values ​​to the cell. A fourth nominal storage value can be used in the erase state.

[0075] like Figure 2As shown, each NAND memory string 208 may include a source-select-gate (SSG) transistor 210 at its source end and a drain-select-gate (DSG) transistor 212 at its drain end. The SSG transistor 210 and DSG transistor 212 may be configured to activate the selected NAND memory string 208 (column of the array) during read and program operations. In some embodiments, the SSG transistors 210 of the NAND memory strings 208 in the same block 204 are coupled to ground via the same source line (SL) 214 (e.g., a common SL). According to some embodiments, the DSG transistor 212 of each NAND memory string 208 is coupled to a corresponding bit line 216 from which data can be read or programmed via an output bus (not shown). In some implementations, each NAND memory string 208 is configured to be selected or unselected by applying a selection voltage (e.g., higher than the threshold voltage of DSG transistor 212) or a non-selection voltage (e.g., 0V) to the corresponding DSG transistor 212 via one or more DSG lines 213 and / or by applying a selection voltage (e.g., higher than the threshold voltage of SSG transistor 210) or a non-selection voltage (e.g., 0V) to the corresponding SSG transistor 210 via one or more SSG lines 215.

[0076] like Figure 2 As shown, NAND memory strings 208 can be organized into multiple blocks 204, each of which may have a common source line 214. In some embodiments, each block 204 is a basic data unit for erase operations, i.e., all memory cells 206 on the same block 204 are erased simultaneously. Memory cells 206 of adjacent NAND memory strings 208 can be coupled via word lines 218, which select which row of memory cells 206 is affected by read and program operations. In some embodiments, each word line 218 is coupled to a page 220 of memory cells 206, which is a basic data unit for program and read operations. The bit size of a page 220 may correspond to the number of NAND memory strings 208 coupled by word lines 218 in a block 204. Each word line 218 may include multiple control gates (gate electrodes) at each memory cell 206 in the corresponding page 220 and gate lines coupling the control gates.

[0077] Figure 8 A side view of a NAND memory string 208 in a 3D memory device according to some aspects of this disclosure is shown. Figure 8 As shown, the NAND memory string 208 can extend vertically through the memory stack layer 804 on the polysilicon layer 805. The polysilicon layer 805 can be... Figure 1A and 1BAn example of polysilicon layer 106 is shown. The memory stack layer 804 may include interleaved gate conductive layers 806 and dielectric layers 808. The number of pairs of gate conductive layers 806 and dielectric layers 808 in the memory stack layer 804 determines the number of memory cells 206 in the memory cell array 201. The gate conductive layer 806 may include a conductive material, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicides, or any combination thereof. In some embodiments, each gate conductive layer 806 includes a metal layer, such as a tungsten layer. In some embodiments, each gate conductive layer 806 includes a doped polysilicon layer. Each gate conductive layer 806 may include a control gate surrounding a memory cell, a gate of a DSG transistor 212 or a gate of an SSG transistor 210, and may extend laterally as a DSG line 213 at the top of the memory stack 804, an SSG line 215 at the bottom of the memory stack 804, or a word line 218 between the DSG line 213 and the SSG line 215.

[0078] like Figure 8 As shown, the NAND memory string 208 includes a channel structure 812 extending vertically through a memory stack layer 804. In some embodiments, the channel structure 812 includes channel holes filled with one or more semiconductor materials (e.g., as a semiconductor channel 820) and one or more dielectric materials (e.g., as a memory film 818). In some embodiments, the semiconductor channel 820 includes silicon, such as polysilicon. In some embodiments, the memory film 818 is a composite dielectric layer including a tunneling layer 826, a storage layer 824 (also referred to as a "charge trap / storage layer"), and a barrier layer 822. The channel structure 812 may have a cylindrical shape (e.g., columnar). According to some embodiments, the semiconductor channel 820, tunneling layer 826, storage layer 824, and barrier layer 822 are arranged radially from the center of the column toward the outer surface in this order. The tunneling layer 826 may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer 824 may include silicon nitride, silicon oxynitride, silicon, or any combination thereof. The barrier layer 822 may comprise silicon oxide, silicon oxynitride, a high-k dielectric, or any combination thereof. In one example, the memory film 818 may comprise a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO). The channel structure 812 may also include a channel plug 816 on the drain terminal of the NAND memory string 208. The channel plug 816 may comprise polysilicon and contact the semiconductor channel 820.

[0079] In some embodiments, the polysilicon layer 805 contacts the semiconductor channel 820 of the channel structure 812 at the source end of the NAND memory string 208. A portion of the memory film 818 of the channel structure 812 at the source end can be removed to expose the semiconductor channel 820, thereby contacting the polysilicon layer 805. In some embodiments, the portion of the semiconductor channel 820 at the source end of the NAND memory string 208 is doped to form a doped region 832 in contact with the polysilicon layer 805. It should be understood that in some examples, the polysilicon layer 805 can be doped with the same dopant as the doped region 832, and the dopant can diffuse to portions of the semiconductor channel 820 to form the doped region 832. In some embodiments, the polysilicon layer 805 comprises N-type doped polysilicon to enable GILD erase operations.

[0080] like Figure 8 As shown, according to some embodiments, the slot structure 828 does not include any conductors (e.g., source contacts) and therefore is not used as part of the source line 214. Instead, source contacts (not shown) may be formed on the opposite side of the polysilicon layer 805 relative to the channel structure 812, such that the source contacts and portions of the polysilicon layer 805 can be used as portions of the source line 214 coupled to the source of the NAND memory string 208, for example, for applying an erase voltage to the source of the NAND memory string 208 during an erase operation.

[0081] Return to reference Figure 2 The peripheral circuitry 202 can be coupled to the memory cell array 201 via bit line 216, word line 218, source line 214, SSG line 215, and DSG line 213. As described above, the peripheral circuitry 202 can include any suitable circuitry for facilitating the operation of the memory cell array 201 by applying and sensing voltage and / or current signals traveling to and from each target memory cell 206 via bit line 216 through word line 218, source line 214, SSG line 215, and DSG line 213. The peripheral circuitry 202 can include various types of peripheral circuitry formed using MOS technology. For example, Figure 3 Some exemplary peripheral circuitry 202 is shown, including a page buffer 304, a column decoder / bit line driver 306, a row decoder / word line driver 308, a voltage generator 310, control logic 312, a register 314, an interface (I / F) 316, and a data bus 318. It should be understood that additional peripheral circuitry 202 may also be included in some examples.

[0082] Page buffer 304 can be configured to buffer data read from or programmed into memory cell array 201 according to control signals of control logic 312. In one example, page buffer 304 may store a page of programming data (write data) to be programmed into a page 220 of memory cell array 201. In another example, page buffer 304 also performs a programming verification operation to ensure that data has been correctly programmed into memory cell 206 coupled to selected word line 218.

[0083] The row decoder / word line driver 308 can be configured to be controlled by control logic 312 and to select block 204 of memory cell array 201 and word line 218 of the selected block 204. The row decoder / word line driver 308 can be further configured to drive memory cell array 201. For example, the row decoder / word line driver 308 can use a word line voltage generated from voltage generator 310 to drive memory cell 206 coupled to the selected word line 218.

[0084] The column decoder / bit line driver 306 can be configured to be controlled by control logic 312 and to select one or more 3D NAND memory strings 208 by applying a bit line voltage generated from voltage generator 310. For example, the column decoder / bit line driver 306 can apply a column signal to select from page buffer 304 a set of N data bits to be output in a read operation.

[0085] Control logic 312 can be coupled to each peripheral circuit 202 and configured to control the operation of the peripheral circuit 202. Register 314 can be coupled to control logic 312 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit 202.

[0086] Interface 316 may be coupled to control logic 312 and configured to interface memory cell array 201 with a memory controller (not shown). In some embodiments, interface 316 acts as a control buffer to buffer and relay control commands received from the memory controller and / or host (not shown) to control logic 312, and to buffer and relay status information received from control logic 312 to the memory controller and / or host. Interface 316 may also be coupled to page buffer 304 and column decoder / bit line driver 306 via data bus 318, and acts as an I / O interface and data buffer to buffer and relay programming data received from the memory controller and / or host to page buffer 304, and to buffer and relay read data from page buffer 304 to the memory controller and / or host. In some embodiments, interface 316 and data bus 318 are part of the I / O circuitry of peripheral circuitry 202.

[0087] Voltage generator 310 can be configured to be controlled by control logic 312 and generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, and check voltage) and bit line voltages to be supplied to memory cell array 201. In some embodiments, voltage generator 310 is part of a voltage source that provides various voltage levels for different peripheral circuits 202, as described in detail below. Consistent with the scope of this disclosure, in some embodiments, the voltages supplied by voltage generator 310 to (e.g.) row decoder / word line driver 308, column decoder / bit line driver 306, and page buffer 304 are higher than certain levels sufficient to perform memory operations. For example, the voltage supplied to the page buffer circuitry in page buffer 304 and / or the logic circuitry in control logic 312 may be between 2V and 3.3V, for example, 3.3V, and the voltage supplied to the drive circuitry in row decoder / word line driver 308 and / or column decoder / bit line driver 306 may be between 5V and 30V.

[0088] Unlike logic devices (e.g., microprocessors), memory devices (e.g., 3D NAND flash memory) require a wide range of voltages to be supplied to various peripheral memory circuits. For example, Figure 4A Block diagrams of peripheral circuitry provided with various voltages according to some aspects of this disclosure are shown. In some embodiments, the memory device (e.g., memory device 200) includes a low-low voltage (LLV) source 401, a low voltage (LV) source 403, and a high voltage (HV) source 405, each configured to provide a voltage at a corresponding level (Vdd1, Vdd2, or Vdd3). For example, Vdd3 > Vdd2 > Vdd1. Each voltage source 401, 403, or 405 can receive a voltage input at an appropriate level from an external power source (e.g., a battery). Each voltage source 401, 403, or 405 may also include a voltage converter and / or voltage regulator to convert the external voltage input to the corresponding level (Vdd1, Vdd2, or Vdd3) and maintain the voltage at the corresponding level (Vdd1, Vdd2, or Vdd3) and output a voltage through the corresponding power rail. In some embodiments, a voltage generator 310 of the memory device 200 is part of the voltage sources 401, 403, and 405.

[0089] In some implementations, the LLV source 401 is configured to provide a voltage below 2V, for example, between 0.9V and 2V (e.g., 0.9V, 0.95V, 1V, 1.05V, 1.1V, 1.15V, 1.2V, 1.25V, 1.3V, 1.35V, 1.4V, 1.45V, 1.5V, 1.55V, 1.6V, 1.65V, 1.7V, 1.75V, 1.8V, 1.85V, 1.9V, 1.95V, any range defined by any one of these values ​​as a lower limit, or any range defined by any two of these values). In one example, the voltage is 1.2V. In some implementations, the LV source 403 is configured to provide a voltage between 2V and 3.3V (e.g., 2V, 2.1V, 2.2V, 2.3V, 2.4V, 2.5V, 2.6V, 2.7V, 2.8V, 2.9V, 3V, 3.1V, 3.2V, 3.3V, any range defined by any one of these values ​​as a lower limit, or any range defined by any two of these values). In one example, the voltage is 3.3V. In some implementations, HV source 405 is configured to provide a voltage greater than 3.3V, for example, between 5V and 30V (e.g., 5V, 6V, 7V, 8V, 9V, 10V, 11V, 12V, 13V, 14V, 15V, 16V, 17V, 18V, 19V, 20V, 21V, 22V, 23V, 24V, 25V, 26V, 27V, 28V, 29V, 30V, any range defined by any one of these values ​​as a lower limit, or any range defined by any two of these values). It should be understood that the voltage ranges described above with respect to HV source 405, LV source 403, and LLV source 401 are for illustrative purposes and not limiting, and that HV source 405, LV source 403, and LLV source 401 can provide any other suitable voltage range.

[0090] Based on the appropriate voltage levels (Vdd1, Vdd2, or Vdd3) of the memory peripheral circuitry (e.g., peripheral circuitry 202), it can be classified as LLV circuitry 402, LV circuitry 404, and HV circuitry 406, which can be coupled to LLV source 401, LV source 403, and HV source 405, respectively. In some embodiments, HV circuitry 406 includes one or more drive circuits coupled to the memory cell array (e.g., memory cell array 201) via word lines, bit lines, SSG lines, DSG lines, source lines, etc., and is configured to drive the memory cell array by applying voltages at appropriate levels to the word lines, bit lines, SSG lines, DSG lines, source lines, etc., when performing memory operations (e.g., read, program, or erase). In one example, HV circuit 406 may include word line drive circuitry coupled to the word line and applying a programming voltage (Vprog) or a pass voltage (Vpass) in the range of, for example, 5V to 30V to the word line during programming operations (e.g., in row decoder / word line driver 308). In another example, HV circuit 406 may include bit line drive circuitry coupled to the bit line and applying an erase voltage (Veras) in the range of, for example, 5V to 30V to the bit line during erase operations (e.g., in column decoder / bit line driver 306). In some embodiments, LV circuitry 404 includes page buffer circuitry (e.g., in a latch of page buffer 304) and is configured to buffer data read from or programmed into the memory cell array. For example, a voltage of, for example, 3.3V may be provided to the page buffer by LV source 403. LV circuitry 404 may also include logic circuitry (e.g., in control logic 312). In some implementations, the LLV circuit 402 includes I / O circuitry configured to interface the memory cell array with a memory controller (e.g., in interface 316 and / or data bus 318). For example, a voltage of, for instance, 1.2V may be supplied to the I / O circuitry from the LLV source 401.

[0091] As described above, in order to reduce the total area occupied by the memory peripheral circuitry, the peripheral circuitry 202 can be formed in different planes based on different performance requirements (e.g., the applied voltage). For example, Figure 4BA schematic diagram of peripheral circuits provided with various voltages in separate semiconductor structures, arranged according to some aspects of this disclosure, is shown. In some embodiments, the LLV circuit 402 and HV circuit 406 are separated, for example, in semiconductor structures 408 and 410, respectively, due to the significant difference in voltage between them and the resulting differences in device dimensions, such as different substrate thicknesses and different gate dielectric thicknesses. In one example, the thickness of the semiconductor layer (e.g., substrate or thinned substrate) in which the HV circuit 406 is formed in semiconductor structure 410 may be greater than the thickness of the semiconductor layer (e.g., substrate or thinned substrate) in which the LLV circuit 402 is formed in semiconductor structure 408. In another example, the thickness of the gate dielectric of the transistor forming the HV circuit 406 may be greater than the thickness of the gate dielectric of the transistor forming the LLV circuit 402. For example, the thickness difference may be at least 5 times. It is understood that stacked LLV circuit 402 and HV circuit 406 in different planes can be formed at a bonding interface (e.g., in...) Figure 1A and 1B In the two separate semiconductor structures 408 or 410 (in the middle).

[0092] The LV circuit 404 can be formed in semiconductor structures 408 or 410, or in another semiconductor, that is, in the same plane as the LLV circuit 402 or HV circuit 406, or in a different plane from the LLV circuit 402 and HV circuit 406. Figure 4BAs shown, in some embodiments, some of the LV circuits 404 are formed in semiconductor structure 408, i.e., in the same plane as the LLV circuit 402, while some of the LV circuits 404 are formed in semiconductor structure 410, i.e., in the same plane as the HV circuit 406. That is, the LV circuits 404 can also be separated into different planes. For example, when the same voltage is applied to the LV circuits 404 in different semiconductor structures 408 and 410, the thickness of the gate dielectric of the transistor forming the LV circuit 404 in semiconductor structure 408 can be the same as the thickness of the gate dielectric of the transistor forming the LV circuit 404 in semiconductor structure 410. In some embodiments, the same voltage is applied to the LV circuits 404 in semiconductor structure 408 and 410 such that the voltage applied to the HV circuit 406 in semiconductor structure 410 is higher than the voltage applied to the LV circuits 404 in semiconductor structures 408 or 410, which in turn is higher than the voltage applied to the LLV circuit 402 in semiconductor structure 408. Furthermore, according to some embodiments, since the voltage applied to the LV circuit 404 is between the voltages applied to the HV circuit 406 and the LLV circuit 402, the thickness of the gate dielectric of the transistor forming the LV circuit 404 is between the thickness of the gate dielectric of the transistor forming the HV circuit 406 and the thickness of the gate dielectric of the transistor forming the LLV circuit 402. For example, the thickness of the gate dielectric of the transistor forming the LV circuit 404 can be greater than the thickness of the gate dielectric of the transistor forming the LLV circuit 402, but less than the thickness of the gate dielectric of the transistor forming the HV circuit 406.

[0093] Based on different performance requirements (e.g., associated with different applied voltages), the peripheral circuitry 202 can be divided into at least two stacked semiconductor structures 408 and 410 in different planes. In some embodiments, the I / O circuitry in the interface 316 and / or data bus 318 (as LLV circuitry 402) and the logic circuitry in the control logic 312 (as part of the LV circuitry) are disposed in semiconductor structure 408, while the page buffer circuitry in page buffer 304 and the drive circuitry in row decoder / word line driver 308 and column decoder / bit line driver 306 are disposed in semiconductor structure 410. For example, Figure 7 A circuit diagram of a word line driver 308 and a page buffer 304 according to some aspects of this disclosure is shown.

[0094] In some embodiments, page buffer 304 includes a plurality of page buffer circuits 702, each coupled to a NAND memory string 208 via a corresponding bit line 216. That is, memory device 200 may include bit lines 216 coupled to the NAND memory string 208, and page buffer 304 may include page buffer circuits 702 coupled to both bit lines 216 and the NAND memory string 208. Each page buffer circuit 702 may include one or more latches, switches, power supplies, nodes (e.g., data nodes and I / O nodes), current mirrors, verification logic, sensing circuitry, etc. In some embodiments, each page buffer circuit 702 is configured to store sense data corresponding to read data received from the corresponding bit line 216 and output the stored sense data during a read operation; each page buffer circuit 702 is also configured to store programming data and output the stored programming data to the corresponding bit line 216 during a programming operation.

[0095] In some embodiments, word line driver 308 includes a plurality of string drivers 704 (also referred to as drive circuitry) respectively coupled to word line 218. Word line driver 308 may also include a plurality of local word lines 706 (LWLs) respectively coupled to string drivers 704. Each string driver 704 may include a gate coupled to a decoder (not shown), a source / drain coupled to the corresponding local word line 706, and another source / drain coupled to the corresponding word line 218. In some memory operations, the decoder may select certain string drivers 704, for example, by applying a voltage signal greater than a threshold voltage of the string drivers 704 and applying a voltage (e.g., programming voltage, pass voltage, or erase voltage) to each local word line 706, such that a voltage is applied to the corresponding word line 218 by each selected string driver 704. Conversely, the decoder may also not select certain string drivers 704, for example, by applying a voltage signal less than a threshold voltage of the string drivers 704, such that each unselected string driver 704 floats the corresponding word line 218 during memory operations.

[0096] In some embodiments, the page buffer circuit 702 includes a portion of the LV circuit 404 disposed within the semiconductor structures 408 and / or 410. In one example, since the number of page buffer circuits 702 increases with the number of bits, which can occupy a large area for memory devices with a large number of memory cells, the page buffer circuit 702 may be semiconductor structures 408 and 410. In some embodiments, the string driver 704 includes a portion of the HV circuit 406 disposed within the semiconductor structure 410.

[0097] Consistent with the scope of this disclosure, each peripheral circuit 202 may include multiple transistors as its basic building blocks. The transistors may be 2D (also known as planar transistors) or 3D (3D transistors) metal-oxide-semiconductor field-effect transistors (MOSFETs). For example, Figure 5A and 5B Perspective and side views of a planar transistor 500 according to some aspects of this disclosure are shown respectively. Figure 6A and 6B Perspective and side views of a 3D transistor 600 according to some aspects of this disclosure are shown respectively. Figure 5B It shows Figure 5A A side view of the cross-section of the planar transistor 500 in the BB plane. Figure 6B It shows Figure 6A A side view of the 3D transistor 600 in the BB plane cross-section.

[0098] like Figure 5A and 5B As shown, the planar transistor 500 may be a MOSFET on a substrate 502, which may include silicon (e.g., single-crystal silicon, c-Si), silicon-germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable semiconductor material. Trench isolation 503, such as shallow trench isolation (STI), may be formed in the substrate 502 and between adjacent planar transistors 500 to reduce current leakage. Trench isolation 503 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric (e.g., aluminum oxide, hafnium oxide, zirconium oxide, etc.). In some embodiments, the high-k dielectric material includes any dielectric material having a dielectric constant or k value higher than that of silicon nitride (k>7). In some embodiments, trench isolation 503 includes silicon oxide.

[0099] like Figure 5A and 5B As shown, the planar transistor 500 may further include a gate structure 508 on the substrate 502. In some embodiments, the gate structure 508 is on the top surface of the substrate 502. Figure 5BAs shown, the gate structure 508 may include a gate dielectric 507 on and in contact with the top surface of the substrate 502. The gate structure 508 may also include a gate electrode 509 on and in contact with the gate dielectric 507. The gate dielectric 507 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. In some embodiments, the gate dielectric 507 includes silicon oxide, i.e., a gate oxide. The gate electrode 509 may include any suitable conductive material, such as polysilicon, a metal (e.g., W, Cu, Al, etc.), a metal compound (e.g., TiN, TaN, etc.), or a silicide. In some embodiments, the gate electrode 509 includes doped polysilicon, i.e., gate polysilicon.

[0100] like Figure 5A As shown, the planar transistor 500 may further include a pair of source and drain electrodes 506 in the substrate 502. The source and drain electrodes 506 may be doped with any suitable P-type dopant, such as boron (B) or gallium (Ga), or any suitable N-type dopant, such as phosphorus (P) or arsenic (As). In the planar view, the source and drain electrodes 506 may be separated by a gate structure 508. That is, according to some embodiments, in the planar view, the gate structure 508 is formed between the source and drain electrodes 506. When the gate voltage applied to the gate electrode 509 of the gate structure 508 is higher than the threshold voltage of the planar transistor 500, a channel of the planar transistor 500 in the substrate 502 may be laterally formed between the source and drain electrodes 506 under the gate structure 508. Figure 5A and 5B As shown, the gate structure 508 can be above and contact the top surface of the portion (active region) of the substrate 502 in which a channel can be formed. That is, according to some embodiments, the gate structure 508 contacts only one side of the active region, i.e., in the plane of the top surface of the substrate 502. It should be understood that, although Figure 5A and 5B The planar transistor 500 may include additional components such as wells and spacers, though not shown in the diagram.

[0101] like Figure 6A and 6BAs shown, the 3D transistor 600 may be a MOSFET on a substrate 602, which may include silicon (e.g., monocrystalline silicon, c-Si), SiGe, GaAs, Ge, silicon-on-insulator (SOI), or any other suitable material. In some embodiments, the substrate 602 comprises monocrystalline silicon. Trench isolation 603, such as STI, may be formed in the substrate 602 and between adjacent 3D transistors 600 to reduce current leakage. The trench isolation 603 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric (e.g., aluminum oxide, hafnium oxide, zirconium oxide, etc.). In some embodiments, the trench isolation 603 comprises silicon oxide.

[0102] like Figure 6A and 6B As shown, unlike the planar transistor 500, the 3D transistor 600 may also include a 3D semiconductor body 604 above the substrate 602. That is, in some embodiments, the 3D semiconductor body 604 extends at least partially above the top surface of the substrate 602 to expose not only the top surface of the 3D semiconductor body 604 but also both side surfaces. Figure 6A and 6B As shown, for example, the 3D semiconductor body 604 can be a 3D structure, also referred to as a "fin," to expose its three sides. According to some embodiments, the 3D semiconductor body 604 is formed from a substrate 602 and therefore has the same semiconductor material as the substrate 602. In some embodiments, the 3D semiconductor body 604 comprises monocrystalline silicon. Since a channel can be formed in the 3D semiconductor body 604 opposite to the substrate 602, the 3D semiconductor body 604 can be considered as the active region of the 3D transistor 600.

[0103] like Figure 6A and 6B As shown, the 3D transistor 600 may further include a gate structure 608 on the substrate 602. Unlike the planar transistor 500, where the gate structure 508 contacts only one side of the active region, i.e., in a plane on the top surface of the substrate 502, the gate structure 608 of the 3D transistor 600 can contact multiple sides of the active region, i.e., in multiple planes on the top surface and sides of the 3D semiconductor body 604. That is, the active region of the 3D transistor 600, i.e., the 3D semiconductor body 604, can be at least partially surrounded by the gate structure 608.

[0104] The gate structure 608 may include a gate dielectric 607 over the 3D semiconductor body 604, for example, contacting the top surface and two sides of the 3D semiconductor body 604. The gate structure 608 may also include a gate electrode 609 over and in contact with the gate dielectric 607. The gate dielectric 607 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. In some embodiments, the gate dielectric 607 includes silicon oxide, i.e., a gate oxide. The gate electrode 609 may include any suitable conductive material, such as polysilicon, a metal (e.g., W, Cu, Al, etc.), a metal compound (e.g., TiN, TaN, etc.), or a silicide. In some embodiments, the gate electrode 609 includes doped polysilicon, i.e., gate polysilicon.

[0105] like Figure 6A As shown, the 3D transistor 600 may further include a pair of source and drain electrodes 606 within the 3D semiconductor body 604. The source and drain electrodes 606 may be doped with any suitable P-type dopant, such as B or Ga, or any suitable N-type dopant, such as P or Ar. In a planar view, the source and drain electrodes 606 may be separated by a gate structure 608. That is, according to some embodiments, in a planar view, the gate structure 608 is formed between the source and drain electrodes 606. As a result, when the gate voltage applied to the gate electrode 609 of the gate structure 608 is higher than the threshold voltage of the 3D transistor 600, multiple channels of the 3D transistor 600 can be formed laterally between the source and drain electrodes 606 surrounded by the gate structure 608. Unlike the planar transistor 500, in which only a single channel can be formed on the top surface of the substrate 502, multiple channels can be formed on the top surface and sides of the 3D semiconductor body 604 in the 3D transistor 600. In some implementations, the 3D transistor 600 includes a multi-gate transistor. It should be understood that, although in Figure 6A and 6B Not shown, but the 3D transistor 600 may include additional components such as wells, spacers, and stress sources (also called strain elements) at the source and drain 606.

[0106] It should also be understood that Figure 6A and 6B An example of a 3D transistor that can be used in memory peripheral circuitry is shown, and any other suitable 3D multi-gate transistor can also be used in memory peripheral circuitry, including, for example, full-ring gate (GAA) silicon-free (SON) transistors, multi-gate independent FETs (MIGET), tri-gate FETs, ΠE gate FETs and ΩΩT gate FETs, quad-gate FETs, cylindrical FETs or multi-bridge / stacked nanowire FETs.

[0107] Whether it's a planar transistor 500 or a 3D transistor 600, each transistor in the memory peripheral circuit can include a transistor with a thickness T (gate dielectric thickness, for example, ...). Figure 5B and 6B The gate dielectric (e.g., gate dielectrics 507 and 607) shown in the diagram. The gate dielectric thickness T of the transistor can be designed to adapt to the voltage applied to the transistor. For example, refer back to the reference. Figure 4A and 4B The gate dielectric thickness of the transistors in the HV circuit 406 (e.g., a drive circuit such as the string driver 704) can be greater than the gate dielectric thickness of the transistors in the LV circuit 404 (e.g., the page buffer circuit 702 or the logic circuit in control logic 312), which in turn can be greater than the gate dielectric thickness of the transistors in the LLV circuit 402 (e.g., the I / O circuits in interface 316 and data bus 318). In some embodiments, the difference between the gate dielectric thickness of the transistors in the HV circuit 406 and the dielectric thickness of the transistors in the LLV circuit 402 is at least 5 times, for example, between 5 and 50 times. For example, the gate dielectric thickness of the transistors in the HV circuit 406 can be at least 5 times greater than the gate dielectric thickness of the transistors in the LLV circuit 402.

[0108] In some implementations, the dielectric thickness of the transistors in the LLV circuit 402 is between 2 nm and 4 nm (e.g., 2 nm, 2.1 nm, 2.2 nm, 2.3 nm, 2.4 nm, 2.5 nm, 2.6 nm, 2.7 nm, 2.8 nm, 2.9 nm, 3 nm, 3.1 nm, 3.2 nm, 3.3 nm, 3.4 nm, 3.5 nm, 3.6 nm, 3.7 nm, 3.8 nm, 3.9 nm, 4 nm, any range defined by any one of these values ​​as a lower limit, or any range defined by any two of these values). It should be understood that this thickness may correspond to the range of LLV voltages applied to the LLV circuit 402, such as below 2 V (e.g., 1.2 V), as described in detail above. In some implementations, the dielectric thickness of the transistor in the LV circuit 404 is between 4 nm and 10 nm (e.g., 4 nm, 4.5 nm, 5 nm, 5.5 nm, 6 nm, 6.5 nm, 7 nm, 7.5 nm, 8 nm, 8.5 nm, 9 nm, 9.5 nm, 10 nm, any range defined by any one of these values ​​as a lower limit, or any range defined by any two of these values). It should be understood that this thickness may correspond to the range of LV voltages applied to the LV circuit 404, such as between 2 V and 3.3 V (e.g., 3.3 V), as described in detail above. In some embodiments, the dielectric thickness of the transistor in HV circuit 406 is between 20 nm and 100 nm (e.g., 20 nm, 21 nm, 22 nm, 23 nm, 24 nm, 25 nm, 26 nm, 27 nm, 28 nm, 29 nm, 30 nm, 31 nm, 32 nm, 33 nm, 34 nm, 35 nm, 36 nm, 37 nm, 38 nm, 39 nm, 40 nm, 45 nm, 50 nm, 55 nm, 60 nm, 65 nm, 70 nm, 75 nm, 80 nm, 85 nm, 90 nm, 95 nm, 100 nm, any range defined by any one of these values ​​as a lower limit, or any range defined by any two of these values). It should be understood that this thickness may be comparable to the range of HV voltages applied to HV circuit 406, as described in detail above, for example, greater than 3.3 V (e.g., between 5 V and 30 V).

[0109] Figure 9A and 9B A schematic cross-sectional view of 3D memory devices 900 and 901 having two stacked semiconductor structures according to various aspects of this disclosure is shown. 3D memory devices 900 and 901 can be... Figure 1AAn example of a 3D memory device 100 is provided, wherein the memory array cells of the first semiconductor structure 102 are vertically disposed between the peripheral circuits of the first semiconductor structure 102 and the peripheral circuits of the second semiconductor structure 104. That is, the two separate portions of the peripheral circuits can be disposed on opposite sides of the 3D memory device 900 or 901 in the vertical direction, respectively. For example... Figure 9A and 9B As shown, according to some embodiments, a second semiconductor structure 104, including some of the peripheral circuitry, is bonded to a first semiconductor structure 102 on one side having a memory cell array to form a bonding interface 103 between the second semiconductor structure 104 and the memory cell array of the first semiconductor structure 102.

[0110] In addition, such as Figure 9A and 9B As shown, the 3D memory device 900 or 901 may further include a pad-out interconnect layer 902 for pad-out destinations, i.e., for interconnecting with external devices using contact pads on which bonding wires can be soldered. Figure 9A In one example shown, a second semiconductor structure 104, including some of the peripheral circuitry on one side of the 3D memory device 900, may include a pad-out interconnect layer 902. Figure 9B In another example shown, the first semiconductor structure 102, including some of the memory cell array and peripheral circuitry on the other side of the 3D memory device 901, may include a pad-out interconnect layer 902, allowing the 3D memory device 901 to be led out from the pads on the other peripheral circuitry side. In either example, the 3D memory device 900 or 901 may be led out from the peripheral circuitry side pads to reduce the interconnect distance between the contact pads and the peripheral circuitry, thereby reducing parasitic capacitance from the interconnect and improving the electrical performance of the 3D memory device 900 or 901.

[0111] Figure 10 Some aspects of this disclosure are shown. Figure 9A and 9B A schematic diagram of a cross-section of the 3D memory device 1000. Figure 9A and 9B Examples of 3D memory devices 900 and 901. (See example...) Figure 10 As shown, the 3D memory device 1000 may include a stacked first semiconductor structure 102 and a second semiconductor structure 104. In some embodiments, the first semiconductor structure 102 includes a semiconductor layer 1002, a polysilicon layer 106, a bonding layer 1008, a memory cell array vertically disposed between the polysilicon layer 106 and the bonding layer 1008, and some of peripheral circuitry vertically disposed between the semiconductor layer 1002 and the polysilicon layer 106.

[0112] The memory cell array may include an array of NAND memory strings (e.g., NAND memory string 208 disclosed herein), and the source of the array of NAND memory strings may be in contact with the polysilicon layer 106 (e.g., as shown in the image). Figure 8 (As shown in the diagram). The polysilicon layer 106 may be a deposited polysilicon layer (e.g., N-type doped, P-type doped, or undoped), suitable for channel structures in "floating gate" type NAND memory strings or, for example, "charge trap" type NAND memory strings suitable for GIDL erase operations (e.g., as shown in the diagram). Figure 8 Certain designs of the channel structure 812 in the middle. The bonding layer 1008 may include a dielectric of conductive bonding contacts (not shown) and electrically isolating bonding contacts, which can be used for hybrid bonding, for example, as described in detail below.

[0113] In some embodiments, peripheral circuitry in the first semiconductor structure 102 contacts the semiconductor layer 1002 but not the polysilicon layer 106. That is, transistors of the peripheral circuitry (e.g., planar transistors 500 and 3D transistors 600) may contact the semiconductor layer 1004. The semiconductor layer 1002 may comprise a semiconductor material, such as monocrystalline silicon (e.g., a silicon substrate or a thinned silicon substrate). It should be understood that in some examples, unlike the polysilicon layer 106 in the first semiconductor structure 102, the semiconductor layer 1002 on which transistors are formed may comprise monocrystalline silicon, but not polycrystalline silicon, due to the superior carrier mobility of monocrystalline silicon desired for transistor performance. Through-contacts (e.g., ILV / TSV) through the polysilicon layer 106 may form direct, short-distance (e.g., submicron or micron-scale) electrical connections between the memory cell array in the first semiconductor structure 102 and the peripheral circuitry.

[0114] In some embodiments, the second semiconductor structure 104 includes a semiconductor layer 1004, a bonding layer 1010, and some of the peripheral circuitry of a memory cell array vertically positioned between the semiconductor layer 1004 and the bonding layer 1010. Transistors of the peripheral circuitry (e.g., planar transistors 500 and 3D transistors 600) may contact the semiconductor layer 1004. Similar to semiconductor layer 1002, semiconductor layer 1004 may include a semiconductor material, such as monocrystalline silicon (e.g., a silicon substrate or a thinned silicon substrate). It should be understood that in some examples, unlike the polycrystalline silicon layer 106 in the first semiconductor structure 102, the semiconductor layer 1004 on which transistors are formed may include monocrystalline silicon, rather than polycrystalline silicon, due to the superior carrier mobility of monocrystalline silicon desired for transistor performance.

[0115] Similar to the bonding layer 1008 in the first semiconductor structure 102, the bonding layer 1010 may further include a dielectric material for conductive bonding contacts (not shown) and electrically isolating bonding contacts. According to some embodiments, a bonding interface 103 is perpendicularly positioned between and in contact with the bonding layers 1008 and 1010, respectively. That is, the bonding layers 1008 and 1010 can be disposed on opposite sides of the bonding interface 103, and the bonding contacts of the bonding layer 1008 can contact the bonding contacts of the bonding layer 1010 at the bonding interface 103. As a result, unlike through-contacts (e.g., ILV / TSV), a large number (e.g., millions) of bonding contacts spanning the bonding interface 103 can provide direct, short-distance (e.g., micrometer-scale) electrical connections between adjacent semiconductor structures 102 and 104.

[0116] like Figure 10 As shown, according to some embodiments, since the first semiconductor structure 102 and the second semiconductor structure 104 are bonded face-to-face (e.g., in...), Figure 10 In this configuration, semiconductor layer 1002 is disposed on the bottom side of the first semiconductor structure 102, while semiconductor layer 1004 is disposed on the top side of the second semiconductor structure 104. Therefore, the transistors of the peripheral circuits in the first semiconductor structure 102 and the second semiconductor structure 104 are disposed facing each other. Furthermore, within the first semiconductor structure 102, since polysilicon layer 106 is perpendicularly positioned between the memory cell array and the peripheral circuits, and the memory cell array and the peripheral circuits are formed on polysilicon layer 106 and semiconductor layer 1002 respectively, the memory cell array and the peripheral circuits face the same direction (e.g., in...). Figure 10 (in the positive y-direction). It should be understood that, for ease of explanation, Figure 9A and 9B The pads in the 902 interconnect layer are brought out from the pads. Figure 10 The 3D memory device 1000 is omitted in the above description and may be included in the above description. Figure 9A and 9B In the 3D memory device 1000.

[0117] As described above, the first semiconductor structure 102 and the second semiconductor structure 104 may have peripheral circuitry, which includes transistors to which different voltages are applied. For example, the second semiconductor structure 104 may include... Figure 4B An example of semiconductor structure 408 for LLV circuit 402 (and LV circuit 404 in some examples), and the first semiconductor structure 102 may include Figure 4BAn example of semiconductor structure 410 for HV circuit 406 (and LV circuit 404 in some examples), and vice versa. Therefore, in some embodiments, semiconductor layers 1002 and 1004 in the first semiconductor structure 102 and the second semiconductor structure 104 have different thicknesses to accommodate transistors to which different voltages are applied. In one example, the first semiconductor structure 102 may include HV circuit 406, and the second semiconductor structure 104 may include LLV circuit 402, and the thickness of semiconductor layer 1002 in the first semiconductor structure 102 may be greater than the thickness of semiconductor layer 1004 in the second semiconductor structure 104. Furthermore, in some embodiments, the gate dielectrics of the transistors in the first semiconductor structure 102 and the second semiconductor structure 104 also have different thicknesses to accommodate the different applied voltages. In one example, the first semiconductor structure 102 may include HV circuit 406, and the second semiconductor structure 104 may include LLV circuit 402, and the thickness of the gate dielectric of the transistor in the first semiconductor structure 102 may be greater than (e.g., at least 5 times) the thickness of the gate dielectric of the transistor in the second semiconductor structure 104. Compared to the transistor in the second semiconductor structure 104, the thicker gate dielectric can withstand the higher operating voltage applied to the transistor in the first semiconductor structure 102, thus avoiding breakdown during high-voltage operation.

[0118] Figure 11A and 11B The various aspects of this disclosure are shown. Figure 10 Side views of various examples of the 3D memory device 1000. (See also:) Figure 11A As shown, as Figure 10 In one example of a 3D memory device 1000, according to some embodiments, the 3D memory device 1100 is included in the vertical direction (e.g., Figure 11A A bonded chip of a first semiconductor structure 102 and a second semiconductor structure 104 stacked on top of each other in different planes (in the y-direction). According to some embodiments, the first semiconductor structure 102 and the second semiconductor structure 104 are bonded at a bonding interface 103 therebetween.

[0119] like Figure 11AAs shown, the first semiconductor structure 102 may include a semiconductor layer 1002 having a semiconductor material. In some embodiments, the semiconductor layer 1002 is a silicon substrate having monocrystalline silicon. The first semiconductor structure 102 may also include a device layer 1102 above and in contact with the semiconductor layer 1002. In some embodiments, the device layer 1102 includes a first peripheral circuit 1104 and a second peripheral circuit 1106. The first peripheral circuit 1104 may include an HV circuit 406, such as a driving circuit (e.g., a serial driver 704 in a row decoder / word line driver 308 and a driver in a column decoder / bit line driver 306), and the second peripheral circuit 1106 may include an LV circuit 404, such as a page buffer circuit (e.g., a page buffer circuit 702 in a page buffer 304) and logic circuitry (e.g., in control logic 312). In some embodiments, the first peripheral circuit 1104 includes a plurality of transistors 1108 in contact with the semiconductor layer 1002, and the second peripheral circuit 1106 includes a plurality of transistors 1110 in contact with the semiconductor layer 1002. Transistors 1108 and 1110 may include any transistor disclosed herein, such as planar transistor 500 and 3D transistor 600. As described in detail above with respect to transistors 500 and 600, in some embodiments, each transistor 1108 or 1110 includes a gate dielectric, and because the voltage applied to transistor 1108 is higher than the voltage applied to transistor 1110, the thickness of the gate dielectric of transistor 1108 (e.g., in HV circuit 406) is greater than the thickness of the gate dielectric of transistor 1110 (e.g., in LV circuit 404). Trench isolation (e.g., STI) and doped regions (e.g., the well, source, and drain of transistors 1108 and 1110) may also be formed on or therein in semiconductor layer 1002.

[0120] In some embodiments, the first semiconductor structure 102 further includes an interconnect layer 1112 above the device layer 1102 for transmitting electrical signals to peripheral circuits 1106 and 1104. For example... Figure 11AAs shown, interconnect layer 1112 may be vertically positioned between polysilicon layer 106 and device layer 1102 (including transistors 1108 and 1110 of peripheral circuits 1104 and 1106). Interconnect layer 1112 may include multiple interconnects (also referred to herein as “contacts”), including lateral lines and vias. As used herein, the term “interconnect” may broadly include any suitable type of interconnect, such as mid-process (MEOL) interconnects and back-end process (BEOL) interconnects. Interconnects in interconnect layer 1112 may be coupled to transistors 1108 and 1110 of peripheral circuits 1104 and 1106 in device layer 1102. Interconnect layer 1112 may also include one or more interlayer dielectric (ILD) layers (also referred to as “intermetallic dielectric (IMD) layers”) in which lateral lines and vias may be formed. That is, interconnect layer 1112 may include lateral lines and vias in multiple ILD layers. In some embodiments, devices in device layer 1102 are coupled to each other via interconnects in interconnect layer 1112. For example, peripheral circuit 1104 can be coupled to peripheral circuit 1106 via interconnect layer 1112. Interconnects in interconnect layer 1112 may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. The ILD layer in interconnect layer 1112 may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low dielectric constant (low k) dielectrics, or any combination thereof. In some embodiments, interconnects in interconnect layer 1112 include W, which has a relatively high thermal budget (compatible with high-temperature processes) and good quality (fewer defects, such as voids) among conductive metallic materials.

[0121] like Figure 11A As shown, the first semiconductor structure may further include a polysilicon layer 106 above and in contact with the interconnect layer 1112. According to some embodiments, the polysilicon layer 106 is a doped polysilicon layer on the interconnect layer 1112, as described in detail below with respect to the manufacturing process. It should be understood that in some examples, trench isolation and doped regions (not shown) may also be formed in the polysilicon layer 106.

[0122] like Figure 11A As shown, the first semiconductor structure 102 may further include an array of memory cells, such as an array of NAND memory strings 208 above and in contact with the polysilicon layer 106. The sources of the NAND memory strings 208 may be in contact with the polysilicon layer 106. In some embodiments, the polysilicon layer 106 is perpendicularly positioned between the NAND memory strings 208 and the device layer 1102, which includes transistors 1108 and 1110. In some embodiments, each NAND memory string 208 is a "charge-trapping" type NAND memory string, which includes any suitable channel structure disclosed herein, such as those described above. Figure 8The channel structure 812 is described in detail. In some embodiments, the NAND memory string 208 is a "floating gate" type NAND memory string, and the polysilicon layer 106 is the source plate of the floating gate type NAND memory string.

[0123] According to some implementations, each NAND memory string 208 extends vertically through multiple pairs of layers, each comprising a conductive layer and a dielectric layer. The stacked and interleaved conductive and dielectric layers are also referred to herein as a stacked layer structure, for example, memory stack 1127. Memory stack 1127 may be... Figure 8 Examples of memory stack layer 804 include conductive layers and dielectric layers in memory stack layer 1127, which may be examples of gate conductive layer 806 and dielectric layer 808 in memory stack layer 804, respectively. According to some embodiments, the staggered conductive and dielectric layers in memory stack layer 1127 alternate in the vertical direction. Each conductive layer may include a gate electrode (gate line) surrounded by an adhesive layer and a gate dielectric layer. The gate electrode of the conductive layer may extend laterally as a word line, terminating at one or more stepped structures in memory stack layer 1127.

[0124] like Figure 11A As shown, the first semiconductor structure 102 may further include an interconnect layer 1128 above and in contact with the NAND memory string 208, for transmitting electrical signals to and from the NAND memory string 208. In some embodiments, the memory stack layer 1127 and the NAND memory string 208 are perpendicularly positioned between the interconnect layer 1128 and the polysilicon layer 106. The interconnect layer 1128 may include multiple interconnects, such as MEOL interconnects and BEOL interconnects. In some embodiments, the interconnects in the interconnect layer 1128 may also include local interconnects, such as bit line contacts and word line contacts. The interconnect layer 1128 may also include one or more ILD layers in which lateral lines and vias may be formed. The interconnects in the interconnect layer 1128 may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. The ILD layers in the interconnect layer 1128 may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0125] like Figure 11AAs shown, the first semiconductor structure 102 may further include one or more contacts 1124 extending vertically through the polysilicon layer 106. In some embodiments, the contacts 1124 couple interconnects in the interconnect layer 1128 to interconnects in the interconnect layer 1112 to provide electrical connection between the NAND memory string 208 and transistors 1108 and 1110 through the polysilicon layer 106. The contacts 1124 may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. In some embodiments, the contacts 1124 include W. In some embodiments, the contacts 1124 include vias surrounded by dielectric spacers (e.g., having silicon oxide) to electrically isolate the vias from the polysilicon layer 106. Depending on the thickness of the polysilicon layer 106, the contact 1124 can be an ILV with a depth (in the vertical direction) in the submicron range (e.g., between 10 nm and 1 μm), or a TSV with a depth (in the vertical direction) in the micron range or tens of micron range (e.g., between 1 μm and 100 μm).

[0126] like Figure 11A As shown, the first semiconductor structure 102 may further include a bonding layer 1008 at the bonding interface 103, located above and in contact with the interconnect layer 1128. The bonding layer 1008 may include a dielectric material comprising a plurality of bonding contacts and electrically isolating bonding contacts. The bonding contacts may comprise conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. In some embodiments, the bonding contacts of the bonding layer 1008 comprise Cu. The remaining region of the bonding layer 1008 may be formed of a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. The bonding contacts in the bonding layer 1008 and the surrounding dielectric material can be used for hybrid bonding (also known as “metal / dielectric hybrid bonding”), a direct bonding technique (e.g., forming a bond between surfaces without using an intermediate layer, such as solder or adhesive), and can simultaneously achieve metal-to-metal (e.g., Cu-Cu) bonding and dielectric-to-dielectric (e.g., SiO2-SiO2) bonding.

[0127] like Figure 11AAs shown, the second semiconductor structure 104 can be bonded face-to-face to the top of the first semiconductor structure 102 at the bonding interface 103. The second semiconductor structure 104 may also include a bonding layer 1010 at the bonding interface 103, for example, on the opposite side of the bonding interface 103 relative to the bonding layer 1008 in the first semiconductor structure 102. The bonding layer 1010 may include a dielectric material of a plurality of bonding contacts and electrically isolating bonding contacts. The bonding contacts may include a conductive material, such as Cu. The remaining region of the bonding layer 1010 may be formed of a dielectric material such as silicon oxide. The bonding contacts in the bonding layer 1010 and the surrounding dielectric material may be used for hybrid bonding. In some embodiments, the bonding interface 103 is the location where the bonding layers 1008 and 1010 meet and bond. In fact, the bonding interface 103 can be a layer with a specific thickness, including the top surface of the bonding layer 1008 of the first semiconductor structure 102 and the bottom surface of the bonding layer 1010 of the second semiconductor structure 104.

[0128] like Figure 11A As shown, the second semiconductor structure 104 may further include an interconnect layer 1126 above the bonding layer 1010 for transmitting electrical signals. The interconnect layer 1126 may include multiple interconnects, such as MEOL interconnects and BEOL interconnects. The interconnect layer 1126 may also include one or more ILD layers, in which lateral lines and vias may be formed. The interconnects in the interconnect layer 1126 may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. The ILD layers in the interconnect layer 1126 may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. In some embodiments, the interconnects in the interconnect layer 1126 include Cu, which has a relatively low resistivity (better electrical performance) among conductive metal materials. As described below regarding the manufacturing process, although Cu has a relatively low thermal budget (incompatible with high-temperature processes), interconnects with Cu interconnect layers 1126 can become feasible because the fabrication of interconnect layer 1126 can be performed after the high-temperature process of forming device layer 1114 in second semiconductor structure 104, and separately from the high-temperature process of forming first semiconductor structure 102.

[0129] like Figure 11AAs shown, the second semiconductor structure 104 may include a device layer 1114 above and in contact with the interconnect layer 1126. In some embodiments, the interconnect layer 1126 is perpendicular between the bonding interface 103 and the device layer 1114. In some embodiments, the device layer 1114 includes a third peripheral circuit 1116 and a fourth peripheral circuit 1118. The third peripheral circuit 1116 may include an LLV circuit 402, such as I / O circuitry (e.g., in interface 316 and data bus 318), and the fourth peripheral circuit 1118 may include an LV circuit 404, such as a page buffer circuit (e.g., page buffer circuit 702 in page buffer 304) and logic circuitry (e.g., in control logic 312). In some embodiments, the third peripheral circuit 1116 includes a plurality of transistors 1120, and the fourth peripheral circuit 1118 also includes a plurality of transistors 1122. Transistors 1120 and 1122 may include any transistors disclosed herein, such as planar transistor 500 and 3D transistor 600. As described in detail above with respect to transistors 500 and 600, in some embodiments, each transistor 1120 or 1122 includes a gate dielectric, and because the voltage applied to transistor 1120 is lower than the voltage applied to transistor 1122, the thickness of the gate dielectric of transistor 1120 (e.g., in LLV circuit 402) is less than the thickness of the gate dielectric of transistor 1122 (e.g., in LV circuit 404).

[0130] Furthermore, different voltages applied to the different transistors 1120, 1122, 1108, and 1110 in the second semiconductor structure 104 and the first semiconductor structure 102 can lead to differences in device dimensions between the second semiconductor structure 104 and the first semiconductor structure 102. In some embodiments, because the voltage applied to transistor 1108 is higher than the voltage applied to transistor 1120, the thickness of the gate dielectric of transistor 1108 (e.g., in HV circuit 406) is greater than the thickness of the gate dielectric of transistor 1120 (e.g., in LLV circuit 402). In some embodiments, because the voltages applied to transistors 1122 and 1110 are the same, the thickness of the gate dielectric of transistor 1122 (e.g., in LV circuit 404) is the same as the thickness of the gate dielectric of transistor 1110 (e.g., in LV circuit 404). In some embodiments, since the voltage applied to transistor 1108 is higher than the voltage applied to transistor 1120, the thickness of semiconductor layer 1002 in which transistor 1108 is formed (e.g., in HV circuit 406) is greater than the thickness of semiconductor layer 1004 in which transistor 1120 is formed (e.g., in LLV circuit 402).

[0131] like Figure 11AAs shown, the second semiconductor structure 104 may further include a semiconductor layer 1004 having a semiconductor material. In some embodiments, the semiconductor layer 1004 is a thinned silicon substrate having single-crystal silicon, on which transistors 1120 and 1122 may be formed. The semiconductor layer 1004 may be disposed above and in contact with transistors 1120 and 1122 of the peripheral circuits 1116 and 1118 in the device layer 1114. In some embodiments, transistors 1120 and 1122 are disposed vertically between the bonding interface 103 and the semiconductor layer 1004. Trench isolation (e.g., STI) and doped regions (e.g., the well, source, and drain of transistors 1120 and 1122) may also be formed on or in the semiconductor layer 1004.

[0132] like Figure 11A As shown, the second semiconductor structure 104 may further include a pad-out interconnect layer 902 above and in contact with the semiconductor layer 1004. In some embodiments, the semiconductor layer 1004 is vertically disposed between the pad-out interconnect layer 902 and transistors 1120 and 1122. The pad-out interconnect layer 902 may include interconnects in one or more ILD layers, for example, contact pads 1132. The pad-out interconnect layer 902 and interconnect layer 1126 may be formed on opposite sides of the semiconductor layer 1004. In some embodiments, for example, for pad-out purposes, the interconnects in the pad-out interconnect layer 902 may transmit electrical signals between the 3D memory 1100 and external devices.

[0133] like Figure 11A As shown, the second semiconductor structure 104 may further include one or more contacts 1130 extending vertically through the semiconductor layer 1004. In some embodiments, the contacts 1130 couple interconnects in the interconnect layer 1126 to contact pads 1132 in the interconnect layer 902 for electrical connection through the semiconductor layer 1004. The contacts 1130 may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. In some embodiments, the contacts 1130 include W. In some embodiments, the contacts 1130 include vias surrounded by dielectric spacers (e.g., having silicon oxide) to electrically isolate the vias from the semiconductor layer 1004. Depending on the thickness of the semiconductor layer 1004, the contacts 1130 may be ILVs with depths in the submicron range (e.g., between 10 nm and 10 μm) or TSVs with depths in the micron or tens of micron ranges (e.g., between 1 μm and 100 μm).

[0134] As a result, the peripheral circuits 1104, 1106, 1116, and 1118 in the first semiconductor structure 102 and the second semiconductor structure 104 can be coupled to the NAND memory string 208 in the first semiconductor structure 102 through various interconnect structures, including interconnect layers 1112, 1126, and 1128, bonding layers 1008 and 1010, and contact 1124. Furthermore, the peripheral circuits 1104, 1106, 1116, and 1118 in the 3D memory device 1100 and the NAND memory string 208 can be further coupled to external devices through contact 1130 and pads leading out from the interconnect layer 902.

[0135] It should also be understood that the pad leads of 3D memory devices are not limited to those from sources such as... Figure 11A The second semiconductor structure 104 of the peripheral circuit 1116 shown (corresponding to) Figure 9A ), and can come from a first semiconductor structure 102 having peripheral circuitry 1104 (corresponding to Figure 9B For example, such as Figure 11B As shown, the 3D memory device 1101 may include a pad-out interconnect layer 902 in a first semiconductor structure 102. The pad-out interconnect layer 902 may contact the semiconductor layer 1002 of the first semiconductor structure 102, on which transistors 1108 of peripheral circuitry 1104 are formed. In some embodiments, the first semiconductor structure 102 further includes one or more contacts 1134 extending vertically through the semiconductor layer 1002. In some embodiments, the contacts 1134 couple interconnects in the interconnect layer 1112 of the first semiconductor structure 102 to contact pads 1132 in the pad-out interconnect layer 902 for electrical connection through the semiconductor layer 1002. The contacts 1134 may include a conductive material, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. In some embodiments, the contacts 1134 include W. In some embodiments, the contacts 1134 include vias surrounded by dielectric spacers (e.g., having silicon oxide) to electrically isolate the vias from the semiconductor layer 1002. Depending on the thickness of the semiconductor layer 1002, the contact 1134 can be an ILV with a thickness in the submicron range (e.g., between 10 nm and 10 μm), or a TSV with a depth in the micron or tens of micron range (e.g., between 1 μm and 100 μm). It should be understood that, for ease of description, details of identical components (e.g., materials, manufacturing processes, functions, etc.) in both 3D memory devices 1100 and 1101 will not be repeated.

[0136] Figure 12A-12G This disclosure illustrates some aspects of the formation of Figure 10 The manufacturing process of 3D memory devices. Figure 13A and 13BThis disclosure illustrates some aspects of the formation of Figure 10 Another manufacturing process for 3D memory devices. Figure 14 This disclosure illustrates some aspects of the formation of Figure 10 The flowchart of the method 1400 for 3D memory devices. Figure 12A-12G Examples of 3D memory devices shown in 13A, 13B and 14 include Figure 11A and 11B The 3D memory devices 1100 and 1101 shown are described together. Figure 12A-12G 13A, 13B, and 14. It should be understood that the operations shown in method 1400 are not exhaustive, and other operations may be performed before, after, or between any of the operations shown. Furthermore, some operations may be performed simultaneously, or in conjunction with... Figure 14 The different execution orders shown.

[0137] refer to Figure 14 Method 1400 begins with operation 1402, wherein a first transistor is formed on a first substrate. The first substrate may be a silicon substrate having monocrystalline silicon. Figure 12A As shown, a plurality of transistors 1204 and 1206 are formed on a silicon substrate 1202. Transistors 1204 and 1206 can be formed by a variety of processes, including but not limited to photolithography, dry / wet etching, thin film deposition, thermal growth, implantation, chemical mechanical polishing (CMP), and any other suitable processes. In some embodiments, doped regions are formed in the silicon substrate 1202 by ion implantation and / or thermal diffusion, which serve, for example, as the well and source / drain regions of transistors 1204 and 1206. In some embodiments, isolation regions (e.g., STI) are also formed in the silicon substrate 1202 by wet / dry etching and thin film deposition. In some embodiments, the thickness of the gate dielectric of transistor 1204 differs from the thickness of the gate dielectric of transistor 1206, for example, by depositing a thicker silicon oxide film in a region of transistor 1204 than in a region of transistor 1206, or by etching back a portion of the silicon oxide film deposited in a region of transistor 1206. It should be understood that the details of fabricating transistors 1204 and 1206 may depend on the type of transistor (e.g., Figure 5A , 5B The variations are due to the planar transistor 500 or 3D transistor 600 in 6A and 6B, and therefore will not be elaborated further for the sake of description.

[0138] In some embodiments, an interconnect layer 1208 is formed over the transistors on the first substrate. The interconnect layer may include multiple interconnects within one or more ILD layers. Figure 12AAs shown, an interconnect layer 1208 can be formed over transistors 1204 and 1206. The interconnect layer 1208 may include MEOL and / or BEOL interconnects in a plurality of ILD layers for electrical connection to transistors 1204 and 1206. In some embodiments, the interconnect layer 1208 includes a plurality of ILD layers and interconnects formed therein using a plurality of processes. For example, the interconnects in the interconnect layer 1208 may include conductive materials deposited by one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof). The fabrication process forming the interconnects may also include photolithography, CMP, wet / dry etching, or any other suitable process. The ILD layers may include dielectric materials deposited by one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, or any combination thereof). Figure 12A The ILD layer and interconnects shown can be collectively referred to as interconnect layer 1208. In some embodiments, the interconnects in interconnect layer 1208 include W, which has a relatively high thermal budget in a conductive metallic material to withstand subsequent high-temperature processes.

[0139] Method 1400 proceeds to operation 1404, such as... Figure 14 As shown, a polysilicon layer is formed above the first transistor. Figure 12A As shown, a polysilicon layer 1211 is formed over the interconnect layer 1208 and transistors 1204 and 1206 on the first silicon substrate 1202. The polysilicon layer 1211 can be formed by depositing polysilicon on the interconnect layer 1208 using one or more thin-film deposition processes (including but not limited to CVD, PVD, ALD, or any combination thereof). In some embodiments, the polysilicon layer 1211 is doped with P-type or N-type dopant using an in-situ doping process during the deposition process or an ion implantation / diffusion process after the deposition process.

[0140] Method 1400 proceeds to operation 1406, such as... Figure 14 As shown, an array of NAND memory strings is formed on a polysilicon layer. In some embodiments, a memory stack layer is formed on the polysilicon layer to form the array of NAND memory strings. Figure 12CAs shown, a stacked layer structure, such as a memory stacked layer 1226 comprising staggered conductive and dielectric layers, is formed on a polysilicon layer 1211. To form the memory stacked layer 1226, in some embodiments, a dielectric stacked layer (not shown) comprising staggered sacrificial layers (not shown) and dielectric layers is formed on the polysilicon layer 1211. In some embodiments, each sacrificial layer comprises a silicon nitride layer, and each dielectric layer comprises a silicon oxide layer. The staggered sacrificial and dielectric layers can be formed by one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, or any combination thereof). The memory stacked layer 1226 can then be formed by a gate replacement process, for example, by replacing the sacrificial layers with conductive layers using a wet / dry etching process that selectively etches the dielectric layers, and filling the resulting trenches with conductive layers. In some embodiments, each conductive layer comprises a metal layer, such as a W layer. It should be understood that, in some examples, the memory stack 1226 can be formed by alternately depositing conductive layers (e.g., doped polysilicon layers) and dielectric layers (e.g., silicon oxide layers) without a gate replacement process. In some embodiments, a pad oxide layer comprising silicon oxide is formed between the memory stack 1226 and the polysilicon layer 1211.

[0141] like Figure 12C As shown, a NAND memory string 1228 is formed above a polysilicon layer 1211, with each string extending vertically through a memory stack layer 1226 to contact the polysilicon layer 1211. In some embodiments, the fabrication process for forming the NAND memory string 1228 includes forming channel vias through the memory stack layer 1226 (or dielectric stack layer) and into the polysilicon layer 1211 using dry etching and / or wet etching (e.g., deep reactive ion etching (DRIE)), followed by filling the channel vias with multiple layers (e.g., memory films (e.g., tunneling layers, storage layers, and barrier layers) and semiconductor layers) using thin-film deposition processes (e.g., ALD, CVD, PVD, or any combination thereof). It should be understood that the details of fabricating the NAND memory string 1228 can depend on the type of channel structure of the NAND memory string 1228 (e.g., Figure 8 The channel structure (812) varies, and therefore will not be elaborated further for ease of description.

[0142] In some implementations, an interconnect layer is formed above an array of NAND memory strings. The interconnect layer may include a plurality of interconnects within one or more ILD layers. Figure 12CAs shown, an interconnect layer 1230 is formed over the memory stack layer 1226 and the NAND memory string 1228. The interconnect layer 1230 may include interconnects of MEOL and / or BEOL in a plurality of ILD layers for electrical connection to the NAND memory string 1228. In some embodiments, the interconnect layer 1230 includes a plurality of ILD layers and interconnects formed therein using a plurality of processes. For example, the interconnects in the interconnect layer 1230 may include conductive materials deposited by one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof). The fabrication processes forming the interconnects may also include photolithography, CMP, wet / dry etching, or any other suitable process. The ILD layers may include dielectric materials deposited by one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, or any combination thereof). Figure 12D The ILD layer and interconnect shown can be collectively referred to as interconnect layer 1230.

[0143] In some implementations, contacts are formed through the polysilicon layer. For example... Figure 12C As shown, one or more contacts 1224 are formed, each extending vertically through the polysilicon layer 1211. The contacts 1224 can couple interconnects in interconnect layers 1230 and 1208. The contacts 1224 can be formed by first patterning contact holes through the polysilicon layer 1211 using a patterning process (e.g., photolithography and dry / wet etching of the dielectric material in the dielectric layer). The contact holes can be filled with a conductor (e.g., W or Cu). In some embodiments, filling the contact holes includes depositing a spacer (e.g., a silicon oxide layer) before depositing the conductor.

[0144] In some implementations, a first bonding layer is formed over the interconnect layer. The first bonding layer may include a plurality of first bonding contacts. For example... Figure 12C As shown, a bonding layer 1232 is formed over the interconnect layer 1230. The bonding layer 1232 may include a plurality of bonding contacts surrounded by a dielectric. In some embodiments, a dielectric layer is deposited on the top surface of the interconnect layer 1230 by one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, or any combination thereof). Then, by patterning contact holes through the dielectric layer first by using a patterning process (e.g., photolithography and dry / wet etching of the dielectric material in the dielectric layer), bonding contacts that penetrate the dielectric layer and contact the interconnects in the interconnect layer 1230 can be formed. The contact holes may be filled with a conductor (e.g., Cu). In some embodiments, filling the contact holes includes depositing an adhesive layer, a barrier layer, and / or a seed layer prior to depositing the conductor.

[0145] Method 1400 proceeds to operation 1408, such as... Figure 14As shown, a second transistor is formed on a second substrate. The second substrate can be a silicon substrate with monocrystalline silicon. Figure 12D As shown, a plurality of transistors 1214 and 1216 are formed on a silicon substrate 1210 having monocrystalline silicon. Transistors 1214 and 1216 can be formed by a variety of processes, including but not limited to photolithography, dry / wet etching, thin film deposition, thermal growth, implantation, CMP, and any other suitable process. In some embodiments, doped regions are formed in the silicon substrate 1210 by ion implantation and / or thermal diffusion, which serve as, for example, the well and source / drain regions of transistors 1214 and 1216. In some embodiments, isolation regions (e.g., STI) are also formed in the silicon substrate 1210 by wet / dry etching and thin film deposition. In some embodiments, the thickness of the gate dielectric of transistor 1214 differs from the thickness of the gate dielectric of transistor 1216, for example, by depositing a thicker silicon oxide film in the region of transistor 1214 than in the region of transistor 1216, or by etching back a portion of the silicon oxide film deposited in the region of transistor 1216. It should be understood that the details of fabricating transistors 1214 and 1216 may depend on the type of transistor (e.g., Figure 5A , 5B The variations (either the planar transistor 500 or the 3D transistor 600 in 6A and 6B) will not be elaborated upon for ease of description.

[0146] In some embodiments, an interconnect layer 1220 is formed over the transistors on the second substrate. The interconnect layer may include multiple interconnects within one or more ILD layers. Figure 12D As shown, an interconnect layer 1220 can be formed over transistors 1214 and 1216. The interconnect layer 1220 may include interconnects of MEOL and / or BEOL in multiple ILD layers for electrical connection to transistors 1214 and 1216. In some embodiments, the interconnect layer 1220 includes multiple ILD layers and interconnects formed therein using multiple processes. For example, the interconnects in the interconnect layer 1220 may include conductive materials deposited by one or more thin-film deposition processes (including but not limited to CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof). The fabrication process forming the interconnects may also include photolithography, CMP, wet / dry etching, or any other suitable process. The ILD layers may include dielectric materials deposited by one or more thin-film deposition processes (including but not limited to CVD, PVD, ALD, or any combination thereof). Figure 12CThe ILD layer and interconnects shown can be collectively referred to as interconnect layer 1220. Unlike interconnect layer 1208, in some embodiments, the interconnects in interconnect layer 1220 include Cu, which has a relatively low resistivity among conductive metal materials. It should be understood that although Cu has a relatively low thermal budget (incompatible with high-temperature processes), it becomes feasible to use Cu as the conductive material for the interconnects in interconnect layer 1220 because there are no longer high-temperature processes after the fabrication of interconnect layer 1220.

[0147] In some implementations, a second bonding layer is formed over the interconnect layer. The second bonding layer may include a plurality of second bonding contacts. For example... Figure 12D As shown, a bonding layer 1222 is formed over the interconnect layer 1220. The bonding layer 1222 may include a plurality of bonding contacts surrounded by a dielectric. In some embodiments, a dielectric layer is deposited on the top surface of the interconnect layer 1220 by one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, or any combination thereof). Then, by patterning contact holes through the dielectric layer first by using a patterning process (e.g., photolithography and dry / wet etching of the dielectric material in the dielectric layer), bonding contacts that penetrate the dielectric layer and contact the interconnects in the interconnect layer 1220 can be formed. The contact holes may be filled with a conductor (e.g., Cu). In some embodiments, filling the contact holes includes depositing an adhesive layer, a barrier layer, and / or a seed layer prior to depositing the conductor.

[0148] Method 1400 proceeds to operation 1410, such as... Figure 14 As shown, a first substrate and a second substrate are bonded face-to-face. After bonding the first and second substrates, a first bonding contact in the first bonding layer can contact a second bonding contact in the second bonding layer at the bonding interface. Bonding may include hybrid bonding.

[0149] like Figure 12E As shown, a silicon substrate 1210 and components formed thereon (e.g., transistors 1214 and 1216) are flipped upside down. A downward-facing bonding layer 1222 is bonded to an upward-facing bonding layer 1232, i.e., bonded face-to-face, thereby forming a bonding interface 1212. That is, the silicon substrate 1210 and components formed thereon can be bonded face-to-face to the silicon substrate 1202 and components formed thereon, such that the bonding contacts in the bonding layer 1232 contact the bonding contacts in the bonding layer 1222 at the bonding interface 1212. In some embodiments, a processing technique, such as plasma treatment, wet treatment, and / or heat treatment, is applied to the bonding surface prior to bonding. Although... Figure 12EAs not shown, but it should be understood that in some examples, the silicon substrate 1202 and the components formed thereon (e.g., transistors 1204, 1206, memory stack 1226, and NAND memory string 1228) can be flipped upside down, and the downside bonding layer 1232 can be bonded to the upside bonding layer 1222, i.e., bonded face to face, thereby also forming the bonding interface 1212.

[0150] As a result of bonding (e.g., hybrid bonding), the bonding contacts on opposite sides of bonding interface 1212 can be mixed with each other. After bonding, according to some embodiments, the bonding contacts in bonding layer 1232 and bonding layer 1222 are aligned and in contact with each other, such that the memory stack layer 1226 and NAND memory string 1228 formed therethrough, as well as transistors 1204 and 1206, can be coupled to transistors 1214 and 1216 through the bonding contacts bonded on bonding interface 1212.

[0151] like Figure 14 As shown, method 1400 proceeds to operation 1412, in which the first substrate or the second substrate is thinned. In some embodiments, such as Figure 12F As shown, silicon substrate 1210 ( Figure 12E The silicon substrate 1210 is thinned to form a semiconductor layer 1234 having monocrystalline silicon. The thinning can be achieved by processes including, but not limited to, wafer grinding, dry etching, wet etching, CMP, any other suitable process, or any combination thereof. In some embodiments, such as... Figure 13A As shown, silicon substrate 1202 ( Figure 12E The silicon substrate 1202 can be thinned to form a semiconductor layer 1302 having monocrystalline silicon (as shown in the diagram). Similarly, the silicon substrate 1202 can be thinned by processes including but not limited to wafer grinding, dry etching, wet etching, CMP, any other suitable process or any combination thereof.

[0152] like Figure 14 As shown, method 1400 proceeds to operation 1414, in which a pad-out interconnect layer is formed. The pad-out interconnect layer can be formed on a thinned second substrate or on a thinned first substrate.

[0153] In some implementations, such as Figure 12GAs shown, a pad-out interconnect layer 1236 is formed on semiconductor layer 1234 (thinned silicon substrate 1210). The pad-out interconnect layer 1236 may include interconnects formed in one or more ILD layers, such as contact pads 1238. Contact pads 1238 may include conductive materials, including but not limited to W, Co, Cu, Al, doped silicon, silicides, or any combination thereof. ILD layers may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. In some embodiments, after bonding and thinning, contacts 1235 extending vertically through semiconductor layer 1234 are formed, for example by wet / dry etching, followed by deposition of a dielectric material as spacers and a conductive material as conductors. Contacts 1235 can couple the contact pads 1238 in the pad-out interconnect layer 1236 to interconnects in interconnect layer 1220. It should be understood that in some examples, contacts 1235 may be thinned (e.g., Figure 12D As shown, the semiconductor layer 1234 is formed in the silicon substrate 1210 before thinning and is exposed from the back side of the silicon substrate 1210 (at the location where thinning occurs) after thinning.

[0154] In some implementations, such as Figure 13B As shown, a pad-out interconnect layer 1306 is formed on a semiconductor layer 1302 (a thinned silicon substrate 1202). The pad-out interconnect layer 1306 may include interconnects formed in one or more ILD layers, such as contact pads 1308. Contact pads 1308 may include conductive materials, including but not limited to W, Co, Cu, Al, doped silicon, silicides, or any combination thereof. The ILD layers may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. In some embodiments, after bonding and thinning, contacts 1304 extending vertically through the semiconductor layer 1302 are formed, for example by wet / dry etching, followed by deposition of a dielectric material as a spacer and a conductive material as a conductor. Contacts 1304 can couple the contact pads 1308 in the pad-out interconnect layer 1306 to the interconnects in the interconnect layer 1208. It should be understood that in some examples, the contact 1304 may be formed in the silicon substrate 1202 before thinning (forming the semiconductor layer 1234) and exposed from the back side of the silicon substrate 1202 (the location where thinning occurs) after thinning.

[0155] Figure 15A and 15B The various aspects of this disclosure are shown. Figure 9A and 9B A schematic diagram of a cross-section of the 3D memory devices shown. 3D memory devices 1500 and 1501 can be... Figure 9A and 9BExamples of 3D memory devices 900 and 901. (See example...) Figure 15A As shown, the 3D memory device 1500 may include a stacked first semiconductor structure 102 and a second semiconductor structure 104. In some embodiments, the first semiconductor structure 102 includes a semiconductor layer 1002, a polysilicon layer 106, a bonding layer 1008, a memory cell array vertically disposed between the polysilicon layer 106 and the bonding layer 1008, and some peripheral circuitry vertically disposed between the semiconductor layer 1002 and the polysilicon layer 106.

[0156] The memory cell array may include an array of NAND memory strings (e.g., NAND memory string 208 disclosed herein), and the source of the array of NAND memory strings may be in contact with the polysilicon layer 106 (e.g., as shown in the image). Figure 8 (As shown in the diagram). The polysilicon layer 106 may be a deposited polysilicon layer (e.g., N-type doped, P-type doped, or undoped), suitable for channel structures in "floating gate" type NAND memory strings or, for example, "charge trap" type NAND memory strings suitable for GIDL erase operations (e.g., as shown in the diagram). Figure 8 Certain designs of the channel structure 812 in the middle. The bonding layer 1008 may include a dielectric of conductive bonding contacts (not shown) and electrically isolating bonding contacts, which can be used for hybrid bonding, for example, as described in detail below.

[0157] In some embodiments, peripheral circuitry in the first semiconductor structure 102 contacts the semiconductor layer 1002 but not the polysilicon layer 106. That is, transistors of the peripheral circuitry (e.g., planar transistors 500 and 3D transistors 600) may contact the semiconductor layer 1002. The semiconductor layer 1002 may comprise a semiconductor material, such as monocrystalline silicon (e.g., a silicon substrate or a thinned silicon substrate). It should be understood that in some examples, unlike the polysilicon layer 106 in the first semiconductor structure 102, the semiconductor layer 1002 on which transistors are formed may comprise monocrystalline silicon, but not polycrystalline silicon, due to the superior carrier mobility of monocrystalline silicon desired for transistor performance. Through-contacts (e.g., ILV / TSV) through the polysilicon layer 106 may form direct, short-distance (e.g., submicron or micron-scale) electrical connections between the memory cell array in the first semiconductor structure 102 and the peripheral circuitry.

[0158] In some embodiments, the second semiconductor structure 104 includes a semiconductor layer 1004, a bonding layer 1010, and some of the peripheral circuitry of the memory cell array. The semiconductor layer 1004 may be perpendicularly positioned between the peripheral circuitry and the bonding layer 1010. Transistors of the peripheral circuitry (e.g., planar transistors 500 and 3D transistors 600) may contact the semiconductor layer 1004. Similar to semiconductor layer 1002, semiconductor layer 1004 may include a semiconductor material such as monocrystalline silicon (e.g., a silicon substrate or a thinned silicon substrate). It should be understood that in some examples, unlike the polycrystalline silicon layer 106 in the first semiconductor structure 102, the semiconductor layer 1004 on which transistors are formed may include monocrystalline silicon, rather than polycrystalline silicon, due to the superior carrier mobility of monocrystalline silicon desired for transistor performance. The peripheral circuitry and the bonding layer 1010 may be formed on opposite sides of the semiconductor layer 1004, such that the semiconductor layer 1004 is perpendicularly positioned between the peripheral circuitry and the bonding layer 1010. In some embodiments, transistors of the peripheral circuit are formed on the front side of the semiconductor layer 1004, and bonding contacts of the bonding layer 1010 are formed on the back side of the semiconductor layer 1004.

[0159] Similar to the bonding layer 1008 in the first semiconductor structure 102, the bonding layer 1010 may further include a dielectric material for conductive bonding contacts (not shown) and electrically isolating bonding contacts. According to some embodiments, a bonding interface 103 is perpendicularly positioned between and in contact with the bonding layers 1008 and 1010, respectively. That is, the bonding layers 1008 and 1010 can be disposed on opposite sides of the bonding interface 103, and the bonding contacts of the bonding layer 1008 can contact the bonding contacts of the bonding layer 1010 at the bonding interface 103. As a result, a large number (e.g., millions) of bonding contacts across the bonding interface 103, combined with through contacts (e.g., ILV / TSV) through the semiconductor layer 1004, enable direct, short-distance (e.g., micrometer-scale) electrical connections between adjacent semiconductor structures 102 and 104.

[0160] It should be understood that in some examples, the first semiconductor structure 102 and the second semiconductor structure 104 may not include bonding layers 1008 and 1010 respectively disposed on opposite sides of the bonding interface 103, such as... Figure 15A As shown. In Figure 15BIn the 3D memory device 1501, the semiconductor layer 1004 in the second semiconductor structure 104 can be a single-crystal silicon layer transferred from a silicon substrate or SOI substrate and attached to the top surface of the first semiconductor structure 102 by transfer bonding. Conversely, unlike hybrid bonding, the bonding interface 103 between the first semiconductor structure 102 and the second semiconductor structure 104 can be generated by transfer bonding. Through-contacts (e.g., ILV / TSV) perpendicularly passing through the semiconductor layer 1004 between the first semiconductor structure 102 and the second semiconductor structure 104 can provide direct, short-distance (e.g., submicron-level) electrical connections between adjacent semiconductor structures 102 and 104.

[0161] like Figure 15A and 15B As shown, according to some embodiments, since the first semiconductor structure 102 and the second semiconductor structure 104 are bonded in a face-to-back manner (e.g., in...), Figure 15A and 15B In this configuration, semiconductor layers 1002 and 1004 are respectively disposed on the bottom sides of the first semiconductor structure 102 and the second semiconductor structure 104. Therefore, the transistors of the peripheral circuits in the first semiconductor structure 102 and the second semiconductor structure 104 are configured to face the same direction (e.g., Figure 15A and 15B (in the positive y-direction). Furthermore, within the first semiconductor structure 102, since the polysilicon layer 106 is perpendicularly positioned between the memory cell array and the peripheral circuitry, and the memory cell array and peripheral circuitry are formed on the polysilicon layer 106 and the semiconductor layer 1002 respectively, the memory cell array and peripheral circuitry face the same direction (e.g., in...). Figure 15A and 15B (in the positive y-direction). It should be understood that, for ease of explanation, Figure 9A and Figure 9B The pads in the 902 interconnect layer are brought out from the pads. Figure 15A and Figure 15B The 3D memory devices 1500 and 1501 are omitted in the above description and may be included in the following: Figure 9A and Figure 9B In the 3D memory devices 1500 and 1501.

[0162] As described above, the first semiconductor structure 102 and the second semiconductor structure 104 can have peripheral circuits for transistors to which different voltages are applied. For example, the second semiconductor structure 104 may include... Figure 4B An example of semiconductor structure 408 for LLV circuit 402 (and LV circuit 404 in some examples), and the first semiconductor structure 102 may include Figure 4BAn example of semiconductor structure 410 for HV circuit 406 (and LV circuit 404 in some examples), and vice versa. Therefore, in some embodiments, semiconductor layers 1002 and 1004 in the first semiconductor structure 102 and the second semiconductor structure 104 have different thicknesses to accommodate transistors to which different voltages are applied. In one example, the first semiconductor structure 102 may include HV circuit 406, the second semiconductor structure 104 may include LLV circuit 402, and the thickness of semiconductor layer 1002 in the first semiconductor structure 102 may be greater than the thickness of semiconductor layer 1004 in the second semiconductor structure 104. Furthermore, in some embodiments, the gate dielectrics of the transistors in the first semiconductor structure 102 and the second semiconductor structure 104 also have different thicknesses to accommodate the different applied voltages. In one example, the first semiconductor structure 102 may include HV circuit 406, the second semiconductor structure 104 may include LLV circuit 402, and the thickness of the gate dielectric of the transistor in the first semiconductor structure 102 may be greater than (e.g., at least 5 times) the thickness of the gate dielectric of the transistor in the second semiconductor structure 104.

[0163] Figure 16A and 16B The various aspects of this disclosure are shown. Figure 15A and 15B Side views of various examples of 3D memory devices 1500 and 1501. Figure 16A As shown, as Figure 15A and 15B An example of 3D memory devices 1500 and 1501, according to some embodiments, 3D memory device 1600 is a bonded chip including a first semiconductor structure 102 and a second semiconductor structure 104, the first semiconductor structure and the second semiconductor structure being aligned in the vertical direction (e.g., Figure 16A The first semiconductor structure 102 and the second semiconductor structure 104 are stacked on different planes in the y-direction. According to some embodiments, the first semiconductor structure 102 and the second semiconductor structure 104 are bonded at the bonding interface 103 therebetween.

[0164] like Figure 16AAs shown, the first semiconductor structure 102 may include a semiconductor layer 1002 having a semiconductor material. In some embodiments, the semiconductor layer 1002 is a silicon substrate having monocrystalline silicon. The first semiconductor structure 102 may also include a device layer 1602 above and in contact with the semiconductor layer 1002. In some embodiments, the device layer 1602 includes a first peripheral circuit 1604 and a second peripheral circuit 1606. The first peripheral circuit 1604 may include an HV circuit 406, such as a driving circuit (e.g., a serial driver 704 in a row decoder / word line driver 308 and a driver in a column decoder / bit line driver 306), and the second peripheral circuit 1606 may include an LV circuit 404, such as a page buffer circuit (e.g., a page buffer circuit 702 in a page buffer 304) and logic circuitry (e.g., in control logic 312). In some embodiments, the first peripheral circuit 1604 includes a plurality of transistors 1608 in contact with the semiconductor layer 1002, and the second peripheral circuit 1606 includes a plurality of transistors 1610 in contact with the semiconductor layer 1002. Transistors 1608 and 1610 may include any transistor disclosed herein, such as planar transistor 500 and 3D transistor 600. As described in detail above with respect to transistors 500 and 600, in some embodiments, each transistor 1608 or 1610 includes a gate dielectric, and because the voltage applied to transistor 1608 is higher than the voltage applied to transistor 1610, the thickness of the gate dielectric of transistor 1608 (e.g., in HV circuit 406) is greater than the thickness of the gate dielectric of transistor 1610 (e.g., in LV circuit 404). Trench isolation (e.g., STI) and doped regions (e.g., the well, source, and drain of transistors 1608 and 1610) may also be formed on or therein in semiconductor layer 1002.

[0165] In some embodiments, the first semiconductor structure 102 further includes an interconnect layer 1612 above the device layer 1102 for transmitting electrical signals to peripheral circuits 1106 and 1104. For example... Figure 16AAs shown, interconnect layer 1612 may be perpendicularly positioned between polysilicon layer 106 and device layer 1602 (including transistors 1608 and 1610 of peripheral circuits 1604 and 1606). Interconnect layer 1612 may include multiple interconnects, such as MEOL interconnects and BEOL interconnects. Interconnects in interconnect layer 1612 may be coupled to transistors 1608 and 1610 of peripheral circuits 1604 and 1606 in device layer 1602. Interconnect layer 1612 may also include one or more ILD layers in which lateral lines and vias may be formed. That is, interconnect layer 1612 may include lateral lines and vias in multiple ILD layers. In some embodiments, devices in device layer 1602 are coupled to each other through interconnects in interconnect layer 1612. For example, peripheral circuit 1604 may be coupled to peripheral circuit 1606 through interconnect layer 1612. Interconnects in interconnect layer 1612 may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. The ILD layer in interconnect layer 1612 may include a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low dielectric constant (low k) dielectric, or any combination thereof. In some embodiments, the interconnects in interconnect layer 1612 include W, which has a relatively high thermal budget (compatible with high-temperature processes) and good quality (fewer defects, such as voids) in a conductive metallic material.

[0166] like Figure 16A As shown, the first semiconductor structure may further include a polysilicon layer 106 above and in contact with the interconnect layer 1612. According to some embodiments, the polysilicon layer 106 is a doped polysilicon layer on the interconnect layer 1612, as described in detail below with respect to the manufacturing process. It should be understood that in some examples, trench isolation and doped regions (not shown) may also be formed in the polysilicon layer 106.

[0167] like Figure 16A As shown, the first semiconductor structure 102 may further include an array of memory cells, such as an array of NAND memory strings 208 above and in contact with the polysilicon layer 106. The sources of the NAND memory strings 208 may be in contact with the polysilicon layer 106. In some embodiments, the polysilicon layer 106 is perpendicularly positioned between the NAND memory strings 208 and the device layer 1602, which includes transistors 1608 and 1610. In some embodiments, each NAND memory string 208 is a "charge-trapping" type NAND memory string, which includes any suitable channel structure disclosed herein, such as those described above. Figure 8 The channel structure 812 is described in detail. In some embodiments, the NAND memory string 208 is a "floating gate" type NAND memory string, and the polysilicon layer 106 is the source plate of the floating gate type NAND memory string.

[0168] According to some implementations, each NAND memory string 208 extends vertically through multiple pairs, each including a conductive layer and a dielectric layer. The stacked and interleaved conductive and dielectric layers are also referred to herein as a stacked layer structure, for example, memory stack 1627. Memory stack 1627 may be... Figure 8 Examples of memory stack layer 804 include the conductive layer and dielectric layer in memory stack layer 1627, which may be examples of gate conductive layer 806 and dielectric layer 808 in memory stack layer 804, respectively. According to some embodiments, the staggered conductive and dielectric layers in memory stack layer 1627 alternate in the vertical direction. Each conductive layer may include a gate electrode (gate line) surrounded by an adhesive layer and a gate dielectric layer. The gate electrode of the conductive layer may extend laterally as a word line, terminating at one or more stepped structures in memory stack layer 1627.

[0169] like Figure 16A As shown, the first semiconductor structure 102 may further include an interconnect layer 1628 above and in contact with the NAND memory string 208, for transmitting electrical signals to and from the NAND memory string 208. In some embodiments, the memory stack layer 1627 and the NAND memory string 208 are perpendicularly positioned between the interconnect layer 1628 and the polysilicon layer 106. The interconnect layer 1628 may include multiple interconnects, such as MEOL interconnects and BEOL interconnects. In some embodiments, the interconnects in the interconnect layer 1628 may also include local interconnects, such as bit line contacts and word line contacts. The interconnect layer 1628 may also include one or more ILD layers in which lateral lines and vias may be formed. The interconnects in the interconnect layer 1628 may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. The ILD layers in the interconnect layer 1628 may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0170] like Figure 16AAs shown, the first semiconductor structure 102 may further include one or more contacts 1624 extending vertically through the polysilicon layer 106. In some embodiments, the contacts 1624 couple interconnects in the interconnect layer 1628 to interconnects in the interconnect layer 1612 to provide electrical connection between the NAND memory string 208 and transistors 1608 and 1610 through the polysilicon layer 106. The contacts 1624 may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. In some embodiments, the contacts 1624 include W. In some embodiments, the contacts 1624 include vias surrounded by dielectric spacers (e.g., having silicon oxide) to electrically isolate the vias from the polysilicon layer 106. Depending on the thickness of the polysilicon layer 106, the contact 1624 can be an ILV with a depth (in the vertical direction) in the submicron range (e.g., between 10 nm and 10 μm), or a TSV with a depth (in the vertical direction) in the micron range or tens of micron range (e.g., between 1 μm and 100 μm).

[0171] like Figure 16A As shown, the first semiconductor structure 102 may further include a bonding layer 1008 at the bonding interface 103, located above and in contact with the interconnect layer 1628. The bonding layer 1008 may include a dielectric material comprising a plurality of bonding contacts and electrically isolating bonding contacts. The bonding contacts may comprise conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. In some embodiments, the bonding contacts of the bonding layer 1008 comprise Cu. The remaining region of the bonding layer 1008 may be formed of a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. The bonding contacts in the bonding layer 1008 and the surrounding dielectric material may be used for hybrid bonding (also known as “metal / dielectric hybrid bonding”), a direct bonding technique (e.g., forming a bond between surfaces without using an intermediate layer, such as solder or adhesive), and may simultaneously achieve metal-to-metal (e.g., Cu-Cu) bonding and dielectric-to-dielectric (e.g., SiO2-SiO2) bonding.

[0172] like Figure 16AAs shown, the second semiconductor structure 104 can be bonded to the top of the first semiconductor structure 102 at the bonding interface 103 in a back-to-back manner. The second semiconductor structure 104 may also include a bonding layer 1010 at the bonding interface 103, for example, on the opposite side of the bonding interface 103 relative to the bonding layer 1008 in the first semiconductor structure 102. The bonding layer 1010 may include a dielectric material of a plurality of bonding contacts and electrically isolating bonding contacts. The bonding contacts may include a conductive material, such as Cu. The remaining region of the bonding layer 1010 may be formed of a dielectric material such as silicon oxide. The bonding contacts in the bonding layer 1010 and the surrounding dielectric material may be used for hybrid bonding. In some embodiments, the bonding interface 103 is the location where the bonding layers 1008 and 1010 meet and bond. In fact, the bonding interface 103 can be a layer with a specific thickness, including the top surface of the bonding layer 1008 of the first semiconductor structure 102 and the bottom surface of the bonding layer 1010 of the second semiconductor structure 104.

[0173] like Figure 16AAs shown, the second semiconductor structure 104 may further include a semiconductor layer 1004 having a semiconductor material. A bonding layer 1010 may be formed on the back side of the semiconductor layer 1004 and vertically disposed between the semiconductor layer 1004 and the bonding interface 103. In some embodiments, the semiconductor layer 1004 is a thinned silicon substrate having single-crystal silicon. The second semiconductor structure 104 may further include a device layer 1614 above and in contact with the semiconductor layer 1004. In some embodiments, the device layer 1614 includes a third peripheral circuit 1616 and a fourth peripheral circuit 1618 above and in contact with the semiconductor layer 1004. In some embodiments, the semiconductor layer 1004 is vertically disposed between the bonding interface 103 and the device layer 1614 having the peripheral circuits 1616 and 1618. The third peripheral circuit 1616 may include an LLV circuit 402, such as I / O circuitry (e.g., in interface 316 and data bus 318), and the fourth peripheral circuit 1618 may include an LV circuit 404, such as a page buffer circuit (e.g., page buffer circuit 702 in page buffer 304) and logic circuitry (e.g., in control logic 312). In some embodiments, the third peripheral circuit 1616 includes a plurality of transistors 1620, and the fourth peripheral circuit 1618 also includes a plurality of transistors 1622. Transistors 1620 and 1622 may include any transistors disclosed herein, such as planar transistor 500 and 3D transistor 600. As described in detail above with respect to transistors 500 and 600, in some embodiments, each transistor 1620 or 1622 includes a gate dielectric, and because the voltage applied to transistor 1620 is lower than the voltage applied to transistor 1622, the thickness of the gate dielectric of transistor 1620 (e.g., in LLV circuit 402) is less than the thickness of the gate dielectric of transistor 1622 (e.g., in LV circuit 404).

[0174] Furthermore, different voltages applied to the different transistors 1620, 1622, 1608, and 1610 in the second semiconductor structure 104 and the first semiconductor structure 102 can lead to differences in device dimensions between the second semiconductor structure 104 and the first semiconductor structure 102. In some embodiments, because the voltage applied to transistor 1608 is higher than the voltage applied to transistor 1620, the thickness of the gate dielectric of transistor 1608 (e.g., in HV circuit 406) is greater than the thickness of the gate dielectric of transistor 1620 (e.g., in LLV circuit 402). In some embodiments, because the voltages applied to transistors 1622 and 1610 are the same, the thickness of the gate dielectric of transistor 1622 (e.g., in LV circuit 404) is the same as the thickness of the gate dielectric of transistor 1610 (e.g., in LV circuit 404). In some embodiments, since the voltage applied to transistor 1608 is higher than the voltage applied to transistor 1620, the thickness of semiconductor layer 1002 in which transistor 1608 is formed (e.g., in HV circuit 406) is greater than the thickness of semiconductor layer 1004 in which transistor 1620 is formed (e.g., in LLV circuit 402).

[0175] like Figure 16A As shown, the second semiconductor structure 104 may further include an interconnect layer 1626 that is above and in contact with device layer 1614, transmitting electrical signals from transistors 1620 and 1622 in peripheral circuits 1616 and 1618. Interconnect layer 1626 may include multiple interconnects, such as MEOL interconnects and BEOL interconnects. Interconnect layer 1626 may also include one or more ILD layers, in which lateral lines and vias may be formed. Interconnects in interconnect layer 1626 may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. ILD layers in interconnect layer 1626 may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. In some embodiments, interconnects in interconnect layer 1626 include Cu, which has a relatively low resistivity (better electrical performance) among conductive metal materials. As described below regarding the manufacturing process, although Cu has a relatively low thermal budget (incompatible with high-temperature processes), interconnects with Cu interconnect layers 1626 can become feasible because the fabrication of interconnect layer 1626 can be performed after the high-temperature process of forming device layer 1614 in second semiconductor structure 104, and separately from the high-temperature process of forming first semiconductor structure 102.

[0176] like Figure 16AAs shown, the second semiconductor structure 104 may further include one or more contacts 1630 extending vertically through the semiconductor layer 1004. In some embodiments, contacts 1630, in conjunction with bonding contacts spanning the bonding interface 103, couple interconnects in interconnect layer 1626 to interconnects in interconnect layer 1628 to provide electrical connections between NAND memory string 208 and transistors 1620 and 1622 through the semiconductor layer 1004. Contacts 1630 may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. In some embodiments, contacts 1630 include Cu. In some embodiments, contacts 1630 include vias surrounded by dielectric spacers (e.g., having silicon oxide) to electrically isolate the vias from the semiconductor layer 1004. Depending on the thickness of the semiconductor layer 1004, the contact 1630 can be an ILV with a depth in the submicron range (e.g., between 10 nm and 1 μm), or a TSV with a depth in the micron range or tens of micron range (e.g., between 1 μm and 100 μm).

[0177] like Figure 16A As shown, the second semiconductor structure 104 may further include an interconnect layer 1626 and a pad-out interconnect layer 902 above transistors 1620 and 1622. In some embodiments, transistors 1620 and 1622 are vertically disposed between the pad-out interconnect layer 902 and the semiconductor layer 1004. The pad-out interconnect layer 902 may include interconnects in one or more ILD layers, such as contact pads 1632. The pad-out interconnect layer 902 and the interconnect layer 1626 may be formed on the same side of the semiconductor layer 1004. In some embodiments, for example, for pad-out purposes, the interconnects in the pad-out interconnect layer 902 may transmit electrical signals between the 3D memory device 1600 and external devices.

[0178] As a result, the peripheral circuits 1604, 1606, 1616, and 1618 in the first semiconductor structure 102 and the second semiconductor structure 104 can be coupled to the NAND memory string 208 in the first semiconductor structure 102 through various interconnect structures, including interconnect layers 1612, 1626, and 1628, bonding layers 1008 and 1010, and contacts 1624 and 1630. Furthermore, the peripheral circuits 1604, 1606, 1616, and 1618 and the NAND memory string 208 in the 3D memory device 1600 can be further coupled to external devices through the contact 1630 and pads leading out from the interconnect layer 902.

[0179] It should be understood that the pad leads of 3D memory devices are not limited to those from sources such as... Figure 16A The second semiconductor structure 104 of the peripheral circuit 1616 shown (corresponding to) Figure 9A), and may originate from a first semiconductor structure 102 having peripheral circuitry 1604 (corresponding to Figure 9B For example, such as Figure 16B As shown, the 3D memory device 1601 may include a pad-out interconnect layer 902 in a first semiconductor structure 102. The pad-out interconnect layer 902 may contact the semiconductor layer 1002 of the first semiconductor structure 102, on which transistors 1608 of peripheral circuitry 1604 are formed. In some embodiments, the first semiconductor structure 102 further includes one or more contacts 1634 extending vertically through the semiconductor layer 1002. In some embodiments, the contacts 1634 couple interconnects in the interconnect layer 1612 of the first semiconductor structure 102 to contact pads 1632 in the pad-out interconnect layer 902 for electrical connection through the semiconductor layer 1002. The contacts 1634 may include a conductive material, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. In some embodiments, the contacts 1634 include W. In some embodiments, the contacts 1634 include vias surrounded by dielectric spacers (e.g., having silicon oxide) to electrically isolate the vias from the semiconductor layer 1002. Depending on the thickness of the semiconductor layer 1002, the contact 1634 can be an ILV with a thickness in the submicron range (e.g., between 10 nm and 1 μm) or a TSV with a depth in the micron range or tens of micron range (e.g., between 1 μm and 100 μm).

[0180] like Figure 16B As shown, the second semiconductor structure 104 may further include a passivation layer 1650, which replaces... Figure 16A The pads in the second semiconductor structure 104 lead out interconnect layer 902 to protect and encapsulate the 3D memory device 1601 from the side of the second semiconductor structure 104 without pads. Passivation layer 1650 may include a dielectric material, such as silicon nitride and / or silicon oxide. In some embodiments, the second semiconductor structure 104 in the 3D memory device 1601 also includes an operational / carrier substrate 1651 in contact with the passivation layer 1650, serving as a base substrate for support of the 3D memory device 1601. It should be understood that in some examples, passivation layer 1650 may be omitted or combined with operational substrate 1651 as a single layer for support and protection.

[0181] It should also be understood that in some examples, the first semiconductor structure 102 and the second semiconductor structure 104 of the 3D memory device 1601 may not include bonding layers 1008 and 1010, respectively, such as Figure 16BAs shown in the diagram. The bonding interface 103 may be produced by a transfer bonding process, and the semiconductor layer 1004 may be a single-crystal silicon layer transferred from a silicon substrate or SOI substrate and attached to the top surface of the first semiconductor structure 102 by transfer bonding, as described in detail below regarding the manufacturing process. In some embodiments, a dielectric layer (e.g., a silicon oxide layer) is formed perpendicularly between the bonding interface 103 and the semiconductor layer 1004 and / or between the bonding interface 105 and the interconnect layer 1628 to facilitate transfer bonding of the semiconductor layer 1004 to the interconnect layer 1628. Therefore, it should be understood that in some examples, the bonding interface 103 may include the surface of one or more dielectric layers. It should also be understood that, for ease of description, details of the same components (e.g., materials, manufacturing processes, functions, etc.) in both 3D memory devices 1600 and 1601 will not be repeated.

[0182] Figures 17A-17H This disclosure illustrates some aspects of the formation of Figure 15A and 15B The manufacturing process of 3D memory devices. Figure 19 This disclosure illustrates some aspects of the formation of Figure 15A and 15B The flowchart of the method for 3D memory devices in 1900. Figures 17A-17H Examples of 3D memory devices shown in 19 include Figure 16A The 3D memory device 1600 shown is described together. Figures 17A-17H And 19. It should be understood that the operations shown in method 1900 are not exhaustive, and other operations may be performed before, after, or between any of the operations shown. Furthermore, some operations may be performed simultaneously, or in conjunction with... Figure 19 The different execution orders shown.

[0183] refer to Figure 19 Method 1900 begins with operation 1902, in which a first transistor is formed on a first substrate. The first substrate may be a silicon substrate having monocrystalline silicon. Figure 17AAs shown, a plurality of transistors 1704 and 1706 are formed on a silicon substrate 1702. Transistors 1704 and 1706 can be formed by a variety of processes, including but not limited to photolithography, dry / wet etching, thin film deposition, thermal growth, implantation, CMP, and any other suitable process. In some embodiments, doped regions are formed in the silicon substrate 1702 by ion implantation and / or thermal diffusion, which serve, for example, as the well and source / drain regions of transistors 1704 and 1706. In some embodiments, isolation regions (e.g., STI) are also formed in the silicon substrate 1702 by wet / dry etching and thin film deposition. In some embodiments, the thickness of the gate dielectric of transistor 1704 differs from the thickness of the gate dielectric of transistor 1706, for example, by depositing a thicker silicon oxide film in the region of transistor 1704 than in the region of transistor 1706, or by etching back a portion of the silicon oxide film deposited in the region of transistor 1706. It should be understood that the details of fabricating transistors 1704 and 1706 may depend on the type of transistor (e.g., Figure 5A , 5B The variations are due to the planar transistor 500 or 3D transistor 600 in 6A and 6B, and therefore will not be elaborated further for the sake of description.

[0184] In some embodiments, an interconnect layer 1708 is formed over the transistors on the first substrate. The interconnect layer may include multiple interconnects within one or more ILD layers. For example... Figure 17A As shown, an interconnect layer 1708 can be formed over transistors 1704 and 1706. Interconnect layer 1708 may include MEOL and / or BEOL interconnects in a plurality of ILD layers for electrical connection to transistors 1704 and 1706. In some embodiments, interconnect layer 1708 includes a plurality of ILD layers and interconnects formed therein using a plurality of processes. For example, interconnects in interconnect layer 1708 may include conductive materials deposited by one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof). The fabrication process forming the interconnects may also include photolithography, CMP, wet / dry etching, or any other suitable process. The ILD layers may include dielectric materials deposited by one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, or any combination thereof). Figure 17A The ILD layer and interconnects shown can be collectively referred to as interconnect layer 1708. In some embodiments, the interconnects in interconnect layer 1708 include W, which has a relatively high thermal budget in a conductive metallic material to withstand subsequent high-temperature processes.

[0185] Method 1900 proceeds to operation 1904, such as... Figure 19 As shown, a polysilicon layer is formed above the first transistor. Figure 17BAs shown, a polysilicon layer 1711 is formed over the interconnect layer 1708 and transistors 1704 and 1706 on the first silicon substrate 1702. The polysilicon layer 1711 can be formed by depositing polysilicon on the interconnect layer 1708 using one or more thin-film deposition processes (including but not limited to CVD, PVD, ALD, or any combination thereof). In some embodiments, the polysilicon layer 1711 is doped with P-type or N-type dopants using an in-situ doping process during the deposition process or an ion implantation / diffusion process after the deposition process.

[0186] Method 1900 proceeds to operation 1906, such as... Figure 19 As shown, an array of NAND memory strings is formed on a polysilicon layer. In some embodiments, a memory stack layer is formed on the polysilicon layer to form the array of NAND memory strings. Figure 17C As shown, a stacked layer structure, such as a memory stacked layer 1726 comprising staggered conductive and dielectric layers, is formed on a polysilicon layer 1716. To form the memory stacked layer 1726, in some embodiments, a dielectric stacked layer (not shown) comprising staggered sacrificial layers (not shown) and dielectric layers is formed on the polysilicon layer 1716. In some embodiments, each sacrificial layer comprises a silicon nitride layer, and each dielectric layer comprises a silicon oxide layer. The staggered sacrificial and dielectric layers can be formed by one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, or any combination thereof). The memory stacked layer 1726 can then be formed by a gate replacement process, for example, by replacing the sacrificial layers with conductive layers using a wet / dry etching process that selectively etches the dielectric layers, and filling the resulting trenches with conductive layers. In some embodiments, each conductive layer comprises a metal layer, such as a W layer. It should be understood that, in some examples, the memory stack 1726 can be formed by alternately depositing conductive layers (e.g., doped polysilicon layers) and dielectric layers (e.g., silicon oxide layers) without a gate replacement process. In some embodiments, a pad oxide layer comprising silicon oxide is formed between the memory stack 1726 and the polysilicon layer 1716.

[0187] like Figure 17CAs shown, a NAND memory string 1728 is formed above a polysilicon layer 1716, with each string extending vertically through the memory stack layer 1726 to contact the polysilicon layer 1711. In some embodiments, the fabrication process for forming the NAND memory string 1728 includes forming channel vias through the memory stack layer 1726 (or dielectric stack layer) and into the polysilicon layer 1716 using dry etching and / or wet etching (e.g., DRIE), followed by filling the channel vias with multiple layers (e.g., memory films (e.g., tunneling layers, storage layers, and barrier layers) and semiconductor layers) using thin-film deposition processes (e.g., ALD, CVD, PVD, or any combination thereof). It should be understood that the details of fabricating the NAND memory string 1728 can depend on the type of channel structure of the NAND memory string 1728 (e.g., Figure 8 The channel structure (812) varies, and therefore, for ease of description, the details will not be elaborated further.

[0188] In some implementations, an interconnect layer is formed above an array of NAND memory strings. The interconnect layer may include a plurality of interconnects within one or more ILD layers. Figure 17C As shown, an interconnect layer 1730 is formed over the memory stack layer 1726 and the NAND memory string 1728. The interconnect layer 1730 may include interconnects of MEOL and / or BEOL in a plurality of ILD layers for electrical connection to the NAND memory string 1728. In some embodiments, the interconnect layer 1730 includes a plurality of ILD layers and interconnects formed therein using a plurality of processes. For example, the interconnects in the interconnect layer 1730 may include conductive materials deposited by one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof). The fabrication processes forming the interconnects may also include photolithography, CMP, wet / dry etching, or any other suitable process. The ILD layers may include dielectric materials deposited by one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, or any combination thereof). Figure 17D The ILD layer and interconnect shown can be collectively referred to as interconnect layer 1730.

[0189] In some implementations, contacts are formed through the polysilicon layer. For example... Figure 17CAs shown, one or more contacts 1724 are formed, each extending vertically through the polysilicon layer 1711. Contacts 1724 can couple interconnects in interconnect layers 1730 and 1708. Contacts 1724 can be formed by first patterning contact holes through the polysilicon layer 1711 using a patterning process (e.g., photolithography and dry / wet etching of a dielectric material in a dielectric layer). Contact holes can be filled with a conductor (e.g., W or Cu). In some embodiments, filling the contact holes includes depositing a spacer (e.g., a silicon oxide layer) before depositing the conductor.

[0190] In some implementations, a first bonding layer is formed over the interconnect layer. The first bonding layer may include a plurality of first bonding contacts. For example... Figure 17C As shown, a bonding layer 1732 is formed over the interconnect layer 1730. The bonding layer 1732 may include a plurality of bonding contacts surrounded by a dielectric. In some embodiments, a dielectric layer is deposited on the top surface of the interconnect layer 1730 by one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, or any combination thereof). Then, by patterning contact holes through the dielectric layer first by using a patterning process (e.g., photolithography and dry / wet etching of the dielectric material in the dielectric layer), bonding contacts that penetrate the dielectric layer and contact the interconnects in the interconnect layer 1730 can be formed. The contact holes may be filled with a conductor (e.g., Cu). In some embodiments, filling the contact holes includes depositing an adhesive layer, a barrier layer, and / or a seed layer prior to depositing the conductor.

[0191] Method 1900 proceeds to operation 1908, such as... Figure 19 As shown, a second transistor is formed on the front side of a second substrate. The second substrate can be a silicon substrate with monocrystalline silicon. Figure 17DAs shown, a plurality of transistors 1714 and 1716 are formed on the front side of a silicon substrate 1710 having monocrystalline silicon. Transistors 1714 and 1716 can be formed by a variety of processes, including but not limited to photolithography, dry / wet etching, thin film deposition, thermal growth, implantation, CMP, and any other suitable process. In some embodiments, doped regions are formed in the silicon substrate 1710 by ion implantation and / or thermal diffusion, which serve as, for example, the well and source / drain regions of transistors 1719 and 1716. In some embodiments, isolation regions (e.g., STI) are also formed in the silicon substrate 1710 by wet / dry etching and thin film deposition. In some embodiments, the thickness of the gate dielectric of transistor 1714 differs from the thickness of the gate dielectric of transistor 1716, for example, by depositing a thicker silicon oxide film in the region of transistor 1714 than in the region of transistor 1716, or by etching back a portion of the silicon oxide film deposited in the region of transistor 1716. It should be understood that the details of manufacturing transistors 1714 and 1716 may depend on the type of transistor (e.g., Figure 5A , 5B The variations (either the planar transistor 500 or the 3D transistor 600 in 6A and 6B) will not be elaborated upon for ease of description.

[0192] In some embodiments, an interconnect layer 1720 is formed over the transistors on the second substrate. The interconnect layer may include multiple interconnects within one or more ILD layers. Figure 17D As shown, an interconnect layer 1720 can be formed over transistors 1719 and 1716. Interconnect layer 1720 may include interconnects of MEOL and / or BEOL in multiple ILD layers for electrical connection to transistors 1714 and 1716. In some embodiments, interconnect layer 1720 includes multiple ILD layers and interconnects formed therein using multiple processes. For example, interconnects in interconnect layer 1720 may include conductive materials deposited by one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof). The fabrication process forming the interconnects may also include photolithography, CMP, wet / dry etching, or any other suitable process. The ILD layers may include dielectric materials deposited by one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, or any combination thereof). Figure 17D The ILD layer and interconnects shown can be collectively referred to as interconnect layer 1720. Unlike interconnect layer 1708, in some embodiments, the interconnects in interconnect layer 1720 include Cu, which has a relatively low resistivity among conductive metal materials. It should be understood that although Cu has a relatively low thermal budget (incompatible with high-temperature processes), it becomes feasible to use Cu as the conductive material for the interconnects in interconnect layer 1720 because there are no longer high-temperature processes after the fabrication of interconnect layer 1720.

[0193] In some embodiments, contacts are formed through a thinned second substrate. For example... Figure 17D As shown, contacts 1718 are formed extending vertically from the front side of silicon substrate 1710 into silicon substrate 1710. Contacts 1718 can be coupled to interconnects in interconnect layer 1720. Contacts 1718 can be formed by first patterning contact holes in silicon substrate 1710 using a patterning process (e.g., photolithography and dry / wet etching of dielectric material in dielectric layer). Contact holes can be filled with a conductor (e.g., Cu). In some embodiments, filling contact holes includes depositing a spacer (e.g., silicon oxide layer) before depositing a conductor.

[0194] In some embodiments, the second substrate is thinned. For example... Figure 17E As shown, the silicon substrate 1710 (as shown) Figure 17D The silicon substrate 1710 is thinned to become a semiconductor layer 1709 having monocrystalline silicon. The silicon substrate 1710 can be thinned by processes including, but not limited to, wafer grinding, dry etching, wet etching, CMP, any other suitable process, or any combination thereof. For example, by controlling the duration of the CMP process, the thickness of the semiconductor layer 1709 can be controlled to expose the contacts 1718 from the back side of the thinned silicon substrate 1710. It should be understood that in some examples, contrary to before thinning in the silicon substrate 1710, after thinning, the contacts 1718 can be formed through the back side of the semiconductor layer 1709. In some embodiments, prior to thinning, a dielectric material such as silicon nitride is deposited on the interconnect layer 1720 using one or more thin-film deposition processes (including but not limited to CVD, PVD, ALD, or any combination thereof), while a passivation layer 1721 is formed on the interconnect layer 1720. Then, prior to thinning, the operating substrate 1701 can be attached to the passivation layer 1721, for example, using adhesive bonding, to allow subsequent backside processing of the silicon substrate 1710, such as thinning, contact formation, and bonding.

[0195] In some embodiments, a second bonding layer is formed on the back side of a thinned second substrate. The second bonding layer may include a plurality of second bonding contacts. For example... Figure 17FAs shown, a bonding layer 1722 is formed on the back side of semiconductor layer 1709 (i.e., thinned silicon substrate 1710). Bonding layer 1722 may include a plurality of bonding contacts surrounded by a dielectric. In some embodiments, a dielectric layer is deposited on the back side of semiconductor layer 1709 (opposite to the front side where transistors 1714 and 1716 are formed) by one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, or any combination thereof). Then, by patterning contact holes through the dielectric layer first using a patterning process (e.g., photolithography and dry / wet etching of the dielectric material in the dielectric layer), bonding contacts that penetrate the dielectric layer and contact contacts 1718 on the back side of the thinned silicon substrate 1710 can be formed. The contact holes may be filled with a conductor (e.g., Cu). In some embodiments, filling the contact holes includes depositing an adhesive layer, a barrier layer, and / or a seed layer prior to depositing the conductor.

[0196] Method 1900 proceeds to operation 1910, such as... Figure 19 As shown, a first substrate and a second substrate are bonded together in a face-to-back manner. After bonding the first and second substrates, a first bonding contact in the first bonding layer can contact a second bonding contact in the second bonding layer at the bonding interface. Bonding may include hybrid bonding.

[0197] like Figure 17G As shown, the silicon substrate 1702 and components formed thereon (e.g., transistors 1704 and 1706 and NAND memory string 1728), and the thinned silicon substrate 1710 (i.e., semiconductor layer 1709) and components formed thereon (e.g., transistors 1714 and 1716) are bonded in a face-to-face manner with the bonding layer 1732 facing upward on the front side of the silicon substrate 1702 and the bonding layer 1722 facing downward on the back side of the thinned silicon substrate 1710, thereby forming a bonding interface 1712. That is, the silicon substrate 1702 and the components formed thereon can be bonded to the thinned silicon substrate 1710 and the components formed thereon in a face-to-back manner, such that the bonding contacts in the bonding layer 1732 and the bonding contacts in the bonding layer 1722 contact at the bonding interface 1712. In some embodiments, a processing technique, such as plasma treatment, wet treatment, and / or heat treatment, is applied to the bonding surfaces prior to bonding. As a result of bonding (e.g., hybrid bonding), the bonding contacts on opposite sides of the bonding interface 1712 can be mixed with each other. After bonding, according to some embodiments, the bonding contacts in the bonding layer 1732 and the bonding contacts in the bonding layer 1722 are aligned and contacted with each other, such that the memory stack layer 1726 and the NAND memory string 1728 formed therethrough, as well as transistors 1704 and 1706, can be coupled to transistors 1714 and 1716 across the bonding interface 1712 via the bonded bonding contacts.

[0198] Method 1900 proceeds to optional operation 1912, such as... Figure 19 As shown, the first substrate is thinned. Figure 17H As shown, silicon substrate 1702 (as shown) Figure 17G The silicon substrate 1702 (as shown) is thinned to become a semiconductor layer 1703 having monocrystalline silicon. The silicon substrate 1702 can be thinned by processes including but not limited to wafer grinding, dry etching, wet etching, CMP, any other suitable process or any combination thereof.

[0199] Method 1900 proceeds to operation 1914, such as... Figure 19 As shown, an interconnect layer with pads is formed. The interconnect layer with pads is formed on a thinned first substrate. Figure 17H As shown, a pad-out interconnect layer 1736 is formed on a semiconductor layer 1703 (a thinned silicon substrate 1702). The pad-out interconnect layer 1736 may include interconnects formed in one or more ILD layers, such as contact pads 1938. Contact pads 1738 may include conductive materials, including but not limited to W, Co, Cu, Al, doped silicon, silicides, or any combination thereof. The ILD layers may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. In some embodiments, after bonding and thinning, contacts 1734 extending vertically through the semiconductor layer 1703 are formed, for example by wet / dry etching, followed by deposition of a dielectric material as a spacer and a conductive material as a conductor. Contacts 1734 may couple the contact pads 1738 in the pad-out interconnect layer 1736 to the interconnects in the interconnect layer 1708. It should be understood that in some examples, contacts 1734 may be thinned (e.g., Figure 17G As shown, the semiconductor layer 1703 was formed in the silicon substrate 1702 before thinning and is exposed from the back side of the silicon substrate 1702 (at the location where thinning occurs) after thinning.

[0200] In some implementations, after operation 1910, optional operation 1912 is skipped, and method 1900 proceeds to operation 1914, such as... Figure 19 As shown, an interconnect layer with pads is formed. An interconnect layer with pads can be formed above the second transistor. Although Figure 17G Although not shown, it should be understood that in some examples, after removing the operating substrate 1701 and the passivation layer 1721, a pad-out interconnect layer with contact pads may be formed over the interconnect layer 1720 and transistors 1716 and 1714.

[0201] Figures 18A-18F This disclosure illustrates some aspects of the formation of Figure 15A and15B Another manufacturing process for 3D memory devices. Figure 20 This disclosure illustrates some aspects of the formation of Figure 15A and 15B A flowchart of another method for 3D memory devices in 2000. Figures 18A-18F Examples of 3D memory devices shown in Figure 20 include Figure 16B The 3D memory device 1601 shown is described together. Figures 18A-18F And 20. It should be understood that the operations shown in method 2000 are not exhaustive, and other operations may be performed before, after, or between any of the operations shown. Furthermore, some operations may be performed simultaneously, or in conjunction with... Figure 20 The different execution orders shown.

[0202] refer to Figure 20 Method 2000 begins with operation 2002, in which a first transistor is formed on a first substrate. The first substrate may be a silicon substrate having monocrystalline silicon. Figure 18A As shown, a plurality of transistors 1804 and 1806 are formed on a silicon substrate 1802. Transistors 1804 and 1806 can be formed by a variety of processes, including but not limited to photolithography, dry / wet etching, thin film deposition, thermal growth, implantation, CMP, and any other suitable process. In some embodiments, doped regions are formed in the silicon substrate 1802 by ion implantation and / or thermal diffusion, which serve, for example, as the well and source / drain regions of transistors 1804 and 1806. In some embodiments, isolation regions (e.g., STI) are also formed in the silicon substrate 1802 by wet / dry etching and thin film deposition. In some embodiments, the thickness of the gate dielectric of transistor 1804 differs from the thickness of the gate dielectric of transistor 1806, for example, by depositing a thicker silicon oxide film in the region of transistor 1804 than in the region of transistor 1806, or by etching back a portion of the silicon oxide film deposited in the region of transistor 1806. It should be understood that the details of fabricating transistors 1804 and 1806 may depend on the type of transistor (e.g., Figure 5A , 5B The variations are due to the planar transistor 500 or 3D transistor 600 in 6A and 6B, and therefore will not be elaborated further for the sake of description.

[0203] In some embodiments, an interconnect layer 1808 is formed over the transistors on the first substrate. The interconnect layer may include multiple interconnects within one or more ILD layers. Figure 18AAs shown, an interconnect layer 1808 can be formed over transistors 1804 and 1806. Interconnect layer 1808 may include MEOL and / or BEOL interconnects in a plurality of ILD layers for electrical connection to transistors 1804 and 1806. In some embodiments, interconnect layer 1808 includes a plurality of ILD layers and interconnects formed therein using a plurality of processes. For example, interconnects in interconnect layer 1808 may include conductive materials deposited by one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof). The fabrication process forming the interconnects may also include photolithography, CMP, wet / dry etching, or any other suitable process. The ILD layers may include dielectric materials deposited by one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, or any combination thereof). Figure 18A The ILD layer and interconnects shown can be collectively referred to as interconnect layer 1808. In some embodiments, the interconnects in interconnect layer 1808 include W, which has a relatively high thermal budget in a conductive metallic material to withstand subsequent high-temperature processes.

[0204] Method 2000 proceeds to operation 2004, such as... Figure 20 As shown, a polysilicon layer is formed above the first transistor. Figure 18B As shown, a polysilicon layer 1811 is formed over the interconnect layer 1808 and transistors 1804 and 1806 on the first silicon substrate 1802. The polysilicon layer 1811 can be formed by depositing polysilicon on the interconnect layer 1808 using one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, or any combination thereof). In some embodiments, the polysilicon layer 1811 is doped with P-type or N-type dopants using an in-situ doping process during the deposition process or an ion implantation / diffusion process after the deposition process.

[0205] Method 2000 proceeds to operation 2006, such as... Figure 20 As shown, an array of NAND memory strings is formed on a polysilicon layer. In some embodiments, a memory stack layer is formed on the polysilicon layer to form the array of NAND memory strings. Figure 18CAs shown, a stacked layer structure, such as a memory stacked layer 1826 comprising staggered conductive and dielectric layers, is formed on a polysilicon layer 1816. To form the memory stacked layer 1826, in some embodiments, a dielectric stacked layer (not shown) comprising staggered sacrificial layers (not shown) and dielectric layers is formed on the polysilicon layer 1816. In some embodiments, each sacrificial layer comprises a silicon nitride layer, and each dielectric layer comprises a silicon oxide layer. The staggered sacrificial and dielectric layers can be formed by one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, or any combination thereof). The memory stacked layer 1826 can then be formed by a gate replacement process, for example, by replacing the sacrificial layers with conductive layers using a wet / dry etching process that selectively etches the dielectric layers, and filling the resulting trenches with conductive layers. In some embodiments, each conductive layer comprises a metal layer, such as a W layer. It should be understood that, in some examples, the memory stack 1826 can be formed by alternately depositing conductive layers (e.g., doped polysilicon layers) and dielectric layers (e.g., silicon oxide layers) without a gate replacement process. In some embodiments, a pad oxide layer comprising silicon oxide is formed between the memory stack 1826 and the polysilicon layer 1816.

[0206] like Figure 18C As shown, a NAND memory string 1828 is formed above a polysilicon layer 1816, with each string extending vertically through the memory stack layer 1826 to contact the polysilicon layer 1811. In some embodiments, the fabrication process for forming the NAND memory string 1828 includes forming channel vias through the memory stack layer 1826 (or dielectric stack layer) and into the polysilicon layer 1816 using dry etching and / or wet etching (e.g., DRIE), followed by filling the channel vias with multiple layers (e.g., memory films (e.g., tunneling layers, storage layers, and barrier layers) and semiconductor layers) using thin-film deposition processes (e.g., ALD, CVD, PVD, or any combination thereof). It should be understood that the details of fabricating the NAND memory string 1828 can depend on the type of channel structure of the NAND memory string 1828 (e.g., Figure 8 The channel structure (812) varies, and therefore will not be elaborated further for ease of description.

[0207] In some implementations, an interconnect layer is formed above an array of NAND memory strings. The interconnect layer may include a plurality of interconnects within one or more ILD layers. Figure 18CAs shown, an interconnect layer 1830 is formed over the memory stack layer 1826 and the NAND memory string 1828. The interconnect layer 1830 may include interconnects of MEOL and / or BEOL in a plurality of ILD layers for electrical connection to the NAND memory string 1828. In some embodiments, the interconnect layer 1830 includes a plurality of ILD layers and interconnects formed therein using a plurality of processes. For example, the interconnects in the interconnect layer 1830 may include conductive materials deposited by one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof). The fabrication processes forming the interconnects may also include photolithography, CMP, wet / dry etching, or any other suitable process. The ILD layers may include dielectric materials deposited by one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, or any combination thereof). Figure 18C The ILD layer and interconnect shown can be collectively referred to as interconnect layer 1830.

[0208] In some implementations, contacts are formed through the polysilicon layer. For example... Figure 18C As shown, one or more contacts 1817 are formed, each extending vertically through the polysilicon layer 1811. The contacts 1817 can couple interconnects in interconnect layers 1830 and 1808. The contacts 1817 can be formed by first patterning contact holes through the polysilicon layer 1811 using a patterning process (e.g., photolithography and dry / wet etching of the dielectric material in the dielectric layer). The contact holes can be filled with a conductor (e.g., W or Cu). In some embodiments, filling the contact holes includes depositing a spacer (e.g., a silicon oxide layer) before depositing the conductor.

[0209] Method 2000 proceeds to Operation 2008, such as... Figure 20 As shown, a semiconductor layer is formed over a NAND memory string array. The semiconductor layer may include monocrystalline silicon. In some embodiments, to form the semiconductor layer, another substrate is bonded to the first substrate face-to-face, and the other substrate is thinned to leave the semiconductor layer. Bonding may include transfer bonding. The other substrate may be a silicon substrate having monocrystalline silicon.

[0210] like Figure 18D As shown, a semiconductor layer 1810, such as a single-crystal silicon layer, is formed over the interconnect layer 1830 and the NAND memory string 1828. The semiconductor layer 1810 may be attached over the interconnect layer 1830 to form a bonding interface 1812 perpendicularly between the semiconductor layer 1810 and the interconnect layer 1830. In some embodiments, to form the semiconductor layer 1810, transfer bonding is used to bond another silicon substrate face-to-face. Figure 18D(Not shown in the diagram) and a silicon substrate 1802 (with components formed on the silicon substrate 1802, such as NAND memory strings 1828 and transistors 1804 and 1806, facing the other silicon substrate), thereby forming a bonding interface 1812. The other silicon substrate can then be thinned using any suitable process to leave a semiconductor layer 1810 attached above the interconnect layer 1830.

[0211] Figures 34A-34D A manufacturing process for transfer bonding according to some aspects of this disclosure is illustrated. For example... Figure 34A As shown, a functional layer 3404 can be formed on a base substrate 3402. The functional layer 3404 may include a device layer, an interconnect layer, and / or any suitable layer disclosed herein, such as… Figure 18C The transistors 1804 and 1806, polysilicon layer 106, memory stack layer 1826, NAND memory string 1828, and interconnect layers 1808 and 1830 are included. A transfer substrate 3406 is provided, such as a silicon substrate having monocrystalline silicon. In some embodiments, the transfer substrate 3406 is a monocrystalline silicon substrate. Figure 34B As shown, the transfer substrate 3406 and the base substrate 3402 (and the functional layer 3404 formed thereon) can be bonded face-to-face using any suitable substrate / wafer bonding process, including, for example, anodic bonding and fusion (direct) bonding, thereby forming a bonding interface 3410 between the transfer substrate 3406 and the base substrate 3402. In one example, fusion bonding can be performed between silicon and silicon, silicon and silicon oxide, or silicon oxide and silicon oxide layers using pressure and heat. In another example, anodic bonding can be performed between a silicon oxide layer (in an ionomer glass) and a silicon layer using voltage, pressure, and heat. It should be understood that, depending on the bonding process, a dielectric layer (e.g., a silicon oxide layer) can be formed on one or both sides of the bonding interface 3410. For example, silicon oxide layers can be formed on both the top surfaces of the transfer substrate 3406 and the functional layer 3404 to allow for fusion-bonded SiO2-SiO2 bonding; or, a silicon oxide layer can be formed only on the functional layer 3404 to allow for anodic bonding or fusion-bonded SiO2-Si bonding. In some embodiments where the silicon oxide layer is formed on the transfer substrate 3406 (e.g., Figure 34B As shown, the transfer substrate 3406 can be flipped upside down so that the silicon oxide layer on the transfer substrate 3406 faces downward toward the base substrate 3402 before bonding.

[0212] like Figure 34C As shown, for example, ion implantation can be used to form a cleavage layer 3412 in the transfer substrate 3406. In some embodiments, for example, by controlling the energy of the ion implantation process, a light element such as hydrogen ions is implanted into the transfer substrate 3406 to a desired depth to form the cleavage layer 3412. Figure 34D As shown, the transfer substrate 3406 can be thinned to leave only the semiconductor layer 3414 perpendicularly between the dicing layer 3412 and the bonding interface 3410. In some embodiments, the transfer substrate 3406 is separated at the dicing layer 3412 by applying mechanical force to the transfer substrate 3406, i.e., peeling the remaining portion of the transfer substrate 3406 from the semiconductor layer 3414. It should be understood that the transfer substrate 3406 can be separated at the dicing layer 3412 by any suitable means, not limited to mechanical force alone, such as thermal, acoustic, etc., or any combination thereof. As a result, the semiconductor layer 3414 can be transferred from the transfer substrate 3406 and bonded to the base substrate 3402 (and the functional layer 3404) using a transfer bonding process. In some embodiments, a planarization process, such as chemical mechanical polishing (CMP), is performed on the semiconductor layer 3412 to polish and smooth the top surface of the semiconductor layer 3412 and adjust the thickness of the semiconductor layer 3412. Therefore, the semiconductor layer 3414 can have the same material as the transfer substrate 3406, such as single-crystal silicon. The thickness of the semiconductor layer 3414 can be determined by the depth of the dicing layer 3412, for example, by adjusting the implantation energy, and / or by a planarization process. Furthermore, the remaining portion of the transfer substrate 3406 can be reused in the same manner to form semiconductor layers bonded to other base substrates, thereby reducing the material cost of the transfer bonding process.

[0213] Figures 35A-35D Another manufacturing process for transfer bonding based on some aspects of this disclosure is illustrated. For example... Figure 35A As shown, a functional layer 3404 can be formed on a base substrate 3402. The functional layer 3404 may include a device layer, an interconnect layer, and / or any suitable layer disclosed herein, such as… Figure 18C The transistors 1804 and 1806, polysilicon layer 106, memory stack layer 1826, NAND memory string 1828, and interconnect layers 1808 and 1830 are included. The SOI substrate 3502, including the base / operation layer 3504, buried oxide layer (BOx) 3506, and device layer 3508, can be flipped to face the base substrate 3402. (As shown...) Figure 35BAs shown, the SOI substrate 3502 and the base substrate 3402 (and the functional layer 3404 formed thereon) can be bonded face-to-face using any suitable substrate / wafer bonding process, including, for example, anodic bonding and fusion (direct) bonding, thereby forming a bonding interface 3512 between the SOI substrate 3502 and the base substrate 3402. In one example, fusion bonding can be performed between silicon and silicon, silicon and silicon oxide, or silicon oxide and silicon oxide layers using pressure and heat. In another example, anodic bonding can be performed between a silicon oxide layer (in ionomer glass) and a silicon layer using voltage, pressure, and heat. It should be understood that, depending on the bonding process, a dielectric layer (e.g., a silicon oxide layer) can be formed on one or both sides of the bonding interface 3512. For example, silicon oxide layers can be formed on the top surfaces of both the SOI substrate 3502 and the functional layer 3404 to allow for fusion-bonded SiO2-SiO2 bonding. Alternatively, a silicon oxide layer may be formed only on functional layer 3404 to allow for the use of anodic bonding or fused bonding of SiO2-Si bonds.

[0214] like Figure 35C and 35D As shown, the SOI substrate 3502 can be thinned by sequentially removing the base / operation layer 3504 and the buried oxide layer 3506, for example, using wet / dry etching and / or CMP processes. Figure 35B As shown, only device layer 3508 (as a semiconductor layer) is left at bonding interface 3512. As a result, device layer 3508 can be transferred from SOI substrate 3502 using another transfer bonding process and bonded to base substrate 3402 (and functional layer 3404) as the semiconductor layer. Therefore, the transferred semiconductor layer can have the same material as device layer 3508, such as single-crystal silicon. The thickness of the semiconductor layer can be the same as that of device layer 3508. It should be understood that in some examples, device layer 3508 can be further thinned using wet / dry etching and / or CMP processes, such that the transferred semiconductor layer can be thinner than device layer 3508.

[0215] Return to reference Figure 20 Method 2000 proceeds to operation 2010, in which a second transistor is formed on the semiconductor layer. For example... Figure 18EAs shown, a plurality of transistors 1814 and 1816 are formed on a semiconductor layer 1810 having monocrystalline silicon. Transistors 1814 and 1816 can be formed by a variety of processes, including but not limited to photolithography, dry / wet etching, thin film deposition, thermal growth, implantation, CMP, and any other suitable process. In some embodiments, doped regions are formed in the semiconductor layer 1810 by ion implantation and / or thermal diffusion, which serve, for example, as the well and source / drain regions of transistors 1814 and 1816. In some embodiments, isolation regions (e.g., STI) are also formed in the semiconductor layer 1810 by wet / dry etching and thin film deposition. In some embodiments, the thickness of the gate dielectric of transistor 1814 differs from the thickness of the gate dielectric of transistor 1816, for example, by depositing a thicker silicon oxide film in the region of transistor 1814 than in the region of transistor 1816, or by etching back a portion of the silicon oxide film deposited in the region of transistor 1816. It should be understood that the details of fabricating transistors 1814 and 1816 may depend on the type of transistor (e.g., Figure 5A , 5B The variations (either the planar transistor 500 or the 3D transistor 600 in 6A and 6B) will not be elaborated upon for ease of description.

[0216] In some embodiments, an interconnect layer is formed over the transistors on the second substrate. The interconnect layer may include multiple interconnects within one or more ILD layers. For example... Figure 18E As shown, an interconnect layer 1820 can be formed over transistors 1820 and 1816. The interconnect layer 1820 may include interconnects of MEOL and / or BEOL in multiple ILD layers for electrical connection to transistors 1814 and 1816. In some embodiments, the interconnect layer 1820 includes multiple ILD layers and interconnects formed therein using multiple processes. For example, the interconnects in the interconnect layer 1820 may include conductive materials deposited by one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof). The fabrication process forming the interconnects may also include photolithography, CMP, wet / dry etching, or any other suitable process. The ILD layers may include dielectric materials deposited by one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, or any combination thereof). Figure 17D The ILD layer and interconnects shown can be collectively referred to as interconnect layer 1820. Unlike interconnect layer 1808, in some embodiments, the interconnects in interconnect layer 1820 include Cu, which has a relatively low resistivity among conductive metal materials. It should be understood that although Cu has a relatively low thermal budget (incompatible with high-temperature processes), it becomes feasible to use Cu as the conductive material for the interconnects in interconnect layer 1820 because there are no longer high-temperature processes after the fabrication of interconnect layer 1820.

[0217] In some embodiments, contacts are formed perpendicularly through the semiconductor layer. Contact 1818 may extend perpendicularly through the semiconductor layer 1810 from the front side. Contact 1818 may be coupled to an interconnect in interconnect layer 1820. Contact 1818 may further extend through a dielectric layer (if present) on the back side of semiconductor layer 1810 to align and contact an interconnect in interconnect layer 1830 at bonding interface 1812. Thus, contact 1818 couples the interconnect in interconnect layer 1820 through semiconductor layer 1810 and across bonding interface 1812 to the interconnect in interconnect layer 1830. Contact 1818 may be formed by first patterning contact holes in semiconductor layer 1810 using a patterning process (e.g., photolithography and dry / wet etching of the dielectric material in the dielectric layer). Contact holes may be filled with a conductor (e.g., W or Cu). In some embodiments, filling contact holes includes depositing a spacer (e.g., a silicon oxide layer) before depositing a conductor.

[0218] Method 2000 skips optional operation 2012 and proceeds to operation 2014, as follows. Figure 20 As shown, an interconnect layer with pads is formed therein. An interconnect layer with pads can also be formed above the second transistor. (As shown...) Figure 18F As shown, a pad-lead interconnect layer 1836 is formed above the interconnect layer 1820 on the semiconductor layer 1810 and above transistors 1814 and 1816. The pad-lead interconnect layer 1836 may include interconnects formed in one or more ILD layers, such as contact pads 1838. Contact pads 1838 may include conductive materials, including but not limited to W, Co, Cu, Al, doped silicon, silicides, or any combination thereof. The ILD layer may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0219] In some embodiments, in order to form pads to lead out interconnect layers on the first substrate, after operation 2010, method 2000 proceeds to optional operation 2012, such as... Figure 20 As shown, the first substrate is thinned. It should be understood that, although not shown, in some examples, processes including, but not limited to, wafer grinding, dry etching, wet etching, CMP, any other suitable process, or any combination thereof, can be used to thin the silicon substrate 1802. Figure 18E(As shown) to form a semiconductor layer with monocrystalline silicon. After thinning, for example by wet / dry etching, followed by deposition of a dielectric material as spacers and a conductive material as conductors, contacts extending vertically through the thinned silicon substrate 1802 can be formed. It should be understood that in some examples, the contacts may be formed in the silicon substrate 1802 before thinning and exposed from the back side of the silicon substrate 1802 (at the location where thinning occurs) after thinning.

[0220] Method 2000 proceeds to operation 2014, such as... Figure 20 As shown, a pad-out interconnect layer is formed therein. The pad-out interconnect layer can be formed on a thinned first substrate. It should be understood that, although not shown, in some examples, a pad-out interconnect layer with contact pads can be formed on a thinned silicon substrate 1802.

[0221] Figure 21A and 21B A schematic cross-sectional view of 3D memory devices 2100 and 2101 having two stacked semiconductor structures according to various aspects of this disclosure is shown. 3D memory devices 2100 and 2101 can be... Figure 1B An example of a 3D memory device 101 is shown, wherein the peripheral circuitry of a first semiconductor structure 102 is vertically disposed between the memory cell array of the first semiconductor structure 102 and the peripheral circuitry of the second semiconductor structure 104. That is, two separate portions of the peripheral circuitry can be disposed adjacent to each other in the vertical direction. For example... Figure 21A and 21B As shown, according to some embodiments, a second semiconductor structure 104, including some of the peripheral circuitry, is bonded to a first semiconductor structure 102 on the side having the peripheral circuitry to form a bonding interface 105 between the second semiconductor structure 104 and the peripheral circuitry of the first semiconductor structure 102.

[0222] In addition, such as Figure 21A and 21B As shown, the 3D memory device 2100 or 2101 may further include a pad-out interconnect layer 902 for pad-out destinations, i.e., contact pads on which bonding wires can be soldered for interconnection with external devices. Figure 21B In one example shown, a second semiconductor structure 104 including some peripheral circuitry on one side of the 3D memory device 2101 may include a pad-out interconnect layer 902, allowing the 3D memory device 2101 to be led out from the peripheral circuitry-side pads. This reduces the interconnect distance between the contact pads and the peripheral circuitry, thereby reducing parasitic capacitance from the interconnects and improving the electrical performance of the 3D memory device 2101. Figure 21AIn another example shown, the first semiconductor structure 102, which includes a memory cell array and some peripheral circuitry on the other side of the 3D memory device 2100, may include a pad-out interconnect layer 902, such that the 3D memory device 901 can be led out from the memory cell array-side pads.

[0223] Figure 22A and 22B The public aspects of this disclosure are shown. Figure 21A and 21B A schematic diagram of a cross-section of the 3D memory devices shown. 3D memory devices 2200 and 2201 can be... Figure 21A and 21B Examples of 3D memory devices 2100 and 2101. (See example...) Figure 22A As shown, the 3D memory device 2200 may include a stacked first semiconductor structure 102 and a second semiconductor structure 104. In some embodiments, the first semiconductor structure 102 includes a semiconductor layer 1002, a bonding layer 1014, a memory cell array, some peripheral circuitry in peripheral circuitry vertically between the semiconductor layer 1002 and the polysilicon layer 106, and the polysilicon layer 106 vertically between the memory cell array and the peripheral circuitry.

[0224] The memory cell array may include an array of NAND memory strings (e.g., NAND memory string 208 disclosed herein), and the source of the array of NAND memory strings may be in contact with the polysilicon layer 106 (e.g., as shown in the image). Figure 8 (As shown in the diagram). The polysilicon layer 106 may be a deposited polysilicon layer (e.g., N-type doped, P-type doped, or undoped), suitable for channel structures in "floating gate" type NAND memory strings or, for example, "charge trap" type NAND memory strings suitable for GIDL erase operations (e.g., Figure 8 Certain designs of the channel structure 812 in the first semiconductor structure 102. Through-contacts (e.g., ILV / TSV) through the polysilicon layer 106 enable direct, short-distance (e.g., submicron or micron-scale) electrical connections between the memory cell array in the first semiconductor structure 102 and peripheral circuitry. The bonding layer 1014 may include dielectrics for conductive bonding contacts (not shown) and electrically isolating bonding contacts, which can be used for hybrid bonding, as described in detail below.

[0225] In some embodiments, the peripheral circuitry in the first semiconductor structure 102 contacts the semiconductor layer 1002 but not the polysilicon layer 106. That is, the transistors of the peripheral circuitry (e.g., planar transistor 500 and 3D transistor 600) may contact the semiconductor layer 1002. The semiconductor layer 1002 may include a semiconductor material, such as monocrystalline silicon (e.g., a silicon substrate or a thinned silicon substrate). It should be understood that in some examples, unlike the polysilicon layer 106 in the first semiconductor structure 102, the semiconductor layer 1002 on which transistors are formed may include monocrystalline silicon, but not polycrystalline silicon, due to the superior carrier mobility of monocrystalline silicon desired for transistor performance. The peripheral circuitry and the bonding layer 1014 may be formed on opposite sides of the semiconductor layer 1002, such that the semiconductor layer 1002 is vertically disposed between the peripheral circuitry and the bonding layer 1014. In some embodiments, transistors of peripheral circuits are formed on the front side of semiconductor layer 1002, and bonding contacts of bonding layer 1014 are formed on the back side of semiconductor layer 1002.

[0226] In some embodiments, the second semiconductor structure 104 includes a semiconductor layer 1004, a bonding layer 1012, and some peripheral circuitry in the peripheral circuitry of a memory cell array vertically positioned between the semiconductor layer 1004 and the bonding layer 1012. Transistors (e.g., planar transistors 500 and 3D transistors 600) of the peripheral circuitry may contact the semiconductor layer 1004. Similar to semiconductor layer 1002, semiconductor layer 1004 may include a semiconductor material such as monocrystalline silicon (e.g., a silicon substrate or a thinned silicon substrate). It should be understood that in some examples, unlike the polycrystalline silicon layer 106 in the first semiconductor structure 102, the semiconductor layer 1004 on which transistors are formed may include monocrystalline silicon, rather than polycrystalline silicon, due to the superior carrier mobility of monocrystalline silicon desired for transistor performance.

[0227] Similar to the bonding layer 1014 in the first semiconductor structure 102, the bonding layer 1012 may further include a dielectric material for conductive bonding contacts (not shown) and electrically isolating bonding contacts. According to some embodiments, a bonding interface 105 is perpendicularly positioned between and in contact with the bonding layers 1012 and 1014, respectively. That is, the bonding layers 1012 and 1014 may be disposed on opposite sides of the bonding interface 105, and the bonding contacts of the bonding layer 1012 may contact the bonding contacts of the bonding layer 1014 at the bonding interface 105. As a result, a large number (e.g., millions) of bonding contacts across the bonding interface 105, combined with through contacts (e.g., ILV / TSV) through the semiconductor layer 1002, enable direct, short-distance (e.g., micrometer-scale) electrical connections between adjacent semiconductor structures 102 and 104.

[0228] It should be understood that in some examples, the first semiconductor structure 102 and the second semiconductor structure 104 may not include, respectively, the following: Figure 22A The bonding layers 1014 and 1012 are shown disposed on opposite sides of the bonding interface 105. Figure 22B In the 3D memory device 2201, the semiconductor layer 1002 in the first semiconductor structure 102 can be a single-crystal silicon layer transferred from a silicon substrate or SOI substrate and attached to the top surface of the second semiconductor structure 104 by transfer bonding. Conversely, in contrast to hybrid bonding, the bonding interface 105 between the first semiconductor structure 102 and the second semiconductor structure 104 can be generated by transfer bonding. Through-contacts (e.g., ILV / TSV) perpendicularly passing through the semiconductor layer 1002 between the first semiconductor structure 102 and the second semiconductor structure 104 can provide direct, short-distance (e.g., submicron-level) electrical connections between adjacent semiconductor structures 102 and 104.

[0229] like Figure 22A and 22B As shown, according to some embodiments, since the first semiconductor structure 102 and the second semiconductor structure 104 are bonded back-to-back (e.g., in...), Figure 22A and 22B In this configuration, semiconductor layers 1002 and 1004 are respectively disposed on the bottom sides of the first semiconductor structure 102 and the second semiconductor structure 104. Therefore, the transistors of the peripheral circuits in the first semiconductor structure 102 and the second semiconductor structure 104 are configured to face the same direction (e.g., Figure 12A and 12B (in the positive y-direction). Furthermore, within the first semiconductor structure 102, since the polysilicon layer 106 is perpendicularly positioned between the memory cell array and the peripheral circuitry, and the memory cell array and peripheral circuitry are formed on the polysilicon layer 106 and the semiconductor layer 1002 respectively, the memory cell array and peripheral circuitry face the same direction (e.g., in...). Figure 22A and 22B (in the positive y-direction). It should be understood that, for ease of explanation, Figure 21A and 21B The pads in the 902 interconnect layer are brought out from the pads. Figure 22A and 22B The 3D memory devices 2200 and 2201 in the above are omitted, and may be included as described above. Figure 21A and 21B In the 3D memory devices 2200 and 2201 described.

[0230] As described above, the first semiconductor structure 102 and the second semiconductor structure 104 may have peripheral circuitry, which includes transistors to which different voltages are applied. For example, the first semiconductor structure 102 may include... Figure 4BAn example of semiconductor structure 408 for LLV circuit 402 (and LV circuit 404 in some examples), and the second semiconductor structure 104 may include Figure 4B An example of semiconductor structure 410 for HV circuit 406 (and LLV circuit 404 in some examples), and vice versa. Therefore, in some embodiments, semiconductor layers 1002 and 1004 in the first semiconductor structure 102 and the second semiconductor structure 104 have different thicknesses to accommodate transistors to which different voltages are applied. In one example, the second semiconductor structure 104 may include HV circuit 406, the first semiconductor structure 102 may include LLV circuit 402, and the thickness of semiconductor layer 1002 in the first semiconductor structure 102 may be less than the thickness of semiconductor layer 1004 in the second semiconductor structure 104. Furthermore, in some embodiments, the gate dielectrics of the transistors in the first semiconductor structure 102 and the second semiconductor structure 104 also have different thicknesses to accommodate the different applied voltages. In one example, the second semiconductor structure 104 may include HV circuit 406, the first semiconductor structure 102 may include LLV circuit 402, and the thickness of the gate dielectric of the transistor in the second semiconductor structure 104 may be greater than (e.g., at least 5 times) the thickness of the gate dielectric of the transistor in the first semiconductor structure 102.

[0231] Figure 23A and 23B The various aspects of this disclosure are shown. Figure 22A and 22B Side views of various examples of 3D memory devices 2200 and 2201. Figure 23A As shown, as Figure 22A and 22B An example of 3D memory devices 2200 and 2201, according to some embodiments, 3D memory device 2300 is a bonded chip including a first semiconductor structure 102 and a second semiconductor structure 104, which in the vertical direction (e.g., Figure 23A The first semiconductor structure 102 and the second semiconductor structure 104 are stacked on different planes in the y-direction. According to some embodiments, the first semiconductor structure 102 and the second semiconductor structure 104 are bonded at the bonding interface 105 therebetween.

[0232] like Figure 23AAs shown, the second semiconductor structure 104 may include a semiconductor layer 1004 having a semiconductor material. In some embodiments, the semiconductor layer 1004 is a silicon substrate having monocrystalline silicon. The second semiconductor structure 104 may also include a device layer 2302 above and in contact with the semiconductor layer 1004. In some embodiments, the device layer 2302 includes a first peripheral circuit 2304 and a second peripheral circuit 2306. The first peripheral circuit 2304 may include an HV circuit 406, such as a driving circuit (e.g., a serial driver 704 in a row decoder / word line driver 308 and a driver in a column decoder / bit line driver 306), and the second peripheral circuit 2306 may include an LV circuit 404, such as a page buffer circuit (e.g., a page buffer circuit 702 in a page buffer 304) and logic circuitry (e.g., in control logic 312). In some embodiments, the first peripheral circuit 2304 includes a plurality of transistors 2308 in contact with the semiconductor layer 1004, and the second peripheral circuit 2306 includes a plurality of transistors 2310 in contact with the semiconductor layer 1004. Transistors 2308 and 2310 may include any transistor disclosed herein, such as planar transistor 500 and 3D transistor 600. As described in detail above with respect to transistors 500 and 600, in some embodiments, each transistor 2308 or 2310 includes a gate dielectric, and because the voltage applied to transistor 2308 is higher than the voltage applied to transistor 2310, the thickness of the gate dielectric of transistor 2308 (e.g., in HV circuit 406) is greater than the thickness of the gate dielectric of transistor 2310 (e.g., in LV circuit 404). Trench isolation (e.g., STI) and doped regions (e.g., the well, source, and drain of transistors 2308 and 2310) may also be formed on or therein in semiconductor layer 1004.

[0233] In some embodiments, the second semiconductor structure 104 further includes an interconnect layer 2312 above the device layer 2302 for transmitting electrical signals to peripheral circuits 2306 and 2304. For example... Figure 23AAs shown, interconnect layer 2312 may be vertically positioned between bonding interface 105 and device layer 2302 (including transistors 2308 and 2310 of peripheral circuits 2304 and 2306). Interconnect layer 2312 may include multiple interconnects, such as MEOL interconnects and BEOL interconnects. Interconnects in interconnect layer 2312 may be coupled to transistors 2308 and 2310 of peripheral circuits 2304 and 2306 in device layer 2302. Interconnect layer 2312 may also include one or more ILD layers, in which lateral lines and vias may be formed. That is, interconnect layer 2312 may include lateral lines and vias in multiple ILD layers. In some embodiments, devices in device layer 2302 are coupled to each other through interconnects in interconnect layer 2312. For example, peripheral circuit 2304 may be coupled to peripheral circuit 2306 through interconnect layer 2312. Interconnects in interconnect layer 2312 may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. The ILD layer in interconnect layer 2312 may include a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof. In some embodiments, the interconnects in interconnect layer 2312 include W, which has a relatively high thermal budget (compatible with high-temperature processes) and good quality (fewer defects, such as voids) in a conductive metallic material.

[0234] like Figure 23A As shown, the first semiconductor structure 102 can be bonded to the top of the second semiconductor structure 104 at the bonding interface 105 in a back-to-back manner. The first semiconductor structure 102 may also include a semiconductor layer 1002 having a semiconductor material. In some embodiments, the bonding interface 105 is the location where the semiconductor layer 1002 of the first semiconductor structure 102 and the interconnect layer 2312 of the second semiconductor structure 104 meet and bond. In practice, the bonding interface 105 may be a layer of a specific thickness, comprising the top surface of the interconnect layer 2312 of the second semiconductor structure 104 and the bottom surface of the semiconductor layer 1002 of the first semiconductor structure 102. The bonding interface 105 may be generated by a transfer bonding process, and the semiconductor layer 1002 may be a single-crystal silicon layer transferred from a silicon substrate or SOI substrate and attached to the top surface of the first semiconductor structure 102 by transfer bonding, as described in detail below regarding the manufacturing process. In some embodiments, a dielectric layer (e.g., a silicon oxide layer) is vertically formed between the bonding interface 105 and the semiconductor layer 1002 and / or between the bonding interface 105 and the interconnect layer 2312 to facilitate transfer bonding from the semiconductor layer 1002 to the interconnect layer 2312. Therefore, it should be understood that in some examples, the bonding interface 105 may include the surface of one or more dielectric layers.

[0235] like Figure 23AAs shown, the first semiconductor structure 102 may further include a device layer 2314 above and in contact with the semiconductor layer 1002. In some embodiments, the device layer 2314 includes a third peripheral circuit 2316 and a fourth peripheral circuit 2318 above and in contact with the semiconductor layer 1002. In some embodiments, the semiconductor layer 1002 is vertically disposed between the bonding interface 105 and the device layer 2314 having peripheral circuits 2316 and 2318. The third peripheral circuit 2316 may include an LLV circuit 402, such as I / O circuitry (e.g., in interface 316 and data bus 318), and the fourth peripheral circuit 2318 may include an LV circuit 404, such as a page buffer circuit (e.g., page buffer circuit 702 in page buffer 304) and logic circuitry (e.g., in control logic 312). In some embodiments, the third peripheral circuit 2316 includes a plurality of transistors 2320, and the fourth peripheral circuit 2318 also includes a plurality of transistors 2322. Transistors 2320 and 2322 may include any transistor disclosed herein, such as planar transistor 500 and 3D transistor 600. As described in detail above with respect to transistors 500 and 600, in some embodiments, each transistor 2320 or 2322 includes a gate dielectric, and because the voltage applied to transistor 2320 is lower than the voltage applied to transistor 2322, the thickness of the gate dielectric of transistor 2320 (e.g., in LLV circuit 402) is less than the thickness of the gate dielectric of transistor 2322 (e.g., in LV circuit 404).

[0236] Furthermore, different voltages applied to the different transistors 2320, 2322, 2308, and 2310 in the first semiconductor structure 102 and the second semiconductor structure 104 can lead to differences in device dimensions between the first semiconductor structure 102 and the second semiconductor structure 104. In some embodiments, because the voltage applied to transistor 2308 is higher than the voltage applied to transistor 2320, the thickness of the gate dielectric of transistor 2308 (e.g., in HV circuit 406) is greater than the thickness of the gate dielectric of transistor 2320 (e.g., in LLV circuit 402). In some embodiments, because the voltages applied to transistors 2322 and 2310 are the same, the thickness of the gate dielectric of transistor 2322 (e.g., in LV circuit 404) is the same as the thickness of the gate dielectric of transistor 2310 (e.g., in LV circuit 404). In some embodiments, since the voltage applied to transistor 2308 is higher than the voltage applied to transistor 2320, the thickness of semiconductor layer 1004 in which transistor 2308 is formed (e.g., in HV circuit 406) is greater than the thickness of semiconductor layer 1002 in which transistor 2320 is formed (e.g., in LLV circuit 402).

[0237] like Figure 23A As shown, the first semiconductor structure 102 may further include an interconnect layer 2326 above and in contact with device layer 2314, through which electrical signals are transmitted from transistors 2320 and 2322 of peripheral circuits 2316 and 2318. Interconnect layer 2326 may include multiple interconnects, such as MEOL interconnects and BEOL interconnects. Interconnect layer 2326 may also include one or more ILD layers in which lateral lines and vias can be formed. Interconnects in interconnect layer 2326 may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. ILD layers in interconnect layer 2326 may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. In some embodiments, interconnects in interconnect layer 2326 include W, which has a relatively high thermal budget (compatible with high-temperature processes) and good quality (fewer defects, such as voids) among conductive metal materials.

[0238] like Figure 23A As shown, the first semiconductor structure 102 may further include one or more contacts 2330 extending vertically through the semiconductor layer 1002. In some embodiments, the contacts 2330 further extend through a dielectric layer (if present) on the back side of the semiconductor layer 1002 to make interconnect contact with the interconnect layer 2312 at the bonding interface 105. The contacts 2330 can thus couple the interconnects in the interconnect layer 2326 to the interconnects in the interconnect layer 2312 to make electrical connections through the semiconductor layer 1004 and across the bonding interface 105 between the first semiconductor structure 102 and the second semiconductor structure 104. The contacts 2330 may include a conductive material, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. In some embodiments, the contacts 2330 include W. In some embodiments, the contacts 2330 include vias surrounded by dielectric spacers (e.g., having silicon oxide) to electrically isolate the vias from the semiconductor layer 1002. Depending on the thickness of the semiconductor layer 1002, the contact 2330 can be an ILV with a depth in the submicron range (e.g., between 10 nm and 1 μm), or a TSV with a depth in the micron range or tens of micron range (e.g., between 1 μm and 100 μm).

[0239] like Figure 23A As shown, the first semiconductor structure may further include a polysilicon layer 106 above and in contact with the interconnect layer 2326. According to some embodiments, the polysilicon layer 106 is a doped polysilicon layer on the interconnect layer 2326, as described in detail below with respect to the manufacturing process. It should be understood that in some examples, trench isolation and doped regions (not shown) may also be formed in the polysilicon layer 106.

[0240] like Figure 23AAs shown, the first semiconductor structure 102 may further include an array of memory cells, such as an array of NAND memory strings 208 above and in contact with the polysilicon layer 106. The sources of the NAND memory strings 208 may be in contact with the polysilicon layer 106. In some embodiments, the polysilicon layer 106 is perpendicular between the NAND memory strings 208 and a device layer 2314 including transistors 2320 and 2322. In some embodiments, each NAND memory string 208 is a "charge-trapping" type NAND memory string, which includes any suitable channel structure disclosed herein, such as those described above relative to... Figure 8 The channel structure 812 is described in detail. In some embodiments, the NAND memory string 208 is a "floating gate" type NAND memory string, and the polysilicon layer 106 is the source plate of the floating gate type NAND memory string.

[0241] According to some implementations, each NAND memory string 208 extends vertically through multiple pairs of layers, each comprising a conductive layer and a dielectric layer. The stacked and interleaved conductive and dielectric layers are also referred to herein as a stacked layer structure, for example, a memory stack 2327. The memory stack 2327 may be... Figure 8 Examples of memory stack layer 804 include conductive layers and dielectric layers in memory stack layer 2327, which may be examples of gate conductive layer 806 and dielectric layer 808 in memory stack layer 804, respectively. According to some embodiments, the staggered conductive and dielectric layers in memory stack layer 2327 alternate in the vertical direction. Each conductive layer may include a gate electrode (gate line) surrounded by an adhesive layer and a gate dielectric layer. The gate electrode of the conductive layer may extend laterally as a word line, terminating at one or more stepped structures in memory stack layer 2327.

[0242] like Figure 23A As shown, the first semiconductor structure 102 may further include an interconnect layer 2328 above and in contact with the NAND memory string 208, for transmitting electrical signals to and from the NAND memory string 208. In some embodiments, the memory stack layer 2327 and the NAND memory string 208 are perpendicularly positioned between the interconnect layer 2328 and the polysilicon layer 106. The interconnect layer 2328 may include multiple interconnects, such as MEOL interconnects and BEOL interconnects. In some embodiments, the interconnects in the interconnect layer 2328 may also include local interconnects, such as bit line contacts and word line contacts. The interconnect layer 2328 may also include one or more ILD layers in which lateral lines and vias can be formed. The interconnects in the interconnect layer 2328 may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. The ILD layers in the interconnect layer 2328 may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0243] like Figure 23A As shown, the first semiconductor structure 102 may further include one or more contacts 2324 extending vertically through the polysilicon layer 106. In some embodiments, the contacts 2324 couple interconnects in interconnect layer 2328 to interconnects in interconnect layer 2326 to make electrical connections between NAND memory string 208 and transistors 2320 and 2322 through the polysilicon layer 106. The contacts 2324 may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. In some embodiments, the contacts 2324 include W or Cu. In some embodiments, the contacts 2324 include vias surrounded by dielectric spacers (e.g., having silicon oxide) to electrically isolate the vias from the polysilicon layer 106. Depending on the thickness of the polysilicon layer 106, the contacts 2324 may be ILVs with depths in the submicron range (e.g., between 10 nm and 1 μm) or TSVs with depths in the micron or tens of micron ranges (e.g., between 1 μm and 100 μm).

[0244] like Figure 23A As shown, the first semiconductor structure 102 may further include an interconnect layer 2328 and a pad-out interconnect layer 902 above the NAND memory string 208. In some embodiments, the NAND memory string 208 is vertically disposed between the pad-out interconnect layer 902 and the polysilicon layer 106. The pad-out interconnect layer 902 may include interconnects in one or more ILD layers, such as contact pads 2332. In some embodiments, for example, for pad-out purposes, the interconnects in the pad-out interconnect layer 902 may transmit electrical signals between the 3D memory device 2300 and external devices.

[0245] As a result, the peripheral circuits 2304, 2306, 2316, and 2318 in the second semiconductor structure 104 and the first semiconductor structure 102 can be coupled to the NAND memory string 208 in the first semiconductor structure 102 through various interconnect structures, including interconnect layers 2312, 2326, and 2328 and contacts 2324 and 2330. Furthermore, the peripheral circuits 2304, 2306, 2316, and 2318 in the 3D memory device 2300 and the NAND memory string 208 can be further coupled to external devices through the contact 2330 and pads leading out from the interconnect layer 902.

[0246] It should be understood that the pad leads of 3D memory devices are not limited to those from, for example... Figure 23A The first semiconductor structure 102 shown has a NAND memory string 208 and peripheral circuitry 2316 (corresponding to...) Figure 21A ), and can come from a second semiconductor structure 104 having peripheral circuitry 2304 (corresponding to Figure 21B For example, such as Figure 23B As shown, the 3D memory device 2301 may include a pad-out interconnect layer 902 in a second semiconductor structure 104. The pad-out interconnect layer 902 may contact the semiconductor layer 1004 of the second semiconductor structure 104, on which transistors 2308 of peripheral circuitry 2304 are formed. In some embodiments, the second semiconductor structure 104 further includes one or more contacts 2334 extending vertically through the semiconductor layer 1004. In some embodiments, the contacts 2334 couple interconnects in the interconnect layer 2312 of the second semiconductor structure 104 to contact pads 2332 in the pad-out interconnect layer 902 for electrical connection through the semiconductor layer 1004. The contacts 2334 may include a conductive material, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. In some embodiments, the contacts 2334 include W. In some embodiments, the contacts 2334 include vias surrounded by dielectric spacers (e.g., having silicon oxide) to electrically isolate the vias from the semiconductor layer 1004. Depending on the thickness of the semiconductor layer 1004, the contact 2334 can be an ILV with a thickness in the submicron range (e.g., between 10 nm and 1 μm), or a TSV with a depth in the micron range or tens of micron range (e.g., between 1 μm and 100 μm).

[0247] like Figure 23B As shown, the first semiconductor structure 102 may further include a passivation layer 2350, which replaces... Figure 23A The first semiconductor structure 102 has pads leading out from the interconnect layer 902 to protect and encapsulate the 3D memory device 2301 from the side of the first semiconductor structure 102 without pads. The passivation layer 2350 may include a dielectric material such as silicon nitride and / or silicon oxide. In some embodiments, the first semiconductor structure 102 in the 3D memory device 2301 also includes an operational / carrier substrate 2351 in contact with the passivation layer 2350, serving as a base substrate for support of the 3D memory device 2301. It should be understood that in some examples, the passivation layer 2350 may be omitted or combined with the operational substrate 2351 as a single layer for support and protection.

[0248] It should also be understood that, in some examples, the first semiconductor structure 102 and the second semiconductor structure 104 of the 3D memory device 2301 may also include bonding layers 1012 and 1014 at the bonding interface 105 (on opposite sides of the bonding interface 105), such as Figure 23BAs shown. That is, in contrast to transfer bonding, the bonding interface 105 can be generated by hybrid bonding. A bonding layer 1012 can be disposed between the bonding interface 105 and the interconnect layer 2312, and a bonding layer 1014 can be disposed between the bonding interface 105 and the semiconductor layer 1002. In some embodiments, the bonding layer 1014 is formed on the back side of the semiconductor layer 1002 (e.g., a thinned silicon substrate) opposite to the front side on which the device layer 2314 is formed. In practice, the bonding interface 105 can be a layer of a specific thickness, comprising the top surface of the bonding layer 1012 of the second semiconductor structure 104 and the bottom surface of the bonding layer 1014 of the first semiconductor structure 102.

[0249] Bonding layers 1012 and 1014 may include a dielectric material comprising multiple bonding contacts and electrically isolating bonding contacts. The bonding contacts may comprise conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. In some embodiments, the bonding contacts of bonding layers 1012 and 1014 comprise Cu. The remaining regions of bonding layers 1012 and 1014 may be formed of a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. The bonding contacts and surrounding dielectric in bonding layers 1012 and 1014 can be used for hybrid bonding (also known as “metal / dielectric hybrid bonding”), a direct bonding technique (e.g., forming a bond between surfaces without using an intermediate layer, such as solder or adhesive), and can simultaneously achieve metal-to-metal (e.g., Cu-Cu) bonding and dielectric-to-dielectric (e.g., SiO2-SiO2) bonding.

[0250] Figures 24A-24F This disclosure illustrates some aspects of the formation of Figure 22A and 22B The manufacturing process of 3D memory devices. Figure 26 This disclosure illustrates some aspects of the formation of Figure 22A and 22B The flowchart of the method 2600 for 3D memory devices. Figures 24A-24F Examples of 3D memory devices shown in Figure 26 include: Figure 23A The 3D memory device 2300 shown is described together. Figures 24A-24F And 26. It should be understood that the operations shown in method 2600 are not exhaustive, and other operations may be performed before, after, or between any of the operations shown. Furthermore, some operations may be performed simultaneously, or in conjunction with... Figure 26 The different execution orders shown.

[0251] refer to Figure 26Method 2600 begins with operation 2602, wherein a first transistor is formed on a first substrate. The first substrate may be a silicon substrate having monocrystalline silicon. Figure 24A As shown, a plurality of transistors 2404 and 2406 are formed on a silicon substrate 2402. Transistors 2404 and 2406 can be formed by a variety of processes, including but not limited to photolithography, dry / wet etching, thin film deposition, thermal growth, implantation, CMP, and any other suitable process. In some embodiments, doped regions are formed in the silicon substrate 2402 by ion implantation and / or thermal diffusion, which serve, for example, as the well and source / drain regions of transistors 2404 and 2406. In some embodiments, isolation regions (e.g., STI) are also formed in the silicon substrate 2402 by wet / dry etching and thin film deposition. In some embodiments, the thickness of the gate dielectric of transistor 2404 differs from the thickness of the gate dielectric of transistor 2406, for example, by depositing a thicker silicon oxide film in a region of transistor 2404 than in a region of transistor 2406, or by etching back a portion of the silicon oxide film deposited in a region of transistor 2406. It should be understood that the details of fabricating transistors 2404 and 2406 may depend on the type of transistor (e.g., Figure 5A , 5B The variations are due to the planar transistor 500 or 3D transistor 600 in 6A and 6B, and therefore will not be elaborated further for the sake of description.

[0252] In some embodiments, an interconnect layer 2408 is formed over the transistors on the first substrate. The interconnect layer may include multiple interconnects within one or more ILD layers. Figure 24A As shown, an interconnect layer 2408 can be formed over transistors 2404 and 2406. The interconnect layer 2408 may include MEOL and / or BEOL interconnects in a plurality of ILD layers for electrical connection to transistors 2404 and 2406. In some embodiments, the interconnect layer 2408 includes a plurality of ILD layers and interconnects formed therein using a plurality of processes. For example, the interconnects in the interconnect layer 2408 may include conductive materials deposited by one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof). The fabrication process forming the interconnects may also include photolithography, CMP, wet / dry etching, or any other suitable process. The ILD layers may include dielectric materials deposited by one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, or any combination thereof). Figure 24A The ILD layer and interconnects shown can be collectively referred to as interconnect layer 2408. In some embodiments, the interconnects in interconnect layer 2408 include W, which has a relatively high thermal budget in a conductive metallic material to withstand subsequent high-temperature processes.

[0253] Method 2600 proceeds to operation 2604, such as... Figure 26 As shown, a semiconductor layer is formed over a first transistor. The semiconductor layer may include monocrystalline silicon. In some embodiments, to form the semiconductor layer, another substrate is bonded to the first substrate face-to-face, and the other substrate is thinned to leave the semiconductor layer. Bonding may include transfer bonding. The other substrate may be a silicon substrate having monocrystalline silicon.

[0254] like Figure 24B As shown, a semiconductor layer 2410, such as a single-crystal silicon layer, is formed over interconnect layer 2408 and transistors 2404 and 2406. Semiconductor layer 2410 may be attached over interconnect layer 2408 to form a bonding interface 2412 perpendicularly between semiconductor layer 2410 and interconnect layer 2408. In some embodiments, multiple dielectric layers (e.g., silicon oxide layers) are formed between bonding interface 2412 and semiconductor layer 2410 and / or between bonding interface 2412 and interconnect layer 2408 to facilitate transfer bonding of semiconductor layer 2410. In some embodiments, to form semiconductor layer 2410, transfer bonding is used to bond another silicon substrate (e.g., components formed on silicon substrate 2402, such as transistors 2404 and 2406, facing the other silicon substrate) in a face-to-face manner. Figure 24B (Not shown in the image) and a silicon substrate 2402, thereby forming a bonding interface 2412. Another silicon substrate can then be thinned using any suitable process to leave a semiconductor layer 2410 attached above the interconnect layer 2408. See above reference... Figures 34A-34D and Figures 35A-35D The details of various transfer bonding processes have been described, so they will not be repeated for the sake of simplicity.

[0255] Method 2600 proceeds to operation 2606, in which a second transistor is formed on the semiconductor layer. For example... Figure 24CAs shown, a plurality of transistors 2414 and 2416 are formed on a semiconductor layer 2410 having monocrystalline silicon. Transistors 2414 and 2416 can be formed by a variety of processes, including but not limited to photolithography, dry / wet etching, thin film deposition, thermal growth, implantation, CMP, and any other suitable process. In some embodiments, doped regions are formed in the semiconductor layer 2410 by ion implantation and / or thermal diffusion, which serve, for example, as the well and source / drain regions of transistors 2414 and 2416. In some embodiments, isolation regions (e.g., STI) are also formed in the semiconductor layer 2410 by wet / dry etching and thin film deposition. In some embodiments, the thickness of the gate dielectric of transistor 2414 differs from the thickness of the gate dielectric of transistor 2416, for example, by depositing a thicker silicon oxide film in a region of transistor 2414 than in a region of transistor 2416, or by etching back a portion of the silicon oxide film deposited in a region of transistor 2416. It should be understood that the details of fabricating transistors 2414 and 2416 may depend on the type of transistor (e.g., Figure 5A , 5B The variations are due to the planar transistor 500 or 3D transistor 600 in 6A and 6B, and therefore will not be elaborated further for the sake of description.

[0256] In some implementations, an interconnect layer is formed over the transistor. The interconnect layer may include multiple interconnects within one or more ILD layers. For example... Figure 24C As shown, an interconnect layer 2420 can be formed over transistors 2414 and 2416. The interconnect layer 2420 may include MEOL and / or BEOL interconnects in a plurality of ILD layers for electrical connection to transistors 2414 and 2416. In some embodiments, the interconnect layer 2420 includes a plurality of ILD layers and interconnects formed therein using a plurality of processes. For example, the interconnects in the interconnect layer 2420 may include conductive materials deposited by one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof). The fabrication process forming the interconnects may also include photolithography, CMP, wet / dry etching, or any other suitable process. The ILD layers may include dielectric materials deposited by one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, or any combination thereof). Figure 24C The ILD layer and interconnects shown can be collectively referred to as interconnect layer 2420. In some embodiments, the interconnects in interconnect layer 2420 include W, which has a relatively high thermal budget in a conductive metallic material to withstand subsequent high-temperature processes.

[0257] In some embodiments, contacts are formed through the semiconductor layer. Contact 2418 may extend perpendicularly through the semiconductor layer 2410 from the front side. Contact 2418 may be coupled to an interconnect in interconnect layer 2420. Contact 2418 may further extend through a dielectric layer (if present) on the back side of semiconductor layer 2410 to align and contact an interconnect in interconnect layer 2408 at bonding interface 2412. Thus, contact 2418 couples the interconnect in interconnect layer 2408 to the interconnect in interconnect layer 2420 through semiconductor layer 2410 and across bonding interface 2412. Contact 2418 may be formed by first patterning contact holes in semiconductor layer 2410 using a patterning process (e.g., photolithography and dry / wet etching of the dielectric material in the dielectric layer). Contact holes may be filled with a conductor (e.g., W). In some embodiments, filling contact holes includes depositing a spacer (e.g., a silicon oxide layer) before depositing a conductor.

[0258] Method 2600 proceeds to operation 2608, such as... Figure 26 As shown, a polysilicon layer is formed above the second transistor. Figure 24D As shown, a polysilicon layer 2411 is formed over the interconnect layer 2420 and transistors 2414 and 2416 on the semiconductor layer 2410. The polysilicon layer 2411 can be formed by depositing polysilicon on the interconnect layer 2420 using one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, or any combination thereof). In some embodiments, the polysilicon layer 2411 is doped with a P-type or N-type dopant using an in-situ doping process during or after the deposition process, or during an ion implantation / diffusion process.

[0259] Method 2600 proceeds to operation 2010, such as... Figure 26 As shown, an array of NAND memory strings is formed on a polysilicon layer. In some embodiments, a memory stack layer is formed on the polysilicon layer to form the array of NAND memory strings. Figure 24E As shown, a stacked layer structure is formed on the polysilicon layer 2411, such as a memory stacked layer 2426 including staggered conductive and dielectric layers. In order to form the memory stacked layer 2426, in some embodiments, a dielectric stacked layer (not shown) including staggered sacrificial layers (not shown) and dielectric layers is formed on the polysilicon layer 2411.

[0260] In some embodiments, each sacrificial layer comprises a silicon nitride layer, and each dielectric layer comprises a silicon oxide layer. The staggered sacrificial and dielectric layers can be formed using one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, or any combination thereof). The memory stack 2426 can then be formed using a gate replacement process, for example, by replacing the sacrificial layers with conductive layers using a wet / dry etching process selectively applied to the dielectric layers, and filling the resulting trenches with the conductive layers. In some embodiments, each conductive layer comprises a metal layer, such as a W layer. It should be understood that in some examples, the memory stack 2426 can be formed by alternately depositing conductive layers (e.g., doped polysilicon layers) and dielectric layers (e.g., silicon oxide layers) without a gate replacement process.

[0261] In some embodiments, a pad oxide layer comprising silicon oxide is formed between the memory stack layer 2426 and the polysilicon layer 2411.

[0262] like Figure 24E As shown, a NAND memory string 2428 is formed over a polysilicon layer 2411, with each string extending vertically through a memory stack layer 2426 to contact the polysilicon layer 2411. In some embodiments, the fabrication process for forming the NAND memory string 2428 includes forming channel vias through the memory stack layer 2426 (or dielectric stack layer) and into the polysilicon layer 2411 using dry etching and / or wet etching (e.g., DRIE), followed by filling the channel vias with multiple layers (e.g., memory films (e.g., tunneling layers, storage layers, and barrier layers) and semiconductor layers) using thin-film deposition processes (e.g., ALD, CVD, PVD, or any combination thereof). It should be understood that the details of fabricating the NAND memory string 2428 can depend on the type of channel structure of the NAND memory string 2428 (e.g., Figure 8 The channel structure (812) varies, and therefore will not be elaborated further for ease of description.

[0263] In some implementations, an interconnect layer is formed above an array of NAND memory strings. The interconnect layer may include a plurality of interconnects within one or more ILD layers. Figure 24EAs shown, an interconnect layer 2430 is formed over the memory stack layer 2426 and the NAND memory string 2428. The interconnect layer 2430 may include interconnects of MEOL and / or BEOL in a plurality of ILD layers for electrical connection to the NAND memory string 2428. In some embodiments, the interconnect layer 2430 includes a plurality of ILD layers and interconnects formed therein using a plurality of processes. For example, the interconnects in the interconnect layer 2430 may include conductive materials deposited by one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof). The fabrication processes forming the interconnects may also include photolithography, CMP, wet / dry etching, or any other suitable process. The ILD layers may include dielectric materials deposited by one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, or any combination thereof). Figure 24E The ILD layer and interconnect shown can be collectively referred to as interconnect layer 2430.

[0264] In some implementations, contacts are formed through the polysilicon layer. For example... Figure 24E As shown, one or more contacts 2417 are formed, each extending vertically through the polysilicon layer 2411. The contacts 2417 can couple interconnects in interconnect layers 2430 and 2408. The contacts 2417 can be formed by first patterning contact holes through the polysilicon layer 2411 using a patterning process (e.g., photolithography and dry / wet etching of the dielectric material in the dielectric layer). The contact holes can be filled with a conductor (e.g., W or Cu). In some embodiments, filling the contact holes includes depositing a spacer (e.g., a silicon oxide layer) before depositing the conductor.

[0265] Method 2600 skips optional operation 2612 and proceeds to operation 2614, such as... Figure 26 As shown, an interconnect layer with pads is formed. This interconnect layer can be formed above the array of NAND memory strings. Figure 24F As shown, a pad-lead interconnect layer 2436 is formed above the interconnect layer 2430 and the NAND memory string 2428 on the polysilicon layer 2411. The pad-lead interconnect layer 2436 may include interconnects formed in one or more ILD layers, such as contact pads 2438. The contact pads 2438 may include conductive materials, including but not limited to W, Co, Cu, Al, doped silicon, silicides, or any combination thereof. The ILD layer may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0266] In some embodiments, in order to form pads to lead out interconnect layers on the first substrate, after operation 2610, method 2600 proceeds to optional operation 2612, such as... Figure 26As shown, the first substrate is thinned. It should be understood that, although not shown, in some examples, processes including, but not limited to, wafer grinding, dry etching, wet etching, CMP, any other suitable process, or any combination thereof, can be used to thin the silicon substrate 2402. Figure 24E (As shown) to form a semiconductor layer with monocrystalline silicon. After thinning, for example by wet / dry etching, followed by deposition of a dielectric material as spacers and a conductive material as conductors, contacts extending vertically through the thinned silicon substrate 2402 can be formed. It should be understood that in some examples, the contacts may be formed in the silicon substrate 2402 before thinning and exposed from the back side of the silicon substrate 2402 (at the location where thinning occurs) after thinning.

[0267] Method 2600 proceeds to operation 2614, such as... Figure 26 As shown, a pad-out interconnect layer is formed therein. The pad-out interconnect layer can be formed on a thinned first substrate. It should be understood that, although not shown, in some examples, a pad-out interconnect layer with contact pads can be formed on a thinned silicon substrate 2402.

[0268] Figure 25A-25G This disclosure illustrates some aspects of the formation of Figure 22A and 22B Another manufacturing process for 3D memory devices. Figure 27 This disclosure illustrates some aspects of the formation of Figure 22A and 22B The flowchart of another method 2700 for 3D memory devices. Figure 25A-25G Examples of 3D memory devices shown in Figure 27 include: Figure 23B The 3D memory device 2301 shown is described together. Figure 25A-25G And 27. It should be understood that the operations shown in method 2700 are not exhaustive, and other operations may be performed before, after, or between any of the operations shown. Furthermore, some operations may be performed simultaneously, or in conjunction with... Figure 27 The different execution orders shown.

[0269] refer to Figure 27 Method 2700 begins with operation 2702, wherein a first transistor is formed on the front side of a first substrate. The first substrate may be a silicon substrate having monocrystalline silicon. Figure 25AAs shown, a plurality of transistors 2514 and 2516 are formed on the front side of silicon substrate 2510. Transistors 2514 and 2516 can be formed by a variety of processes, including but not limited to photolithography, dry / wet etching, thin film deposition, thermal growth, implantation, CMP, and any other suitable process. In some embodiments, doped regions are formed in silicon substrate 2510 by ion implantation and / or thermal diffusion, which serve, for example, as well as the well and source / drain regions of transistors 2514 and 2516. In some embodiments, isolation regions (e.g., STI) are also formed in silicon substrate 2510 by wet / dry etching and thin film deposition. In some embodiments, the thickness of the gate dielectric of transistor 2514 differs from the thickness of the gate dielectric of transistor 2516, for example, by depositing a thicker silicon oxide film in the region of transistor 2514 than in the region of transistor 2516, or by etching back a portion of the silicon oxide film deposited in the region of transistor 2516. It should be understood that the details of fabricating transistors 2514 and 2516 may depend on the type of transistor (e.g., Figure 5A , 5B The variations are due to the planar transistor 500 or 3D transistor 600 in 6A and 6B, and therefore will not be elaborated further for the sake of description.

[0270] In some embodiments, an interconnect layer 2520 is formed over the transistors on the first substrate. The interconnect layer may include multiple interconnects within one or more ILD layers. Figure 25A As shown, an interconnect layer 2520 can be formed over transistors 2514 and 2516. The interconnect layer 2520 may include MEOL and / or BEOL interconnects in a plurality of ILD layers for electrical connection to transistors 2514 and 2516. In some embodiments, the interconnect layer 2520 includes a plurality of ILD layers and interconnects formed therein using a plurality of processes. For example, the interconnects in the interconnect layer 2520 may include conductive materials deposited by one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof). The fabrication process forming the interconnects may also include photolithography, CMP, wet / dry etching, or any other suitable process. The ILD layers may include dielectric materials deposited by one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, or any combination thereof). Figure 25A The ILD layer and interconnects shown can be collectively referred to as interconnect layer 2520. In some embodiments, the interconnects in interconnect layer 2508 include W, which has a relatively high thermal budget in a conductive metallic material to withstand subsequent high-temperature processes.

[0271] In some embodiments, contacts are formed through a thinned first substrate. For example... Figure 25AAs shown, contacts 2518 are formed extending vertically from the front side of silicon substrate 2510 into silicon substrate 2510. Contacts 2518 can be coupled to interconnects in interconnect layer 2520. Contacts 2518 can be formed by first patterning contact holes in silicon substrate 2510 using a patterning process (e.g., photolithography and dry / wet etching of dielectric material in dielectric layer). Contact holes can be filled with a conductor (e.g., Cu). In some embodiments, filling contact holes includes depositing a spacer (e.g., silicon oxide layer) before depositing a conductor.

[0272] Method 2700 proceeds to operation 2704, such as... Figure 27 As shown, a polysilicon layer is formed above the first transistor. Figure 25B As shown, a polysilicon layer 2511 is formed over the interconnect layer 2520 and transistors 2514 and 2516 on the first silicon substrate 2510. The polysilicon layer 2511 can be formed by depositing polysilicon on the interconnect layer 2520 using one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, or any combination thereof). In some embodiments, the polysilicon layer 2511 is doped with a P-type or N-type dopant using an in-situ doping process during or after the deposition process, or during an ion implantation / diffusion process.

[0273] Method 2700 proceeds to operation 2706, such as... Figure 27 As shown, an array of NAND memory strings is formed on a polysilicon layer. In some embodiments, a memory stack layer is formed on the polysilicon layer to form the array of NAND memory strings. Figure 25C As shown, a stacked layer structure is formed on the polysilicon layer 2511, such as a memory stacked layer 2526 including staggered conductive and dielectric layers. In order to form the memory stacked layer 2526, in some embodiments, a dielectric stacked layer (not shown) including staggered sacrificial layers (not shown) and dielectric layers is formed on the polysilicon layer 2511.

[0274] In some embodiments, each sacrificial layer includes a silicon nitride layer, and each dielectric layer includes a silicon oxide layer. The staggered sacrificial and dielectric layers can be formed by one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, or any combination thereof). The memory stack 2526 can then be formed by a gate replacement process, for example, by replacing the sacrificial layers with a conductive layer using a wet / dry etching process with a sacrificial layer selective for the dielectric layers, and filling the resulting trenches with the conductive layer.

[0275] In some implementations, each conductive layer includes a metal layer, such as a W layer. It should be understood that in some examples, the memory stack layer 2526 can be formed by alternately depositing conductive layers (e.g., doped polysilicon layers) and dielectric layers (e.g., silicon oxide layers) without a gate replacement process.

[0276] In some embodiments, a pad oxide layer comprising silicon oxide is formed between the memory stack layer 2526 and the polysilicon layer 2511.

[0277] like Figure 25C As shown, a NAND memory string 2528 is formed over a polysilicon layer 2511, with each string extending vertically through a memory stack layer 2526 to contact the polysilicon layer 2511. In some embodiments, the fabrication process for forming the NAND memory string 2528 includes forming channel vias through the memory stack layer 2526 (or dielectric stack layer) and into the polysilicon layer 2511 using dry etching and / or wet etching (e.g., DRIE), followed by filling the channel vias with multiple layers (e.g., memory films (e.g., tunneling layers, storage layers, and barrier layers) and semiconductor layers) using thin-film deposition processes (e.g., ALD, CVD, PVD, or any combination thereof). It should be understood that the details of fabricating the NAND memory string 2528 can depend on the type of channel structure of the NAND memory string 2528 (e.g., Figure 8 The channel structure (812) varies, and therefore will not be elaborated further for ease of description.

[0278] In some implementations, an interconnect layer is formed above an array of NAND memory strings. The interconnect layer may include a plurality of interconnects within one or more ILD layers. Figure 25C As shown, an interconnect layer 2530 is formed over the memory stack layer 2526 and the NAND memory string 2528. The interconnect layer 2530 may include interconnects of MEOL and / or BEOL in a plurality of ILD layers for electrical connection to the NAND memory string 2528. In some embodiments, the interconnect layer 2530 includes a plurality of ILD layers and interconnects formed therein using a plurality of processes. For example, the interconnects in the interconnect layer 2530 may include conductive materials deposited by one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof). The fabrication processes forming the interconnects may also include photolithography, CMP, wet / dry etching, or any other suitable process. The ILD layers may include dielectric materials deposited by one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, or any combination thereof). Figure 25C The ILD layer and interconnect shown can be collectively referred to as interconnect layer 2530.

[0279] In some implementations, contacts are formed through the polysilicon layer. For example... Figure 25C As shown, one or more contacts 2517 are formed, each extending vertically through the polysilicon layer 2511. The contacts 2517 can couple interconnects in interconnect layers 2530 and 2508. The contacts 2517 can be formed by first patterning contact holes through the polysilicon layer 2511 using a patterning process (e.g., photolithography and dry / wet etching of the dielectric material in the dielectric layer). The contact holes can be filled with a conductor (e.g., W or Cu). In some embodiments, filling the contact holes includes depositing a spacer (e.g., a silicon oxide layer) before depositing the conductor.

[0280] In some embodiments, the first substrate is thinned. For example... Figure 25E As shown, the silicon substrate 2510 (as shown) Figure 25C The silicon substrate 2510 is thinned to become a semiconductor layer 2509 having monocrystalline silicon. The silicon substrate 2510 can be thinned by processes including, but not limited to, wafer grinding, dry etching, wet etching, CMP, any other suitable process, or any combination thereof. For example, the thickness of the semiconductor layer 2509 can be controlled by controlling the duration of the CMP process to expose the contacts 2518 from the back side of the thinned silicon substrate 2510. It should be understood that in some examples, contrary to before thinning in the silicon substrate 2510, the contacts 2518 can be formed from the back side of the semiconductor layer 2509 after thinning. In some embodiments, prior to thinning, a passivation layer 2523 is formed on the interconnect layer 2530 by depositing a dielectric material such as silicon nitride on the interconnect layer 2530 using one or more thin-film deposition processes (including but not limited to CVD, PVD, ALD, or any combination thereof). Then, prior to thinning, the operating substrate 2501 can be attached to the passivation layer 2523, for example, using adhesive bonding, to allow subsequent backside processing of the silicon substrate 2510, such as thinning, contact formation, and bonding.

[0281] In some embodiments, a first bonding layer is formed on the back side of a thinned first substrate. The first bonding layer may include a plurality of first bonding contacts. For example... Figure 25EAs shown, a bonding layer 2522 is formed on the back side of semiconductor layer 2509 (i.e., thinned silicon substrate 2510). Bonding layer 2522 may include a plurality of bonding contacts surrounded by a dielectric. In some embodiments, a dielectric layer is deposited on the back side of semiconductor layer 2509 (opposite to the front side where transistors 2514 and 2516 are formed) by one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, or any combination thereof). Bonding contacts that penetrate the dielectric layer and contact the contacts 2518 on the back side of the thinned silicon substrate 2510 can then be formed by first patterning contact holes through the dielectric layer using a patterning process (e.g., photolithography and dry / wet etching of the dielectric material in the dielectric layer). The contact holes may be filled with a conductor (e.g., Cu). In some embodiments, filling the contact holes includes depositing an adhesive layer, a barrier layer, and / or a seed layer prior to depositing the conductor.

[0282] Method 2700 proceeds to operation 2708, such as... Figure 27 As shown, a second transistor is formed on a second substrate. The second substrate can be a silicon substrate with monocrystalline silicon. Figure 25D As shown, a plurality of transistors 2504 and 2506 are formed on a silicon substrate 2502 having monocrystalline silicon. Transistors 2504 and 2506 can be formed by a variety of processes, including but not limited to photolithography, dry / wet etching, thin film deposition, thermal growth, implantation, CMP, and any other suitable process. In some embodiments, doped regions are formed in the silicon substrate 2502 by ion implantation and / or thermal diffusion, which serve, for example, as the well and source / drain regions of transistors 2504 and 2506. In some embodiments, isolation regions (e.g., STI) are also formed in the silicon substrate 2502 by wet / dry etching and thin film deposition. In some embodiments, the thickness of the gate dielectric of transistor 2504 differs from the thickness of the gate dielectric of transistor 2506, for example, by depositing a thicker silicon oxide film in regions of transistor 2504 than in regions of transistor 2506, or by etching back a portion of the silicon oxide film deposited in regions of transistor 2506. It should be understood that the details of fabricating transistors 2504 and 2506 can depend on the type of transistor (e.g., Figure 5A , 5B The variations are due to the planar transistor 500 or 3D transistor 600 in 6A and 6B, and therefore will not be elaborated further for ease of description.

[0283] In some embodiments, an interconnect layer is formed over the transistors on the second substrate. The interconnect layer may include multiple interconnects within one or more ILD layers. For example... Figure 25DAs shown, an interconnect layer 2508 can be formed over transistors 2504 and 2506. Interconnect layer 2508 may include interconnects of MEOL and / or BEOL in multiple ILD layers for electrical connection to transistors 2504 and 2506. In some embodiments, interconnect layer 2508 includes multiple ILD layers and interconnects formed therein using multiple processes. For example, interconnects in interconnect layer 2508 may include conductive materials deposited by one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof). The fabrication process forming the interconnects may also include photolithography, CMP, wet / dry etching, or any other suitable process. The ILD layers may include dielectric materials deposited by one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, or any combination thereof). Figure 25D The ILD layer and interconnects shown can be collectively referred to as interconnect layer 2520. Unlike interconnect layer 2520, in some embodiments, the interconnects in interconnect layer 2508 comprise Cu, which has a relatively low resistivity among conductive metal materials. It should be understood that although Cu has a relatively low thermal budget (incompatible with high-temperature processes), it becomes feasible to use Cu as the conductive material for the interconnects in interconnect layer 2508 because no high-temperature processes are performed after the fabrication of interconnect layer 2508.

[0284] In some implementations, a second bonding layer is formed over the interconnect layer. The second bonding layer may include a plurality of second bonding contacts. For example... Figure 25D As shown, a bonding layer 2521 is formed on interconnect layer 2508. Bonding layer 2521 may include a plurality of bonding contacts surrounded by a dielectric. In some embodiments, a dielectric layer is deposited on the top surface of interconnect layer 2508 by one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, or any combination thereof). Then, by first patterning contact holes through the dielectric layer using a patterning process (e.g., photolithography and dry / wet etching of the dielectric material in the dielectric layer), bonding contacts that penetrate the dielectric layer and contact the interconnects in interconnect layer 2508 can be formed. The contact holes may be filled with a conductor (e.g., Cu). In some embodiments, filling the contact holes includes depositing an adhesive layer, a barrier layer, and / or a seed layer prior to depositing the conductor.

[0285] Method 2700 proceeds to operation 2710, such as... Figure 27 As shown, a first substrate and a second substrate are bonded back-to-back. After bonding the first and second substrates, a first bonding contact in the first bonding layer can contact a second bonding contact in the second bonding layer at the bonding interface. Bonding may include hybrid bonding.

[0286] like Figure 25FAs shown, the thinned silicon substrate 2510 (i.e., semiconductor layer 2509) and components formed thereon (e.g., transistors 2514 and 2516 and NAND memory string 2528) are bonded to the silicon substrate 2502 and components formed thereon (e.g., transistors 2504 and 2506) in a face-to-face manner, with the bonding layer 2521 facing upward on the front side of the silicon substrate 2502 and the bonding layer 2522 facing downward on the back side of the thinned silicon substrate 2510, thereby forming a bonding interface 2524. That is, the thinned silicon substrate 2510 and components formed thereon can be bonded to the silicon substrate 2502 and components formed thereon in a back-to-face manner, such that the bonding contacts in the bonding layer 2521 and the bonding contacts in the bonding layer 2522 contact at the bonding interface 2524. In some embodiments, a processing technique, such as plasma treatment, wet treatment, and / or heat treatment, is applied to the bonding surfaces prior to bonding. As a result of bonding (e.g., hybrid bonding), the bonding contacts on opposite sides of the bonding interface 2524 can be mixed with each other. After bonding, according to some embodiments, the bonding contacts in the bonding layer 2521 and the bonding contacts in the bonding layer 2522 are aligned and contacted with each other, such that the memory stack layer 2526 and the NAND memory string 2528 formed therethrough, as well as transistors 2514 and 2516, can be coupled to transistors 2504 and 2506 across the bonding interface 2524 via the bonded bonding contacts.

[0287] Method 2700 proceeds to optional operation 2712, such as... Figure 27 As shown, the second substrate is thinned. Figure 25F As shown, silicon substrate 2502 ( Figure 25E The silicon substrate 2502 (as shown) is thinned to become a semiconductor layer 2503 having monocrystalline silicon. The silicon substrate 2502 can be thinned by processes including but not limited to wafer grinding, dry etching, wet etching, CMP, any other suitable process or any combination thereof.

[0288] Method 2700 proceeds to operation 2714, such as... Figure 27 As shown, a pad-out interconnect layer is formed therein. The pad-out interconnect layer can be formed on a thinned second substrate. As... Figure 25FAs shown, a pad-out interconnect layer 2536 is formed on a semiconductor layer 2503 (thinned silicon substrate 2502). The pad-out interconnect layer 2536 may include interconnects formed in one or more ILD layers, such as contact pads 2538. Contact pads 2538 may include conductive materials, including but not limited to W, Co, Cu, Al, doped silicon, silicides, or any combination thereof. The ILD layers may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. In some embodiments, after bonding and thinning, contacts 2534 extending vertically through the semiconductor layer 2503 are formed, for example by wet / dry etching, followed by deposition of a dielectric material as a spacer and a conductive material as a conductor. Contacts 2534 can couple the contact pads 2538 in the pad-out interconnect layer 2536 to the interconnects in the interconnect layer 2508. It should be understood that in some examples, contacts 2534 may be formed before thinning (e.g., Figure 25F The semiconductor layer 2503 shown is formed in the silicon substrate 2502 and exposed from the back side of the silicon substrate 2502 (at the location where the thinning occurs) after thinning.

[0289] In some implementations, after operation 2710, optional operation 2712 is skipped, and method 2700 proceeds to operation 2714, such as... Figure 27 As shown, an interconnect layer with pads is formed. This interconnect layer can be formed above the array of NAND memory strings. Although in Figure 25F Although not shown, it should be understood that in some examples, after removing the operating substrate 2501 and the passivation layer 2523, a pad-out interconnect layer with contact pads may be formed over the interconnect layer 2530 and the NAND memory string 2528.

[0290] Figure 28A and 28B Some aspects of this disclosure are shown. Figure 21A and 21B A schematic diagram of a cross-section of the 3D memory devices shown. 3D memory devices 2800 and 2801 can be... Figure 21A and 21B Examples of 3D memory devices 2100 and 2101. (See example...) Figure 28A As shown, the 3D memory device 2800 may include a stacked first semiconductor structure 102 and a second semiconductor structure 104. In some embodiments, the first semiconductor structure 102 includes a semiconductor layer 1002, a bonding layer 1014, a memory cell array, some peripheral circuitry in peripheral circuitry vertically between the semiconductor layer 1002 and the polysilicon layer 106, and the polysilicon layer 106 vertically between the memory cell array and the peripheral circuitry.

[0291] The memory cell array may include an array of NAND memory strings (e.g., NAND memory string 208 disclosed herein), and the source of the array of NAND memory strings may be in contact with the polysilicon layer 106 (e.g., as shown in the image). Figure 8 (As shown in the diagram). The polysilicon layer 106 may be a deposited polysilicon layer (e.g., N-type doped, P-type doped, or undoped), suitable for channel structures in "floating gate" type NAND memory strings or, for example, "charge trap" type NAND memory strings suitable for GIDL erase operations (e.g., Figure 8 Certain designs of the channel structure 812 in the first semiconductor structure 102. Through-contacts (e.g., ILV / TSV) through the polysilicon layer 106 enable direct, short-distance (e.g., submicron or micron-scale) electrical connections between the memory cell array in the first semiconductor structure 102 and peripheral circuitry. The bonding layer 1014 may include dielectrics for conductive bonding contacts (not shown) and electrically isolating bonding contacts, which can be used for hybrid bonding, as described in detail below.

[0292] In some embodiments, the peripheral circuitry in the first semiconductor structure 102 contacts the semiconductor layer 1002 but not the polysilicon layer 106. That is, the transistors of the peripheral circuitry (e.g., planar transistor 500 and 3D transistor 600) may contact the semiconductor layer 1002. The semiconductor layer 1002 may include a semiconductor material, such as monocrystalline silicon (e.g., a silicon substrate or a thinned silicon substrate). It should be understood that in some examples, unlike the polysilicon layer 106 in the first semiconductor structure 102, the semiconductor layer 1002 on which transistors are formed may include monocrystalline silicon, but not polycrystalline silicon, due to the superior carrier mobility of monocrystalline silicon desired for transistor performance. The peripheral circuitry and the bonding layer 1014 may be formed on opposite sides of the semiconductor layer 1002, such that the semiconductor layer 1002 is vertically disposed between the peripheral circuitry and the bonding layer 1014. In some embodiments, transistors of peripheral circuits are formed on the front side of semiconductor layer 1002, and bonding contacts of bonding layer 1014 are formed on the back side of semiconductor layer 1002.

[0293] In some embodiments, the second semiconductor structure 104 includes a bonding layer 1012, some peripheral circuitry in the peripheral circuitry of the memory cell array, and a semiconductor layer 1004 perpendicularly disposed between the peripheral circuitry and the bonding layer 1012. Transistors of the peripheral circuitry (e.g., planar transistors 500 and 3D transistors 600) may be in frontal contact with the semiconductor layer 1004. Similar to semiconductor layer 1002, semiconductor layer 1004 may include a semiconductor material such as monocrystalline silicon (e.g., a silicon substrate or a thinned silicon substrate). It should be understood that in some examples, unlike the polycrystalline silicon layer 106 in the first semiconductor structure 102, the semiconductor layer 1004 on which transistors are formed may include monocrystalline silicon, rather than polycrystalline silicon, due to the superior carrier mobility of monocrystalline silicon desired for transistor performance. The peripheral circuitry and the bonding layer 1012 may be formed on opposite sides of the semiconductor layer 1004, such that the semiconductor layer 1004 is perpendicularly disposed between the peripheral circuitry and the bonding layer 1012. In some embodiments, transistors of peripheral circuits are formed on the front side of semiconductor layer 1004, and bonding contacts of bonding layer 1012 are formed on the back side of semiconductor layer 1004.

[0294] Similar to the bonding layer 1014 in the first semiconductor structure 102, the bonding layer 1012 may further include a dielectric material for conductive bonding contacts (not shown) and electrically isolating bonding contacts. According to some embodiments, a bonding interface 105 is perpendicularly positioned between and contacts the bonding layers 1012 and 1014. That is, the bonding layers 1012 and 1014 may be disposed on opposite sides of the bonding interface 105, and the bonding contacts of the bonding layer 1012 may contact the bonding contacts of the bonding layer 1014 at the bonding interface 105. As a result, a large number (e.g., millions) of bonding contacts across the bonding interface 105, combined with through contacts (e.g., ILV / TSV) passing through semiconductor layers 1002 and 1004, enable direct, short-distance (e.g., micrometer-scale) electrical connections between adjacent semiconductor structures 102 and 104.

[0295] It should be understood that in some examples, the first semiconductor structure 102 and the second semiconductor structure 104 may not include, respectively, the following: Figure 28A The bonding layers 1014 and 1012 are shown disposed on opposite sides of the bonding interface 105. Figure 28BIn the 3D memory device 2801, the semiconductor layer 1004 in the second semiconductor structure 104 can be a single-crystal silicon layer transferred from a silicon substrate or SOI substrate and attached to the bottom surface of the first semiconductor structure 102 by transfer bonding. Conversely, unlike hybrid bonding, the bonding interface 105 between the first semiconductor structure 102 and the second semiconductor structure 104 can be generated by transfer bonding. Through-contacts (e.g., ILV / TSV) perpendicularly passing between the first semiconductor structure 102 and the second semiconductor structure 104 through the semiconductor layers 1002 and 1004 can provide direct, short-distance (e.g., submicron-level) electrical connections between adjacent semiconductor structures 102 and 104.

[0296] like Figure 28A and 28B As shown, according to some embodiments, since the first semiconductor structure 102 and the second semiconductor structure 104 are bonded back-to-back (e.g., in...), Figure 28A and 28B In this configuration, semiconductor layer 1002 is disposed on the bottom side of the first semiconductor structure 102, while semiconductor layer 1004 is disposed on the top side of the second semiconductor structure 104. Therefore, the transistors of the peripheral circuits in the first semiconductor structure 102 and the second semiconductor structure 104 are arranged back-to-back. Furthermore, within the first semiconductor structure 102, since polysilicon layer 106 is perpendicularly positioned between the memory cell array and the peripheral circuits, and the memory cell array and the peripheral circuits are formed on polysilicon layer 106 and semiconductor layer 1002 respectively, the memory cell array and the peripheral circuits face the same direction (e.g., in...). Figure 28A and 28B (in the positive y-direction). It should be understood that, for ease of explanation, Figure 21A and 21B The pads in the 902 interconnect layer are brought out from the pads. Figure 28A and 28B The 3D memory devices 2800 and 2801 are omitted from the above description and may be included in the following: Figure 21A and 21B In the 3D memory devices 2800 and 2801.

[0297] As described above, the first semiconductor structure 102 and the second semiconductor structure 104 may have peripheral circuitry, which includes transistors to which different voltages are applied. For example, the second semiconductor structure 104 may include... Figure 4B An example of semiconductor structure 408 for LLV circuit 402 (and LV circuit 404 in some examples), and the first semiconductor structure 102 may include Figure 4BAn example of semiconductor structure 410 for HV circuit 406 (and LV circuit 404 in some examples), and vice versa. Therefore, in some embodiments, semiconductor layers 1002 and 1004 in the first semiconductor structure 102 and the second semiconductor structure 104 have different thicknesses to accommodate transistors to which different voltages are applied. In one example, the first semiconductor structure 102 may include HV circuit 406, the second semiconductor structure 104 may include LLV circuit 402, and the thickness of semiconductor layer 1002 in the first semiconductor structure 102 may be greater than the thickness of semiconductor layer 1004 in the second semiconductor structure 104. Furthermore, in some embodiments, the gate dielectrics of the transistors in the first semiconductor structure 102 and the second semiconductor structure 104 also have different thicknesses to accommodate the different applied voltages. In one example, the first semiconductor structure 102 may include HV circuit 406, the second semiconductor structure 104 may include LLV circuit 402, and the thickness of the gate dielectric of the transistor in the first semiconductor structure 102 may be greater than (e.g., at least 5 times) the thickness of the gate dielectric of the transistor in the second semiconductor structure 104.

[0298] Figure 29A and 29B The various aspects of this disclosure are shown. Figure 28A and 28B Side views of various examples of 3D memory devices 2800 and 2801. Figure 29A As shown, as Figure 28A and 28B One example of 3D memory devices 2800 and 2801 is, according to some embodiments, a 3D memory device 2900, which is a bonded chip including a first semiconductor structure 102 and a second semiconductor structure 104, which are oriented vertically (e.g., Figure 29A The first semiconductor structure 102 and the second semiconductor structure 104 are stacked on different planes in the y-direction. According to some embodiments, the first semiconductor structure 102 and the second semiconductor structure 104 are bonded at the bonding interface 105 therebetween.

[0299] like Figure 29AAs shown, the second semiconductor structure 104 may include a semiconductor layer 1004 having a semiconductor material. In some embodiments, the semiconductor layer 1004 is a silicon substrate having single-crystal silicon. The second semiconductor structure 104 may also include a device layer 2902 above and in contact with the semiconductor layer 1004. In some embodiments, the device layer 2902 includes a first peripheral circuit 2904 and a second peripheral circuit 2906. The first peripheral circuit 2904 may include an LLV circuit 402, such as I / O circuitry (e.g., in interface 316 and data bus 318), and the second peripheral circuit 2906 may include an LV circuit 404, such as a page buffer circuit (e.g., page buffer circuit 702 in page buffer 304) and logic circuitry (e.g., in control logic 312). In some embodiments, the first peripheral circuit 2904 includes a plurality of transistors 2908 in contact with the semiconductor layer 1004, and the second peripheral circuit 2906 includes a plurality of transistors 2910 in contact with the semiconductor layer 1004. Transistors 2908 and 2910 may include any transistor disclosed herein, such as planar transistor 500 and 3D transistor 600. As described in detail above with respect to transistors 500 and 600, in some embodiments, each transistor 2908 or 2910 includes a gate dielectric, and because the voltage applied to transistor 2908 is lower than the voltage applied to transistor 2910, the thickness of the gate dielectric of transistor 2908 (e.g., in LLV circuit 402) is less than the thickness of the gate dielectric of transistor 2910 (e.g., in LV circuit 404). Trench isolation (e.g., STI) and doped regions (e.g., the well, source, and drain of transistors 2908 and 2910) may also be formed on or therein in semiconductor layer 1004.

[0300] In some embodiments, the second semiconductor structure 104 further includes an interconnect layer 2912 above the device layer 2902 for transmitting electrical signals to and from peripheral circuits 2906 and 2904. For example... Figure 29AAs shown, device layer 2902 (including transistors 2908 and 2910 of peripheral circuits 2904 and 2906) is perpendicularly positioned between bonding interface 105 and interconnect layer 2912. Interconnect layer 2912 may include multiple interconnects, such as MEOL interconnects and BEOL interconnects. Interconnects in interconnect layer 2912 may be coupled to transistors 2908 and 2910 of peripheral circuits 2904 and 2906 in device layer 2902. Interconnect layer 2912 may also include one or more ILD layers in which lateral lines and vias can be formed. That is, interconnect layer 2912 may include lateral lines and vias in multiple ILD layers. In some embodiments, devices in device layer 2902 are coupled to each other through interconnects in interconnect layer 2912. For example, peripheral circuit 2904 may be coupled to peripheral circuit 2906 through interconnect layer 2912. Interconnects in interconnect layer 2912 may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. The ILD layer in interconnect layer 2912 may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric or any combination thereof.

[0301] In some embodiments, the interconnects in interconnect layer 2912 include Cu, which has a relatively low resistivity (better electrical performance) among conductive metal materials. As described below regarding the manufacturing process, although Cu has a relatively low thermal budget (incompatible with high-temperature processes), the interconnects of interconnect layer 1126 with Cu can become feasible because the fabrication of interconnect layer 2912 can be performed after the high-temperature process that forms device layer 2902 and NAND memory string 208 in first semiconductor structure 102.

[0302] like Figure 29A As shown, the second semiconductor structure 104 may further include one or more contacts 2931 extending vertically through the semiconductor layer 1004. In some embodiments, the contacts 2931 further extend through a dielectric layer (if present) on the back side of the semiconductor layer 1004 to the bonding interface 105. The contacts 2931 may be coupled to interconnects in the interconnect layer 2912. The contacts 2931 may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. In some embodiments, the contacts 2931 include W or Cu. In some embodiments, the contacts 2931 include vias surrounded by dielectric spacers (e.g., having silicon oxide) to electrically isolate the vias from the semiconductor layer 1004. Depending on the thickness of the semiconductor layer 1004, the contacts 2931 may be ILVs with depths in the submicron range (e.g., between 10 nm and 1 μm) or TSVs with depths in the micron or tens of micron ranges (e.g., between 1 μm and 100 μm).

[0303] like Figure 29AAs shown, the first semiconductor structure 102 can be bonded back-to-back to the top of the second semiconductor structure 104 at the bonding interface 105. The first semiconductor structure 102 may also include a semiconductor layer 1002 having a semiconductor material. In some embodiments, the bonding interface 105 is the location where the semiconductor layer 1002 of the first semiconductor structure 102 and the semiconductor layer 1004 of the second semiconductor structure 104 meet and bond. In practice, the bonding interface 105 may be a layer of a specific thickness, comprising the top surface of the semiconductor layer 1004 of the second semiconductor structure 104 and the bottom surface of the semiconductor layer 1002 of the first semiconductor structure 102. The bonding interface 105 may be generated by a transfer bonding process, and the semiconductor layer 1004 may be a single-crystal silicon layer transferred from a silicon substrate or SOI substrate and attached to the bottom surface of the first semiconductor structure 102 by transfer bonding, as described in detail below regarding the manufacturing process. In some embodiments, a dielectric layer (e.g., a silicon oxide layer) is vertically formed between the bonding interface 105 and the semiconductor layer 1002 and / or between the bonding interface 105 and the semiconductor layer 1004 to facilitate transfer bonding of the semiconductor layer 1004 to the semiconductor layer 1002. Therefore, it should be understood that in some examples, the bonding interface 105 may include the surface of one or more dielectric layers.

[0304] like Figure 29AAs shown, the first semiconductor structure 102 may also include a device layer 2914 below and in contact with the semiconductor layer 1002. In some embodiments, the device layer 2914 includes a third peripheral circuit 2916 and a fourth peripheral circuit 2918 below and in contact with the semiconductor layer 1002. In some embodiments, the semiconductor layer 1002 is vertically disposed between the bonding interface 105 and the device layer 2914 having peripheral circuits 2916 and 2918. The third peripheral circuit 2916 may include an HV circuit 406, such as a driver circuit (e.g., a serial driver 704 in a row decoder / word line driver 308 and a driver in a column decoder / bit line driver 306), and the fourth peripheral circuit 2918 may include an LV circuit 404, such as a page buffer circuit (e.g., a page buffer circuit 702 in a page buffer 304) and logic circuitry (e.g., in control logic 312). In some embodiments, the third peripheral circuit 2916 includes a plurality of transistors 2920, and the fourth peripheral circuit 2918 also includes a plurality of transistors 2922. Transistors 2920 and 2922 may include any transistor disclosed herein, such as planar transistor 500 and 3D transistor 600. As described in detail above with respect to transistors 500 and 600, in some embodiments, each transistor 2920 or 2922 includes a gate dielectric, and because the voltage applied to transistor 2920 is higher than the voltage applied to transistor 2922, the thickness of the gate dielectric of transistor 2920 (e.g., in HV circuit 406) is greater than the thickness of the gate dielectric of transistor 2922 (e.g., in LV circuit 404).

[0305] Furthermore, different voltages applied to the different transistors 2920, 2922, 2908, and 2910 in the first semiconductor structure 102 and the second semiconductor structure 104 can lead to differences in device dimensions between the first semiconductor structure 102 and the second semiconductor structure 104. In some embodiments, because the voltage applied to transistor 2908 is lower than the voltage applied to transistor 2920, the thickness of the gate dielectric of transistor 2908 (e.g., in LLV circuit 402) is less than the thickness of the gate dielectric of transistor 2920 (e.g., in HV circuit 406). In some embodiments, because the voltages applied to transistors 2922 and 2910 are the same, the thickness of the gate dielectric of transistor 2922 (e.g., in LV circuit 404) is the same as the thickness of the gate dielectric of transistor 2910 (e.g., in LV circuit 404). In some embodiments, since the voltage applied to transistor 2920 is higher than the voltage applied to transistor 2908, the thickness of semiconductor layer 1002 in which transistor 2920 is formed (e.g., in HV circuit 406) is greater than the thickness of semiconductor layer 1004 in which transistor 2908 is formed (e.g., in LLV circuit 402).

[0306] like Figure 29A As shown, the first semiconductor structure 102 may further include an interconnect layer 2926 below and in contact with device layer 2914, through which electrical signals are transmitted from transistors 2920 and 2922 of peripheral circuits 2916 and 2918. Interconnect layer 2926 may include multiple interconnects, such as MEOL interconnects and BEOL interconnects. Interconnect layer 2926 may also include one or more ILD layers in which lateral lines and vias can be formed. Interconnects in interconnect layer 2926 may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. ILD layers in interconnect layer 2926 may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. In some embodiments, interconnects in interconnect layer 2926 include W, which has a relatively high thermal budget (compatible with high-temperature processes) and good quality (fewer defects, such as voids) among conductive metal materials.

[0307] like Figure 29A As shown, the first semiconductor structure 102 may further include one or more contacts 2930 extending vertically through the semiconductor layer 1002. In some embodiments, the contacts 2930 further extend through a dielectric layer (if present) on the back side of the semiconductor layer 1002 to contact the contact 2931 at the bonding interface 105. The contacts 2930 may be coupled to interconnects in the interconnect layer 2926. Thus, contacts 2930 and 2931 may couple the interconnects in the interconnect layer 2926 to the interconnects in the interconnect layer 2912 to provide electrical connection through the semiconductor layers 1002 and 1004 and across the bonding interface 105 between the first semiconductor structure 102 and the second semiconductor structure 104. The contacts 2930 may include a conductive material, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. In some embodiments, the contacts 2930 include W. In some embodiments, contact 2930 includes a via surrounded by a dielectric spacer (e.g., having silicon oxide) to electrically isolate the via from semiconductor layer 1002. Depending on the thickness of semiconductor layer 1002, contact 2930 may be an ILV with a depth in the submicron range (e.g., between 10 nm and 10 μm) or a TSV with a depth in the micron or tens of micron range (e.g., between 1 μm and 100 μm).

[0308] like Figure 23A As shown, the first semiconductor structure may further include a polysilicon layer 106 below and in contact with the interconnect layer 2926. According to some embodiments, the polysilicon layer 106 is a doped polysilicon layer on the interconne...

Claims

1. A three-dimensional (3D) memory device, comprising: A first semiconductor structure, the first semiconductor structure comprising: NAND memory string array; The first peripheral circuit of the NAND memory string array includes a first transistor; A polysilicon layer, the polysilicon layer being located between the NAND memory string array and the first peripheral circuit, the polysilicon layer being in contact with the source of the NAND memory string array; and A first semiconductor layer, wherein the first semiconductor layer is in contact with the first transistor; A second semiconductor structure, the second semiconductor structure comprising: The second peripheral circuit of the NAND memory string array, the second peripheral circuit including a second transistor; and A second semiconductor layer, which is in contact with the second transistor; and a bonding interface, which is located between the first semiconductor structure and the second semiconductor structure. The second semiconductor layer is located between the second peripheral circuit and the bonding interface; and The polycrystalline silicon layer is located between the first semiconductor layer and the second semiconductor layer.

2. The 3D memory device according to claim 1, wherein, The first peripheral circuit is located between the first semiconductor layer and the polysilicon layer.

3. The 3D memory device according to claim 1 or 2, wherein, Each of the first semiconductor layer and the second semiconductor layer comprises monocrystalline silicon.

4. The 3D memory device according to claim 1 or 2, wherein, The thickness of the first semiconductor layer is greater than the thickness of the second semiconductor layer.

5. The 3D memory device according to claim 1 or 2, wherein, The first transistor includes a first gate dielectric; The second transistor includes a second gate dielectric; and The thickness of the first gate dielectric is greater than the thickness of the second gate dielectric.

6. The 3D memory device according to claim 5, wherein, The difference between the thicknesses of the first gate dielectric and the second gate dielectric is at least 5 times.

7. The 3D memory device according to claim 5, wherein, The first semiconductor structure further includes a third peripheral circuitry for the NAND memory string array, the third peripheral circuitry including a third transistor, the third transistor including a third gate dielectric; and The second semiconductor structure further includes a fourth peripheral circuit of the NAND memory string array, the fourth peripheral circuit including a fourth transistor including a fourth gate dielectric.

8. The 3D memory device according to claim 7, wherein, The third gate dielectric and the fourth gate dielectric have the same thickness.

9. The 3D memory device according to claim 8, wherein, The thickness of the third gate dielectric and the fourth gate dielectric is between the thickness of the first gate dielectric and the second gate dielectric.

10. The 3D memory device according to claim 7, wherein, The third and fourth peripheral circuits include at least one of a page buffer circuit or a logic circuit.

11. The 3D memory device according to claim 1 or 2, wherein, The first semiconductor structure further includes a first interconnect layer between the polysilicon layer and the first peripheral circuit, the first interconnect layer including a first interconnect coupled to the first transistor; and The second semiconductor structure further includes a second interconnect layer, such that the second peripheral circuit is located between the bonding interface and the second interconnect layer, the second interconnect layer including a second interconnect coupled to the second transistor.

12. The 3D memory device according to claim 11, wherein, The first interconnect comprises tungsten, and the second interconnect comprises copper.

13. The 3D memory device according to claim 11, wherein, The first semiconductor structure further includes: A third interconnect layer, the third interconnect layer being between the bonding interface and the NAND memory string array, the third interconnect layer including a third interconnect coupled to the NAND memory string array; and A first contact, the first contact passing through the polysilicon layer and coupled to the third interconnect; and The second semiconductor structure further includes a second contact that passes through the second semiconductor layer and couples the third interconnect to the second interconnect.

14. The 3D memory device according to claim 1 or 2, wherein, The first semiconductor structure further includes a first pad leading to an interconnect layer in contact with the first semiconductor layer, or The second semiconductor structure also includes a second pad leading out an interconnect layer above the second transistor.

15. The 3D memory device according to claim 1 or 2, wherein, The first peripheral circuit includes a driving circuit, and the second peripheral circuit includes an input / output (I / O) circuit.

16. The 3D memory device according to claim 1 or 2, further comprising: A first voltage source, the first voltage source being coupled to the first peripheral circuit and configured to provide a first voltage to the first peripheral circuit; as well as A second voltage source, coupled to the second peripheral circuit and configured to provide a second voltage to the second peripheral circuit. Wherein, the first voltage is greater than the second voltage.

17. The 3D memory device according to claim 1 or 2, wherein, The first semiconductor structure further includes a first bonding layer, such that the NAND memory string array is located between the first bonding layer and the polysilicon layer, and the first bonding layer includes a first bonding contact; The second semiconductor structure further includes a second bonding layer, such that the second semiconductor layer is located between the second bonding layer and the second peripheral circuit, and the second bonding layer includes second bonding contacts; and The first bonding contact contacts the second bonding contact at the bonding interface.

18. The 3D memory device according to claim 1 or 2, wherein, The first transistor is formed on the first semiconductor layer, and the second transistor is formed on the second semiconductor layer.

19. A system comprising: A memory device configured to store data, and the memory device comprising: A first semiconductor structure, the first semiconductor structure comprising: NAND memory string array; The first peripheral circuit of the NAND memory string array includes a first transistor; A polysilicon layer, the polysilicon layer being located between the NAND memory string array and the first peripheral circuit, the polysilicon layer being in contact with the source of the NAND memory string array; and A first semiconductor layer, wherein the first semiconductor layer is in contact with the first transistor; A second semiconductor structure, the second semiconductor structure comprising: The second peripheral circuit of the NAND memory string array, the second peripheral circuit including a second transistor; and A second semiconductor layer, the second semiconductor layer being in contact with the second transistor; and A bonding interface is located between the first semiconductor structure and the second semiconductor structure, wherein the second semiconductor layer is located between the bonding interface and the second peripheral circuit, and the polysilicon layer is located between the first semiconductor layer and the second semiconductor structure; and A memory controller coupled to the memory device and configured to control the NAND memory string array via the first peripheral circuitry and the second peripheral circuitry.

20. A method for forming a three-dimensional (3D) memory device, comprising: A first transistor is formed on a first substrate; A polycrystalline silicon layer is formed above the first transistor on the first substrate; A NAND memory string array is formed on the polysilicon layer; A second transistor is formed on the front side of the second substrate; as well as The first substrate and the second substrate are bonded together, with the bonding interface located between the NAND memory string array and the second transistor, and the second substrate located between the bonding interface and the second transistor.

21. The method of claim 20, further comprising forming a pad-out interconnect layer over the second transistor after bonding the first substrate and the second substrate.

22. The method of claim 20, further comprising: After bonding the first substrate and the second substrate, the first substrate is thinned; as well as An interconnect layer with pads is formed on the thinned first substrate.

23. The method according to any one of claims 20-22, wherein, Bonding the first substrate and the second substrate includes hybrid bonding.

24. The method according to any one of claims 20-22, further comprising: A first bonding layer is formed over the NAND memory string array, the first bonding layer including a first bonding contact; as well as A second bonding layer is formed on the back side of the second substrate, the second bonding layer including second bonding contacts. After the first substrate and the second substrate are bonded, the first bonding contact contacts the second bonding contact at the bonding interface.

25. The method according to any one of claims 20-22, further comprising forming a first contact through the polysilicon layer.

26. The method according to any one of claims 20-22, further comprising: Before bonding the first substrate and the second substrate, the second substrate is thinned; as well as A second contact is formed through the thinned second substrate.

27. The method according to any one of claims 20-22, wherein, Forming the first transistor includes forming a first gate dielectric; and Forming the second transistor includes forming a second gate dielectric; and The thickness of the first gate dielectric is greater than the thickness of the second gate dielectric.

28. A method for forming a three-dimensional (3D) memory device, comprising: A first transistor is formed on a first substrate; A polycrystalline silicon layer is formed above the first transistor on the first substrate; A NAND memory string array is formed on the polysilicon layer; A semiconductor layer is formed above the NAND memory string array, wherein the semiconductor layer comprises monocrystalline silicon; and A second transistor is formed on the semiconductor layer. The polysilicon layer is located between the first transistor and the NAND memory string array, and the semiconductor layer is located between the NAND memory string array and the second transistor.

29. The method of claim 28, further comprising forming a pad-out interconnect layer above the second transistor.

30. The method of claim 28, further comprising: After forming the second transistor, the first substrate is thinned; as well as An interconnect layer with pads is formed on the thinned first substrate.

31. The method according to any one of claims 28-30, further comprising forming a first contact through the polysilicon layer prior to forming the semiconductor layer.

32. The method according to any one of claims 28-30, further comprising forming a second contact through the semiconductor layer.

33. The method according to any one of claims 28-30, wherein, Forming the semiconductor layer includes: Bonding the second substrate and the first substrate; and The second substrate is thinned to leave the semiconductor layer.

34. The method according to claim 33, wherein, Bonding the second substrate and the first substrate includes transfer bonding.

35. The method according to any one of claims 28-30, wherein, Forming the first transistor includes forming a first gate dielectric; Forming the second transistor includes forming a second gate dielectric; and The thickness of the first gate dielectric is greater than the thickness of the second gate dielectric.

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