A board structure, an X-ray flat panel detection device, a system and its control method

Abstract

This invention provides a board structure, an X-ray flat panel detection device, a system, and a control method thereof. The board structure includes: a base plate, a main control board, a ROIC board, and a gate driver board, all of which are independent of each other. The base plate is divided into a main control area, a reading area, and a scanning area. The base plate includes a first FMC connector disposed in the main control area, a second FMC connector disposed in the reading area, and a third FMC connector disposed in the scanning area. The main control board includes a first FMC interface for coupling with the first FMC connector, the ROIC board includes a second FMC interface for coupling with the second FMC connector, and the gate driver board includes a third FMC interface for coupling with the third FMC connector. The main control board is used to acquire control commands, and according to the control commands, loads a first control signal to the ROIC board and a second control signal to the gate driver board through the base plate to obtain image data of the object under test.

Description

Technical Field

[0001] This invention relates to the field of X-ray imaging technology, and in particular to a board structure, an X-ray flat panel detection device, a system, and a control method thereof. Background Technology

[0002] In recent years, X-ray inspection has been widely used in medical imaging, industrial inspection, security inspection, and scientific research due to its advantages such as fast imaging speed, high resolution, and high signal-to-noise ratio. Currently, the most common X-ray inspection technology is digital radiography (DR), which emerged in the late 1990s. DR technology uses a flat panel detector (FPD) with a pixel size of less than 0.1 mm, thus achieving image quality and resolution almost comparable to film photography systems. It also overcomes the shortcomings of film photography systems and facilitates computer processing of images.

[0003] Current flat panel detectors often employ an integrated structure that combines the main control board, read-out integrated circuit (ROIC) board, and gate driver board into a single unit, or a semi-integrated structure that combines the main control board and ROIC board. Consequently, the structure and functionality are relatively fixed. For example, if the model, number, or spacing of the ROIC chips on the ROIC board changes, the entire integrated structure must be replaced. Similarly, if the model, number, or spacing of the gate driver chips on the gate driver board changes, the entire integrated structure must be replaced. In other words, if any parameter of either the ROIC board or the gate driver board changes, the entire integrated structure needs to be replaced. This results in longer development cycles, increased material and R&D costs, and also amplifies potential risks and reduces the success rate of R&D.

[0004] Improving the manufacturing efficiency of flat panel detectors has become an urgent technical problem to be solved. Summary of the Invention

[0005] This invention provides a board structure, an X-ray flat panel detection device, a system, and a control method thereof, which are used to improve the manufacturing efficiency of flat panel detectors.

[0006] In a first aspect, embodiments of the present invention provide a board structure, including:

[0007] The baseboard, main control board, ROIC board, and gate driver board are independent of each other; among them:

[0008] The base plate is divided into a main control area, a reading area and a scanning area. The base plate includes a first FMC connector disposed in the main control area, a second FMC connector disposed in the reading area and a third FMC connector disposed in the scanning area.

[0009] The main control board includes a first FMC interface for coupling with the first FMC connector, the ROIC board includes a second FMC interface for coupling with the second FMC connector, and the gate driver board includes a third FMC interface for coupling with the third FMC connector.

[0010] The main control board is used to acquire control commands, and according to the control commands, load a first control signal to the ROIC board and a second control signal to the gate driver board through the base plate to obtain image data of the object under test.

[0011] In one possible implementation, the ROIC board further includes a first chip connector coupled to the second FMC interface and configured to correspond one-to-one with the ROIC chip. The first chip connector is used to couple to the corresponding ROIC chip, and the orthographic projection of the first chip connector on the ROIC board does not overlap with the orthographic projection of the second FMC interface on the ROIC board. The ROIC board is used to obtain the configuration instruction parsed by the main control board from the control instruction through the second FMC interface, and to configure the signal of the ROIC chip according to the configuration instruction. After the signal configuration, the board sends the first control signal to the ROIC chip through the second FMC interface so that the ROIC chip reads image data according to the first control signal.

[0012] In one possible implementation, the board structure further includes a first buffer coupled between the second FMC interface and the first chip connector. The first buffer is used to receive the first control signal, divide the first control signal into a plurality of first signals, and send each of the first signals in parallel to the corresponding ROIC chip.

[0013] In one possible implementation, the gate driver board further includes a second chip connector that corresponds one-to-one with the gate driver chip. The second chip connector is used to couple to the corresponding gate driver chip. The orthographic projection of the second chip connector on the gate driver board does not overlap with the orthographic projection of the third FMC interface on the gate driver board. The gate driver board is used to send the second control signal to the gate driver chip through the third FMC interface, so that the gate driver chip scans the object under test according to the second control signal.

[0014] In one possible implementation, the board structure further includes a second buffer coupled between the third FMC interface and the second chip connector. The second buffer is used to receive the second control signal, divide the second control signal into multiple second signals, and send each of the second signals in parallel to the corresponding gate driver chip.

[0015] In one possible implementation, the ROIC board further includes a plurality of SPI traces coupled between the first FMC connector and the second FMC interface, wherein each SPI trace is of equal length and thickness.

[0016] In one possible implementation, the main control board includes an external interface for receiving control commands from a host computer via the external interface.

[0017] In one possible implementation, the external interface includes a USB interface, a Gigabit Ethernet interface, a 10 Gigabit Ethernet interface, and a UART interface.

[0018] Secondly, embodiments of the present invention provide an X-ray flat panel detection device, comprising:

[0019] The board structure as described in any of the above, and the probe panel coupled to the ROIC board and the gate driver board in the board structure, respectively.

[0020] Thirdly, embodiments of the present invention provide an X-ray flat panel detection system, comprising:

[0021] The board structure described in any of the above items, and the host computer coupled to the board structure; wherein:

[0022] The host computer is used to send control commands to the board structure;

[0023] The board structure is used to obtain image data of the object under test according to the control command, and send the image data to the host computer.

[0024] Fourthly, embodiments of the present invention provide a control method for the X-ray flat panel detection system as described above, comprising:

[0025] The main control board receives control commands from the host computer.

[0026] According to the control command, a first control signal is applied to the ROIC board via the base plate, and a second control signal is applied to the gate driver board to obtain image data of the object under test;

[0027] The image data is sent to the host computer.

[0028] In one possible implementation, the step of loading a first control signal onto the ROIC board via the base plate and a second control signal onto the gate driver board according to the control command to obtain image data of the object under test includes:

[0029] The control commands are parsed to obtain configuration commands;

[0030] The configuration command is received by the baseboard and sent to the ROIC board via the SPI protocol to configure the signal of the ROIC chip coupled to the ROIC board.

[0031] After configuring the ROIC chip, a first control signal is applied to the ROIC board, and a second control signal is applied to the gate driver board to obtain image data of the object under test.

[0032] In one possible implementation, loading the first control signal onto the ROIC board includes:

[0033] The first control signal is received through a first buffer coupled between the second FMC interface and the first chip connector on the ROIC board;

[0034] The first control signal is divided into multiple first signals, and each of the first signals is sent in parallel to the ROIC board;

[0035] The first signal is applied to the ROIC chip coupled to the ROIC board.

[0036] In one possible implementation, loading the second control signal onto the gate driver board includes:

[0037] The second control signal is received through a second buffer coupled between the third FMC interface and the second chip connector on the gate driver board;

[0038] The second control signal is divided into multiple second signals, and each of the second signals is sent to the gate driver board in parallel.

[0039] The corresponding second signal is applied to the gate driver chip coupled to the gate driver board.

[0040] The beneficial effects of this invention are as follows:

[0041] This invention provides a board structure, an X-ray flat panel detection device, a system, and a control method thereof. The board structure includes a base plate, a main control board, a ROIC board, and a gate driver board, all of which are independent of each other. The base plate includes a first FMC connector disposed in its main control area, a second FMC connector disposed in its reading area, and a third FMC connector disposed in its scanning area. The main control board includes a first FMC interface for coupling with the first FMC connector, the ROIC board includes a second FMC interface for coupling with the second FMC connector, and the gate driver board includes a third FMC interface for coupling with the third FMC connector. After being coupled to the corresponding FMC interface through the FMC connector, the main control board can obtain control commands and, according to the control commands, load a first control signal to the ROIC board and a second control signal to the gate driver board through the base plate, thereby obtaining image data of the object under test.

[0042] In this way, the main control board and the baseboard can be integrated or separated by plugging and unplugging the first FMC connector and the first FMC interface; the ROIC board and the baseboard can be integrated or separated by plugging and unplugging the second FMC connector and the second FMC interface; and the gate driver board and the baseboard can be integrated or separated by plugging and unplugging the third FMC connector and the third FMC interface. Because the FMC connectors and FMC interfaces can be flexibly plugged and unplugged, related boards in the board structure can be easily replaced. For example, if the parameters of the ROIC board change, simply unplug it from the baseboard and insert the ROIC board to be replaced; similarly, if the parameters of the gate driver board change, simply unplug it from the baseboard and insert the gate driver board to be replaced. This ensures signal interconnection between the main control board, the ROIC board, and the gate driver board, maintaining the performance of the flat panel detector while improving the compatibility and applicability of the board structure, thereby increasing the manufacturing efficiency of the flat panel detector. Attached Figure Description

[0043] Figure 1 This is a schematic diagram of one possible structure of a circuit board provided in an embodiment of the present invention;

[0044] Figure 2 for Figure 1 A schematic diagram of one possible structure of the midsole plate;

[0045] Figure 3 for Figure 1 A schematic diagram of one type of main control board structure;

[0046] Figure 4 for Figure 1 A schematic diagram of one type of ROIC board structure;

[0047] Figure 5 for Figure 1 A schematic diagram of one possible structure of the gate drive board;

[0048] Figure 6 This is a schematic diagram of one possible structure of the ROIC board in a board structure provided by an embodiment of the present invention;

[0049] Figure 7 This is a schematic diagram of one possible structure of the ROIC board in a board structure provided by an embodiment of the present invention;

[0050] Figure 8 This is a schematic diagram of one possible structure of the gate driving board in a board structure provided by an embodiment of the present invention;

[0051] Figure 9 This is a schematic diagram of one possible structure of the gate driving board in a board structure provided by an embodiment of the present invention;

[0052] Figure 10 This is a schematic diagram of one mode of driving a gate driver chip using a daisy-chain sequential driving mode in related technologies;

[0053] Figure 11 This is a schematic diagram of one mode of using a parallel-driven gate driver chip in a board structure provided by an embodiment of the present invention;

[0054] Figure 12 This is a schematic diagram of one possible connection of the ROIC board configuration in a board structure provided by an embodiment of the present invention;

[0055] Figure 13 This is a schematic diagram of one possible structure of the main control board in a board structure provided by an embodiment of the present invention;

[0056] Figure 14 This is a schematic diagram of one structure of an X-ray flat panel detection device provided in an embodiment of the present invention;

[0057] Figure 15 This is a schematic diagram of one structure of an X-ray flat panel detection system provided in an embodiment of the present invention;

[0058] Figure 16 for Figure 15 The flowchart of the control method for the X-ray flat panel detection system is shown.

[0059] Figure 17 for Figure 16 Flowchart of the method for step S102;

[0060] Figure 18 for Figure 17Flowchart of the method for loading the first control signal onto the ROIC board in step S203;

[0061] Figure 19 for Figure 17 Flowchart of the method for loading the second control signal onto the gate driver board in step S203;

[0062] Figure 20 This is a timing diagram for controlling one of the CPV, OE, STVL, and STVR when using a daisy-chain sequential drive mode to drive the gate driver chip in related technologies.

[0063] Figure 21 This is a timing diagram for controlling one of CPV, OE, STVL and STVR when driving the gate driver chip in parallel driving mode in an embodiment of the present invention.

[0064] Figure 22 This is a schematic diagram of one circuit structure of the second buffer provided in an embodiment of the present invention. Detailed Implementation

[0065] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Furthermore, the embodiments and features in the embodiments of the present invention can be combined with each other without conflict. Based on the described embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0066] Unless otherwise defined, the technical or scientific terms used in this invention shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention pertains. The terms "comprising" or "including," or similar terms as used in this invention, mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects.

[0067] It should be noted that the dimensions and shapes of the figures in the accompanying drawings do not reflect actual proportions and are intended only to illustrate the content of the invention. Furthermore, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

[0068] In related technologies, the main control board, ROIC board, and gate driver board are often integrated or designed as a single unit through the internal circuitry of the flat panel detector's circuit board structure. If any structural parameter of any board in the circuit board structure changes, the entire circuit board needs to be replaced. This reduces the manufacturing efficiency of the flat panel detector.

[0069] In view of this, embodiments of the present invention provide a board structure, an X-ray flat panel detection device, a system and a control method thereof, for improving the manufacturing efficiency of flat panel detectors.

[0070] Combination Figures 1-5 As shown, where, as Figure 1 The diagram shown is a schematic representation of one embodiment of a circuit board structure provided by the present invention. The circuit board structure includes:

[0071] The system consists of four independent components: a baseboard 1, a main control board 2, a ROIC board 3, and a gate driver board 4.

[0072] The base plate 1 is divided into a main control area A, a reading area B and a scanning area C. The base plate 1 includes a first FMC (FPGA Mezzanine Card) connector 11 disposed in the main control area A, a second FMC connector 12 disposed in the reading area B and a third FMC connector 13 disposed in the scanning area C.

[0073] The main control board 2 includes a first FMC interface 21 for coupling with the first FMC connector 11, the ROIC board 3 includes a second FMC interface 31 for coupling with the second FMC connector 21, and the gate drive board 4 includes a third FMC interface 41 for coupling with the third FMC connector 31.

[0074] The main control board 2 is used to acquire control commands, and according to the control commands, loads a first control signal to the ROIC board 3 and a second control signal to the gate drive board 4 through the base plate 1 to obtain image data of the object under test.

[0075] like Figures 2-5 The figures shown are respectively Figure 1 The diagram shows the structure of the baseboard 1, main control board 2, ROIC board 3, and gate driver board 4 in the board structure. In actual implementation, this board structure includes independent baseboard 1, main control board 2, ROIC board 3, and gate driver board 4. That is, the baseboard 1, main control board 2, ROIC board 3, and gate driver board 4 in the board structure are structurally independent and are designed separately. Compared with existing integrated or semi-integrated boards, only the relevant boards on the baseboard 1 need to be replaced according to the relevant parameters, which improves the compatibility and applicability of the board structure.

[0076] The base plate 1 is divided into a main control area A, a reading area B, and a scanning area C. One possible division of the main control area A, reading area B, and scanning area C is as follows: Figure 2As shown, the base plate 1 can also be divided into areas according to actual application needs, which will not be described in detail here.

[0077] The base plate 1 includes a first FMC connector 11 disposed in the main control area A, a second FMC connector 12 disposed in the reading area B, and a third FMC connector 13 disposed in the scanning area C; wherein, the number of first FMC connectors 11 can be one or more, the number of second FMC connectors 12 can be one or more, and the number of third FMC connectors 13 can be one or more. Figure 1 The diagram illustrates the following configurations: the first FMC connector 11 has 4 connectors, the second FMC connector 12 has 2 connectors, and the third FMC connector 13 has 1 connector. Of course, the specific number of each connector can be set according to actual application needs, and will not be detailed here.

[0078] The main control board 2 includes a first FMC interface 21 for coupling with the first FMC connector 11. Since the first FMC connector 11 and the first FMC interface 21 can be flexibly plugged in and out, this ensures a flexible design between the main control board 2 and the base plate 1. The ROIC board 3 includes a second FMC interface 31 for coupling with the second FMC connector 12. Since the second FMC connector 12 and the second FMC interface 31 can be flexibly plugged in and out, this ensures a flexible design between the ROIC board 3 and the base plate 1. The gate driver board 4 includes a third FMC interface 41 for coupling with the third FMC connector 13. Since the third FMC connector 13 and the third FMC interface 41 can be flexibly plugged in and out, this ensures a flexible design between the gate driver board 4 and the base plate 1. Because the FMC connectors and FMC interfaces can be flexibly plugged in and out, the relevant boards in the board structure can be flexibly replaced by plugging and unplugging the FMC connectors and FMC interfaces. For example, when the parameters of ROIC board 3 change, simply remove it from base plate 1 and insert the replacement ROIC board 3 into base plate 1; similarly, when the parameters of gate driver board 4 change, simply remove it from base plate 1 and insert the replacement gate driver board 4 into base plate 1. This ensures signal interconnection between main control board 2, ROIC board 3, and gate driver board 4, guaranteeing the performance of the flat panel detector while improving the compatibility and applicability of the board structure, thereby increasing the manufacturing efficiency of the flat panel detector. Furthermore, since only the corresponding board needs to be replaced, the development difficulty of the board structure is reduced, the development cycle is shortened, development costs are lowered, and the R&D success rate is increased.

[0079] It should be noted that, for the FMC connectors and FMC interfaces mentioned above, when the FMC connector is a female, the FMC interface is a male; and when the FMC connector is a male, the FMC interface is a female. The specific design of each FMC connector and FMC interface can be determined based on the actual application and will not be specified here.

[0080] After the first FMC connector 11 is coupled to the first FMC interface 21, the second FMC connector 12 is coupled to the second FMC interface 31, and the third FMC connector 13 is coupled to the third FMC interface 41, the main control board 2 can obtain control commands. Based on these commands, it loads a first control signal to the ROIC board 3 and a second control signal to the gate driver board 4 via the baseboard 1, thereby obtaining image data of the object under test. The first control signal includes AFE (Analog Front End) signals such as frame synchronization signals SYNC and ACLK, and the second control signal includes phase shift signal CPV, frame start signal STV, gate switch signal OE, and reset signal RST. The object under test can be a human arm, chest cavity, or other parts, without limitation. Since the pin rates in the FMC connectors and FMC interfaces can reach several Gb / s and have strong anti-interference capabilities, environmental compatibility and practicality are improved. Furthermore, it ensures high-speed, high-bandwidth transmission requirements while maintaining interconnectivity between boards and functional modules on the board structure.

[0081] In embodiments of the present invention, such as Figure 6 The diagram shows one possible structure of the ROIC board 3. Specifically, the ROIC board 3 further includes a first chip connector 32 coupled to the second FMC interface 31 and corresponding to each ROIC chip 6. The first chip connector 32 is used to couple to the corresponding ROIC chip 6. The orthographic projection of the first chip connector 32 on the ROIC board 3 does not overlap with the orthographic projection of the second FMC interface 31 on the ROIC board 3. The ROIC board 3 is used to obtain the configuration instruction after the main control board 2 parses the control instruction through the second FMC interface 31, and to configure the signal of the ROIC chip 6 according to the configuration instruction. After the signal configuration, the ROIC board 3 sends the first control signal to the ROIC chip 6 through the second FMC interface 31 so that the ROIC chip 6 reads image data according to the first control signal.

[0082] In practical implementation, the ROIC board 3 also includes a first chip connector 32 coupled to the second FMC interface 31 and corresponding to a ROIC chip 6. The number of first chip connectors 32 can be one or more. In actual applications, the number of first chip connectors 32 on the ROIC board 3 is equal to the number of ROIC chips 6 that it can couple with, and the first chip connectors 32 are corresponding to the ROIC chips 6. The ROIC board 3 can supply power to the corresponding ROIC chips 6 through the first chip connectors 32, thereby ensuring the normal operation of the ROIC chips 6. The orthographic projection of the first chip connector 32 on the ROIC board 3 and the orthographic projection of the second FMC interface 31 on the ROIC board 3 do not interfere with each other, thus simplifying the board structure design.

[0083] The ROIC board 3 can obtain the configuration instructions parsed by the main control board 2 through the second FMC interface 31, and configure the ROIC chip 6 according to the configuration instructions. For example, it can initialize the transfer register in the ROIC chip 6 used to implement analog-to-digital conversion, or it can initialize the configuration register 62 in the ROIC chip 6. After the signal configuration, the ROIC board 3 sends a first control signal to the corresponding ROIC chip 6 through the second FMC interface 31, so that the ROIC chip 6 reads the image data according to the first control signal.

[0084] In embodiments of the present invention, such as Figure 7 The diagram shows one possible structure of the ROIC board 3. Specifically, the board structure further includes a first buffer 33 coupled between the second FMC interface 31 and the first chip connector 32. The first buffer 33 is used to receive the first control signal, divide the first control signal into multiple first signals, and send each of the first signals in parallel to the corresponding ROIC chip 6.

[0085] In specific implementation, the board structure also includes a first buffer 33 coupled between the second FMC interface 31 and the first chip connector 32. The first buffer 33 may include multiple first buffer units, the number of which is equal to the number of first chip connectors 32 and the number of ROIC chips 6. The first buffer 33 is used to receive a first control signal and divide it into multiple first signals. That is, after passing through the first buffer 33, the first control signal can be divided into multiple first signals. The first buffer 33 can also send each first signal in parallel to the corresponding ROIC chip 6, thereby enabling parallel control of multiple ROIC chips 6. Compared to the daisy-chain sequential driving mode of the ROIC chips 6 in the prior art, where each frame synchronization signal SYNC passes through one ROIC chip 6 before being transmitted to the next, ultimately traversing all ROIC chips 6, the parallel control driving mode of the ROIC chips 6 in this embodiment reduces the reading time of each frame, improves the image frame reading speed, and thus improves the performance of the board structure.

[0086] In embodiments of the present invention, such as Figure 8 The diagram shows one possible structure of the gate driver board 4. Specifically, the gate driver board 4 further includes a second chip connector 42 corresponding to each gate driver chip 7. The second chip connector 42 is used to couple to the corresponding gate driver chip 7. The orthographic projection of the second chip connector 42 on the gate driver board 4 does not overlap with the orthographic projection of the third FMC interface 41 on the gate driver board 4. The gate driver board 4 is used to send the second control signal to the gate driver chip 7 through the third FMC interface 41, so that the gate driver chip 7 scans the object under test according to the second control signal.

[0087] In practical implementation, the gate driver board 4 also includes a second chip connector 42 corresponding to each gate driver chip 7. The number of second chip connectors 42 can be one or more. In actual applications, the number of second chip connectors 42 on the gate driver board 4 is equal to the number of gate driver chips 7 that it can couple with, and the second chip connectors 42 are corresponding to the gate driver chips 7. The gate driver board 4 can supply power to the corresponding gate driver chips 7 through the second chip connectors 42, thus ensuring the normal operation of the gate driver chips 7. The orthographic projection of the second chip connector 42 on the gate driver board 4 and the orthographic projection of the third FMC interface 41 on the gate driver board 4 do not affect each other, thus simplifying the board structure design. In practical applications, the first chip connector 32 and the second chip connector 42 can be a 50-pin connector from Hirose, with a corresponding pitch of 0.5mm; of course, other chip connectors can be selected according to actual application needs, and no limitation is made here.

[0088] The gate driver board 4 can send a second control signal to the gate driver chip 7 through the third FMC interface 41, so that the gate driver chip 7 scans the object under test according to the second control signal. In this way, the scanning control of the gate driver chip 7 is realized, ensuring the performance of the board structure.

[0089] In embodiments of the present invention, such as Figure 9 The diagram shows one possible structure of the gate driver board 4. Specifically, the board structure further includes a second buffer 43 coupled between the third FMC interface 41 and the second chip connector 42. The second buffer 43 is used to receive the second control signal, divide the second control signal into multiple second signals, and send each second signal in parallel to the corresponding gate driver chip 7.

[0090] In specific implementation, the board structure also includes a second buffer 43 coupled between the third FMC interface 41 and the second chip connector 42. This second buffer 43 can include multiple second buffer units, the number of which is equal to the number of second chip connectors 42 and the number of gate driver chips 7. The second buffer 43 can receive a second control signal and divide it into multiple second signals. That is, after passing through the second buffer 43, the second control signal can be divided into multiple second signals. The second buffer 43 can also send each second signal in parallel to the corresponding gate driver chip 7, thereby enabling parallel control of multiple gate driver chips 7. Compared to... Figure 10In the related technologies shown, the gate driver chip 7 is driven in a daisy-chain sequential mode, where the start-of-frame signal (STV) passes through one gate driver chip 7 before being transmitted to the next, and so on, eventually traversing all gate driver chips 7. In contrast, the parallel driving mode of the gate driver chips 7 in this embodiment of the invention reduces the scanning time of each frame, increases the scanning speed of the image frames, and thus increases the frame rate. Figure 11 The diagram shown illustrates one mode of the parallel-driven gate driver chip 7 provided in this embodiment of the invention. STVL represents the start signal of the corresponding channel of the gate driver chip, and STVR represents the end signal of the corresponding channel of the gate driver chip. Figure 10 and Figure 11 This illustration is based on the case where there are 6 gate drivers (7 in total), but in actual applications, it is not limited to this.

[0091] When the board structure of this invention is applied to a flat panel detector, on the one hand, it can ensure that a large number of images of the object under test are acquired per unit time, and the amount of information obtained is greater, which is beneficial for disease diagnosis; on the other hand, when the number of images acquired is fixed, the radiation dose to the object under test can also be reduced, thereby improving the performance of the board structure.

[0092] It should be noted that only the ROIC chip 6 can be set to parallel drive mode, only the gate driver chip 7 can be set to parallel drive mode, or both ROIC chip 6 and gate driver chip 7 can be set to parallel drive mode. The specific drive mode can be set according to the actual application and is not limited here. When using parallel drive mode, the corresponding acquisition area can be flexibly configured according to user needs, and there will be no problem of failure to image formation due to configuration failure caused by the malfunction of a single chip. In addition, the specific location of the malfunctioning chip can be quickly located. Furthermore, the main functions of the main control board 2 are implemented by FPGA (Field Programmable Gate Array) chips or DSP (Digital Signal Processing) chips.

[0093] In embodiments of the present invention, such as Figure 12 The diagram shows one possible connection configuration of the ROIC board 3. Specifically, the ROIC board 3 also includes multiple SPI (Serial Peripheral Interface) traces 5 coupled between the first FMC connector 11 and the second FMC interface 31, with each SPI trace 5 having the same length and thickness.

[0094] In practical implementation, the ROIC board 3 also includes multiple SPI traces 5 coupled between the first FMC connector 11 and the second FMC interface 31. Each SPI trace 5 enables the initialization configuration of the corresponding ROIC chip 6. All SPI traces 5 are of equal length and thickness, thus ensuring SPI timing requirements and enabling the initialization configuration of each ROIC chip 6 coupled to the first chip connector 32 on the ROIC board 3, thereby guaranteeing the performance of the ROIC board 3. Figure 12 The diagram shows six ROIC chips 6, each including a conversion register 61 and a configuration register 62. In practical applications, the number of ROIC chips is not limited to this.

[0095] In embodiments of the present invention, such as Figure 13 The diagram shows one possible structure of the main control board 2. Specifically, the main control board 2 includes an external interface 20, which is used to receive control commands from a host computer. The external interface 20 includes a USB (Universal Serial Bus) interface 201, a Gigabit Ethernet interface 202, a 10 Gigabit Ethernet interface 203, and a UART (Universal Asynchronous Receiver / Transmitter) interface 204. In other words, the external interface 20 is quite comprehensive, meeting the application requirements of different scenarios and different transmission bandwidths, thus improving the performance of the board structure.

[0096] In practical implementation, the host computer can send control commands to the main control board 2 through the external interface 20, and the main control board 2 receives the corresponding control commands. In actual applications, the main control board 2 can determine which of the external interfaces 20 to use to receive control commands based on bandwidth and application scenarios. For example, for scenarios requiring high frame rates, large bandwidth, and dynamic data acquisition, the 10 Gigabit Ethernet interface 203 with an effective bandwidth of up to 1GB / s can be used to receive control commands. Correspondingly, the host computer also needs to be configured with a corresponding 10 Gigabit Ethernet interface 203, which places high demands on the host computer's configuration. On the other hand, for scenarios requiring static data acquisition, the Gigabit Ethernet interface 202 with an effective bandwidth of up to 60MB / s can be used to receive control commands. Correspondingly, the host computer also needs to be configured with a corresponding Gigabit Ethernet interface 202, which places lower demands on the host computer's configuration. In addition, the USB interface 201 has an effective bandwidth of up to 300MB / s, and its bandwidth and host computer configuration requirements are between those of the Gigabit Ethernet interface 202 and the 10 Gigabit Ethernet interface 203.

[0097] It should be noted that when using the separate board structure of this invention, the ROIC board 3 or the gate driver board 4 can be replaced quickly to meet requirements, based on parameters such as the size of the probe panel to be installed, the type of ROIC chip 6, the type of gate driver chip 7, the number of chips, and the chip spacing. This can be achieved using a separate system architecture and online parameter adjustment technologies. Furthermore, this reduces the development difficulty of the board structure, shortens the development cycle, reduces the development complexity, and improves the success rate of research and development. In addition to the interfaces mentioned above, other types of interfaces can be configured on the ROIC board 3 and the gate driver board 4 according to actual application needs; no limitations are imposed here.

[0098] Based on the same inventive concept, such as Figure 14 As shown, this embodiment of the invention also provides an X-ray flat panel detection device. The X-ray flat panel detection device includes:

[0099] The board structure 100 as described in any of the above, and the probe panel 200 respectively coupled to the ROIC board 3 and the gate drive board 4 in the board structure 100.

[0100] In practical implementation, the detection panel 200 may have a surface layer of scintillator material, with a next layer of a photodiode array made of amorphous silicon. The scintillator converts attenuated X-rays passing through the object under test into visible light; the photodiode array converts the visible light into electrical signals, storing charge on the capacitance of the photodiodes themselves. The amount of stored charge in each pixel is proportional to the intensity of the incident X-rays. Under the control of the ROIC chip 6 and the gate driver chip 7 by the board structure 100, image data acquisition is achieved.

[0101] The principle of this X-ray flat panel detection device in solving the problem is similar to that of the aforementioned board structure 100. Therefore, the implementation of this X-ray flat panel detection device can refer to the implementation of the aforementioned board structure 100, and the repeated parts will not be described again.

[0102] Based on the same inventive concept, such as Figure 15 As shown, this embodiment of the invention also provides an X-ray flat panel detection system, comprising:

[0103] The board structure 100 as described in any of the above, and the host computer 300 coupled to the board structure 100; wherein:

[0104] The host computer 300 is used to send control commands to the board structure 100;

[0105] The board structure 100 is used to obtain image data of the object under test according to the control command, and send the image data to the host computer 300.

[0106] In the specific implementation process, the host computer 300 can perform image processing on the acquired image data and complete image display, storage and analysis.

[0107] The principle of this X-ray flat panel detection system is similar to that of the aforementioned board structure 100. Therefore, the implementation of this X-ray flat panel detection system can refer to the implementation of the aforementioned board structure 100. The repeated parts will not be described again.

[0108] Based on the same inventive concept, such as Figure 16 As shown, embodiments of the present invention provide a method as follows: Figure 15 The control method for the X-ray flat panel detection system shown includes:

[0109] S101: Receive control commands from the host computer via the main control board;

[0110] S102: According to the control command, a first control signal is applied to the ROIC board through the base plate, and a second control signal is applied to the gate driver board to obtain image data of the object under test;

[0111] S103: Send the image data to the host computer.

[0112] It should be noted that the host computer can only send control commands to the main control board after the X-ray flat panel detection system is powered on. After receiving the control command, the main control board can verify whether the control command is correct. After confirming that it is correct, it responds and replies to the host computer. Then, the host computer sends the control command to the ROIC board and the gate driver board via the first connector on the baseboard and the first FMC interface on the main control board through the SPI protocol. Then, the image data of the object under test is acquired through the ROIC board and the gate driver board.

[0113] In the specific implementation process, the control method of the X-ray flat panel detection system is similar to the principle of the aforementioned board structure 100. The implementation process of the control method for steps S101 to S103 can refer to the implementation of the aforementioned part, and the repeated parts will not be described again.

[0114] In embodiments of the present invention, such as Figure 17 As shown, step S102: According to the control command, a first control signal is applied to the ROIC board via the base plate, and a second control signal is applied to the gate driver board to obtain image data of the object under test, including:

[0115] S201: Parse the control command to obtain the configuration command;

[0116] S202: Receive the configuration command through the baseboard and send the configuration command to the ROIC board via the SPI protocol to configure the signal of the ROIC chip coupled to the ROIC board;

[0117] S203: After configuring the ROIC chip, a first control signal is applied to the ROIC board and a second control signal is applied to the gate driver board to obtain image data of the object under test.

[0118] The specific implementation process of steps S201 to S203 can be referred to the description in the relevant parts above, and the repeated parts will not be repeated.

[0119] In embodiments of the present invention, such as Figure 18 As shown, the step S203 of loading the first control signal onto the ROIC board includes:

[0120] S301: Receive the first control signal through a first buffer coupled between the second FMC interface and the first chip connector on the ROIC board;

[0121] S302: Divide the first control signal into multiple first signals, and send each of the first signals in parallel to the ROIC board;

[0122] S303: Apply the corresponding first signal to the ROIC chip coupled to the ROIC board.

[0123] The specific implementation process of steps S301 to S303 can be referred to the description in the relevant parts above, and the repeated parts will not be repeated.

[0124] In embodiments of the present invention, such as Figure 19 As shown, loading the second control signal onto the gate driver board in step S203 includes:

[0125] S401: Receive the second control signal through a second buffer coupled between the third FMC interface and the second chip connector on the gate driver board;

[0126] S402: Divide the second control signal into multiple second signals, and send each of the second signals in parallel to the gate driver board;

[0127] S403: Apply the corresponding second signal to the gate driver chip coupled to the gate driver board.

[0128] The specific implementation process of steps S401 to S403 can be referred to the description in the relevant sections above; repeated details will not be repeated here. Figure 20This is a timing diagram for controlling one of the CPV, OE, STVL, and STVR mechanisms when using a daisy-chain sequential drive mode to drive the gate driver chip in related technologies. For example... Figure 21 The diagram shown is a timing diagram of one of the control parameters of CPV, OE, STVL and STVR when the gate driver chip is driven in parallel driving mode in an embodiment of the present invention. Figure 20 and Figure 21 The diagram illustrates a scenario with three gate driver chips, but it is not limited to this. Combined with... Figure 20 and Figure 21 It is evident that the control method provided in this embodiment of the invention effectively reduces the scanning time of one frame and improves the frame rate of the X-ray flat panel detection system.

[0129] like Figure 22 The diagram shown is one of the circuit schematics for the second buffer 43. Figure 22 The diagram illustrates one possible input and output configuration of the CPV, OE1, STV1L, and STV1R signals controlling a gate driver chip via a second buffer 43. Pin 2 corresponds to the CPV signal input, pin 3 to the OE1 signal input, pin 4 to the STV1L signal input, pin 5 to the STV1R signal input, pin 10 to the CPV signal output, pin 9 to the OE1 signal output, pin 8 to the STV1L signal output, and pin 7 to the STV1R signal output. The specific values ​​of capacitors C4 and C5 are not limited. Since the external power supply VCC_3V3 can power the second buffer 43, the drive current of the corresponding circuits can be increased through the second buffer 43, improving the performance of the X-ray flat panel detector. Furthermore, the circuit structures of the first buffer 33 and the second buffer 43 can be configured according to actual application needs, and are not limited here.

[0130] This invention provides a board structure, an X-ray flat panel detection device, a system, and a control method thereof. The board structure includes a base plate 1, a main control board 2, a ROIC board 3, and a gate driver board 4, which are independent of each other. The base plate 1 includes a first FMC connector 11 disposed in its main control area A, a second FMC connector 12 disposed in its reading area B, and a third FMC connector 13 disposed in its scanning area C. The main control board 2 includes a first FMC interface 21 for coupling with the first FMC connector 11. The ROIC board 3 includes a second FMC interface 31 for coupling with the second FMC connector 12. The gate driver board 4 includes a third FMC interface 41 for coupling with the third FMC connector 13. After being coupled to the corresponding FMC interface through the FMC connector, the main control board 2 can obtain control commands. According to the control commands, it loads a first control signal to the ROIC board 3 and a second control signal to the gate driver board 4 through the base plate 1, thereby obtaining image data of the object under test.

[0131] In this way, the main control board 2 and the base plate 1 can be combined and separated by plugging and unplugging the first FMC connector 11 and the first FMC interface 21; the ROIC board 3 and the base plate 1 can be combined and separated by plugging and unplugging the second FMC connector 12 and the second FMC interface 31; and the gate driver board 4 and the base plate 1 can be combined and separated by plugging and unplugging the third FMC connector 13 and the third FMC interface 41. Because the FMC connectors and FMC interfaces can be flexibly plugged and unplugged, the relevant boards in the board structure can be flexibly replaced by plugging and unplugging the FMC connectors and FMC interfaces. For example, when the relevant parameters of the ROIC board 3 change, it can simply be unplugged from the base plate 1 and the ROIC board 3 to be replaced can be inserted into the base plate 1; similarly, when the relevant parameters of the gate driver board 4 change, it can simply be unplugged from the base plate 1 and the gate driver board 4 to be replaced can be inserted into the base plate 1. This ensures signal interconnection between the main control board 2, ROIC board 3, and gate driver board 4, guaranteeing the performance of the flat panel detector while improving the compatibility and applicability of the board structure, thereby increasing the manufacturing efficiency of the flat panel detector.

[0132] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0133] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A board card structure, characterized by, The application relates to a board card structure of a multi-chip infrared image sensor, which comprises a bottom plate, a main control plate, an ROIC plate and a gate drive plate. The bottom plate is divided into a main control area, a reading area and a scanning area, and comprises a first FMC connector arranged in the main control area, a second FMC connector arranged in the reading area and a third FMC connector arranged in the scanning area. The main control plate comprises a first FMC interface for coupling with the first FMC connector, the ROIC plate comprises a second FMC interface for coupling with the second FMC connector, and the gate drive plate comprises a third FMC interface for coupling with the third FMC connector. The main control plate is used for obtaining a control instruction, loading a first control signal to the ROIC plate and loading a second control signal to the gate drive plate through the bottom plate according to the control instruction, and obtaining image data of a measured object. The ROIC plate further comprises a first chip connector coupled with the second FMC interface and arranged in one-to-one correspondence with ROIC chips, the first chip connector is used for coupling with the corresponding ROIC chip, the orthographic projection of the first chip connector on the ROIC plate and the orthographic projection of the second FMC interface on the ROIC plate do not overlap with each other, the ROIC plate is used for obtaining a configuration instruction after the control instruction is parsed by the main control plate through the second FMC interface, and performing signal configuration on the ROIC chip according to the configuration instruction, and after the signal configuration, the first control signal is sent to the ROIC chip through the second FMC interface, so that the ROIC chip reads image data according to the first control signal. The board card structure further comprises a first buffer coupled between the second FMC interface and the first chip connector, the first buffer is used for receiving the first control signal, dividing the first control signal into a plurality of first signals, and sending each first signal to the corresponding ROIC chip in parallel.

2. The board card structure of claim 1, wherein, The gate drive plate further comprises a second chip connector arranged in one-to-one correspondence with gate drive chips, the second chip connector is used for coupling with the corresponding gate drive chip, the orthographic projection of the second chip connector on the gate drive plate and the orthographic projection of the third FMC interface on the gate drive plate do not overlap with each other, and the gate drive plate is used for sending the second control signal to the gate drive chip through the third FMC interface, so that the gate drive chip scans the measured object according to the second control signal.

3. The board card structure of claim 1, wherein, The board card structure further comprises a second buffer coupled between the third FMC interface and the second chip connector, the second buffer is used for receiving the second control signal, dividing the second control signal into a plurality of second signals, and sending each second signal to the corresponding gate drive chip in parallel.

4. The board card structure of claim 3, wherein, The ROIC plate further comprises a plurality of SPI wires coupled between the first FMC connector and the second FMC interface, and each SPI wire is equal in length and thickness.

5. The board card structure according to any one of claims 1 to 4, wherein ​ 6. The board card structure according to any one of claims 1 to 4, wherein The main control board includes an external interface, which is used to receive control commands from the host computer.

7. The board card structure of claim 6, wherein, The external interfaces include a USB interface, a gigabit network interface, a 10-gigabit network interface, and a UART interface.

8. An X-ray flat panel detector device, characterized by include: The board structure as described in any one of claims 1-7, and the probe panel coupled to the ROIC board and the gate driver board in the board structure respectively.

9. An X-ray flat panel detector system, characterized by include: The board structure as described in any one of claims 1-7, and the host computer coupled to the board structure; wherein: The host computer is used to send control commands to the board structure; The board structure is used to obtain image data of the object under test according to the control command, and send the image data to the host computer.

10. A control method of an X-ray flat panel detection system as claimed in claim 9, characterized in that, include: The main control board receives control commands from the host computer. According to the control command, a first control signal is applied to the ROIC board via the base plate, and a second control signal is applied to the gate driver board to obtain image data of the object under test; The image data is sent to the host computer.

11. The control method according to claim 10, characterized by, The step of loading a first control signal onto the ROIC board via the base plate and a second control signal onto the gate driver board according to the control command to obtain image data of the object under test includes: The control commands are parsed to obtain configuration commands; The configuration command is received by the baseboard and sent to the ROIC board via the SPI protocol to configure the signal of the ROIC chip coupled to the ROIC board. After configuring the ROIC chip, a first control signal is applied to the ROIC board, and a second control signal is applied to the gate driver board to obtain image data of the object under test.

12. The control method according to claim 11, characterized by, The step of loading the first control signal onto the ROIC board includes: The first control signal is received through a first buffer coupled between the second FMC interface and the first chip connector on the ROIC board; The first control signal is divided into multiple first signals, and each of the first signals is sent in parallel to the ROIC board; The first signal is applied to the ROIC chip coupled to the ROIC board.

13. The control method according to claim 11, wherein The step of loading a second control signal onto the gate driver board includes: The second control signal is received through a second buffer coupled between the third FMC interface and the second chip connector on the gate driver board; The second control signal is divided into multiple second signals, and each of the second signals is sent to the gate driver board in parallel. The corresponding second signal is applied to the gate driver chip coupled to the gate driver board.

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