A test circuit and method of operation thereof

Abstract

The embodiment of the present disclosure provides a test circuit, which comprises a control circuit and N structure units to be tested, wherein N is an integer greater than 1; the control circuit comprises a first signal generation unit; the first signal generation unit is used for receiving a clock signal and a first input signal, and outputting a first selection signal according to the first input signal to select at least one of the N structure units to be tested.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor testing technology, and includes, but is not limited to, a test circuit and its operating method. Background Technology

[0002] As semiconductor devices continue to evolve and manufacturing processes become increasingly complex, test structures are typically used to assess process maturity and device performance during the development of semiconductor devices. When dealing with a large number of test structures, a significant number of pads are usually required as address input ports, which reduces chip area utilization. Summary of the Invention

[0003] In view of this, the main objective of this disclosure is to provide a test circuit and its operation method.

[0004] To achieve the above objectives, the technical solution disclosed herein is implemented as follows:

[0005] This disclosure provides a test circuit, the test circuit comprising:

[0006] The control circuit and N structural units to be tested, where N is an integer greater than 1;

[0007] The control circuit includes a first signal generation unit;

[0008] The first signal generation unit is used to receive a clock signal and a first input signal, and output a first selection signal according to the first input signal to select at least one of the N structural units to be tested.

[0009] In the above scheme, the test circuit further includes M address pads and a first decoding circuit;

[0010] The M address pads are used to output M initial address signals;

[0011] The first decoding circuit is used to receive the M initial address signals and decode and output 2. M Each of the test structural units includes 2 first address signals; each of the test structural units includes 2 M There are N test structures, and the N test structure units constitute an N×2 M The array of structures to be tested; each of the first address signals is used to select the N×2 array. M 2 in the array of structures under test M row or 2 M One of the columns, where M is an integer greater than 1.

[0012] In the above scheme, the control circuit is further configured to select the N×2 in response to the first address signal. M 2 in the array of structures under testM row or 2 M After selecting one of the N structural units to be tested, at least one of the N structural units to be tested is selected in response to the first selection signal.

[0013] In the above scheme, the control circuit further includes a second signal generation unit, which is used to receive a second input signal and a first selection signal, and output a second selection signal to select at least one of the N structural units to be tested.

[0014] In the above scheme, the control circuit is further configured to select the N×2 in response to the first address signal. M 2 in the array of structures under test M row or 2 M After selecting one of the N test structural units, at least one of them is selected in response to two adjacent valid bits in the second selection signal.

[0015] In the above scheme, the first signal generation unit includes N series-connected D flip-flops. The clock input terminal of the D flip-flops receives the clock signal, the data input terminal of the first-stage D flip-flop receives the first input signal, the data input terminals of the second to Nth-stage D flip-flops are connected to the non-inverting output terminal of the previous-stage D flip-flop, and the non-inverting output terminal of the Nth-stage D flip-flop outputs the first selection signal.

[0016] In the above scheme, the data input terminal of the first-stage D flip-flop is connected to the inverting output terminal of the first-stage D flip-flop.

[0017] In the above scheme, the reset terminals of the N D flip-flops receive reset signals.

[0018] In the above scheme, the second signal generation unit includes (N+1) OR gates. One of the input terminals of the first and (N+1)th OR gates serves as two second input terminals of the second signal generation unit to receive the second input signal. The remaining input terminals of adjacent OR gates are connected in pairs to serve as N first input terminals of the second signal generation unit to receive the first selection signal.

[0019] In the above scheme, each end of the N structural units to be tested is also provided with a switch unit; the second selection signal controls the opening or closing of the switch unit.

[0020] In the above scheme, the number of switching units is (N+1).

[0021] This disclosure also provides an operation method for a test circuit, the test circuit including N structural units to be tested, where N is an integer greater than 1; the method includes:

[0022] receiving a clock signal and a first input signal, and outputting a first selection signal to select at least one of the N DUT units according to the first input signal.

[0023] In the above solution, the test circuit further comprises M address pads and a first decoding circuit.

[0024] The M address pads are configured to output M initial address signals.

[0025] The first decoding circuit is configured to receive the M initial address signals, decode and output 2 M first address signals; each of the DUT units comprises 2 M DUTs, the N DUT units form an N×2 M DUT array, and M is an integer greater than 1.

[0026] In response to the first address signal, one of 2 M rows or 2 M columns in the N×2 M DUT array is selected, and M is an integer greater than 1.

[0027] In the above solution, after the one of 2 M rows or 2 M columns in the N×2 M DUT array is selected in response to the first address signal, the method further comprises:

[0028] In response to the first selection signal, at least one of the N DUT units is selected.

[0029] In the above solution, the method further comprises:

[0030] receiving a second input signal and the first selection signal, and outputting a second selection signal to select at least one of the N DUT units.

[0031] In the above solution, after the one of 2 M rows or 2 M columns in the N×2 M DUT array is selected in response to the first address signal, the method further comprises:

[0032] In response to two adjacent valid bits in the second selection signal, at least one of the N DUT units is selected.

[0033] The test circuit provided by the embodiment of the present disclosure comprises a control circuit and N structure units to be tested, N is an integer greater than 1; the control circuit comprises a first signal generation unit; the first signal generation unit is configured to receive a clock signal and a first input signal, and output a first selection signal to select at least one of the N structure units to be tested according to the first input signal. In this way, the test circuit provided by the embodiment of the present disclosure replaces the row address pad or the column address pad by the control circuit, reduces the use of the address pad, and can improve the area utilization of the test circuit. BRIEF DESCRIPTION OF DRAWINGS

[0034] Figure 1 a block diagram of a test circuit shown for an exemplary embodiment of the present disclosure;

[0035] Figure 2 a block diagram of a test circuit shown for an embodiment of the present disclosure;

[0036] Figure 3 a circuit structure schematic diagram of a first signal generation unit shown in an embodiment of the present disclosure;

[0037] Figure 4 a circuit structure schematic diagram of a first signal generation unit shown for another embodiment of the present disclosure;

[0038] Figure 5 a first signal generation unit shown for Figure 4 a timing diagram of the first selection signal generated by the first signal generation unit shown;

[0039] Figure 6 a circuit structure schematic diagram of a first signal generation unit shown for another embodiment of the present disclosure;

[0040] Figure 7 a circuit structure schematic diagram of a first signal generation unit shown for another embodiment of the present disclosure;

[0041] Figure 8 a first signal generation unit shown for Figure 7 a timing diagram of the first selection signal generated by the first signal generation unit shown;

[0042] Figure 9 a block diagram of a test circuit shown for another embodiment of the present disclosure;

[0043] Figure 10 a circuit structure schematic diagram of a control circuit shown for an embodiment of the present disclosure;

[0044] Figure 11 a circuit structure schematic diagram of another control circuit shown for an embodiment of the present disclosure;

[0045] Figure 12 a control circuit shown for Figure 11The first signal generation unit shown generates a timing chart of the first selection signal. DETAILED DESCRIPTION

[0046] The technical solutions of the present disclosure will be further described in detail below in conjunction with the drawings and examples. Although the exemplary implementation methods of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the implementation described herein. On the contrary, these implementations are provided to enable a more thorough understanding of the present disclosure and to convey the scope of the present disclosure to those skilled in the art.

[0047] The present disclosure will be described in more detail in the following paragraphs with reference to the accompanying drawings. The advantages and features of the present disclosure will be more apparent from the following description and claims. It should be noted that the drawings are all very simplified and use non-precise proportions, only for the purpose of facilitating, clarifying and assisting in the description of the embodiments of the present disclosure.

[0048] It should be understood that spatial relationship terms such as "below", "under", "lower", "underneath", "above", "upper", etc. can be used herein for the convenience of description to describe the relationship between one element or feature and other elements or features shown in the drawings. It should be understood that in addition to the orientation shown in the drawings, the spatial relationship terms are intended to include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, then the element or feature described as "below" or "under" or "underneath" the other element will be oriented "above" the other element or feature. Therefore, the exemplary terms "below" and "under" can include both the upward and downward orientations. The device can be additionally oriented (rotated 90 degrees or other orientations) and the spatial descriptions used herein are interpreted accordingly.

[0049] The terms used herein are only for the purpose of describing specific embodiments and not as a limitation of the present disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the terms "comprise" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0050] It should be noted that the technical solutions described in the embodiments of the present disclosure can be combined arbitrarily without conflict.

[0051] With the continuous development of semiconductor devices, the manufacturing process involves many complex steps, each of which may have specific manufacturing deviations, ultimately leading to a decrease in yield. To improve the yield of semiconductor devices, it is common practice to test the test structures in the test chip to obtain the data necessary for improving the manufacturing process and design yield.

[0052] In the aforementioned test chip, the test structure needs to be individually connected to the pads. Each test structure requires two or more pads, and the size of a pad is usually large, such as 60μm×60μm. This results in the pads occupying most of the area of ​​the test chip, leading to a very low area utilization rate of the test chip.

[0053] For the reasons mentioned above, ordinary addressable test chips can significantly reduce the number of pads by introducing address decoding circuits, thereby improving the area utilization of the test chip. Figure 1 This is a block diagram illustrating a test circuit as an exemplary embodiment of the present disclosure. Figure 1 As shown, the test circuit 100 includes M row address pads 101, a row decoding circuit 102, N column address pads 103, a column decoding circuit 104, and a test structure array 105. Here, M and N are both integers greater than 1.

[0054] M row address pads 101 provide M row address bits. After passing through the row decoding circuit 102, the M row address bits can be output as AND-2. M Each row address corresponds to 2 M Row address signal (Row <1> To Row < 2 M >). N column address pads 103 provide N column address bits, which, after passing through column decoding circuit 104, can be output as AND-2. N Each column address corresponds to 2 N Individual column address signal (Col <1> To Col < 2 N Therefore, M row address pads 101 and N column address pads 103 can control 2 M ×2 N There are 106 test structures, that is, the test structure array 105 is 2 M ×2 N The test structure array.

[0055] The number of address pads was reduced by introducing an address decoding circuit, but the large area occupied by the pads did not allow for the placement of test structures and the pads themselves were large, so the problem of large test circuit area and low area utilization still existed.

[0056] The present disclosure provides the following implementation methods.

[0057] Figure 2This is a block diagram illustrating a test circuit according to an embodiment of this disclosure. It should be noted that... Figure 2 The following explanation uses a control circuit to replace the column address pads as an example. Figure 2 As shown, the test circuit 200 includes:

[0058] The control circuit 206 and N test structural units 204, where N is an integer greater than 1;

[0059] The control circuit 206 includes a first signal generation unit 207;

[0060] The first signal generation unit 207 is used to receive a clock signal clock and a first input signal d_in1, and output a first selection signal Sel_1 according to the first input signal d_in1 to select at least one of the N test structure units 204.

[0061] In this embodiment of the disclosure, the test circuit 200 further includes M address pads 201 and a first decoding circuit 202. In a specific example, the M address pads 201 serve as row address pads providing M initial address signals (ADDR1 to ADDRM), and the first decoding circuit 202 serves as a row decoding circuit receiving the M initial address signals and decoding the output. M Each row address corresponds to 2 M The first address signal (Row) <1> To Row < 2 M >), where M is an integer greater than 1. The larger the value of M, the more first address signals the first decoding circuit 202 can output.

[0062] In some embodiments, each structural unit 204 under test includes 2 M There are 205 structures to be tested, and N structural units to be tested constitute an N×2 M The array of structures under test 203; each first address signal is used to select N×2 M 2 in the array of structures under test 203 M row or 2 M In the sequence, M is an integer greater than 1. Figure 2 In the test circuit shown, each first address signal is used to select N×2 M 2 in the array of structures under test 203 M In the row, M is an integer greater than 1.

[0063] In this embodiment of the disclosure, the control circuit 206 is further configured to, in response to the first address signal, select N×2 M 2 in the array of structures under test 203 M row or 2 M After selecting one of the N test structural units 204, at least one is selected in response to the first selection signal Sel_1. For example...Figure 2 As shown, N×2 M 2 in the array of structures under test 203 M Each row in the array contains N test structures 205. It can be understood that the control circuit selects N×2 in response to the first address signal. M 2 in the array of structures under test 203 M After one of the rows, in response to the first selection signal Sel_1, from the selected 2 M Selecting at least one of the N structural units 204 to be tested from one row will select N×2 M The structure under test 205 corresponding to the structure under test array 203.

[0064] In one embodiment, the control circuit 206 is configured to respond to the first address signal Row <2> Select N×2 M 2 in the array of structures under test 203 M After the second row, in response to the first selection signal Sel_1, the Nth test unit among the N test units 204 is selected. Thus, the control circuit uses the first address signal Row... <2> The first selection signal Sel_1 selected N×2 M The test structure 205 corresponding to the second row and Nth column in the test structure array 203.

[0065] Figure 3 This is a schematic diagram of the circuit structure of the first signal generation unit shown in one embodiment of this disclosure. Figure 3 As shown, the first signal generation unit includes N cascaded D flip-flops. The clock input terminal CLK of the D flip-flops receives the clock signal clock. The data input terminal of the first-stage D flip-flop DFF1 receives the first input signal d_in1. The second to Nth stages of the D flip-flops (DFF2 to DFF...) n The data input terminal D is connected to the non-inverting output terminal Q of the previous stage D flip-flop. The non-inverting output terminal Q of the N-stage D flip-flop outputs the first selection signal Sel_1. The clock signal clock is provided by the clock signal pad.

[0066] Generally, the first input signal d_in1 is provided by the data signal pad. In this embodiment, the data input terminal D of the first-stage D flip-flop DFF1 is connected to the inverted output terminal Q′ of the first-stage D flip-flop DFF1. It can be understood that the output value of the inverted output terminal Q′ of the first-stage D flip-flop DFF1 serves as the first input signal d_in1 and is output to the data input terminal D of the first-stage D flip-flop DFF1. Thus, there is no need to specifically set up a data signal pad for outputting the first input signal d_in1, increasing the area utilization of the test circuit by reducing the use of the data signal pad.

[0067] It should be noted that Figure 3 The first signal generation unit composed of N series D flip-flops outputs a first selection signal Sel_1 when a clock pulse of the clock signal clock arrives. It can be understood that the first signal generation unit composed of N series D flip-flops outputs N first selection signals Sel_1 corresponding to N clock pulses in turn when N clock pulses of the clock signal clock arrive in turn, and the N first selection signals Sel_1 correspond to N structure units to be tested in one-to-one correspondence. Each first selection signal Sel_ is an N-bit binary number, which is output in parallel by Q1 to QN of the non-inverted output end Q of the N-stage D flip-flop when the clock pulse arrives. n .

[0068] In the embodiment of the present disclosure, the reset end RST of the N D flip-flops receives a reset signal reset. The N D flip-flops enter an initial state after being reset in response to the reset signal reset being at an effective level. The reset signal reset is provided by a reset signal pad. In some embodiments, the initial states of the first-stage to N-stage D flip-flops (DFF1 to DFFN) are all low logic level “0”. n .

[0069] Figure 4 The circuit structure schematic diagram of the first signal generation unit is shown for another embodiment of the present disclosure. It should be noted that Figure 4 Taking N equal to 4 as an example for description. As shown in Figure 4 , the first signal generation unit includes 4 series D flip-flops DFF1, DFF2, DFF3 and DFF4, the clock input end CLK of the D flip-flop DFF1, DFF2, DFF3 and DFF4 receives the clock signal clock, the data input end D of the first-stage D flip-flop DFF1 receives the first input signal d_in1, the data input end D of the second to fourth-stage D flip-flops (DFF2 to DFF4) is connected to the non-inverted output end Q of the previous-stage D flip-flop, and the non-inverted output end Q of the 4-stage D flip-flop outputs the first selection signal Sel_1.

[0070] The data input end D of the first-stage D flip-flop DFF1 is connected to the inverted output end Q' of the first-stage D flip-flop DFF1, so that the output value of the inverted output end Q' of the first-stage D flip-flop DFF1 is output as the first input signal d_in1 to the data input end D of the first-stage D flip-flop DFF1.

[0071] Figure 5 The timing diagram of the first selection signal generated by the first signal generation unit shown in Figure 4 is shown in Table 1, which is the logic level value of each signal corresponding to Figure 4 different stages.

[0072] Table 1

[0073] CP d_in1 Q1 Q2 Q3 Q4 0 1 0 0 0 0 1 0 1 0 0 0 2 1 0 1 0 0 3 0 1 0 1 0 4 1 0 1 0 1

[0074] Please see Figure 4 , Figure 5 As shown in Table 1, before time T1, the four D flip-flops in the first signal generation unit respond to the reset signal (which is at an active level) and enter their initial state after being reset. In a specific example, the initial state of the four D flip-flops in the first signal generation unit is a low logic level "0", that is, the initial states Q1Q2Q3Q4 of the four D flip-flops are set to 0000. Since the data input terminal D of the first-stage D flip-flop DFF1 is connected to the inverted output terminal Q′ of the first-stage D flip-flop DFF1, the first input signal d_in1 is a high logic level "1" before time T1.

[0075] At time T1, the first clock pulse CP1 of the clock signal arrives. At this time, the first input signal d_in1 received by the data input terminal D of DFF1 is still at the high logic level "1" before time T1. The non-inverting output terminal Q of the first-stage flip-flop DFF1 outputs Q1, which is at the high logic level "1". The inverting output terminal Q′ of the first-stage flip-flop DFF1 outputs the low logic level "0". Therefore, before the next clock pulse arrives, the first input signal d_in1 will be at the low logic level "0". Since there is a certain transmission delay time from the data input terminal D to the non-inverting output terminal Q, the second-stage flip-flop DFF2, the third-stage flip-flop DFF3, and the fourth-stage flip-flop DFF4 will follow in their original state. That is, the data input terminals D of the second-stage flip-flop DFF2, the third-stage flip-flop DFF3, and the fourth-stage flip-flop DFF4 will receive Q1, Q2, and Q3 respectively before the arrival of the first clock pulse CP1. When the first clock pulse CP1 arrives, the four-bit binary number Q1Q2Q3Q4, which is output in parallel by the non-inverting output terminals Q of the four D flip-flops, is 1000. It is understandable that when the first clock pulse CP1 arrives, the first selection signal Sel_1 is 1000.

[0076] At T2, the second clock pulse CP2 of the clock signal clock arrives, at this time the first input signal d_in1 received by the data input terminal D of the DFF1 is still the low logic level "0" before T2, the non-inverted output terminal Q of the first flip-flop DFF1 outputs Q1, Q1 is the low logic level "0", the inverted output terminal Q' of the first flip-flop DFF1 outputs the high logic level "1", thus the first input signal d_in1 is the high logic level "1" before the next clock pulse arrives. The data input terminals D of the second flip-flop DFF2, the third flip-flop DFF3 and the fourth flip-flop DFF4 respectively receive Q1, Q2 and Q3 before the second clock pulse CP2 arrives. When the second clock pulse CP2 arrives, the four-bit binary number Q1Q2Q3Q4 outputted by the non-inverted output terminals Q of the four D flip-flops in parallel is 0100. It can be understood that the first selection signal Sel_1 is 0100 when the second clock pulse CP2 arrives.

[0077] At T3, the third clock pulse CP3 of the clock signal clock arrives, at this time the first input signal d_in1 received by the data input terminal D of the DFF1 is still the high logic level "1" before T3, the non-inverted output terminal Q of the first flip-flop DFF1 outputs Q1, Q1 is the high logic level "1", the inverted output terminal Q' of the first flip-flop DFF1 outputs the low logic level "0", thus the first input signal d_in1 is the low logic level "0" before the next clock pulse arrives. The data input terminals D of the second flip-flop DFF2, the third flip-flop DFF3 and the fourth flip-flop DFF4 respectively receive Q1, Q2 and Q3 before the third clock pulse CP3 arrives. When the third clock pulse CP3 arrives, the four-bit binary number Q1Q2Q3Q4 outputted by the non-inverted output terminals Q of the four D flip-flops in parallel is 1010. It can be understood that the first selection signal Sel_1 is 1010 when the third clock pulse CP3 arrives.

[0078] At T4, the fourth clock pulse CP4 of the clock signal clock arrives, the first input signal d_in1 received by the data input terminal D of the DFF1 is still the low logic level "0" before T4, the non-inverted output terminal Q of the first flip-flop DFF1 outputs Q1, and Q1 is a low logic level "0", the inverted output terminal Q' of the first flip-flop DFF1 outputs a high logic level "1", so the first input signal d_in1 is a high logic level "1" before the next clock pulse arrives. The data input terminals D of the second flip-flop DFF2, the third flip-flop DFF3 and the fourth flip-flop DFF4 receive Q1, Q2 and Q3 respectively before the fourth clock pulse CP4 arrives. When the fourth clock pulse CP4 arrives, the four-bit binary number Q1Q2Q3Q4 output in parallel by the non-inverted output terminals Q of the four D flip-flops is 0101. It can be understood that the first selection signal Sel_1 is 0101 when the fourth clock pulse CP3 arrives.

[0079] Figure 4 The first signal generation unit composed of the four D flip-flops in series outputs a first selection signal Sel_1 when a clock pulse of the clock signal clock arrives. It can be understood that the first signal generation unit composed of the four D flip-flops in series outputs four first selection signals Sel_1 corresponding to the four clock pulses in turn when the four clock pulses of the clock signal clock arrive in turn, and the four first selection signals Sel_1 correspond to the four structure units to be tested in turn. Each first selection signal Sel_ is a four-bit binary number composed of Q1, Q2, Q3 and Q4 output in parallel by the non-inverted output terminals Q of the four D flip-flops when a clock pulse arrives.

[0080] In some embodiments, N is equal to 4 and M is equal to 3 are taken as examples, Figure 2 The test circuit shown includes four structure units to be tested, each of which includes eight structures to be tested, and the four structure units to be tested constitute a 4x8 structure array to be tested. In a specific example, the four first selection signals Sel_1 output in turn by the first signal generation unit are 1000, 0100, 1010 and 0101 respectively when the four pulses CP1, CP2, CP3 and CP4 of the clock signal clock arrive in turn. The four first selection signals 1000, 0100, 1010 and 0101 correspond to the four structure units to be tested in turn, and the control circuit is configured to select at least one of the four structure units to be tested in response to the first selection signal Sel_1 after selecting one of the eight rows of the 4x8 structure array to be tested in response to the first address signal.

[0081] In some embodiments, when N equals 4 and M equals 3, the test circuit needs to set 3 address pads to control the 4x8 array of structures under test, which reduces 2 address pads relative to the test circuit shown in Figure 1 , and reduces the overall area occupied by the address pads, thereby increasing the area utilization of the test circuit.

[0082] The test circuit provided by the embodiments of the present disclosure can reduce the number of address pads to log2N when facing an Nx2 M array of structures under test, and can greatly reduce the area occupied by the test circuit when controlling the same number of structures under test, or greatly increase the number of structures under test in the same size test circuit. In summary, the test circuit provided by the embodiments of the present disclosure can improve the area utilization of the test circuit.

[0083] It should be noted that in other variants of the present disclosure, the row address pad and the column address pad can be replaced by two first signal generation units at the same time. It is easy to understand that when facing an Nx2 M array of structures under test, the number of pads in the test circuit can be reduced to two (a clock signal pad and a reset signal pad), and no address pad is needed. After selecting one of the 2 M rows in the Nx2 M array of structures under test by one first signal generation unit, at least one of the N structures under test is selected by another first signal generation unit. One of the two first signal generation units includes 2 M D flip-flops in series, and the other includes N D flip-flops in series. The circuit structure of the first signal generation unit can refer to the related description in the embodiments of the present disclosure, which will not be repeated here.

[0084] Figure 6 The circuit structure of the first signal generation unit is shown in another embodiment of the present disclosure. As shown in Figure 6 , the first signal generation unit includes N D flip-flops in series. The clock input end CLK of the D flip-flop receives the clock signal clock. The data input end D of the first-stage D flip-flop DFF1 receives the first input signal d_in1 from the data pad. The data input ends D of the second to N-stage D flip-flops (DFF2 to DFF n ) are connected to the non-inverted output end Q of the previous-stage D flip-flop. The non-inverted output ends Q of the N-stage D flip-flops output the first selection signal.

[0085] In some embodiments, the first input signal d_in_1 is at a high logic level "1" when a first clock pulse of the clock signal clock arrives, and the first input signal d_in_1 is at a low logic level "0" when other clock pulses of the clock signal clock arrive.

[0086] It should be noted that, Figure 6 The first signal generation unit shown by the N serially connected D flip-flops outputs a first selection signal when a clock pulse of the clock signal clock arrives. It can be understood that each first selection signal is an N-bit binary number, which is output in parallel by Q1 to QN of the positive output terminals Q of the N-stage D flip-flops when the clock pulse arrives. n In some embodiments, each first selection signal includes two adjacent valid bits at a high logic level "1".

[0087] In the embodiments of the present disclosure, the reset terminals RST of the N D flip-flops receive a reset signal reset. The N D flip-flops enter an initial state after being reset in response to the reset signal reset being at a valid level.

[0088] In some embodiments, the initial state of the first-stage D flip-flop DFF1 is a high logic level "1", and the initial state of the second-stage to Nth-stage D flip-flops (DFF2 to DFF n ) is a low logic level "0".

[0089] Figure 6 The to-be-tested structure unit 204 shown in FIG. 2 is Figure 2 A simple schematic diagram of the to-be-tested structure unit shown in FIG. 2 is Figure 6 Each to-be-tested structure unit 204 shown in FIG. 2 includes 2 M to-be-tested structures, and Figure 6 The to-be-tested structure unit shown in FIG. 2 is Figure 2 one of the N to-be-tested structure units in FIG. 2. It can be understood that, when each clock pulse of the clock signal clock arrives, Figure 6 the first selection signal Sel_1 in FIG. 2 is used to select at least one of the (N-1) to-be-tested structure units 204.

[0090] In a specific implementation manner, Figure 6 The (N-1) to-be-tested structure units shown in FIG. 2 constitute an (N-1) × 2 M to-be-tested structure array, and the (N-1) × 2 MThe structures under test (DUTs) in the array of structures under test (DUTs) can be two-ended structures, such as resistors. Each DUT cell 204 is controlled by two adjacent bits in the N-bit binary number of the first selection signal, so the N-bit binary number of the first selection signal can control the two ends of (N-1) DUT cells. A DUT cell is selected by two adjacent valid bits that are at a high logic level "1" in the N-bit binary number of the first selection signal.

[0091] In some embodiments, N equals 4 and M equals 3 as an example. Figure 7 This is a schematic diagram of the circuit structure of the first signal generation unit shown in yet another embodiment of this disclosure. Figure 7 As shown, the first signal generation unit includes four cascaded D flip-flops DFF1, DFF2, DFF3, and DFF4. The clock input terminal CLK of the D flip-flops DFF1, DFF2, DFF3, and DFF4 receives the clock signal clock. The data input terminal D of the first-stage D flip-flop DFF1 receives the first input signal d_in1 from the data pad. The data input terminals D of the second to fourth-stage D flip-flops (DFF2 to DFF4) are connected to the non-inverting output terminal Q of the previous stage D flip-flop. The non-inverting output terminal Q of each D flip-flop outputs a first selection signal.

[0092] Figure 8 for Figure 7 The timing diagram shown is the generation of the first selection signal by the first signal generation unit. Table 2 shows the timing diagram of the first signal generation unit generating the first selection signal. Figure 8 The logic level values ​​of each signal at different stages.

[0093] Table 2

[0094] CP d_in1 Q1 Q2 Q3 Q4 0 0 1 0 0 0 1 1 1 1 0 0 2 0 0 1 1 0 3 0 0 0 1 1

[0095] Please see Figure 7 , Figure 8 As shown in Table 2, before time T1, the four D flip-flops in the first signal generation unit are reset and enter their initial state in response to the reset signal at an active level. In a specific example, the initial state of the first-stage D flip-flop DFF1 is a high logic level "1", and the initial states of the second to fourth-stage D flip-flops (DFF2 to DFF4) are low logic levels "0", that is, the initial states Q1Q2Q3Q4 of the four D flip-flops are set to 1000. Before time T1, the first input signal d_in1 is a low logic level "0".

[0096] At T1, the first clock pulse CP1 of the clock signal clock arrives, at which time the first input signal d_in1 received by the data input D of the DFF1 is a high logic level "1", thus the non-inverted output Q of the first stage flip-flop DFF1 outputs Q1, which is a high logic level "1". The data inputs D of the second stage flip-flop DFF2, the third stage flip-flop DFF3 and the fourth stage flip-flop DFF4 respectively receive Q1, Q2 and Q3 before the arrival of the first clock pulse CP1. When the first clock pulse CP1 arrives, the four-bit binary number Q1Q2Q3Q4 output in parallel by the non-inverted outputs Q of the four D flip-flops is 1100. It can be understood that the first selection signal is 1100 when the first clock pulse CP1 arrives. Specifically, the control circuit is configured to select the first one of the three under-test structure units 204 in response to the adjacent two active bits (Q1 and Q2) in the high logic level "1" in the first selection signal after selecting one of the 8 rows in the 3x8 under-test structure array in response to the first address signal.

[0097] At T2, the second clock pulse CP2 of the clock signal clock arrives, at which time the first input signal d_in1 received by the data input D of the DFF1 is a low logic level "0", thus the non-inverted output Q of the first stage flip-flop DFF1 outputs Q1, which is a low logic level "0". The data inputs D of the second stage flip-flop DFF2, the third stage flip-flop DFF3 and the fourth stage flip-flop DFF4 respectively receive Q1, Q2 and Q3 before the arrival of the second clock pulse CP2. When the second clock pulse CP2 arrives, the four-bit binary number Q1Q2Q3Q4 output in parallel by the non-inverted outputs Q of the four D flip-flops is 0110. It can be understood that the second selection signal is 0110 when the second clock pulse CP2 arrives. Specifically, the control circuit is configured to select the second one of the three under-test structure units 204 in response to the adjacent two active bits (Q2 and Q3) in the high logic level "1" in the second selection signal after selecting one of the 8 rows in the 3x8 under-test structure array in response to the first address signal.

[0098] At time T3, the third clock pulse CP3 of the clock signal clock arrives. At this time, the first input signal d_in1 received by the data input terminal D of DFF1 is at a low logic level "0". Therefore, the non-inverting output terminal Q of the first-stage flip-flop DFF1 outputs Q1, which is at a low logic level "0". The data input terminals D of the second-stage flip-flop DFF2, the third-stage flip-flop DFF3, and the fourth-stage flip-flop DFF4 receive Q1, Q2, and Q3 respectively before the arrival of the third clock pulse CP3. When the third clock pulse CP3 arrives, the four-bit binary number Q1Q2Q3Q4, which is output in parallel by the non-inverting output terminals Q of the four D flip-flops, is 0011. It can be understood that the first selection signal is 0011 when the third clock pulse CP3 arrives. Specifically, the control circuit is configured to select one of the eight rows in the 3×8 array of structures under test in response to the first address signal, and then select the third structure under test unit 204 out of the three structure under test units in response to the two adjacent valid bits (Q3 and Q4) at a high logic level "1" in the first selection signal.

[0099] In some embodiments, when N equals 5 and M equals 3, the test circuit needs to set up 3 address pads to control 4×8 structures under test in a 5×8 array of structures under test, relative to Figure 1 The test circuit shown reduces the number of address pads by 2 (log24) when controlling 4×8 structures under test, which can increase the area utilization of the test circuit.

[0100] The test circuit provided in this embodiment replaces the row address pads or column address pads with a first signal generation unit, when facing N×2 M When arranging the array of structures under test, it is possible to control (N-1)×2 of them. M For each structure under test, the number of address pads is reduced by log2(N-1), which can improve the area utilization of the test circuit.

[0101] Figure 9 This is a block diagram illustrating a test circuit according to another embodiment of the present disclosure. It should be noted that... Figure 9 The following explanation uses a control circuit to replace the column address pads as an example. Figure 9 As shown, the test circuit 200 includes:

[0102] The control circuit 206 and N test structural units 204, where N is an integer greater than 1;

[0103] The control circuit 206 includes a first signal generation unit 207;

[0104] The first signal generation unit 207 is used to receive a clock signal clock and a first input signal d_in1, and output a first selection signal Sel_1 according to the first input signal d_in1 to select at least one of the N test structure units 204.

[0105] In this embodiment of the disclosure, the test circuit 200 further includes M address pads 201 and a first decoding circuit 202. In a specific example, the M address pads 201 serve as row address pads providing M initial address signals (ADDR1 to ADDRM), and the first decoding circuit 202 serves as a row decoding circuit receiving the M initial address signals and decoding the output. M Each row address corresponds to 2 M The first address signal (Row) <1> To Row < 2 M >), where M is an integer greater than 1. The larger the value of M, the more first address signals the first decoding circuit 202 can output.

[0106] In some embodiments, each structural unit 204 under test includes 2 M There are 205 structures to be tested, and N structural units to be tested constitute an N×2 M The array of structures under test 203; each first address signal is used to select N×2 M 2 in the array of structures under test 203 M In the row, M is an integer greater than 1.

[0107] In some embodiments, the control circuit 206 further includes a second signal generation unit 208, which is used to receive a second input signal d_in2 and a first selection signal Sel_1, and output a second selection signal Sel_2 to select at least one of the N test structural units 204.

[0108] In this embodiment of the disclosure, the control circuit is further configured to select N×2 in response to the first address signal. M 2 in the array of structures under test M After one of the rows, at least one of the N test structural units is selected in response to two adjacent valid bits in the second selection signal Sel_2.

[0109] like Figure 9 As shown, N×2 M 2 in the array of structures under test 203 M Each row in the array contains N test structures 205. It can be understood that the control circuit selects N×2 in response to the first address signal. M 2 in the array of structures under test 203 M After one of the rows, in response to the second selection signal Sel_2, from the selected 2 MSelecting at least one of the N structural units 204 to be tested from one row will select N×2 M The structure under test 205 corresponding to the structure under test array 203.

[0110] In one embodiment, the control circuit 206 is configured to respond to the first address signal Row <2> Select N×2 M 2 in the array of structures under test 203 M After the second row, in response to the second selection signal Sel_2, the Nth test unit among the N test units 204 is selected. Thus, the control circuit uses the first address signal Row... <2> The second selection signal Sel_2 selected N×2 M The test structure 205 corresponding to the second row and Nth column in the test structure array 203.

[0111] Figure 10 This is a schematic diagram of the circuit structure of a control circuit according to an embodiment of this disclosure. Figure 10 As shown, the first signal generation unit 207 in the control circuit includes N D flip-flops connected in series. The clock input terminal CLK of the D flip-flops receives the clock signal clock. The data input terminal D of the first-stage D flip-flop DFF1 receives the first input signal d_in1 from the data pad. The second to Nth stages of the D flip-flops (DFF2 to DFF...) n The data input terminal D is connected to the non-inverting output terminal Q of the previous stage D flip-flop. The clock signal clock and the first input signal d_in1 are provided by the clock signal pad and the data signal pad, respectively.

[0112] Figure 10 The first signal generation unit 207 in the control circuit shown outputs a first selection signal when the clock pulse of the clock signal arrives. It can be understood that each... Figure 9 The first selection signal Sel_1 shown is an N-bit binary number, which is composed of... Figure 10 The non-inverting output Q of the N-stage D flip-flop shown outputs Q1 to Q2 in parallel when the clock pulse arrives. n composition.

[0113] In some embodiments, each first selection signal includes a valid bit at a high logic level "1".

[0114] In this embodiment of the disclosure, the reset terminals RST of the N D flip-flops receive a reset signal. The N D flip-flops, in response to the active reset signal, are reset and enter their initial state. The reset signal is provided by the reset signal pad.

[0115] In some embodiments, the first to Nth level D flip-flops (DFF1 to DFF) n The initial state of all of them is a low logic level "0".

[0116] like Figure 10 As shown, the second signal generation unit 208 in the control circuit includes (N+1) OR gates (OR1 to OR2). n+1 The first and (N+1)th OR gates are used as two second inputs N2 of the second signal generation unit 208 to receive the second input signal d_in_2; the remaining inputs of the adjacent OR gates are connected in pairs to serve as N first inputs N1 of the second signal generation unit 208, which are connected one-to-one with the N positive outputs Q of the N D flip-flops.

[0117] When the clock pulse of the clock signal arrives, (N+1) OR gates (OR1 to OR2) are executed. n+1 The N first input terminals N1 of the N-stage D flip-flop receive the first selection signal output from the non-inverting output terminal Q, and (N+1) OR gates (OR1 to OR2) are used. n+1 The two second input terminals N2 of the first selection signal receive the second input signal d_in_2. The second input signal d_in_2 and the first selection signal are logically operated on by (N+1) OR gates to output the second selection signal. Each second selection signal is an (N+1)-bit binary number, which is generated by the outputs of the (N+1) OR gates from 01 to 01 when the clock pulse arrives. n+1 The structure is as follows: Specifically, the first OR gate OR1 receives the first bit (Q1) of the second input signal d_in_2 and the first N-bit binary number of the first selection signal and outputs O1. The second OR gate OR2 receives the first bit (Q1) of the first N-bit binary number of the first selection signal and the second bit (Q2) of the first selection signal and outputs O2. This process continues for the Nth OR gate... n Receive = the (N-1)th bit (Q) of the N-bit binary number of the first selection signal n-1 ) and the Nth bit (Q) of the N-bit binary number of the first selection signal n And output O n The (N+1)th OR gate n+1 The Nth bit (Q) of the N-bit binary number received from the second input signal d_in_2 and the first selection signal n And output O n+1 Understandably, each Figure 9 The second selection signal Sel_2 shown is an (N+1)-bit binary number, which is composed of... Figure 10 The diagram shows the outputs O1 to O2 from the outputs of (N+1) OR gates when the clock pulse arrives.n+1 Composition.

[0118] In some embodiments, the first input signal d_in_1 is at a high logic level "1" when a first clock pulse of the clock signal clock arrives, and the first input signal d_in_1 is at a low logic level "0" when other clock pulses of the clock signal clock arrive. The second input signal d_in_2 remains at a low logic level "0".

[0119] In some embodiments, each second selection signal includes two adjacent valid bits at a high logic level "1".

[0120] Figure 10 The to-be-tested structure unit 204 shown in FIG. 2 is Figure 9 a simple schematic of the to-be-tested structure unit shown in FIG. 2, that is Figure 10 each to-be-tested structure unit 204 shown in FIG. 2 includes 2 M to-be-tested structures.

[0121] In a specific embodiment, Figure 10 the N to-be-tested structure units shown constitute an N×2 M to-be-tested structure array, and the to-be-tested structures in the N×2 M to-be-tested structure array can be two-terminal to-be-tested structures such as resistors. Each to-be-tested structure unit 204 is controlled by two adjacent bits in an (N+1)-bit binary number of the second selection signal, and thus the (N+1)-bit binary number of the second selection signal can control two terminals of the N to-be-tested structure units. One to-be-tested structure unit is selected by two adjacent valid bits at a high logic level "1" in the (N+1)-bit binary number of the second selection signal.

[0122] In some embodiments, an example is described with N equal to 4 and M equal to 3. Figure 11 Another circuit structure schematic of a control circuit shown in an embodiment of the present disclosure. As Figure 11 shown, the first signal generation unit 207 in the control circuit includes four D flip-flops DFF1, DFF2, DFF3 and DFF4 connected in series, the clock input terminals CLK of the D flip-flops DFF1, DFF2, DFF3 and DFF4 receive the clock signal clock, the data input terminal D of the first-stage D flip-flop DFF1 receives the first input signal d_in1 from a data pad, the data input terminals D of the second to fourth-stage D flip-flops (DFF2 to DFF4) are connected to the non-inverted output terminals Q of the previous-stage D flip-flop, and the non-inverted output terminals Q of each D flip-flop output a first selection signal.

[0123] The second signal generating unit 208 in the control circuit includes five OR gates (OR1 to OR5). One input of the first and fifth OR gates is connected to two second inputs N2 of the second signal generating unit 208, for receiving the second input signal d_in_2. The remaining inputs of the adjacent OR gates are connected two by two, as four first inputs N1 of the second signal generating unit 208, and are connected one by one with the four positive outputs Q of the four D flip-flops. At each clock pulse of the clock signal clock, the four first inputs N1 of the five OR gates (OR1 to OR5) receive the four first selection signals Sel_1 output by the positive outputs Q of the four D flip-flops, and the two second inputs N2 of the five OR gates (OR1 to OR5) receive the second input signal d_in_2. A five-bit binary number O1O2O3O4O5 output by the five OR gates (OR1 to OR5) is the second selection signal.

[0124] Figure 12 For Figure 11 the first signal generating unit 207 generates the first selection signal, and Table 3 shows the logic level values of the corresponding signals at different stages. Figure 12

[0125] Table 3

[0126] CP d_in1 Q1 Q2 Q3 Q4 0 0 0 0 0 0 1 1 1 0 0 0 2 0 0 1 0 0 3 0 0 0 1 0 4 0 0 0 0 1

[0127] Please refer to Figure 11 , Figure 12 and Table 3. Before the time T1, the four D flip-flops in the first signal generating unit 207 are reset to the initial state in response to the reset signal reset being at the active level. In a specific example, the initial state of the first to fourth D flip-flops (DFF1 to DFF4) is a low logic level "0", i.e. the initial state Q1Q2Q3Q4 of the four D flip-flops is set to 0000. The first input signal d_in1 is at a low logic level "0" before the time T1.

[0128] ​At T1, the first clock pulse CP1 of the clock signal clock arrives, the first input signal d_in1 received by the data input terminal D of the DFF1 is high logic level "1", therefore the positive output terminal Q of the first stage flip-flop DFF1 outputs Q1, Q1 is high logic level "1". The data input terminals D of the second stage flip-flop DFF2, the third stage flip-flop DFF3 and the fourth stage flip-flop DFF4 respectively receive Q1, Q2 and Q3 before the arrival of the first clock pulse CP1. When the first clock pulse CP1 arrives, the four-bit binary number Q1Q2Q3Q4 output in parallel by the four D flip-flops is 1000, i.e. the first selection signal is 1000. The second input signal d_in2 remains low logic level "0", therefore the five-bit binary number output by the five or gates after the logic operation on the second input signal d_in2 and the first selection signal is 11000, i.e. the second selection signal is 11000. Specifically, the control circuit is configured to, after selecting one of the 8 rows in the 4x8 structure array to be tested in response to the first address signal, select the first structure unit 204 of the 4 structure units to be tested in response to the two adjacent effective bits (O1 and O2) in the second selection signal being high logic level "1", i.e. select the corresponding structure to be tested in the structure array to be tested.

[0129] At T2, the second clock pulse CP2 of the clock signal clock arrives, the first input signal d_in1 received by the data input terminal D of the DFF1 is low logic level "0", the four-bit binary number Q1Q2Q3Q4 output in parallel by the four D flip-flops is 0100, i.e. the first selection signal is 0100. The second input signal d_in2 remains low logic level "0", the five-bit binary number output by the five or gates is 01100, i.e. the second selection signal is 01100. Specifically, the control circuit is configured to, after selecting one of the 8 rows in the 4x8 structure array to be tested in response to the first address signal, select the second structure unit 204 of the 4 structure units to be tested in response to the two adjacent effective bits (O2 and O3) in the second selection signal being high logic level "1", i.e. select the corresponding structure to be tested in the structure array to be tested.

[0130] At T3, the third clock pulse CP3 of the clock signal clock arrives, at this time the first input signal d_in1 received by the data input terminal D of the DFF1 is low logic level "0", the four-bit binary number Q1Q2Q3Q4 output in parallel by the four D flip-flops is 0010, that is, the first selection signal is 0010. The second input signal d_in2 remains low logic level "0", the five-bit binary number output by the five OR gates is 00110, that is, the second selection signal is 00110. Specifically, the control circuit is configured to, after selecting one of the 8 rows in the 4x8 structure array to be tested in response to the first address signal, select the third structure unit 204 of the four structure units to be tested in response to the two adjacent effective bits (O3 and O4) in the second selection signal being high logic level "1", that is, select the corresponding structure to be tested in the structure array to be tested.

[0131] At T4, the fourth clock pulse CP4 of the clock signal clock arrives, at this time the first input signal d_in1 received by the data input terminal D of the DFF1 is low logic level "0", the four-bit binary number Q1Q2Q3Q4 output in parallel by the four D flip-flops is 0001, that is, the first selection signal is 0001. The second input signal d_in2 remains low logic level "0", the five-bit binary number output by the five OR gates is 00011, that is, the second selection signal is 00011. Specifically, the control circuit is configured to, after selecting one of the 8 rows in the 4x8 structure array to be tested in response to the first address signal, select the fourth structure unit 204 of the four structure units to be tested in response to the two adjacent effective bits (O4 and O5) in the second selection signal being high logic level "1", that is, select the corresponding structure to be tested in the structure array to be tested.

[0132] In some embodiments, when N is equal to 4 and M is equal to 3, the test circuit needs to set 3 address pads to control the 4x8 structure array to be tested, relative to Figure 1 the test circuit shown in the figure, 2 address pads are reduced, the area occupied by the address pads is reduced, and the area utilization rate of the test circuit can be increased.

[0133] The test circuit provided by the embodiments of the present disclosure can reduce the number of address pads to log2N when facing an Nx2 M structure array to be tested by setting a first signal generation unit and a second signal generation unit in the control circuit instead of a row address pad or a column address pad, thereby improving the area utilization rate of the test circuit.

[0134] It should be noted that in other modified examples formed by the present disclosure, the row address pad and the column address pad can be replaced by the control circuit in two embodiments of the present disclosure at the same time. It is easy to understand that when facing an Nx2 MWhen testing an array of structures under test (SUT), the number of pads in the test circuit can be reduced to three (clock signal pad, reset signal pad, and data signal pad), eliminating the need for address pads. An N×2 array can be selected via a single control circuit. M 2 in the array of structures under test M After one of the rows is selected, at least one of the N structural units to be tested is selected through another control circuit. One of the two control circuits includes 2 M A series of D flip-flops and (2) M The circuit consists of N+1 OR gates and N series-connected D flip-flops and (N+1) OR gates. The circuit structure of the control circuit can be found in the relevant descriptions in the embodiments of this disclosure, and will not be repeated here.

[0135] In some embodiments, each of the N test units is further provided with a switching unit, and the second selection signal Sel_2 controls the switching unit to be turned on or off. In a specific example, two adjacent valid bits of the (N+1) bits of the second selection signal Sel_2 that are at a high logic level "1" control the switching unit to be turned on, and two invalid bits of the (N+1) bits of the second selection signal Sel_2 that are at a low logic level "1" control the switching unit to be turned off. When two adjacent bits of the (N+1) bits of the second selection signal Sel_2 are at a high logic level "1", the corresponding two adjacent switching units are turned on, selecting at least one test unit among the N test units.

[0136] In some embodiments, the number of switching units is (N+1).

[0137] This disclosure also provides an operation method for a test circuit, combined with... Figure 2 As explained, the test circuit 200 includes N structural units to be tested, where N is an integer greater than 1; the operation method includes:

[0138] The system receives a clock signal clock and a first input signal d_in1, and outputs a first selection signal Sel_1 based on the first input signal d_in1 to select at least one of the N test structural units 204.

[0139] In this embodiment of the disclosure, the test circuit 200 further includes M address pads 201 and a first decoding circuit 202. The M address pads 201 are used to output M initial address signals; the first decoding circuit 202 is used to receive the M initial address signals and decode and output 2 M Each first address signal; each test unit 204 includes 2 M There are 205 structures to be tested, and N structural units to be tested constitute an N×2 M The array of structures to be tested is 203, where M is an integer greater than 1; the operation method also includes:

[0140] selecting one of the 8 rows in the 4x8 array of DUTs in response to the first address signals. M M M is an integer greater than 1; M

[0141] selecting at least one of the N DUTs in response to the first selection signals Sel_1.

[0142] The operation method will be described below in conjunction with Figure 2 , Figure 4 and Figure 5 The circuit structure of the first signal generating unit can refer to the relevant description in the above embodiments, which will not be described here again.

[0143] Taking N equal to 4 and M equal to 3 as an example, the test circuit includes 4 DUTs and 3 address pads. Each DUT includes 8 DUTs, and the 4 DUTs form a 4x8 array of DUTs. The 3 address pads provide 3 initial address signals as row address pads, and the 3 initial address signals are decoded by the first decoding circuit to output 8 first address signals corresponding to 8 row addresses one by one.

[0144] When the 4 clock pulses CP1, CP2, CP3 and CP4 of the clock signal clock come in turn, the first signal generating unit outputs 4 first selection signals Sel_1 corresponding to the first input signal d_in1 in turn as 1000, 0100, 1010 and 0101 respectively. The 4 first selection signals 1000, 0100, 1010 and 0101 correspond to the 4 DUTs one by one.

[0145] After selecting one of the 8 rows in the 4x8 array of DUTs in response to the first address signals, at least one of the 4 DUTs is selected in response to the first selection signals Sel_1 to select one of the DUTs in the 4x8 array of DUTs. In this way, the control of the 4x8 array of DUTs is realized by the first signal generating unit and the 3 address pads, and the use of address pads is reduced.

[0146] The embodiments of the present disclosure also provide another operation method of a test circuit, which will be described in conjunction with Figure 9 The test circuit 200 includes N DUTs, and N is an integer greater than 1. The operation method includes:

[0147] receiving a clock signal clock and a first input signal d_in1, and outputting a first selection signal Sel_1 according to the first input signal d_in1;

[0148] ​​The second input signal d_in2 and the first selection signal Sel_1 are received, and the second selection signal Sel_2 is output to select at least one of the N structure units under test.

[0149] In the embodiments of the present disclosure, the test circuit 200 further comprises M address pads 201 and a first decoding circuit 202. The M address pads 201 are configured to output M initial address signals. The first decoding circuit 202 is configured to receive the M initial address signals and decode and output 2 M first address signals. Each structure unit under test 204 comprises 2 M structure units 205 under test. The N structure units under test 204 form an N×2 M structure array 203. M is an integer greater than 1. The operation method further comprises:

[0150] In response to the first address signal, one of 2 M rows or 2 M columns in the N×2 M structure array 203 is selected. M is an integer greater than 1.

[0151] In response to two adjacent valid bits in the second selection signal Sel_2, at least one of the N structure units under test 204 is selected.

[0152] The operation method will be described below in conjunction with Figure 9 , Figure 11 and Figure 12 . The circuit structure of the first signal generation unit and the second signal generation unit in the control circuit can refer to the related description in the above embodiments, which will not be described here again.

[0153] Taking N equal to 4 and M equal to 3 as an example, the test circuit comprises 4 structure units under test and 3 address pads. Each structure unit under test comprises 8 structure units under test. The 4 structure units under test form a 4×8 structure array. The 3 address pads provide 3 initial address signals as row address pads. The 3 initial address signals are decoded by the first decoding circuit and 8 first address signals corresponding to 8 row addresses can be output.

[0154] The first signal generating unit outputs a first selection signal Sel_1 according to the first input signal d_in1 at each clock pulse of the clock signal clock, the first selection signal Sel_1 being a four-bit binary number, and the four-bit binary number of the first selection signal Sel_1 including one significant bit at a high logic level "1". The second signal generating unit outputs a second selection signal Sel_2 after performing a logical operation on the second input signal d_in2 and the first selection signal Sel_1, the second selection signal Sel_2 being a five-bit binary number, and the five-bit binary number of the second selection signal Sel_1 including two adjacent significant bits at a high logic level "1".

[0155] After one of the eight rows in the 4x8 array of DUTs is selected in response to the first address signal, at least one of the four DUTs is selected in response to the two adjacent significant bits in the second selection signal Sel_2, so as to select one of the DUTs in the 4x8 array of DUTs.

[0156] In this way, the control of the 4x8 array of DUTs is realized by the first signal generating unit, the second signal generating unit and the three address pads, the use of address pads is reduced, and the area utilization of the test circuit is improved.

[0157] The test circuit provided by the embodiments of the present disclosure includes a control circuit and N DUTs, N being an integer greater than 1; the control circuit includes a first signal generating unit; the first signal generating unit is configured to receive a clock signal and a first input signal, and output a first selection signal to select at least one of the N DUTs according to the first input signal. In this way, the test circuit provided by the embodiments of the present disclosure replaces the row address pad or the column address pad with the control circuit, reduces the use of address pads, and can improve the area utilization of the test circuit.

[0158] It should be understood that the "one embodiment" or "some embodiments" mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiments are included in at least one embodiment of the present disclosure. Therefore, "in one embodiment" or "in some embodiments" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the present disclosure, the size of the sequence number of each process does not mean the order of execution, and the execution order of each process should be determined according to its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The sequence number of the above-mentioned embodiments of the present disclosure is only for description, and does not represent the advantages and disadvantages of the embodiments.

[0159] The above merely provides the specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and any person skilled in the art can easily think of the changes or replacements within the technical range disclosed by the present disclosure, which should be covered within the protection scope of the present disclosure.

Claims

1. A test circuit, characterized by The test circuit comprises: a control circuit and N to-be-tested structural units, N being an integer greater than 1; the control circuit comprises a first signal generation unit and a second signal generation unit; the first signal generation unit is configured to receive a clock signal and a first input signal, and output a first selection signal according to the first input signal; the second signal generation unit is configured to receive a second input signal and the first selection signal, and output a second selection signal to select at least one of the N to-be-tested structural units; the test circuit further comprises M address pads and a first decoding circuit; the M address pads are configured to output M initial address signals; The first decoding circuit is used for receiving the M initial address signals and decoding and outputting 2 M first address signals; each of the structure units under test comprises 2 M structures under test, and the N structure units under test form an N×2 M structure array; each of the first address signals is used for selecting one of 2 M rows or 2 M columns in the N×2 M structure array, and M is an integer greater than 1. The control circuit is configured to, in response to one of 2 M rows or 2 M columns in the array of N×2 M structures under test being selected in response to the first address signal, select at least one of the N structures under test in response to adjacent two significant bits in the second selection signal. the second signal generation unit comprises (N+1) or gates, one input end of a first or gate and one input end of an (N+1)th or gate serving as two second input ends of the second signal generation unit and being configured to receive the second input signal, and the remaining input ends of adjacent or gates being connected two by two and serving as N first input ends of the second signal generation unit and being configured to receive the first selection signal.

2. The test circuit of claim 1, wherein, The first signal generation unit comprises N series-connected D flip-flops, a clock input end of the D flip-flop receiving the clock signal, a data input end of a first-stage D flip-flop receiving the first input signal, data input ends of second to N-stage D flip-flops being connected to positive-phase output ends of previous-stage D flip-flops, and a positive-phase output end of an N-stage D flip-flop outputting the first selection signal.

3. The test circuit of claim 2, wherein, The data input end of the first-stage D flip-flop is connected to an inverting output end of the first-stage D flip-flop.

4. The test circuit of claim 2, wherein, Reset ends of the N D flip-flops receive a reset signal.

5. The test circuit of claim 1, wherein, Each of the N to-be-tested structural units is further provided with a switch unit, and the second selection signal controls opening or closing of the switch unit.

6. The test circuit of claim 5, wherein, The number of the switch units is (N+1).

7. A method of operating a test circuit as claimed in claim 1, characterized by, The test circuit comprises N to-be-tested structural units, N being an integer greater than 1; and the method comprises: receiving a clock signal and a first input signal, and outputting a first selection signal according to the first input signal; receiving a second input signal and the first selection signal, and outputting a second selection signal to select at least one of the N to-be-tested structural units; the method further comprises: In response to the first address signal, the N×2 M 2 in the array of structures under test M row or 2 M In the list, M is an integer greater than 1; selecting the Nx2 array of structures responsive to the first address signal M one of 2 M rows or 2 M columns of the Nx2 array of structures responsive to the second address signal selecting at least one of the N to-be-tested structural units in response to two adjacent valid bits in the second selection signal.

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