A combined power supply power-off timing control circuit and its working method

Abstract

The present invention relates to a power-off timing control circuit for a combined power supply and its working method. The control circuit includes: a surge suppression circuit, a MOS tube drive circuit and a capacitor energy storage circuit. The combined power supply includes a first power module and a second power module. The surge suppression circuit has an input end connected to an input power supply, and an output end connected to the input end of the MOS tube drive circuit and the input end of the first power module respectively; the output end of the MOS tube drive circuit is connected to the input end of the capacitor energy storage circuit; and the output end of the capacitor energy storage circuit is connected to the input end of the second power module. The present invention can solve the shortcomings of the prior art and can realize the timing control of the power-off of the outputs of different power modules in the event of input power failure, thereby protecting the power loads at the subsequent stage of the power module. The present invention can improve the overall efficiency of the combined power supply and has the characteristics of simple and flexible structure, low cost, and reliable operation.

Description

Technical Field

[0001] The present invention relates to the technical field of electric load protection, and in particular to a combined power supply power-off timing control circuit and a working method thereof. Background Art

[0002] Currently, in the development of space power supply and distribution technology, both domestically and internationally, modular power supply solutions are commonly used in various electronic power supply and distribution systems due to the diverse power supply requirements of loads. Given the complex internal operating principles of downstream loads, stringent requirements are often placed on the power-up and power-down sequences of various voltage lines. Sequencing errors can cause malfunctions in the loads and even cause irreversible damage. Due to the characteristics of modular power supplies, with a shared power bus for the input and isolated outputs, power-up sequencing is relatively easy to achieve, but power-down sequencing is more difficult to control. To improve the reliability of modular power supplies and the safety of electrical equipment, strict management of the power-down sequence of modular power supplies is necessary.

[0003] The conventional approach is to connect a storage capacitor in parallel at the power supply output to maintain energy release. This often requires a very large storage capacitor, which challenges the power module's capacitive load capacity and can even cause overcurrent or even no output. Existing power-off sequence control circuits have many uncontrollable factors and cannot guarantee the power safety of the power module's downstream loads. Summary of the Invention

[0004] The present invention aims to provide a power-off timing control circuit and operating method for a combined power supply. This circuit and operating method address the shortcomings of the prior art by enabling sequential control of the output power-off of different power modules in the event of an input power outage, thereby protecting the downstream loads of the power modules. This invention improves the overall efficiency of the combined power supply and features a simple and flexible structure, low cost, and reliable operation.

[0005] To achieve the above object, the present invention adopts the following technical solutions:

[0006] In a first aspect of the present invention, a power-off timing control circuit for a combined power supply is disclosed.

[0007] The control circuit includes: a surge suppression circuit, a MOS tube driving circuit and a capacitor energy storage circuit. The combined power supply includes a first power supply module and a second power supply module.

[0008] The surge suppression circuit has an input end connected to the input power supply, and an output end connected to the input end of the MOS tube drive circuit and the input end of the first power module respectively;

[0009] The output end of the MOS tube driving circuit is connected to the input end of the capacitor energy storage circuit;

[0010] The output end of the capacitor energy storage circuit is connected to the input end of the second power supply module.

[0011] The surge suppression circuit is used to protect the power safety of the subsequent power supply module. At the moment the input end is powered on, a large surge current will be generated in front of the power supply module, which may burn the internal components. The MOS tube drive circuit is used to control the flow of energy in the energy storage capacitor. When the input port is powered on, the current charges the capacitor in the capacitor energy storage circuit through the MOS tube drive circuit; when the input port is powered off, the NMOS tube in the MOS tube drive circuit cannot be driven, and the energy in the energy storage circuit cannot be transmitted in reverse. The capacitor energy storage circuit is used to provide energy to the power supply module that needs to delay the output after power off.

[0012] Furthermore, the surge suppression circuit includes a resistor R1, a resistor R2, a capacitor C1 and an NMOS transistor VM2;

[0013] The first end of the capacitor C1 is connected to the negative terminal of the input power supply, and the second end is connected to the common node of the resistor R1 and the resistor R2; the common node of the resistor R1 and the resistor R2 is formed by connecting the first end of the resistor R1 and the first end of the resistor R2;

[0014] The second end of the resistor R1 is connected to the positive terminal of the input power supply on one side and to the positive input terminal of the first power module on the other side;

[0015] The second end of the resistor R2 is connected to the negative terminal of the input power supply;

[0016] The NMOS transistor VM2 has a gate connected to the second end of the capacitor C1 , a source connected to the second end of the resistor R2 , and a drain connected to the input end of the capacitor energy storage circuit.

[0017] Furthermore, the surge control circuit further includes a voltage regulator tube V1;

[0018] The voltage regulator tube V1, the resistor R2, and the capacitor C1 are connected in parallel;

[0019] The anode of the voltage regulator tube V1 is connected to the source of the NMOS tube VM2, and the cathode is connected to the gate of the NMOS tube VM2.

[0020] Furthermore, the MOS transistor driving circuit includes an NMOS transistor VM1, a resistor R3 and a voltage regulator V2; the NMOS transistor VM1 in the MOS transistor driving circuit replaces the traditional Schottky diode and uses the low on-resistance of the MOS transistor to achieve low power consumption.

[0021] The NMOS transistor VM1 has a source connected to the positive terminal of the input power supply, a drain connected to the input terminal of the capacitor energy storage circuit, and a gate connected to the first terminal of the resistor R3;

[0022] The second end of the resistor R3 is connected to the cathode of the voltage regulator tube V2;

[0023] The anode of the voltage regulator tube V2 is connected to the positive terminal of the input power supply.

[0024] Furthermore, the MOS tube driving circuit further includes a Schottky diode D1 and an isolated auxiliary power supply M1;

[0025] The anode of the Schottky diode D1 is connected to the positive terminal of the input power supply;

[0026] The isolated auxiliary power supply M1 has a positive input terminal connected to the positive terminal of the input power supply, a negative input terminal connected to the negative terminal of the input power supply, a positive output terminal connected to the second end of the resistor R3, and a negative output terminal connected to the cathode of the Schottky diode D1. The input and output of the isolated auxiliary power supply M1 are isolated from each other via an internal transformer.

[0027] Furthermore, the direction of the body diode in the NMOS transistor VM2 is from the source to the drain;

[0028] The NMOS transistor VM2 is connected in series to the return line of the input power supply.

[0029] Furthermore, the direction of the body diode in the NMOS transistor VM1 is from the source to the drain;

[0030] The NMOS transistor VM1 is connected in series to the positive line of the input power supply.

[0031] Furthermore, the capacitor energy storage circuit includes a resistor R4, a capacitor C2 and a Schottky diode D2;

[0032] One end of the resistor R4 is connected to the output end of the MOS tube driving circuit, and the other end is connected to the positive input end of the second power module and the cathode of the Schottky diode D2;

[0033] The anode of the Schottky diode D2 is connected to the connection node between the resistor R4 and the capacitor C2; one end of the capacitor C2 is connected to the resistor R4, and the other end is connected to the negative input terminal of the second power module.

[0034] In a second aspect of the present invention, a method for operating the power-off timing control circuit of the combined power supply is disclosed.

[0035] The method includes:

[0036] When the input power is powered on, the surge suppression circuit suppresses the surge current at the moment the circuit is turned on, and the current charges the capacitor in the capacitor energy storage circuit through the MOS tube drive circuit; the input power supplies power to the first power module through the surge suppression circuit; the input power supplies power to the second power module after passing through the surge suppression circuit, the MOS tube drive circuit, and the capacitor energy storage circuit in sequence;

[0037] After the input power is cut off, the NMOS transistor in the MOS transistor driving circuit cannot be driven, and the energy in the capacitor energy storage circuit cannot flow to the input end of the first power module. The first power module is powered off, and the capacitor energy storage circuit provides energy to the second power module, causing the second power module to be powered off later than the first power module.

[0038] Furthermore, the surge suppression circuit suppresses the surge current at the moment the circuit is turned on, including:

[0039] When the input power is turned on, as the voltage across the capacitor C1 gradually increases, the on-resistance of the NMOS tube VM2 gradually decreases, thereby suppressing the surge current at the moment the circuit is turned on.

[0040] Furthermore, the input power supplies power to the first power module through the surge suppression circuit; the input power supplies power to the second power module after passing through the surge suppression circuit, the MOS tube drive circuit and the capacitor energy storage circuit in sequence, including:

[0041] When the input power is powered on, when the NMOS tube VM2 is fully turned on, the input power supplies power to the first power module through the surge suppression circuit; at this time, the Schottky diode D1 is turned on, the output negative terminal of the isolation auxiliary power supply M1 is connected to the positive terminal of the input power, and the output positive terminal is connected to the gate terminal of the NMOS tube VM1, thereby driving the NMOS tube VM1 to turn on. The input power first passes through the surge suppression circuit, then through the MOS tube drive circuit, and finally through the energy storage circuit to supply power to the second power module.

[0042] Furthermore, after the input power supply is powered off, the NMOS transistor in the MOS transistor driving circuit cannot be driven, and the energy in the capacitor energy storage circuit cannot flow to the input end of the first power module. The first power module is powered off, and the capacitor energy storage circuit provides energy to the second power module, so that the second power module is powered off later than the first power module, including:

[0043] After the input power is cut off, at the moment the input power is cut off, the NMOS tube VM1 is used to interrupt the reverse transmission of energy in the capacitor energy storage circuit; the isolated auxiliary power supply M1 has no output, the NMOS tube VM1 is not conducting, the direction of the body diode in the NMOS tube VM1 is from the source to the drain, the energy in the capacitor energy storage circuit cannot flow to the input end of the first power module, the first power module is powered off, and the capacitor energy storage circuit provides energy to the second power module, so that the second power module is powered off later than the first power module.

[0044] Compared with the prior art, the advantages of the present invention are:

[0045] (1) The present invention can solve the deficiencies in the prior art by connecting a storage capacitor in parallel to the input end of the second power module where delayed output power-off is required to maintain the release of energy at the output end, and arranging a MOS tube driving circuit between the storage capacitor and the input end of the first power module to prevent energy from flowing back into the first power module, thereby playing a role in power-off timing control. In this way, the timing control of output power-off of different power modules can be achieved when the input power is off, and at the same time, it plays a protective role for the power load at the subsequent stage of the power module.

[0046] (2) The present invention connects an NMOS transistor in series with the positive power input line. Utilizing the isolation characteristics of the transformer within the isolated auxiliary power supply M1, the negative output terminal of the isolated auxiliary power supply M1 is connected to the positive terminal of the input power supply via a Schottky diode D2. This increases the voltage at the gate of the NMOS transistor VM1 relative to the source, thereby driving the NMOS transistor. By utilizing the low on-resistance of the MOS transistor to replace the Schottky diode, the present invention achieves low power consumption.

[0047] (3) The present invention can improve the overall efficiency of the combined power supply and has the characteristics of simple and flexible structure, low cost, and reliable operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Figure 1 It is a principle block diagram of the control circuit in the present invention;

[0049] Figure 2 It is a circuit diagram of the control circuit in the present invention;

[0050] Figure 3 This is a comparison diagram of the power consumption of the NMOS tube and the traditional Schottky diode in the MOS tube driving circuit of the present invention.

[0051] in:

[0052] 1. Surge suppression circuit, 2. MOS tube drive circuit, 3. Capacitor energy storage circuit, 4. First power supply module, 5. Second power supply module. DETAILED DESCRIPTION

[0053] The present invention will be further described below with reference to the accompanying drawings:

[0054] like Figure 1 and Figure 2 A power-off timing control circuit for a combined power supply is shown. The control circuit includes a surge suppression circuit 1, a MOS transistor drive circuit 2, and a capacitor energy storage circuit 3. The combined power supply includes a first power module 4 and a second power module 5, both of which are isolated power modules. The present invention is used to control the power-off timing of the first power module 4 and the second power module 5. The surge suppression circuit 1 is used to protect the power safety of the subsequent power module. At the moment the input port is powered on, a large surge current is generated before the power module, which may burn internal components. The MOS transistor drive circuit 2 is used to control the flow of energy in the energy storage capacitor. When the input port is powered on, current flows through the MOS transistor drive circuit to charge the capacitor in the capacitor energy storage circuit; when the input port is powered off, the NMOS transistor in the MOS transistor drive circuit cannot be driven, and the energy in the energy storage circuit cannot be transmitted in the reverse direction. The capacitor energy storage circuit 3 is used to provide energy to the power module that requires power-off delay output.

[0055] Specifically, the input end of the surge suppression circuit 1 is connected to the input power supply, and the output end is respectively connected to the input end of the MOS tube drive circuit 2 and the input end of the first power module 4; the output end of the MOS tube drive circuit 2 is connected to the input end of the capacitor energy storage circuit 3; the output end of the capacitor energy storage circuit 3 is connected to the input end of the second power module 5.

[0056] Furthermore, the surge suppression circuit 1 includes a resistor R1, a resistor R2, a capacitor C1 and an NMOS transistor VM2;

[0057] The first end of the capacitor C1 is connected to the negative terminal of the input power supply, and the second end is connected to the common node of the resistor R1 and the resistor R2; the common node of the resistor R1 and the resistor R2 is formed by connecting the first end of the resistor R1 and the first end of the resistor R2;

[0058] The second end of the resistor R1 is connected to the positive terminal of the input power supply on one side and to the positive input terminal of the first power module on the other side;

[0059] The second end of the resistor R2 is connected to the negative terminal of the input power supply;

[0060] The gate G of the NMOS transistor VM2 is connected to the second end of the capacitor C1 , the source S is connected to the second end of the resistor R2 , and the drain D is connected to the input end of the capacitor energy storage circuit 3 .

[0061] Furthermore, the surge control circuit 1 further includes a voltage regulator tube V1;

[0062] The voltage regulator tube V1, the resistor R2, and the capacitor C1 are connected in parallel;

[0063] The anode of the voltage regulator tube V1 is connected to the source of the NMOS tube VM2, and the cathode is connected to the gate of the NMOS tube VM2.

[0064] Furthermore, the MOS transistor driving circuit 2 includes an NMOS transistor VM1, a resistor R3 and a voltage regulator transistor V2;

[0065] The NMOS transistor VM1 has a source S connected to the positive terminal of the input power supply, a drain D connected to the input terminal of the capacitor energy storage circuit, and a gate G connected to the first terminal of the resistor R3;

[0066] The second end of the resistor R3 is connected to the cathode of the voltage regulator tube V2;

[0067] The anode of the voltage regulator tube V2 is connected to the positive terminal of the input power supply.

[0068] Furthermore, the MOS transistor driving circuit 2 further includes a Schottky diode D1 and an isolated auxiliary power supply M1.

[0069] The anode of the Schottky diode D1 is connected to the positive terminal of the input power supply;

[0070] The isolated auxiliary power supply M1 has an input positive terminal connected to the positive terminal of the input power supply, an input negative terminal connected to the negative terminal of the input power supply, an output positive terminal connected to the second end of the resistor R3, and an output negative terminal connected to the negative electrode of the Schottky diode D1.

[0071] The isolated auxiliary power supply includes an auxiliary power supply module M1. The auxiliary power supply module M1 can be a micro-power module of Shanghai Juntao Technology Co., Ltd., model ZA18C120P005.

[0072] Furthermore, the direction of the body diode in the NMOS transistor VM2 is from the source to the drain;

[0073] The NMOS transistor VM2 is connected in series to the return line of the input power supply.

[0074] Furthermore, the direction of the body diode in the NMOS transistor VM1 is from the source to the drain;

[0075] The NMOS transistor VM1 is connected in series to the positive line of the input power supply.

[0076] Furthermore, the capacitor energy storage circuit 3 includes a resistor R4, a capacitor C2 and a Schottky diode D2;

[0077] One end of the resistor R4 is connected to the output end of the MOS transistor driving circuit 2, and the other end is connected to the positive input end of the second power module 4 and the cathode of the Schottky diode D2;

[0078] The anode of the Schottky diode D2 is connected to the connection node between the resistor R4 and the capacitor C2; one end of the capacitor C2 is connected to the resistor R4, and the other end is connected to the negative input terminal of the second power module 4.

[0079] A large-capacity capacitor C2 is connected in parallel to the input end of the second power supply module 5 to prevent the power supply module from being damaged by a surge current at the moment of startup.

[0080] The flow direction of the body diodes inside the NMOS transistor VM2 in the surge suppression circuit 1 and the NMOS transistor VM1 in the MOS transistor driving circuit 2 is the same, that is, the source points to the drain. The NMOS transistor VM1 is connected in series to the positive terminal of the input power supply, and the NMOS transistor VM2 is connected in series to the negative terminal of the input power supply.

[0081] In the above circuit, resistors R1 and R2 divide the voltage to provide a driving voltage for NMOS transistor VM2. Capacitor C1 prevents sudden voltage changes in resistor R2, allowing NMOS transistor VM2 to turn on slowly. Zener diode V1 prevents excessive voltage across resistor R2 from causing breakdown in NMOS transistor VM2. Resistor R3 acts as a current limiter. Zener diode V2, like Zener diode V1, prevents excessive voltage at the GS terminal of NMOS transistor VM1 from causing breakdown in NMOS transistor VM1. NMOS transistors VM1 and VM2 are connected in series with the positive and negative lines of the input power supply, respectively, to control on / off. Schottky diode D1 prevents current from flowing to the input terminal. Resistor R4 acts as a current limiter. Capacitor C2 serves as an energy storage capacitor. When the input power is off, Schottky diode D2 utilizes its unidirectional conductivity to supply power to the second power module. An isolated auxiliary power supply M1 provides the driving voltage across the gate and source of NMOS transistor VM1.

[0082] In a second aspect of the present invention, a method for operating the power-off timing control circuit of the combined power supply is disclosed.

[0083] The method includes:

[0084] When the input power is energized, as the voltage across capacitor C1 gradually increases, the on-resistance of NMOS tube VM2 gradually decreases, suppressing the surge current at the moment the circuit is turned on. When NMOS tube VM2 is fully turned on, the input power supplies power to the first power module through the surge suppression circuit. At this time, Schottky diode D1 is turned on, the output negative terminal of the isolated auxiliary power supply M1 is connected to the positive terminal of the input power, and the output positive terminal is connected to the gate terminal of NMOS tube VM1. NMOS tube VM1 is fully turned on, and the input power first passes through the surge suppression circuit, then through the MOS tube drive circuit, and finally through the energy storage circuit to supply power to the second power module.

[0085] In this embodiment, by providing a surge suppression circuit, the peak of the surge current is suppressed; by providing a MOS tube driving circuit, it is equivalent to connecting a switch in series with the input positive line. When the input end is powered on, the MOS tube driving circuit is equivalent to a closed switch, at which time the subsequent energy storage capacitor array is charged. When the input end is powered off, the MOS tube driving circuit is equivalent to an open switch, at which time the energy in the resistance capacitor is reversely transmitted; by providing a capacitor energy storage circuit, the capacitor will be fully charged and the energy will be stored in the capacitor.

[0086] Specifically, when power is applied to the input terminal, the output voltage of the isolated auxiliary power supply M1 drives the NMOS transistor VM1. At this point, a channel is established between the source and drain of the NMOS transistor VM1, allowing current to flow normally. However, because the voltage across capacitor C1 cannot change suddenly, the gate-source voltage of the NMOS transistor VM2 is zero, preventing current from flowing from the drain to the source of VM2. The negative terminal of the input power supply is disconnected, thereby preventing the surge current at the moment of power-on from damaging the first power module 4 and the second power module 5. As the voltage across capacitor C1 gradually increases, the NMOS transistor VM2 fully conducts, and the input voltage, after passing through the surge suppression circuit 1, supplies power to the first power module 1. The input voltage, after passing through the surge suppression circuit 1, the MOS transistor driver circuit 2, and the capacitor energy storage circuit 3, supplies power to the second power module 5.

[0087] After the input power is cut off, the isolated auxiliary power supply M1 has no output, the NMOS tube VM1 is not conducting, the direction of the body diode in the NMOS tube VM1 is from the source to the drain, the energy in the capacitor energy storage circuit cannot flow to the input end of the first power module, and the first power module is powered off, thereby achieving a timing sequence in which the second power module is powered off later than the first power module.

[0088] Specifically, when the input power is disconnected, the output of the isolated auxiliary power supply M1 in the MOS transistor drive circuit 2 is disconnected, and the NMOS transistor VM1 is disconnected. At this time, the energy in the energy storage circuit 3 cannot be transmitted to the input end of the first power module 4 through the MOS transistor drive circuit 2. Therefore, the output of the first power module 4 is disconnected first, and the output of the second power module 5 is disconnected later, thereby realizing power-off timing control of the first power module and the second power module.

[0089] Furthermore, at the moment when the input power is cut off, it is the NMOS transistor VM1 that interrupts the reverse transmission of energy in the capacitor energy storage circuit.

[0090] Specifically, at the moment of power failure, it is the NMOS tube VM1 that interrupts the reverse transmission of energy in the energy storage circuit. Compared with the unidirectional Schottky diode: during the normal power-on process, the MOS tube has an extremely low on-resistance, thereby achieving the purpose of low power consumption.

[0091] The working principle of the present invention is:

[0092] First, the direction of the body diodes in the NMOS transistors VM1 and VM2 is from the source to the drain, the NMOS transistor VM1 is connected in series to the positive line of the input power supply, and the NMOS transistor VM2 is connected in series to the return line of the input power supply.

[0093] When the input power is applied, current flows from the positive terminal Vin+ to the negative terminal Vin-. At the moment the circuit is operational, the voltage across capacitor C1 cannot change suddenly. It slowly increases from zero, gradually increasing the gate and source voltages of NMOS transistor VM2. Before the voltage across capacitor C1 reaches the gate and source threshold voltages of NMOS transistor VM2, a channel between the source and drain of NMOS transistor VM2 is not established, and the input power return line cannot conduct. The output voltage of isolated auxiliary power supply M1 normally drives NMOS transistor VM1, causing it to conduct normally and the positive line of the input power supply to conduct.

[0094] As the input voltage gradually increases, NMOS transistor VM2 is fully turned on, and the input power passes through the surge suppression circuit before supplying power to the first power module 4. The input power passes through the surge suppression circuit 1, MOS transistor drive circuit 2, and capacitor energy storage circuit 3 before supplying power to the second power module 5.

[0095] When the input power is disconnected, the output of the isolated auxiliary power supply M1 in the MOS transistor drive circuit 2 is disconnected, and the NMOS transistor VM1 is disconnected. At this time, the energy stored in the capacitor C2 in the capacitor energy storage circuit 3 cannot be transmitted to the input end of the first power module 4 through the MOS transistor drive circuit 2. Therefore, the output of the first power module 4 is disconnected first, and the output of the second power module is disconnected later, thereby achieving the effect of power-off timing control.

[0096] Assuming that the power of the downstream load of the second power module 5 in the power-off timing control circuit is P, the conversion efficiency of the second power module 5 is η, the input undervoltage point of the second power module 5 is U2, the capacity of the capacitor C2 is C, the input power voltage is U1, and after the input power is cut off, the output of the second power module 5 is cut off later than the power module 1 by a time delta t. According to the principle of conservation of energy, the following formula can be obtained:

[0097]

[0098] In the formula, the circuit can work normally only when U1 is greater than U2.

[0099] After the input power is disconnected, it is the NMOS transistor VM1 in the MOS transistor driver circuit 2 that prevents the energy in the capacitor energy storage circuit 3 from being reversely transferred to the input of the first power module 4. Compared with traditional methods, the Schottky diode is provided here, utilizing the diode's unidirectional conductivity to achieve the same function.

[0100] Compared with the traditional power-off timing control circuit, the power consumption difference between the combined power supply on-off timing control circuit of the present invention is mainly in the MOS tube driving circuit. Assuming that the on-resistance of NMOS tube VM1 is R ds , the input power bus current is I, so the power consumption P1 of NMOS tube VM1 is:

[0101] P1=(I×I)×R ds (2)

[0102] The traditional approach is to use Schottky diodes instead of NMOS tubes in the MOS tube drive circuit, with a conduction voltage drop of U FM , the bus current of the input power supply is I, so the power consumption P2 of the Schottky diode is:

[0103] P2=U FM ×I (3)

[0104] Among them, R in formula (2) ds The value is usually not greater than 20mΩ; in formula (3), U FM The value is not less than 0.2V and gradually increases as the forward current increases.

[0105] With the help of MATLAB tools, the power consumption-current curves in equations (2) and (3) are simulated, as shown in the following example: Figure 3 As shown, it can be intuitively concluded that the combined power supply power-off timing control circuit of this embodiment has the effect of reducing power consumption.

[0106] The above-described embodiments are merely descriptions of preferred implementations of the present invention and are not intended to limit the scope of the present invention. Without departing from the spirit of the present invention, various modifications and improvements made to the technical solutions of the present invention by ordinary technicians in this field should fall within the scope of protection determined by the claims of the present invention.

Claims

1. A power-off timing control circuit for a combined power supply, the combined power supply comprising a first power module (4) and a second power module (5); characterized in that: The control circuit comprises: a surge suppression circuit (1), a MOS tube drive circuit (2) and a capacitor energy storage circuit (3); The surge suppression circuit (1) has an input end connected to an input power supply, and an output end connected to the input end of the MOS tube drive circuit (2) and the input end of the first power module (4) respectively; the output end of the MOS tube drive circuit (2) is connected to the input end of the capacitor energy storage circuit (3); the output end of the capacitor energy storage circuit (3) is connected to the input end of the second power module (5); The surge suppression circuit (1) is used to protect the power safety of the subsequent power supply module; the circuit includes a resistor R1, a resistor R2, a capacitor C1 and an NMOS transistor VM2; the first end of the capacitor C1 is connected to the negative terminal of the input power supply, and the second end is connected to the common node of the resistor R1 and the resistor R2; the common node of the resistor R1 and the resistor R2 is formed by connecting the first end of the resistor R1 and the first end of the resistor R2; the second end of the resistor R1 is connected to the positive terminal of the input power supply and to the input positive terminal of the first power supply module; the second end of the resistor R2 is connected to the negative terminal of the input power supply; the NMOS transistor VM2 has a gate connected to the second end of the capacitor C1, a source connected to the second end of the resistor R2, and a drain connected to the input end of the capacitor energy storage circuit (3); The MOS transistor drive circuit (2) is used to control the flow of energy in the capacitor energy storage circuit; the circuit includes an NMOS transistor VM1, a resistor R3 and a voltage regulator V2; the NMOS transistor VM1 has a source connected to the positive terminal of the input power supply, a drain connected to the input terminal of the capacitor energy storage circuit (3), and a gate connected to the first end of the resistor R3; the second end of the resistor R3 is connected to the cathode of the voltage regulator V2; the anode of the voltage regulator V2 is connected to the positive terminal of the input power supply; the MOS transistor drive circuit (2) also includes a Schottky diode D1 and an isolation auxiliary Auxiliary power supply M1; the positive electrode of the Schottky diode D1 is connected to the positive terminal of the input power supply; the isolated auxiliary power supply M1, its input positive terminal is connected to the positive terminal of the input power supply, the input negative terminal is connected to the negative terminal of the input power supply, the output positive terminal is connected to the second end of the resistor R3, and the output negative terminal is connected to the negative terminal of the Schottky diode D1; the input and output of the isolated auxiliary power supply M1 are isolated from each other via an internal transformer; the direction of the body diode in the NMOS transistor VM1 is from source to drain; the NMOS transistor VM1 is connected in series to the positive line of the input power supply.

2. The circuit according to claim 1, wherein: The surge suppression circuit (1) further includes a voltage regulator tube V1; The voltage regulator tube V1, the resistor R2, and the capacitor C1 are connected in parallel; The anode of the voltage regulator tube V1 is connected to the source of the NMOS tube VM2, and the cathode is connected to the gate of the NMOS tube VM2.

3. The circuit according to claim 2, characterized in that The direction of the body diode in the NMOS transistor VM2 is from source to drain; The NMOS transistor VM2 is connected in series to the return line of the input power supply.

4. The circuit according to claim 3, characterized in that The capacitor energy storage circuit (3) is used to provide energy to a power supply module that needs to delay power-off output; the circuit includes a resistor R4, a capacitor C2 and a Schottky diode D2; One end of the resistor R4 is connected to the output end of the MOS tube drive circuit (2), and the other end is connected to the positive input end of the second power supply module and the other end is connected to the cathode of the Schottky diode D2; The anode of the Schottky diode D2 is connected to the connection node between the resistor R4 and the capacitor C2; one end of the capacitor C2 is connected to the resistor R4, and the other end is connected to the negative input terminal of the second power module.

5. The operating method of the power-off timing control circuit of the combined power supply according to any one of claims 1 to 4, characterized in that: The method includes: When the input power is powered on, the surge suppression circuit suppresses the surge current at the moment the circuit is turned on, and the current charges the capacitor in the capacitor energy storage circuit through the MOS tube drive circuit; the input power supplies power to the first power module through the surge suppression circuit; the input power supplies power to the second power module after passing through the surge suppression circuit, the MOS tube drive circuit, and the capacitor energy storage circuit in sequence; After the input power is cut off, the NMOS transistor in the MOS transistor driving circuit cannot be driven, and the energy in the capacitor energy storage circuit cannot flow to the input end of the first power module. The first power module is powered off, and the capacitor energy storage circuit provides energy to the second power module, causing the second power module to be powered off later than the first power module.

6. The working method according to claim 5, characterized in that: The surge suppression circuit suppresses the surge current at the moment the circuit is turned on, including: When the input power is turned on, as the voltage across the capacitor C1 gradually increases, the on-resistance of the NMOS tube VM2 gradually decreases, thereby suppressing the surge current at the moment the circuit is turned on.

7. The working method according to claim 6, characterized in that: The input power supplies power to the first power module through the surge suppression circuit; the input power supplies power to the second power module after passing through the surge suppression circuit, the MOS tube drive circuit and the capacitor energy storage circuit in sequence, including: When the input power is powered on, when the NMOS tube VM2 is fully turned on, the input power supplies power to the first power module through the surge suppression circuit; at this time, the Schottky diode D1 is turned on, the output negative terminal of the isolation auxiliary power supply M1 is connected to the positive terminal of the input power, and the output positive terminal is connected to the gate terminal of the NMOS tube VM1, thereby driving the NMOS tube VM1 to turn on. The input power first passes through the surge suppression circuit, then through the MOS tube drive circuit, and finally through the energy storage circuit to supply power to the second power module.

8. The working method according to claim 7, characterized in that: After the input power is cut off, the NMOS transistor in the MOS transistor driving circuit cannot be driven, and the energy in the capacitor energy storage circuit cannot flow to the input end of the first power module. The first power module is powered off, and the capacitor energy storage circuit provides energy to the second power module, so that the second power module is powered off later than the first power module, including: After the input power is cut off, at the moment the input power is cut off, the NMOS tube VM1 is used to interrupt the reverse transmission of energy in the capacitor energy storage circuit; the isolated auxiliary power supply M1 has no output, the NMOS tube VM1 is not conducting, the direction of the body diode in the NMOS tube VM1 is from the source to the drain, the energy in the capacitor energy storage circuit cannot flow to the input end of the first power module, the first power module is powered off, and the capacitor energy storage circuit provides energy to the second power module, so that the second power module is powered off later than the first power module.

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