Wafer defect detection method, storage medium, and data processing device

Abstract

The present disclosure provides a wafer defect detection method, a storage medium and a data processing device, and relates to the technical field of semiconductors. The method comprises the following steps: obtaining target wafer information, obtaining n kinds of wafer characteristic data according to the target wafer information, wherein n is a positive integer greater than 1, processing m kinds of wafer characteristic data in the n kinds of wafer characteristic data by using a target neural network model, and obtaining a defect category of the wafer, wherein m is a positive integer less than or equal to n and greater than 1. In the foregoing manner, the accuracy of detection and classification of defective wafers can be improved, and the detection and classification efficiency can be improved.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of semiconductor technology, and in particular, to a wafer defect detection method, a storage medium and a data processing device. BACKGROUND

[0002] In the field of collection circuit and semiconductor technology, for products that have been mass-produced, a considerable number of wafers are produced every day, and engineers spend a lot of time to view wafers, detect wafers, classify defective wafers, and find out the results affecting yield.

[0003] In the related art, the way of detecting and classifying defective wafers is not accurate and has low efficiency. SUMMARY

[0004] The present disclosure provides a wafer defect detection method, a storage medium and a data processing device, which can effectively improve the accuracy of detecting and classifying defective wafers and improve the detection and classification efficiency of wafer defects.

[0005] Other characteristics and advantages of the present disclosure will become apparent from the following detailed description, or will be learned by practice of the present disclosure.

[0006] According to one aspect of the present disclosure, the present disclosure provides a wafer defect detection method, comprising: obtaining target wafer information; obtaining n kinds of wafer feature data according to the target wafer information, n being a positive integer greater than 1; processing m kinds of wafer feature data in the n kinds of wafer feature data by using a target neural network model to obtain a defect category of the wafer, m being a positive integer less than or equal to n and greater than 1.

[0007] According to another aspect of the present disclosure, a wafer defect detection device is provided, comprising: an acquisition unit configured to obtain target wafer information; the acquisition unit is also configured to obtain n kinds of wafer feature data according to the target wafer information, n being a positive integer greater than 1; a processing unit configured to process m kinds of wafer feature data in the n kinds of wafer feature data by using a target neural network model to obtain a defect category of the wafer, m being a positive integer less than or equal to n and greater than 1.

[0008] According to another aspect of the present disclosure, a data processing device is provided, comprising a processor and a memory; the memory has computer instructions executable on the processor, and the processor executes the steps of the method according to any one of the embodiments of the present disclosure when executing the computer instructions.

[0009] According to another aspect of the present disclosure, a computer readable storage medium is provided, and the computer readable storage medium has computer instructions stored thereon, and the computer instructions execute the steps of the method according to any one of the embodiments of the present disclosure when executed.

[0010] According to yet another aspect of the present disclosure, there is provided a computer program product, which, when executed by a processor, implements the data processing method in any of the embodiments of the present disclosure.

[0011] It should be understood that the general description above and the detailed description below are only exemplary and explanatory, and are not limiting of the present disclosure.

[0012] In the foregoing manner, the present disclosure provides a wafer defect detection method. By obtaining target wafer information, n kinds of wafer feature data are obtained according to the target wafer information, n is a positive integer greater than 1, m kinds of wafer feature data in the n kinds of wafer feature data are processed by using a target neural network model, and the defect category of the wafer is obtained, m is a positive integer less than or equal to n and greater than 1. In the foregoing manner, the accuracy of detecting and classifying defective wafers can be improved, and the detection and classification efficiency can be improved.

[0013] Further, the target neural network model of the present disclosure can be an adaptive resonance neural network model (ARTNN). Since the method of the present disclosure obtains n kinds of wafer feature data, compared with directly processing wafer information in the related art, the amount of data of the wafer feature data obtained in the present disclosure is more. In order to be able to better process the n kinds of wafer feature data and obtain an accurate defect category of the wafer, the adaptive resonance neural network model is used as the target neural network model in the present disclosure, which can process more wafer feature data, has higher efficiency, and has better accuracy. BRIEF DESCRIPTION OF DRAWINGS

[0014] The accompanying drawings, which are incorporated into and form a part of the specification, illustrate one embodiment consistent with the present disclosure and, together with the description, serve to explain the principles of the disclosure. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those of ordinary skill in the art without creative labor based on these drawings.

[0015] Figure 1 A flowchart of a wafer defect detection method in an embodiment of the present disclosure is shown;

[0016] Figure 2 A schematic diagram of first wafer data in an embodiment of the present disclosure is shown;

[0017] Figure 3 A schematic diagram of second wafer data in an embodiment of the present disclosure is shown;

[0018] Figure 4FIG. 1 shows a schematic diagram of a wafer classification result according to an embodiment of the present disclosure;

[0019] Figure 5 FIG. 2 shows a flowchart of another wafer defect detection method according to an embodiment of the present disclosure;

[0020] Figure 6 FIG. 3 shows a schematic diagram of a wafer processing process according to a clustering method according to an embodiment of the present disclosure;

[0021] Figure 7 FIG. 4 shows a structural schematic diagram of a wafer defect detection device according to an embodiment of the present disclosure;

[0022] Figure 8 FIG. 5 shows a structural schematic diagram of a data processing device according to an embodiment of the present disclosure;

[0023] Figure 9 FIG. 6 shows a schematic diagram of a computer readable storage medium according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0024] Example implementations will now be described with reference to the drawings; however, example implementations can be implemented in many different forms and should not be construed as being limited to the examples set forth herein; rather, these implementations are provided so that the disclosure will be thorough and complete, and will fully convey the concept of example implementations to those skilled in the art. The described features, structures, or characteristics can be combined in one or more implementations in any suitable manner.

[0025] In addition, the drawings are only schematic and are not necessarily drawn to scale. Identical or similar elements are denoted by the same reference numerals throughout the drawings, which will be described in the following description of the drawings. Some of the blocks in the flowcharts shown in the drawings can be functional blocks that do not necessarily correspond to physical or logical entities. These functional blocks can be implemented in software, or in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0026] The flowcharts shown in the drawings are only exemplary and do not necessarily include all steps. For example, some steps can be further divided, and some steps can be combined or partially combined, so that the actual execution order can be changed according to the actual situation.

[0027] Due to the related art, the detection and classification method for defective wafers is not accurate and efficient.

[0028] Based on this, the present disclosure provides a wafer defect detection method, by obtaining target wafer information, obtaining n kinds of wafer characteristic data according to the target wafer information, n is a positive integer greater than 1, using a target neural network model to process m kinds of wafer characteristic data in the n kinds of wafer characteristic data, obtaining the defect category of the wafer, m is a positive integer less than or equal to n and greater than 1. Through the above-mentioned mode, the accuracy of detecting and classifying the defective wafer can be improved, and the detection and classification efficiency can be improved.

[0029] In order to facilitate the overall understanding of the technical solutions provided by the embodiments of the present disclosure, Figure 1 A flowchart of a wafer defect detection method is shown, as shown in Figure 1 The method comprises the following steps:

[0030] S102: Obtain target wafer information.

[0031] The target wafer information can include first wafer data and second wafer data.

[0032] In one possible embodiment, the target wafer information can be obtained in the following manner: obtaining initial wafer information, the initial wafer information including the position information and test results of each chip on the wafer; marking binary label data on the corresponding position information of each chip on the wafer according to the position information and test results of each chip on the wafer to obtain the first wafer data, and converting the first wafer data with binary label data to obtain the second wafer data with numerical label data.

[0033] The initial wafer information can include various data information corresponding to the wafer produced on the semiconductor device production line. Specifically, it can include the position information and test results of each chip on the wafer.

[0034] For example, the test results in the initial wafer information include two types of test pass (Pass) and test fail (Fail), and binary label data is marked on the corresponding position information of each chip on the wafer according to the position information and test results of each chip on the wafer to obtain the first wafer data.

[0035] Specifically, the way to mark binary label data on the corresponding position information of each chip on the wafer can be: if the test result of the chip on the wafer is test pass, the binary label data marked on the corresponding position information is the first value, the first value can be 0, and if the test result of the chip on the wafer is test fail, the binary label data marked on the corresponding position information is the second value, the second value can be 1. As shown in Figure 2 Figure 2 ​A wafer including test passed chips and test failed chips is shown, wherein the blank square on the wafer represents a test passed chip, and the square with shadow on the wafer represents a test failed chip.

[0036] Exemplarily, after determining the first wafer data, processing is performed on the basis of the first wafer data, and the second wafer data with numerical data can be obtained.

[0037] Specifically, according to the first wafer data with binary label data, the test failed chips and their position information on the wafer and the test passed chips and their position information are determined, according to the test failed chips and their position information on the wafer and the test passed chips and their position information, the weighted distance of each test passed chip to all test failed chips on the wafer is obtained to determine the numerical label data of the test passed chips on the wafer, and according to the test failed chips and their position information on the wafer, the weighted distance of the target test failed chip to the remaining test failed chips on the wafer is obtained to determine the numerical label data of the target test failed chip on the wafer.

[0038] As Figure 3 shown, after converting the first wafer data with binary label data into the second wafer data with numerical label data, the second wafer data can be specifically represented on the wafer in a gradual numerical value manner, and the specific numerical value corresponding to the chip can be represented by the color of the square representing the chip on the wafer.

[0039] Specifically, the manner of determining the second wafer data with numerical label data from the first wafer data with binary label data can be processed by the following formula, and the specific formula is as follows:

[0040]

[0041]

[0042] In the above formula, N b represents the number of test failed chips on the wafer; y s represents a test failed chip, y r represents a test passed chip, y wc represents the center of the wafer, d(y r ,y s ) represents the distance between the test passed chip and the test failed chip, d(y r ,y wc ) represents the distance between the test passed chip and the center; and m is a constant. Wherein, m is used to determine the weight affected by the surrounding chips, and the specific value can be 1.

[0043] Through the above manner, after the target wafer information is effectively determined, S104 is executed.

[0044] S104: Obtain n kinds of wafer characteristic data according to the target wafer information, n is a positive integer greater than 1.

[0045] In a possible embodiment, through the target wafer information, n kinds of wafer characteristic data in the wafer can be determined, and specific manners that can be adopted include multiple manners.

[0046] For example, a statistical manner can be adopted for processing to obtain n kinds of wafer characteristic data. Specifically, a principal components analysis (PCA) manner can be adopted to process the target wafer information to obtain one kind of wafer characteristic data in the n kinds of wafer characteristic data.

[0047] For example, a singular value decomposition (SVD) manner can also be adopted to process the target wafer information to obtain wafer characteristic data.

[0048] Further, the target wafer information can also be processed by multiple clustering algorithms to obtain n kinds of wafer characteristic data. For example, 500 clustering methods can be used to process the target wafer information to determine 500 wafer characteristic data. In the present disclosure, the more wafer characteristic data obtained by processing the target wafer information, the better, as long as the computing capability supports, the more wafer characteristic data, the better the effect of wafer detection and the higher the accuracy.

[0049] The specific manner of obtaining n kinds of wafer characteristic data through multiple clustering algorithms can be as follows: the first wafer data and the second wafer data are respectively processed by clustering to obtain a first clustering result of the first wafer data and a second clustering result of the second wafer data, and n kinds of wafer characteristic data are obtained according to the first clustering result and the second clustering result.

[0050] In a possible embodiment, the first wafer data and the second wafer data are respectively processed by clustering through clustering models established by two clustering algorithms, and the specific manner can be as follows: the first wafer data and the second wafer data are processed by clustering in the following manner: the first wafer data and the second wafer data are respectively clustered by using a first clustering model to obtain a first initial clustering result of the first wafer data and a second initial clustering result of the second wafer data, and the first wafer data and the second wafer data are respectively clustered by using a second clustering model to obtain a third initial clustering result of the first wafer data and a fourth initial clustering result of the second wafer data.

[0051] The first clustering result includes a first initial clustering result and a third initial clustering result, and the second clustering result includes a second initial clustering result and a fourth initial clustering result.

[0052] Exemplarily, the first clustering model can be modeled using a K-Nearest Neighbor (K-Means) method in a clustering method, and the second clustering model can be modeled using a Particle Swarm Optimization-based K-Nearest Neighbor (PSO-K-Means) method in the clustering method.

[0053] In another possible embodiment, the first wafer data and the second wafer data can also be processed in the following manner: determining a first cluster number of the first wafer data and a second cluster number of the second wafer data, wherein the first cluster number and the second cluster number are used for the first clustering model to obtain the first initial clustering result and the second initial clustering result, respectively; and the first cluster number and the second cluster number are used as a first particle number and a second particle number for the second clustering model to obtain the third initial clustering result and the fourth initial clustering result, respectively.

[0054] The number of clustering clusters that can be obtained after the wafer data is processed by the clustering model can be determined in advance before the wafer data is processed by the clustering model, and the wafer data is processed, which can make the subsequent clustering processing converge more quickly.

[0055] Exemplarily, the manner of determining the first cluster number of the first wafer data and the second cluster number of the second wafer data can specifically use an elbow method.

[0056] It should be noted that the above manner is only an example of processing the target wafer information by two clustering models, and more clustering models can also be used to process the target wafer information to obtain more wafer feature data.

[0057] After the first clustering result and the second clustering result are determined in the above manner, n kinds of wafer feature data can be further determined. Since the determined first clustering result and the second clustering result are both numerical label data, in order to facilitate subsequent processing, the first initial clustering result, the second initial clustering result, the third initial clustering result, and the fourth initial clustering result can be converted into binary label data. Since the first wafer data and the second wafer data are processed by two clustering models in the above manner, four initial clustering results of numerical label data are obtained. Therefore, in the process of converting the binary label data, the wafer feature data that can be obtained is 4 kinds.

[0058] The specific manner can be: converting the first initial clustering result, the second initial clustering result, the third initial clustering result and the fourth initial clustering result of the numerical type into four kinds of wafer feature data of the binary type respectively; wherein the n kinds of wafer feature data include the four kinds of wafer feature data.

[0059] S106: processing m kinds of wafer feature data in the n kinds of wafer feature data by using the target neural network model to obtain the defect category of the wafer, m is a positive integer less than or equal to n and greater than 1.

[0060] In a possible embodiment, the target neural network model can use an unsupervised adaptive resonance neural network model.

[0061] The target neural network model can specifically use the ATR1 version in the adaptive resonance neural network model. The target neural network model can also select other neural network models, for example, it can also be a trained classification model.

[0062] The n kinds of wafer feature data obtained in the above steps are used as the input of the adaptive resonance neural network model for final clustering processing, and the final grouping result can be obtained. It should be noted that the n kinds of wafer feature data obtained do not necessarily have to be all input into the ART model, and can be arbitrarily selected and combined for input into the ART model.

[0063] Exemplarily, the four kinds of wafer feature data obtained above can be input into the adaptive resonance neural network model to obtain the final grouping result, wherein the final grouping result includes the category of the defective wafer and the category of the non-defective wafer. As shown in Figure 4

[0064] Through the way of the present disclosure, the first wafer data and the second wafer data in the target wafer information are clustered and processed by multiple clustering algorithms to obtain multiple initial clustering results, and multiple wafer feature data are extracted from the multiple initial clustering results. In the specific clustering process, as many clustering algorithms as possible can be used to construct a clustering model, and the target wafer information is processed to obtain as many wafer feature data as possible. Finally, the adaptive resonance neural network model is used to distinguish and screen the multiple wafer feature data, remove noise, and finally detect the defective wafer to obtain the defect category of the wafer.

[0065] ​It should be noted that, in order to improve the efficiency of detection and classification, as much wafer feature data as possible is obtained in as few detection times as possible in the present disclosure, so as to quickly complete the detection of the defective wafer. However, in the related art, too many features cannot be effectively processed, and the defective wafer cannot be distinguished and detected from so many features. Therefore, the adaptive resonance neural network model is selected as the target neural network model in the present disclosure.

[0066] Further, by processing the target wafer information through the above-mentioned multiple clustering algorithms, the target wafer information is processed through multiple clustering algorithms, which is more accurate than the way of detecting and classifying the wafer directly through only one clustering algorithm in the related art. Moreover, after obtaining n wafer feature data and processing it through the target neural network model, the screening result is more accurate and the efficiency is higher.

[0067] In a possible implementation manner, Figure 5 A schematic diagram of a wafer defect detection method in the present disclosure is shown. As shown in Figure 5 .

[0068] S502: Obtain target wafer information, wherein the target wafer information includes first wafer data and second wafer data.

[0069] In a possible embodiment, by Figure 6 The target wafer information is processed to obtain the defect category of the final wafer.

[0070] S504: The first wafer data and the second wafer data are respectively clustered by the K-neighbor clustering algorithm and the K-neighbor algorithm based on the particle swarm to obtain the first clustering result and the second clustering result, and four wafer feature data are determined, wherein the first clustering result includes a first initial clustering result and a third initial clustering result, and the second clustering result includes a second initial clustering result and a fourth initial clustering result.

[0071] In a possible embodiment, Figure 6 Partition1 in the above-mentioned formula represents the first initial clustering result, Partition2 represents the second initial clustering result, Partition3 represents the third initial clustering result, and Partition4 represents the fourth initial clustering result.

[0072] The first initial clustering result, the second initial clustering result, the third initial clustering result, and the fourth initial clustering result of the numerical label data are converted into binary label data to obtain the wafer feature data.

[0073] For example, as shown in Table 1 and Table 2 below, the clustering results of the numerical types of Partition 1, Partition 2, Partition 3 and Partition 4 are converted into binary types respectively:

[0074] Table 1 Cluster result of numerical type

[0075] col1 col2 col3 col4 clustering results 0 0 1 0 group1 1 1 1 0 group2

[0076] Table 2 Wafer feature data of binary type

[0077] col1 col2 col3 col4 group1 group2 0 0 1 0 1 0 1 1 1 0 0 1

[0078] In the above Table 1 and Table 2, col1 to col4 are used to represent the clustering results of the numerical type, and after the wafer feature data is converted into the binary type, according to the number of groups of the clustering results in Table 1, corresponding bits are used for representation, for example, it is assumed in the above table that there are 2 groups (group 1 and group 2), then 2 bits are used to represent the wafer feature data of the binary type, the first bit corresponds to group 1, and the second bit corresponds to group 2, when a certain clustering result is group 1, then the 2 bits are represented as "10", and when a certain clustering result is group 2, then the 2 bits are represented as "01".

[0079] S506: processing m wafer feature data in the n wafer feature data by using the target neural network model to obtain the defect category of the wafer, m is a positive integer less than or equal to n and greater than 1.

[0080] Based on the same inventive concept, the embodiment of the present disclosure also provides a wafer defect detection device, as follows. Since the principle of solving the problem of the device embodiment is similar to that of the above-mentioned method embodiment, the implementation of the device embodiment can be referred to the implementation of the above-mentioned method embodiment, and the repeated parts will not be described here.

[0081] Figure 7 A structure diagram of a wafer defect detection device is shown, wherein the wafer defect detection device 70 comprises: an acquisition unit 701, configured to obtain target wafer information; the acquisition unit is further configured to obtain n wafer feature data according to the target wafer information, n is a positive integer greater than 1; a processing unit 702, configured to process m wafer feature data in the n wafer feature data by using a target neural network model to obtain the defect category of the wafer, m is a positive integer less than or equal to n and greater than 1.

[0082] Figure 8 is a structure diagram of a data processing device provided by the embodiment of the present disclosure. As shown in Figure 8As shown, the data processing device in the embodiment of the present disclosure can include one or more processors 801, a memory 802, and an input / output interface 803. The processor 801, the memory 802, and the input / output interface 803 are connected through a bus 804. The memory 802 is configured to store a computer program, the computer program including program instructions, and the input / output interface 803 is configured to receive and output data, such as for performing data interaction between a host and the data processing device, or for performing data interaction between virtual machines in the host; the processor 801 is configured to execute the program instructions stored in the memory 802.

[0083] The processor 801 can obtain semiconductor device demand information and a preventive maintenance original window of each semiconductor device of the same type, obtain a current generation chromosome of each semiconductor device under the constraint of the preventive maintenance original window of each semiconductor device, obtain a current generation three-phase guide vector according to the semiconductor device demand information and the current generation chromosome of each semiconductor device, perform one-way mutation on the current generation chromosome of each semiconductor device under the guidance of the current generation three-phase guide vector to obtain a next generation chromosome of each semiconductor device, obtain a target chromosome of each semiconductor device according to the current generation chromosome and the next generation chromosome of each semiconductor device, and determine a preventive maintenance time of each semiconductor device according to the target chromosome of each semiconductor device, the preventive maintenance time of each semiconductor device being in the preventive maintenance original window of the corresponding semiconductor device.

[0084] In some possible implementation manners, the processor 801 can be a central processing unit (CPU), and can also be another general-purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component, or the like. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor.

[0085] The memory 802 can include a read-only memory and a random access memory, and provide instructions and data for the processor 801 and the input / output interface 803. A part of the memory 802 can also include a non-volatile random access memory. For example, the memory 802 can also store device type information.

[0086] In practice, the data processing device can execute the implementation methods provided by each step in any of the above method embodiments through its built-in functional modules. For details, please refer to the implementation methods provided by each step in the figure shown in the above method embodiments, which will not be repeated here.

[0087] This disclosure provides a data processing device, including a processor, an input / output interface, and a memory, wherein the processor retrieves a computer program from the memory and executes the steps of the method shown in any of the above embodiments.

[0088] This disclosure also provides a computer-readable storage medium storing a computer program. Figure 9 This illustration shows a schematic diagram of a computer-readable storage medium according to an embodiment of the present disclosure, such as... Figure 9 As shown, the computer-readable storage medium 900 stores a program product capable of implementing the methods described above. This computer program is adapted to be loaded by the processor and execute the data processing methods provided in the steps of any of the above embodiments. Specific implementations of the steps in any of the above embodiments can be found here, and will not be repeated here. Furthermore, descriptions of the beneficial effects of using the same methods will not be repeated here either. For technical details not disclosed in the embodiments of the computer-readable storage medium involved in this disclosure, please refer to the description of the method embodiments of this disclosure. As an example, the computer program can be deployed to execute on a single data processing device, or on multiple data processing devices located at one location, or on multiple data processing devices distributed across multiple locations and interconnected via a communication network.

[0089] The computer-readable storage medium can be the data processing apparatus provided in any of the foregoing embodiments, or the internal storage unit of the data processing apparatus, such as the hard disk or memory of the data processing apparatus. The computer-readable storage medium can also be an external storage device of the data processing apparatus, such as a plug-in hard disk, smart media card (SMC), secure digital (SD) card, flash card, etc., equipped on the data processing apparatus. Furthermore, the computer-readable storage medium can include both internal storage units and external storage devices of the data processing apparatus. The computer-readable storage medium is used to store the computer program and other programs and data required by the data processing apparatus. The computer-readable storage medium can also be used to temporarily store data that has been output or will be output.

[0090] The embodiments of the present disclosure further provide a computer program product or computer program, which comprises computer instructions stored in a computer readable storage medium. A processor of a data processing device reads the computer instructions from the computer readable storage medium, and the processor executes the computer instructions, so that the data processing device performs the method provided in any of the various optional manners in the above-described embodiments.

[0091] The terms "first", "second", and the like in the description and claims of the embodiments of the present disclosure and the accompanying drawings are used to distinguish different objects, and are not used to describe a particular order. In addition, the term "comprising" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, device, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but can optionally further include steps or units not listed, or can optionally further include other steps or units inherent to the process, method, device, product, or apparatus.

[0092] Those of ordinary skill in the art can realize that the units and algorithm steps of the examples described in conjunction with the embodiments disclosed herein can be realized in electronic hardware, computer software, or a combination of both. In order to clearly illustrate the interchangeability of hardware and software, the components and steps of the examples have been described in general terms in the description. Whether the functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. A person skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present disclosure.

[0093] The methods and related apparatuses provided by the embodiments of the present disclosure are described with reference to the method flowcharts and / or structural schematic diagrams provided by the embodiments of the present disclosure. Each flow and / or block in the method flowchart and / or structural schematic diagram, and the combination of the flows and / or blocks in the flowchart and / or block diagram can be realized by computer program instructions. These computer program instructions can be provided to a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable application display devices to produce a machine, so that the instructions executed by the computer or other programmable application display devices produce a device that implements the functions specified in the flow Figure 1 The functions specified in one flow or multiple flows and / or structural schematic Figure 1 These computer program instructions can also be stored in a computer readable storage medium that can guide the computer or other programmable application display devices to work in a specific way, so that the instructions stored in the computer readable storage medium produce a manufactured product including instruction devices that implement the functions specified in the flow Figure 1 The functions specified in one flow or multiple flows and / or structural schematic Figure 1The computer program instructions can also be loaded onto a computer or other programmable application display device to cause a series of operational steps to be performed on the computer or other programmable device to produce a computer-implemented process such that the instructions which execute on the computer or other programmable device provide steps for implementing the operations described in the flowcharts or flow diagrams as Figure 1 The computer program instructions can also be loaded onto a computer or other programmable application display device to cause a series of operational steps to be performed on the computer or other programmable device to produce a computer-implemented process such that the instructions which execute on the computer or other programmable device provide steps for implementing the operations described in the flowcharts or flow diagrams as

[0094] Other embodiments of the disclosure will be apparent to those of ordinary skill in the art from a consideration of the specification and practice of the disclosure disclosed herein. It is intended that the disclosure encompass any and all variations, uses, or adaptations of the disclosure following the general principles thereof and including such modifications as would be apparent to one of ordinary skill in the art in light of the disclosure. The specification and examples given are intended as illustrative only and not in a limiting sense. Thus, the true scope of the disclosure is indicated by the appended claims.

Claims

1. A wafer defect detection method, characterized by, The method comprises the following steps: obtaining target wafer information, the target wafer information comprising first wafer data and second wafer data, the specific method comprising: obtaining initial wafer information, the initial wafer information comprising position information and test results of each chip on the wafer; marking binary label data on the corresponding position information of each chip on the wafer according to the position information and test results of each chip on the wafer to obtain the first wafer data; and performing conversion processing on the first wafer data with binary label data to obtain the second wafer data with numerical label data; obtaining n kinds of wafer feature data according to the target wafer information, n being a positive integer greater than 1; processing m kinds of wafer feature data in the n kinds of wafer feature data by using a target neural network model to obtain the defect category of the wafer, m being a positive integer less than or equal to n and greater than 1; wherein the converting the first wafer data with binary label data comprises determining the numerical label data of the test passed chips on the wafer according to the following formula : In the above formula, represents the number of test failed chips on the wafer; represents a test failed chip, represents a test passed chip, represents the center of the wafer, represents the distance between the test passed chip and the test failed chip, represents the distance between the test passed chip and the center of the wafer; m is a constant.

2. The method of claim 1, wherein, marking binary label data on the corresponding position information of each chip on the wafer according to the test results of each chip on the wafer to obtain the first wafer data, comprising: if the test result of the chip on the wafer is test passed, the binary label data marked on the corresponding position information is a first value; if the test result of the chip on the wafer is test failed, the binary label data marked on the corresponding position information is a second value.

3. The method of claim 1, wherein, performing conversion processing on the first wafer data with binary label data to obtain the second wafer data with numerical label data, comprising: determining the test failed chips and their position information and the test passed chips and their position information on the wafer according to the first wafer data with binary label data; obtaining the weighted distance of all test failed chips on the wafer to each test passed chip to determine the numerical label data of the test passed chips on the wafer according to the determination of the test failed chips and their position information and the test passed chips and their position information on the wafer; obtaining the weighted distance of the remaining test failed chips on the wafer to the target test failed chip to determine the numerical label data of the target test failed chip on the wafer according to the determination of the test failed chips and their position information.

4. The method of claim 1, wherein, obtaining n kinds of wafer feature data according to the target wafer information, further comprising: performing principal component analysis on the target wafer information to obtain one kind of wafer feature data in the n kinds of wafer feature data.

5. The method of claim 1, wherein, obtaining n kinds of wafer feature data according to the target wafer information, comprising: performing clustering processing on the first wafer data and the second wafer data respectively to obtain the first clustering result of the first wafer data and the second clustering result of the second wafer data; obtaining n kinds of wafer feature data according to the first clustering result and the second clustering result.

6. The method of claim 5, wherein, performing clustering processing on the first wafer data and the second wafer data respectively to obtain the first clustering result of the first wafer data and the second clustering result of the second wafer data, comprising: respectively using a first clustering model to obtain a first initial clustering result of the first wafer data and a second initial clustering result of the second wafer data; respectively using a second clustering model to obtain a third initial clustering result of the first wafer data and a fourth initial clustering result of the second wafer data; wherein the first clustering result comprises the first initial clustering result and the third initial clustering result, and the second clustering result comprises the second initial clustering result and the fourth initial clustering result.

7. The method of claim 6, wherein, obtaining n kinds of wafer feature data according to the first clustering result and the second clustering result, comprising: respectively converting the first initial clustering result, the second initial clustering result, the third initial clustering result and the fourth initial clustering result of the numerical type into four kinds of wafer feature data of the binary type; wherein the n kinds of wafer feature data include the four kinds of wafer feature data.

8. The method of claim 6, wherein, respectively performing clustering processing on the first wafer data and the second wafer data to obtain a first clustering result of the first wafer data and a second clustering result of the second wafer data, further comprising: determining a first cluster number of the first wafer data and a second cluster number of the second wafer data; wherein the first initial clustering result and the second initial clustering result are obtained by respectively adopting the first cluster number and the second cluster number for the first clustering model; and the third initial clustering result and the fourth initial clustering result are obtained by respectively adopting the first cluster number and the second cluster number as a first particle number and a second particle number for the second clustering model.

9. The method of claim 1, wherein, The target neural network model comprises an adaptive resonance neural network model.

10. A computer readable storage medium having stored thereon computer instructions, wherein, The computer instructions, when executed, perform the steps of the method of any one of claims 1 to 9.

11. A data processing device comprising a memory and a processor, said memory having stored thereon computer instructions executable on said processor, characterized in that, The processor, when executing the computer instructions, performs the steps of the method of any one of claims 1 to 9.

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