Gate drive circuit and display device

Abstract

Disclosed are a gate driving circuit including a first gate output buffer circuit and a control circuit, and a display device including the same. The control circuit can include a first transistor connected between a first driving voltage node and a QB node, two second transistors connected in series between the QB node and a second low voltage node, a third transistor connected between a connection node of the two second transistors and the first driving voltage node, a fourth transistor connected between a gate node of the first transistor and the first driving voltage node, and two fifth transistors connected in series between the gate node of the first transistor and the second low voltage node. A connection node of the two fifth transistors can be electrically connected to a source node or a drain node of the third transistor.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0150885, filed on November 4, 2021, which is incorporated herein by reference for all purposes as if it were fully described herein. Technical Field

[0003] Embodiments of this disclosure relate to gate drive circuits and display devices. Background Technology

[0004] With the development of the information society, the demand for display devices for displaying images is constantly growing in various forms. In recent years, various display devices such as liquid crystal displays and organic light-emitting diode displays have been put into use.

[0005] For image display, the display device includes a display panel having multiple data lines and multiple gate lines therein, a data driving circuit configured to output data signals to the multiple data lines, and a gate driving circuit configured to output gate signals to the multiple gate lines.

[0006] When a conventional display device uses a gate drive circuit to drive multiple gate lines, the gate signal output to the gate line should have a high-level voltage and a low-level voltage according to the gate drive timing.

[0007] However, in conventional gate drive circuits, a phenomenon occurs where the gate signal output from the gate drive circuit has an abnormal waveform. This phenomenon can degrade image quality and gate drive performance. Here, the abnormal waveform can be any waveform that differs from the normal waveform. For example, when the voltage level in the gate signal does not reach the expected level, or when the timing of the voltage level change in the gate signal is mismatched, the corresponding gate signal can be said to have an abnormal waveform.

[0008] Furthermore, when the display device performs sensing-driving to sense the characteristic values ​​of transistors in order to compensate for the deviation between the characteristic values ​​of transistors contained in sub-pixels, the phenomenon of outputting a gate signal with an abnormal signal waveform from the gate drive circuit may be significant. Summary of the Invention

[0009] In the field of displays, gate drive circuits are used to drive gate lines disposed on the display panel. However, there is a problem with the gate drive circuit outputting a gate signal with an abnormal signal waveform. Accordingly, the inventors of this disclosure have recognized the cause of this problem through extensive research and experimentation, and have invented a gate drive circuit and a display device to solve this problem.

[0010] Embodiments of this disclosure may provide a display device and a gate drive circuit configured to output a gate signal having a normal signal waveform.

[0011] Embodiments of this disclosure may provide a display device and a gate driving circuit configured to output a gate signal having a normal signal waveform when performing a gate drive for sensing-driving to sense the mobility of the driving transistor in a sub-pixel.

[0012] Embodiments of this disclosure may provide a gate drive circuit comprising: a first gate output buffer circuit including a first pull-up transistor and a first pull-down transistor; and a control circuit configured to control the voltage of a Q node connected to the gate node of the first pull-up transistor and the voltage of a QB node connected to the gate node of the first pull-down transistor.

[0013] The first pull-up transistor can be connected between the first clock signal input node and the first gate output node, and the first pull-down transistor can be connected between the first gate output node and the first low-level voltage node.

[0014] The control circuit may include: a first transistor connected between a first drive voltage node and the QB node; two second transistors connected in series between the QB node and the second low-level voltage node; a third transistor connected between the connection node of the two second transistors and the first drive voltage node; a fourth transistor connected between the gate node of the first transistor and the first drive voltage node; and two fifth transistors connected in series between the gate node of the first transistor and the second low-level voltage node.

[0015] The connection nodes of the two fifth transistors can be electrically connected to the source node or drain node of the third transistor.

[0016] The drain or source node of the third transistor can be connected to the first driving voltage node, and the source or drain node of the third transistor can be connected to the connection node of the two second transistors and the connection node of the two fifth transistors.

[0017] Each of the two second transistors may have a gate node connected to the Q node.

[0018] The third transistor may have a gate node connected to the QB node.

[0019] Each of the two fifth transistors may have a gate node connected to the Q node.

[0020] The third transistor may include two transistors connected in series between the first drive voltage node and the connection node of the two second transistors.

[0021] The second low-level voltage applied to the second low-level voltage node may be lower than the first low-level voltage applied to the first low-level voltage node.

[0022] Embodiments of this disclosure may provide a display device comprising: a display panel including a plurality of gate lines; and a gate driving circuit configured to drive the plurality of gate lines.

[0023] The gate drive circuit may include: a first gate output buffer circuit including a first pull-up transistor and a first pull-down transistor; and a control circuit configured to control the voltage of the Q node connected to the gate node of the first pull-up transistor and the voltage of the QB node connected to the gate node of the first pull-down transistor.

[0024] The first pull-up transistor can be connected between the first clock signal input node and the first gate output node, and the first pull-down transistor is connected between the first gate output node and the first low-level voltage node.

[0025] The control circuit may include: a first transistor connected between a first drive voltage node and the QB node; two second transistors connected in series between the QB node and the second low-level voltage node; a third transistor connected between the connection node of the two second transistors and the first drive voltage node; a fourth transistor connected between the gate node of the first transistor and the first drive voltage node; and two fifth transistors connected in series between the gate node of the first transistor and the second low-level voltage node.

[0026] The connection nodes of the two fifth transistors can be electrically connected to the source node or drain node of the third transistor.

[0027] The drain or source node of the third transistor can be connected to the first driving voltage node, and the source or drain node of the third transistor can be connected to the connection node of the two second transistors and the connection node of the two fifth transistors.

[0028] Each of the two second transistors may have a gate node connected to the Q node.

[0029] The third transistor may have a gate node connected to the QB node.

[0030] Each of the two fifth transistors may have a gate node connected to the Q node.

[0031] The third transistor may include two transistors connected in series between the first drive voltage node and the connection node of the two second transistors.

[0032] The second low-level voltage applied to the second low-level voltage node may be lower than the first low-level voltage applied to the first low-level voltage node.

[0033] According to various embodiments, a display device includes a display panel and a gate driving circuit. The display panel includes gate lines. The gate driving circuit drives the gate lines in operation and includes a gate output buffer circuit and a control circuit. The gate output buffer circuit is coupled to the gate lines and includes a pull-up transistor and a pull-down transistor, the pull-up transistor having a gate node connected to a Q node and the pull-down transistor having a gate node connected to a QB node. The control circuit includes a first transistor coupled to the QB node. The control circuit performs the following operations in operation: when the voltage of the Q node is at a first level, applying a second low-level voltage of a second low-level voltage node to the gate node and source node of the first transistor; and electrically isolating the second low-level voltage node from the gate node of the first transistor when ripple in the voltage of the Q node is applied to the gate node of a second control transistor connected between the gate node of the first transistor and the second low-level voltage node.

[0034] The second transistor may have a gate node connected to the Q node.

[0035] The pull-up transistor can be connected between the clock signal input node and the gate output node, and the pull-down transistor can be connected between the gate output node and the first low-level voltage node. The second low-level voltage applied to the second low-level voltage node can be lower than the first low-level voltage applied to the first low-level voltage node.

[0036] According to embodiments of this disclosure, it is possible to provide a display device and a gate driving circuit configured to output a gate signal having a normal signal waveform.

[0037] According to embodiments of the present disclosure, it is possible to provide a display device and a gate driving circuit configured to output a gate signal having a normal signal waveform when performing a gate drive for sensing-driving to sense the mobility of the driving transistor in the sub-pixel. Attached Figure Description

[0038] The above and other aspects, features and advantages of this disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0039] Figure 1 This is a configuration diagram of a display device according to an embodiment of the present disclosure.

[0040] Figure 2A and Figure 2B It is the equivalent circuit of a sub-pixel of a display device according to an embodiment of the present disclosure.

[0041] Figure 3 A system of display devices according to an embodiment of the present disclosure is shown.

[0042] Figure 4 A compensation circuit for a display device according to an embodiment of the present disclosure is shown.

[0043] Figure 5A This is an illustration of a first sensing mode of a display device according to an embodiment of the present disclosure.

[0044] Figure 5B This is an illustration of a second sensing mode of a display device according to an embodiment of the present disclosure.

[0045] Figure 6 This is a diagram illustrating various sensing timings of a display device according to embodiments of the present disclosure.

[0046] Figure 7 This is a schematic illustration of the gate driving circuit of a display device according to an embodiment of the present disclosure.

[0047] Figure 8 A gate driving circuit included in a display device according to an embodiment of the present disclosure is shown when the display device has a sensing function.

[0048] Figure 9 It shows Figure 8 The voltage waveform at the main node in the gate drive circuit.

[0049] Figure 10 An improved gate drive circuitry included in a display device according to an embodiment of the present disclosure is shown when the display device has a sensing function.

[0050] Figure 11 and Figure 12 It shows Figure 10 The voltage waveform at the main node in the improved gate drive circuit. Detailed Implementation

[0051] In the following description of examples or embodiments of the invention, reference will be made to the accompanying drawings, in which specific examples or embodiments that can be implemented are illustrated by way of example, and in the drawings, the same reference numerals and symbols may be used to denote the same or similar components, even if these components are shown in different drawings. Furthermore, in the following description of examples or embodiments of the invention, detailed descriptions of well-known functions and components incorporated herein may be omitted where such detailed descriptions would make the subject matter of some embodiments of the invention quite unclear. Words such as “comprising,” “having,” “containing,” “consisting of,” “formed by,” and “determined by” as used herein are generally intended to allow for the addition of other components, unless such words are used with “only.” As used herein, the singular form is intended to include the plural form unless the context explicitly indicates otherwise.

[0052] This document may use designations such as "first," "second," "A," "B," "(A)," or "(B)" to describe elements of the invention. Such designations are not intended to define the substance, order, or number of elements, but are merely used to distinguish the corresponding element from other elements.

[0053] When referring to a first element being "connected or coupled to" a second element, or "in contact with or overlapping" a second element, it should be interpreted as meaning that the first element can not only be "directly connected or coupled to" the second element or "directly in contact with or overlapping" the second element, but also that a third element can be "inserted" between the first and second elements, or that the first and second elements can be "connected or coupled" or "in contact with or overlapping" each other via a fourth element, and so on. Here, the second element can be included in at least one of two or more elements that are "connected or coupled" or "in contact with or overlapping" each other.

[0054] When using time-relative terms such as “after,” “follow,” “next,” or “before,” to describe a process or operation of an element or configuration, or a flow or step in an operation, processing, or manufacturing method, these terms may be used to describe a discontinuous or non-sequential process or operation, unless used with the words “directly” or “immediately.”

[0055] Furthermore, when referring to any external dimensions, relative dimensions, etc., it should be assumed that the numerical or corresponding information of the component or feature (e.g., level, range, etc.) includes the tolerance or error range that may be caused by various factors (e.g., process factors, internal or external influences, noise, etc.), even if no relevant description is specified. In addition, the word "can" fully encompasses the entire meaning of the word "able to".

[0056] Various embodiments of this disclosure will be described in detail below with reference to the accompanying drawings.

[0057] Figure 1 This is a configuration diagram of a display device 100 according to an embodiment of the present disclosure.

[0058] refer to Figure 1 The display device 100 according to the embodiments of the present disclosure may include a display panel 110 and a driving circuit for driving the display panel 110.

[0059] The driving circuit may include a data driving circuit 120, a gate driving circuit 130, etc., and may further include a controller 140 for controlling the data driving circuit 120 and the gate driving circuit 130.

[0060] The display panel 110 may include a substrate SUB and signal lines such as multiple data lines DL and multiple gate lines GL disposed on the substrate SUB. The display panel 110 may include multiple data lines DL and multiple sub-pixels SP connected to the multiple gate lines GL.

[0061] The display panel 110 may include a display area DA for displaying images and a non-display area NDA for not displaying images. In the display panel 110, multiple sub-pixels SP for displaying images can be set in the display area DA. Driving circuits 120, 130, and 140 can be electrically connected to or installed in the non-display area NDA, and pad units to which integrated circuits or printed circuit boards are connected can be set in the non-display area NDA.

[0062] Data drive circuit 120, serving as a circuit for driving multiple data lines DL, can supply data signals to the multiple data lines DL. Gate drive circuit 130, serving as a circuit for driving multiple gate lines GL, can supply gate signals to the multiple gate lines GL. Controller 140 can provide data control signal DCS to data drive circuit 120 to control the operating timing of data drive circuit 120. Controller 140 can provide gate control signal GCS to gate drive circuit 130 to control the operating timing of gate drive circuit 130.

[0063] The controller 140 can start scanning according to the timing implemented in each frame, convert input image data from external input into a data signal format for the data drive circuit 120, provide the converted image data Data to the data drive circuit 120, and control the data drive at an appropriate time according to the scan.

[0064] The controller 140 receives various timing signals from external sources (e.g., host system 150), including vertical synchronization signal VSYNC, horizontal synchronization signal HSYNC, input data enable signal Data EnableDE, clock signal CLK, etc., along with the input image data.

[0065] In order to control the data drive circuit 120 and the gate drive circuit 130, the controller 140 receives timing signals such as the vertical synchronization signal VSYNC, the horizontal synchronization signal HSYNC, the input data enable signal DE, and the clock signal CLK, generates various control signals DCS and GCS, and outputs the control signals DCS and GCS to the data drive circuit 120 and the gate drive circuit 130 respectively.

[0066] For example, in order to control the gate drive circuit 130, the controller 140 outputs various gate control signals GCS, including the gate start pulse (GSP), gate shift clock (GSC), gate output enable signal (GOE), etc.

[0067] In addition, in order to control the data drive circuit 120, the controller 140 also outputs various data control signals DCS, including the source start pulse (SSP), the source sampling clock (SSC), and the source output enable signal (SOE).

[0068] The controller 140 can be implemented as a separate component from the data drive circuit 120, or it can be integrated with the data drive circuit 120 and implemented as an integrated circuit.

[0069] The data driving circuit 120 drives the plurality of data lines DL by receiving image data Data from the controller 140 and providing data voltage to the plurality of data lines DL. Here, the data driving circuit 120 is also referred to as the source driving circuit.

[0070] The data drive circuit 120 may include one or more source driver integrated circuits (SDICs).

[0071] Each source driver integrated circuit (SDIC) may include a shift register, latch circuit, digital-to-analog converter (DAC), output buffer, etc. Each source driver integrated circuit (SDIC) may further include an analog-to-digital converter (ADC) as needed.

[0072] For example, each source driver integrated circuit SDIC can be connected to the display panel 110 via tape-and-reel auto-bonding (TAM) method, or via chip-on-glass (COG) or chip-on-panel (COP) method, or via chip-on-film (COF) method and connected to the display panel.

[0073] The gate drive circuit 130 can output a gate signal with a conduction level voltage or a gate signal with a cutoff level voltage according to the control of the controller 140. The gate drive circuit 130 can sequentially drive the plurality of gate lines GL by sequentially providing gate signals with conduction level voltages to the plurality of gate lines GL.

[0074] The gate driving circuit 130 can be connected to the display panel via the TAB method, to the bonding pads of the display panel 110 via the COG or COP method, or to the display panel 110 via the COF method. Alternatively, the gate driving circuit 130 can be formed in the non-display area NDA of the display panel 110 according to the gate in panel (GIP) type. The gate driving circuit 130 can be disposed on or connected to the substrate SUB. That is, for the GIP type, the gate driving circuit 130 can be disposed in the non-display area NDA of the substrate SUB. For the COG type, COF type, etc., the gate driving circuit 130 can be connected to the substrate SUB.

[0075] Meanwhile, at least one of the data driving circuit 120 and the gate driving circuit 130 may be disposed in the display area DA. For example, at least one of the data driving circuit 120 and the gate driving circuit 130 may be configured not to overlap with the sub-pixel SP or may be configured to partially or completely overlap with the sub-pixel SP.

[0076] When the gate drive circuit 130 opens a specific gate line GL, the data drive circuit 120 can convert the image data Data received from the controller 140 into an analog data voltage and provide the analog data voltage to the plurality of data lines DL.

[0077] The data driving circuit 120 can be connected to one side of the display panel 110 (e.g., the top or bottom side). Depending on the driving method, panel design method, etc., the data driving circuit 120 can be connected to both sides of the display panel 110 (e.g., the top and bottom sides) or to two or more of the four sides of the display panel 110.

[0078] The gate drive circuit 130 can be connected to one side of the display panel 110 (e.g., the left or right side). Depending on the driving method, panel design method, etc., the gate drive circuit 130 can be connected to two opposite sides of the display panel 110 (e.g., the left and right sides) or to two or more of the four sides of the display panel 110.

[0079] Controller 140 may be a timing controller used in conventional display technology, a control device including a timing controller capable of further performing other control functions, a control device different from a timing controller, or circuitry within a control device. Controller 140 may be implemented using various circuits or electronic components, such as integrated circuits (ICs), field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), or processors.

[0080] The controller 140 can be mounted on a printed circuit board or a flexible printed circuit, etc., and can be electrically connected to the data drive circuit 120 and the gate drive circuit 130 through the printed circuit board or flexible printed circuit.

[0081] The controller 140 can send or receive signals to or from the data drive circuit 120 according to one or more predetermined interfaces. Here, for example, the interface may include a low-voltage differential signal transmission (LVDS) interface, an EPI interface, a serial peripheral interface (SPI), etc.

[0082] The controller 140 may include one or more storage media, such as registers.

[0083] The display device 100 according to the embodiment may be a display including a backlight unit, such as a liquid crystal display, and may be a self-emissive display, such as an organic light-emitting diode (OLED) display, a quantum dot display, and a micro light-emitting diode (LED) display.

[0084] When the display device 100 according to the embodiment is an OLED display, each sub-pixel SP may include an OLED that emits light itself as a light-emitting device. When the display device 100 according to the embodiment is a quantum dot display, each sub-pixel SP may include a light-emitting device made of quantum dots, where a quantum dot is a self-emitting semiconductor crystal. When the display device 100 according to the embodiment is a micro-LED display, each sub-pixel SP may include a micro-LED that emits light itself and is made of inorganic materials.

[0085] Figure 2A and Figure 2B It is the equivalent circuit of the sub-pixel SP of the display device 100 according to an embodiment of the present disclosure.

[0086] refer to Figure 2A The plurality of sub-pixels SP disposed on the display panel 110 of the display device 100 according to an embodiment of the present disclosure may each include a light-emitting device ED, a driving transistor DRT, a scanning transistor SCT, and a storage capacitor Cst.

[0087] refer to Figure 2AThe light-emitting device ED may include a pixel electrode PE and a common electrode CE, and may include a light-emitting layer EL disposed between the pixel electrode PE and the common electrode CE.

[0088] The pixel electrode PE of the light-emitting device ED can be an electrode disposed on each sub-pixel SP, and the common electrode CE can be an electrode commonly disposed on all sub-pixels SP. Here, the pixel electrode PE can be an anode electrode, and the common electrode CE can be a cathode electrode. Conversely, the pixel electrode PE can be a cathode electrode, and the common electrode CE can be an anode electrode.

[0089] For example, the light-emitting device (ED) can be an organic light-emitting diode (OLED), a light-emitting diode, or a quantum dot light-emitting device.

[0090] The driving transistor DRT, which is used to drive the light-emitting device ED, may include a first node N1, a second node N2, a third node N3, etc.

[0091] The first node N1 of the driving transistor DRT can be the gate node of the driving transistor DRT and can be electrically connected to the source node or drain node of the scanning transistor SCT. The second node N2 of the driving transistor DRT can be the source node or drain node of the driving transistor DRT and is electrically connected to the pixel electrode PE of the light-emitting device ED. The third node N3 of the driving transistor DRT can be electrically connected to the driving voltage line DVL to provide the driving voltage EVDD.

[0092] The scanning transistor SCT can be controlled by a scanning signal SCAN, which serves as a gate signal, and can be connected between the data line DL and the first node N1 of the driving transistor DRT. In other words, the scanning transistor SCT can be turned on or off according to the scanning signal SCAN provided to the scanning signal line SCL, which serves as a gate line GL, and can control the connection between the first node N1 of the driving transistor DRT and the data line DL.

[0093] The scanning transistor SCT can be turned on by the scanning signal SCAN, which has a turn-on voltage, and the data voltage Vdata provided from the data line DL can be provided to the first node N1 of the driving transistor DRT.

[0094] Here, when the scanning transistor SCT is an n-type transistor, the on-state voltage of the scanning signal SCAN can be a high-level voltage. When the scanning transistor SCT is a p-type transistor, the on-state voltage of the scanning signal SCAN can be a low-level voltage.

[0095] A storage capacitor Cst can be connected between the first node N1 and the second node N2 of the driving transistor DRT. The storage capacitor Cst is charged with a certain amount of charge corresponding to the voltage difference between its terminals and serves to maintain the voltage difference between its terminals for a predetermined frame time. Accordingly, during said predetermined frame time, the corresponding sub-pixel SP can emit light.

[0096] refer to Figure 2B The plurality of sub-pixels SP disposed on the display panel 110 of the display device 100 according to an embodiment of the present disclosure may each include a sensing transistor SENT.

[0097] The sensing transistor SENT can be controlled by a sensing signal SENSE, which serves as a gate signal, and can be connected between the reference voltage line RVL and the second node N2 of the driving transistor DRT. In other words, the sensing transistor SENT can be turned on or off according to the sensing signal SENSE provided to the sensing signal line SENL, which serves as another gate line GL, and can control the connection between the second node N2 of the driving transistor DRT and the reference voltage line RVL.

[0098] The sensing transistor SENT can be turned on by the sensing signal SENSE with a turn-on voltage level, and the reference voltage Vref provided from the reference voltage line RVL can be provided to the second node N2 of the driving transistor DRT.

[0099] Furthermore, the sensing transistor SENT can be turned on by the sensing signal SENSE with a conduction level voltage, and the voltage of the second node N2 of the driving transistor DRT can be provided to the reference voltage line RVL.

[0100] Here, when the sensing transistor SENT is an n-type transistor, the on-state voltage of the sensing signal SENSE can be a high-level voltage. Here, when the sensing transistor SENT is a p-type transistor, the on-state voltage of the sensing signal SENSE can be a low-level voltage.

[0101] The sensing transistor SENT can be used to supply the voltage of the second node N2 of the driving transistor DRT to the reference voltage line RVL when driving the sensor to sense the feature value of the sub-pixel SP. In this case, the voltage supplied to the reference voltage line RVL can be a voltage used to calculate the feature value of the sub-pixel SP or a voltage reflecting the feature value of the sub-pixel SP.

[0102] In this disclosure, the feature values ​​of the sub-pixel SP can be feature values ​​of the driving transistor DRT or the light-emitting device ED. The feature values ​​of the driving transistor DRT can include the threshold voltage and mobility of the driving transistor DRT. The feature values ​​of the light-emitting device ED can include the threshold voltage of the light-emitting device ED.

[0103] Each of the driving transistor DRT, the scanning transistor SCT, and the sensing transistor SENT can be an n-type transistor or a p-type transistor. In this disclosure, for ease of description, by way of example, each of the driving transistor DRT, the scanning transistor SCT, and the sensing transistor SENT can be an n-type transistor.

[0104] The storage capacitor Cst may not be a parasitic capacitor (e.g., Cgs or Cgd) that is an internal capacitor between the gate node and the source node (or drain node) of the driving transistor DRT, or an external capacitor that is intentionally designed outside the driving transistor DRT.

[0105] The scan signal line SCL and the sensing signal line SENL can be different gate lines GL. In this case, the scan signal SCAN and the sensing signal SENSE can be separate gate signals, and the on-off timing of the scan transistor SCT and the sensing transistor SENT in a sub-pixel SP can be independent. That is, the on-off timing of the scan transistor SCT and the sensing transistor SENT in a sub-pixel SP can be the same or different.

[0106] Alternatively, the scan signal line SCL and the sensing signal line SENL can be the same gate line GL. That is, the gate node of the scan transistor SCT and the gate node of the sensing transistor SENT in a sub-pixel SP can be connected to a single gate line GL. In this case, the scan signal SCAN and the sensing signal SENSE can be the same gate signal, and the turn-on / off timing of the scan transistor SCT and the turn-on / off timing of the sensing transistor SENT in a sub-pixel SP can be the same.

[0107] Figure 2A and Figure 2B The structure of the subpixel shown is merely an example and can be modified in various ways by further including one or more transistors or by further including one or more capacitors.

[0108] In addition, Figure 2A and Figure 2B In this paper, the sub-pixel structure is described assuming that the display device 100 is a self-emissive display device. However, when the display device 100 is a liquid crystal display device, each sub-pixel SP may include a transistor, a pixel electrode, etc.

[0109] Figure 3 A system of a display device 100 according to an embodiment of the present disclosure is shown.

[0110] refer to Figure 3The display panel 110 may include a display area DA for displaying images and a non-display area NDA for not displaying images.

[0111] refer to Figure 3 When the data driving circuit 120 includes one or more source driver integrated circuits SDIC and is implemented by a chip-on-film (COF) method, each source driver integrated circuit SDIC can be mounted on a circuit film SF connected to the non-display area NDA of the display panel 110.

[0112] refer to Figure 3 The gate driving circuit 130 can be implemented as a gate in-panel (GIP) type. In this case, the gate driving circuit 130 can be formed in the non-display area NDA of the display panel 110. Figure 3 In contrast, the gate drive circuit 130 can also be implemented as a chip-on-film (COF) type.

[0113] The display device 100 may include at least one source printed circuit board (SPCB) and a control printed circuit board (CPCB) for mounting control components and various electrical components for circuit connections between one or more source driver integrated circuits (SDICs) and other devices.

[0114] The SF film on which the source driver integrated circuit (SDIC) is mounted can be connected to the source integrated circuit board (SPCB). That is, the SF film on which the source driver integrated circuit (SDIC) is mounted can be electrically connected on one side to the display panel 110 and on the other side to the source integrated circuit board (SPCB).

[0115] The controller 140, power management integrated circuit (PMIC) 310, and other components can be mounted on a control printed circuit board (CPCB). The controller 140 can perform overall control functions related to driving the display panel 110, and can control the operation of the data drive circuit 120 and the gate drive circuit 130. The power management integrated circuit 310 can provide various voltages or currents to the data drive circuit 120, the gate drive circuit 130, etc., or can control the various voltages or currents to be provided.

[0116] The source printed circuit board (SPCB) and the control printed circuit board (CPCB) can be connected in a circuit manner via at least one connecting cable (CBL). Here, the connecting cable (CBL) can be, for example, a flexible printed circuit (FPC), a flexible flat cable (FFC), etc.

[0117] The source printed circuit board (SPCB) and the control printed circuit board (CPCB) can be integrated into a single printed circuit board.

[0118] The display device 100 according to embodiments of the present disclosure may further include only a level shifter 300 for adjusting the voltage level. For example, the level shifter 300 may be disposed on a control printed circuit board (CPCB) or a source printed circuit board (SPCB).

[0119] Specifically, in the display device 100 according to an embodiment of the present disclosure, the level shifter 300 can provide signals required for gate driving to the gate driving circuit 130. For example, the level shifter 300 can provide multiple clock signals to the gate driving circuit 130. Accordingly, the gate driving circuit 130 can output multiple gate signals to the multiple gate lines GL based on the multiple clock signals input from the level shifter 300. Here, the multiple gate lines GL can deliver multiple gate signals to the sub-pixels SP disposed in the display area DA of the substrate SUB.

[0120] Figure 4 A compensation circuit for a display device 100 according to an embodiment of the present disclosure is shown.

[0121] refer to Figure 4 The compensation circuit is a circuit that can sense and compensate for the characteristic values ​​of circuit elements in the sub-pixel SP.

[0122] The compensation circuit can be connected to the sub-pixel SP and can include a power switch SPRE, a sampling switch SAM, an analog-to-digital converter ADC, a compensator 400, etc.

[0123] The power switch SPRE controls the connection between the reference voltage line RVL and the reference voltage supply node Nref. The reference voltage Vref output from the power supply unit is provided to the reference voltage supply node Nref, and the reference voltage Vref provided to the reference voltage supply node Nref can be applied to the reference voltage line RVL through the power switch SPRE.

[0124] The sampling switch (SAM) controls the connection between the analog-to-digital converter (ADC) and the reference voltage line RVL. When the ADC is connected to the reference voltage line RVL via the sampling switch (SAM), the ADC can convert the voltage (analog voltage) of the connected reference voltage line RVL into a sensed value corresponding to a digital value.

[0125] A line capacitor Crvl can be formed between the reference voltage line RVL and ground GND. The voltage of the reference voltage line RVL corresponds to the charge of the line capacitor Crvl.

[0126] The analog-to-digital converter (ADC) can provide sensing data, including the sensed values, to the compensator 400.

[0127] The compensator 400 can detect the feature value of the light-emitting device ED or driving transistor DRT contained in the corresponding sub-pixel SP based on the sensing data, and can calculate the compensation value and store the calculated compensation value in the memory 410.

[0128] For example, compensation values ​​used to reduce eigenvalue deviations between light-emitting devices (EDs) or between driving transistors (DRTs) may include gain values ​​for offset and data variation.

[0129] The display controller 140 can change the image data by using the compensation value stored in the memory 410, and can provide the changed image data to the data drive circuit 120.

[0130] The data drive circuit 120 can use a digital-to-analog converter (DAC) to convert the altered image data into a data voltage Vdata corresponding to the analog voltage, and output the converted data voltage Vdata. Accordingly, compensation can be achieved.

[0131] refer to Figure 4 The analog-to-digital converter (ADC), power switch SPRE, and sampling switch SAM can be included in the source driver integrated circuit (SDIC) within the data drive circuit 120. The compensator 400 can be included in the display controller 140.

[0132] As described above, the display device 100 according to embodiments of the present disclosure can perform a compensation process to reduce the eigenvalue deviation between driving transistors (DRTs). Furthermore, in order to perform this compensation process, the display device 100 can perform sensing-driving to detect the eigenvalue deviation between driving transistors (DRTs).

[0133] The display device 100 according to embodiments of the present disclosure can perform sensing-driving in two modes (fast mode and slow mode). Reference will be made below. Figure 5A and Figure 5B Describe the sensing-driving in two modes (fast mode and slow mode).

[0134] Figure 5A This is an illustration of a first sensing mode (S mode) of a display device 100 according to an embodiment of the present disclosure. Figure 5B This is an illustration of a second sensing mode (F mode) of a display device 100 according to an embodiment of the present disclosure.

[0135] refer to Figure 5AThe first sensing mode (S-mode) is a sensing-drive mode used to slowly sense a feature value (e.g., threshold voltage) among the feature values ​​(e.g., threshold voltage, mobility, etc.) of the drive transistor DRT, which requires a relatively long time. The first sensing mode (S-mode) can also be referred to as slow mode or threshold voltage sensing mode.

[0136] refer to Figure 5B The second sensing mode (F mode) is a sensing-drive mode used to quickly sense a feature value (e.g., mobility) among the feature values ​​(e.g., threshold voltage, mobility, etc.) of the driving transistor DRT, which requires a relatively short time. The second sensing mode (F mode) can also be referred to as fast mode or mobility sensing mode.

[0137] refer to Figure 5A and Figure 5B The sensing-drive period of the first sensing mode (S mode) and the sensing-drive period of the second sensing mode (F mode) may include an initialization period Tinit, a tracking period Ttrack, and a sampling period Tsam. Each of the first sensing mode (S mode) and the second sensing mode (F mode) will be described below.

[0138] First, refer to Figure 5A The sensing-driving period of the first sensing mode (S mode) of the display device 100 is described.

[0139] refer to Figure 5A The initialization period Tinit of the sensing-driving period in the first sensing mode (S mode) is the period for initializing the first node N1 and the second node N2 of the driving transistor DRT.

[0140] During the initialization period Tinit, the voltage V1 of the first node N1 of the driving transistor DRT can be initialized to the sense-drive data voltage Vdata_SEN, and the voltage V2 of the second node N2 of the driving transistor DRT can be initialized to the sense-drive reference voltage Vref.

[0141] During the initialization period Tinit, the scan transistor SCT and the sensing transistor SENT can be turned on, and the power switch SPRE can be turned on.

[0142] refer to Figure 5A The tracking period Ttrack of the sensing-driving period in the first sensing mode (S mode) is the period during which the voltage V2 of the second node N2 of the driving transistor DRT, which reflects the threshold voltage Vth or the change of the threshold voltage Vth, is tracked.

[0143] During the tracking period Ttrack, the power switch SPRE can be turned off, or the sensing transistor SENT can be turned off.

[0144] Accordingly, during the tracking period Ttrack, the first node N1 of the driving transistor DRT is in a constant voltage state with a sense-drive data voltage Vdata_SEN, and the second node N2 of the driving transistor DRT is in an electrically floating state. Therefore, the voltage V2 of the second node N2 of the driving transistor DRT can change during the tracking period Ttrack.

[0145] During the tracking period Ttrack, the voltage V2 of the second node N2 of the driving transistor DRT can be increased until the voltage V2 of the second node N2 of the driving transistor DRT reflects the threshold voltage Vth of the driving transistor (DRT).

[0146] During the initialization period Tinit, the voltage difference between the first node N1 and the second node N2 of the initialized driving transistor DRT can be greater than or equal to the threshold voltage Vth of the driving transistor DRT. Accordingly, at the start of the tracking period Ttrack, the driving transistor DRT is turned on to conduct current. Accordingly, at the start of the tracking period Ttrack, the voltage V2 of the second node N2 of the driving transistor DRT can increase.

[0147] During the tracking period Ttrack, the voltage V2 of the second node N2 of the driving transistor DRT does not continuously increase.

[0148] The voltage increase amplitude of the second node N2 of the driving transistor DRT decreases as it approaches the second half of the tracking period Ttrack. Eventually, the voltage V2 of the second node N2 of the driving transistor DRT can saturate.

[0149] The saturation voltage V2 of the second node N2 of the driving transistor DRT can correspond to the difference Vdata_SEN-Vth between the data voltage Vdata_SEN and the threshold voltage Vth, or the difference between the data voltage Vdata_SEN and the threshold voltage deviation ΔVth. Here, the threshold voltage Vth can be a negative threshold voltage Vth or a positive threshold voltage Vth.

[0150] When the voltage V2 of the second node N2 of the driving transistor DRT is saturated, the sampling period Tsam can begin.

[0151] refer to Figure 5AThe sampling period Tsam of the sensing-driving period in the first sensing mode (S mode) is the period during which the voltage Vdata_SEN-Vth or Vdata_SEN-ΔVth, which reflects the threshold voltage Vth or the change of threshold voltage Vth, is measured, reflecting the threshold voltage Vth of the driving transistor DRT.

[0152] In the first sensing mode (S mode), the sampling period Tsam of the sensing-driving phase is the period during which the analog-to-digital converter (ADC) senses the voltage of the reference voltage line RVL. Here, the voltage of the reference voltage line RVL can correspond to the voltage of the second node N2 of the driving transistor DRT, and can also correspond to the charging voltage of the line capacitor Crvl formed in the reference voltage line RVL.

[0153] During the sampling period Tsam, the voltage Vsen sensed by the analog-to-digital converter (ADC) can be either the voltage Vdata_SEN-Vth (which is the data voltage Vdata_SEN minus the threshold voltage Vth) or the voltage Vdata_SEN-ΔVth (which is the data voltage Vdata_SEN minus the threshold voltage change ΔVth). Here, Vth can be a positive or negative threshold voltage.

[0154] refer to Figure 5A During the tracking period Ttrack of the sensing-driving period in the first sensing mode (S mode), the saturation time Tsat required to increase and saturate the voltage V2 of the second node N2 of the driving transistor DRT can be the length of the tracking period Ttrack of the sensing-driving period in the first sensing mode (S mode), and can be the time taken for the change of the threshold voltage Vth of the driving transistor DRT or the threshold voltage Vth to be reflected in the voltage V2 (=Vdata_SEN-Vth) of the second node N2 of the driving transistor DRT.

[0155] This saturation time Tsat can occupy a large portion of the total sensing-driving period in the first sensing mode (S mode). In the first sensing mode (S mode), it may take a significantly long time (saturation time Tsat) for the voltage V2 of the second node N2 of the driving transistor DRT to increase and saturate.

[0156] As mentioned above, the sensing-driving method used to sense the threshold voltage of the driving transistor DRT is called slow mode (first sensing mode (S mode)) because a long saturation time Tsat is required for the voltage state of the second node N2 of the driving transistor DRT to indicate the threshold voltage of the driving transistor DRT.

[0157] Reference Figure 5B The sensing-driving period of the second sensing mode (F mode) of the display device 100 is described.

[0158] refer to Figure 5B The initialization period Tinit of the sensing-driving period in the second sensing mode (F mode) is the period for initializing the first node N1 and the second node N2 of the driving transistor DRT.

[0159] During the initialization period Tinit, the scan transistor SCT and the sensing transistor SENT can be turned on, and the power switch SPRE can be turned on.

[0160] During the initialization period Tinit, the voltage V1 of the first node N1 of the driving transistor DRT can be initialized to the sense-drive data voltage Vdata_SEN, and the voltage V2 of the second node N2 of the driving transistor DRT can be initialized to the sense-drive reference voltage Vref.

[0161] refer to Figure 5B The tracking period Ttrack of the sensing-driving period in the second sensing mode (F mode) is the period during which the voltage V2 of the second node N2 of the driving transistor DRT is changed within a preset tracking time Δt until the voltage V2 of the second node N2 of the driving transistor DRT reaches a voltage that reflects the mobility or mobility change of the driving transistor DRT.

[0162] During the tracking period Ttrack, the preset tracking time Δt can be set to a short time. Therefore, during the short tracking time Δt, the voltage V2 of the second node N2 of the driving transistor DRT is difficult to reflect the threshold voltage Vth. However, during this short tracking time Δt, the voltage V2 of the second node N2 of the driving transistor DRT can change sufficiently to detect the mobility of the driving transistor DRT.

[0163] Accordingly, the second sensing mode (F mode) is a sensing-driving method for sensing the mobility of the driving transistor DRT.

[0164] During the tracking period Ttrack, the second node N2 of the driving transistor DRT can be electrically floated because the power switch SPRE is turned off or the sensing transistor SENT is turned off.

[0165] During the tracking period Ttrack, the scan transistor SCT can be turned off by the scan signal SCAN with a cutoff level voltage, and the first node N1 of the driving transistor DRT can be floating.

[0166] During the initialization period Tinit, the voltage difference between the first node N1 and the second node N2 of the initialized driving transistor DRT can be greater than or equal to the threshold voltage Vth of the driving transistor DRT. Accordingly, at the start of the tracking period Ttrack, the driving transistor DRT is turned on to conduct current.

[0167] Here, when the first node N1 and the second node N2 of the driving transistor DRT are the gate node and the source node, respectively, the voltage difference between the first node N1 and the second node N2 of the driving transistor DRT is Vgs.

[0168] Therefore, during the tracking period Ttrack, the voltage V2 of the second node N2 of the driving transistor DRT can be increased. In this case, the voltage V1 of the first node N1 of the driving transistor DRT can also be increased.

[0169] During the tracking period Ttrack, the rate of increase of the voltage V2 at the second node N2 of the driving transistor DRT varies depending on the current capability (i.e., mobility) of the driving transistor DRT. As the current capability (mobility) of the driving transistor DRT increases, the voltage V2 at the second node N2 of the driving transistor DRT can increase more rapidly.

[0170] After a preset tracking time Δt has elapsed during the tracking period Ttrack, that is, after the voltage V2 of the second node N2 of the driving transistor DRT has increased during the preset tracking time Δt, the sampling period Tsam can begin.

[0171] During the tracking period Ttrack, the rate of increase of the voltage V2 at the second node N2 of the driving transistor DRT corresponds to the voltage change ΔV of the second node N2 of the driving transistor DRT during the preset tracking time Δt. Here, the voltage change ΔV of the second node N2 of the driving transistor DRT can correspond to the voltage change of the reference voltage line RVL.

[0172] refer to Figure 5B When the preset tracking time Δt has elapsed during the tracking period Ttrack, the sampling period Tsam can begin. During the sampling period Tsam, the sampling switch SAM can be turned on, thus electrically connecting the reference voltage line RVL and the analog-to-digital converter ADC.

[0173] An analog-to-digital converter (ADC) can sense the voltage of a reference voltage line RVL. The voltage Vsen sensed by the ADC can be the voltage Vref + ΔV, which increases from the reference voltage Vref by the amount of voltage change ΔV during a certain tracking time Δt.

[0174] The voltage Vsen sensed by the analog-to-digital converter (ADC) can be the voltage of the reference voltage line RVL, and can also be the voltage of the second node N2 of the reference voltage line RVL, which is electrically connected to the sensing transistor SENT.

[0175] refer to Figure 5B During the sampling period Tsam of the sensing-drive phase in the second sensing mode (F mode), the voltage Vsen sensed by the analog-to-digital converter (ADC) can vary depending on the mobility of the driving transistor DRT. The sensed voltage Vsen increases as the driving transistor DRT has a higher mobility. The sensed voltage Vsen decreases as the driving transistor DRT has a lower mobility.

[0176] As mentioned above, the sensing-driving method used to sense the mobility of the driving transistor DRT is called fast mode (second sensing mode (F mode)) because the voltage of the second node N2 of the driving transistor DRT only needs to be changed within a short time Δt.

[0177] refer to Figure 5A According to an embodiment of the present disclosure, the display device 100 can detect the threshold voltage Vth or the change of threshold voltage Vth of the driving transistor DRT in the corresponding sub-pixel SP based on the voltage Vsen sensed by the first sensing mode (S mode), calculate a threshold voltage compensation value for reducing or eliminating the threshold voltage change between driving transistors DRT, and store the calculated threshold voltage compensation value in the memory 410.

[0178] refer to Figure 5B According to an embodiment of the present disclosure, the display device 100 can detect the mobility or mobility change of the driving transistor DRT in the corresponding sub-pixel SP based on the voltage Vsen sensed by the second sensing mode (F mode), calculate a mobility compensation value for reducing or eliminating the mobility change between driving transistors DRT, and store the calculated mobility compensation value in the memory 410.

[0179] When providing a data voltage Vdata for display driving to the corresponding sub-pixel SP, the display device 100 can provide a data voltage Vdata that is changed according to the threshold voltage compensation value and the mobility compensation value.

[0180] As mentioned above, threshold voltage sensing can be performed in the first sensing mode (S mode) because it requires a long sensing time, and mobility sensing can be performed in the second sensing mode (F mode) because it has a short sensing time sufficient for mobility sensing.

[0181] Figure 6This is an illustration showing various sensing timings of a display device 100 according to an embodiment of the present disclosure.

[0182] refer to Figure 6 When a power-on signal is generated, the display device 100 according to an embodiment of the present disclosure can sense the characteristic value of the driving transistor DRT disposed in each sub-pixel SP in the display panel 110. This sensing process is referred to as the power-on sensing process.

[0183] refer to Figure 6 When a power-off signal is generated, the display device 100 according to an embodiment of the present disclosure can sense the characteristic value of the driving transistor DRT disposed in each sub-pixel SP in the display panel 110 before the power-off sequence (e.g., power-off). This sensing process is referred to as the power-off sensing process.

[0184] refer to Figure 6 From the generation of the power-on signal to the generation of the power-off signal, the display device 100 according to an embodiment of the present disclosure can sense the characteristic value of the driving transistor DRT in each sub-pixel SP while the display is being driven. This sensing process is referred to as a real-time sensing process.

[0185] A real-time sensing process can be performed once during each blank time between the effective time (ACT) of the vertical synchronization signal Vsync.

[0186] Since mobility sensing of the driving transistor DRT only requires a short time, mobility sensing can be performed in the second sensing mode (F mode) of the sensing-driving method.

[0187] Since mobility sensing, which can be performed in the second sensing mode (F mode) as a fast mode, only requires a short time, mobility sensing can be performed in one of the sensing processes: the sensing process on, the sensing process off, and the real-time sensing process.

[0188] For example, mobility sensing, which can be performed in the second sensing mode (F mode) as a fast mode, can be performed as a real-time sensing process that can reflect changes in mobility in real time while the display is being driven. That is, mobility sensing can be performed during each idle period while the display is being driven.

[0189] In contrast, threshold voltage sensing of the driving transistor DRT requires a long saturation time Vsat. Therefore, threshold voltage sensing can be performed in the first sensing mode (S mode) of the sensing-driving method.

[0190] Threshold voltage sensing should be performed at a time that does not interfere with the user's viewing. Therefore, threshold voltage sensing of the driving transistor DRT can be performed while the display is not driven (i.e., when the user does not intend to view the display) after a power-off signal is generated based on user input, etc. In other words, threshold voltage sensing can be performed as a shutdown sensing process.

[0191] Figure 7 This is a schematic illustration of the gate driving circuit 130 of a display device 100 according to an embodiment of the present disclosure.

[0192] refer to Figure 7 According to an embodiment of the present disclosure, the gate drive circuit 130 may include a plurality of gate output circuits G-BUF for outputting a plurality of gate signals Gout and a control circuit 700 for controlling the plurality of gate output circuits G-BUF. Here, each of the plurality of gate signals Gout may be a scan signal SCAN or a sensing signal SENSE.

[0193] Each of the plurality of gate output circuits G-BUF can receive a clock signal CLK and a low-level voltage VGL and output a gate signal Gout to the gate output node Nout.

[0194] The gate output circuit G-BUF may include a pull-up transistor Tu (to which the clock signal CLK is input) and a pull-down transistor Td (to which the low-level voltage is input).

[0195] The gate output circuit G-BUF can output the gate signal Gout to the gate output node Nout, to which the pull-up transistor Tu and pull-down transistor Td are connected.

[0196] The pull-up transistor Tu can be connected between the clock signal input node Nclk and the gate output node Nout, and can switch the connection between the clock signal input node Nclk and the gate output node Nout.

[0197] The pull-down transistor Td can be connected between the low-level voltage node Nvss and the gate output node Nout, and can be configured to switch the connection between the low-level voltage node Nvss and the gate output node Nout.

[0198] In a pull-up transistor Tu, a capacitor C can be electrically connected between the gate output node Nout and the Q node, which serves as the gate node. The capacitor C functions to boost the voltage of the Q node based on changes in the voltage of the gate output node Nout.

[0199] The control circuit 700 can control the voltage of the Q node, which is electrically connected to the gate node of the pull-up transistor Tu, and the voltage of the QB node, which is electrically connected to the gate node of the pull-down transistor Td. Here, through this transistor, the QB node can receive both DC voltage and AC signals.

[0200] The control circuit 700 may include a plurality of transistors to control the voltage of each of the Q nodes and the QB nodes. For example, the control circuit 700 may include one or more transistors for charging the Q nodes, one or more transistors for discharging the Q nodes, one or more transistors for charging the QB nodes, and one or more transistors for discharging the QB nodes.

[0201] In order to control the voltage of each of the Q nodes and QB nodes, the control circuit 700 can receive start signals, reset signals, etc., and can further receive carry signals according to the gate driving method.

[0202] Figure 8 A gate drive circuit 130 included in the display device 100 when the display device 100 has a sensing function according to an embodiment of the present disclosure is shown, and Figure 9 It shows Figure 8 The voltage waveforms at the main nodes (Q node, QB node, and T4 gate) in the gate drive circuit 130. However, Figure 8 The gate drive circuit 130 shown is a partial stage of the entire gate drive circuit 130.

[0203] refer to Figure 8 According to embodiments of the present disclosure, the gate drive circuit 130 may include a first gate output buffer circuit GBUF1 and a control circuit 700.

[0204] refer to Figure 8 The first gate output buffer circuit GBUF1 may include a first pull-up transistor Tu1 and a first pull-down transistor Td1.

[0205] The control circuit 700 can control the voltage of the Q node electrically connected to the gate node of the first pull-up transistor Tu1 and control the voltage of the QB node electrically connected to the gate node of the first pull-down transistor Td1.

[0206] The first pull-up transistor Tu1 can be connected between the first clock signal input node Nclk1 and the first gate output node Nout1. The first pull-down transistor Td1 can be connected between the first gate output node Nout1 and the first low-level voltage node Nvss1.

[0207] Here, the first clock signal SCCLK(n) can be input to the first clock signal input node Nclk1. The first level voltage GVSS0 can be applied to the first low level voltage node Nvss1.

[0208] The first gate output buffer circuit GBUF1 can output the first gate signal SCOUT(n) to the first gate line GL through the first gate output node Nout1.

[0209] Capacitor C1 can be connected between the gate node of the first gate output node Nout1 and the gate node of the first pull-up transistor Tu1.

[0210] refer to Figure 8 When the display device 100 according to an embodiment of the present disclosure has a sensing function (e.g., mobility sensing function), the control circuit 700 included in the gate drive circuit 130 according to an embodiment of the present disclosure may include a line selection circuit LSC, Q charging circuits QCC1 and QCC2 for charging Q nodes, Q discharging circuits QDC1 and QDC2 for discharging Q nodes, holding circuits QHM and QLM for stably maintaining the voltage state of Q nodes, QB charging circuit QBCC for charging QB nodes, QB discharging circuits QBDC1 and QBDC2 for discharging QB nodes, QB control circuit QBC, etc.

[0211] refer to Figure 8 The line selection circuit (LSC) may include two main selection transistors Ta and Tb, an auxiliary selection transistor Tc, and a selection capacitor Cls. The LSC can be a circuit used to select the corresponding sub-pixel line as the line for performing sensing-driving.

[0212] The line select signal LSP can be commonly applied to the gate nodes of the two main select transistors Ta and Tb. The line select signal LSP, as a pulse signal, can be commonly applied to the gate nodes of the two main select transistors Ta and Tb in the middle of the frame.

[0213] The source node (or drain node) of the main selection transistor Ta, which is one of the two main selection transistors Ta and Tb, can be electrically connected to the drain node (or source node) of the other main selection transistor Tb, which is the other of the two main selection transistors Ta and Tb.

[0214] The previous carry signal C(n-2) can be applied to the drain node (or source node) of the main selection transistor Ta, which is one of the two main selection transistors Ta and Tb.

[0215] An auxiliary selection transistor Tc can be connected between the connection node of the two main selection transistors Ta and Tb and the second drive voltage node Nvdd. Here, the second drive voltage GVDD can be applied to the second drive voltage node Nvdd.

[0216] The source node (or drain node) of the main selection transistor Tb, which is one of the two main selection transistors Ta and Tb, can be electrically connected to the gate node of the auxiliary selection transistor Tc.

[0217] A selection capacitor Cls can be connected between the gate node and the drain node (or source node) of the auxiliary selection transistor Tc.

[0218] refer to Figure 8 The Q charging circuits QCC1 and QCC2 used to charge the Q nodes may include a first Q charging circuit QCC1 and a second Q charging circuit QCC2.

[0219] refer to Figure 8 The first Q-charging circuit QCC1 can be connected between the second driving voltage node Nvdd and the Q-node. The first Q-charging circuit QCC1 can be a charging circuit for the Q-node that operates during normal display driving for image display during the effective time period. The first Q-charging circuit QCC1 can be configured to provide the second driving voltage GVDD to the Q-node during the effective time period.

[0220] refer to Figure 8 The second Q-charging circuit QCC2 can be connected between the second drive voltage node Nvdd and the Q-node. The second Q-charging circuit QCC2 can be a charging circuit for the Q-node that operates during sensing-driving in the idle period. The second Q-charging circuit QCC2 can be configured to provide the second drive voltage GVDD to the Q-node during the idle period.

[0221] refer to Figure 8 The first Q-charging circuit QCC1 may include two first Q-charging transistors T1 and T1a connected between the second driving voltage node NVdd and the Q-node. Here, the second driving voltage GVDD can be applied to the second driving voltage node Nvdd.

[0222] The gate nodes of the two first Q charging transistors T1 and T1a can be electrically connected to each other. The previous carry signal C(n-2) can be input to the gate nodes of the two first Q charging transistors T1 and T1a.

[0223] The source node (or drain node) of the first Q-charging transistor T1, which is one of the two first Q-charging transistors T1 and T1a, can be electrically connected to the drain node (or source node) of the other first Q-charging transistor T1a. The drain node (or source node) of the first Q-charging transistor T1 can be electrically connected to the second drive voltage node Nvdd. The source node (or drain node) of the first Q-charging transistor T1a can be electrically connected to the Q node.

[0224] The first Q-charging circuit QCC1 may further include two first additional charging transistors T11 and T12 connected between the third drive voltage node Nvdd2 and the connection node of the two first Q-charging transistors T1 and T1a.

[0225] The gate nodes of the two first additional charging transistors T11 and T12 can be commonly connected to the third driving voltage node Nvdd2. Here, the third driving voltage GVDD2 can be applied to the third driving voltage node Nvdd2.

[0226] The source node (or drain node) of the first additional charging transistor T11, which is one of the two first additional charging transistors T11 and T12, can be electrically connected to the drain node (or source node) of the first additional charging transistor T12.

[0227] The drain node (or source node) of the first additional charging transistor T12 can be electrically connected to the connection node of the two first Q charging transistors T1 and T1a.

[0228] The first additional charging transistor T11 can be in a diode-connected state where the gate node and drain node are electrically connected.

[0229] refer to Figure 8 The second Q charging circuit QCC2 may include two second Q charging transistors T1b and T1c connected between the second driving voltage node NVdd and the Q node.

[0230] In the second Q charging circuit QCC2, the source node (or drain node) of the second Q charging transistor T1b, which is one of the two second Q charging transistors T1b and T1c, can be electrically connected to the drain node (or source node) of the second Q charging transistor T1c, which is the other of the two second Q charging transistors T1b and T1c.

[0231] The drain node (or source node) of the second Q-charging transistor T1b can be electrically connected to the second drive voltage node Nvdd. The selection capacitor Cls of the line select circuit LSC can be connected between the gate node and the drain node (or source node) of the second Q-charging transistor T1b.

[0232] A reset signal RESET can be applied to the gate node of the second Q-charge transistor T1c. The source node (or drain node) of the second Q-charge transistor T1c can be electrically connected to this Q node.

[0233] refer to Figure 8 The Q discharge circuits QDC1 and QDC2 used to discharge the Q node may include a first Q discharge circuit QDC1 and a second Q discharge circuit QDC2.

[0234] refer to Figure 8 The first Q-discharge circuit QDC1 can be connected between the second low-level voltage node Nvss2 and the Q-node. The first Q-discharge circuit QDC1 can be a discharge circuit for the Q-node that operates during normal display driving for image display during the effective time period. The first Q-discharge circuit QDC1 can be configured to provide the second low-level voltage GVSS2 to the Q-node during the effective time period.

[0235] refer to Figure 8 The second Q-discharge circuit QDC2 can be connected between the second low-level voltage node Nvss2 and the Q-node. The second Q-discharge circuit QDC2 can be a discharge circuit for the Q-node that operates during sensing-driving in the idle period. The second Q-discharge circuit QDC2 can be configured to provide a second low-level voltage GVSS2 to the Q-node during the idle period.

[0236] refer to Figure 8 The first Q discharge circuit QDC1 may include two first Q discharge transistors T3n and T3na connected between the second low-level voltage node Nvss2 and the Q node.

[0237] The source node (or drain node) of the first Q discharge transistor T3n, which is one of the two first Q discharge transistors T3n and T3na, can be electrically connected to the drain node (or source node) of the first Q discharge transistor T3na, which is the other of the two first Q discharge transistors T3n and T3na.

[0238] The next carry signal C(n+2) can be commonly applied to the gate nodes of the two first Q discharge transistors T3n and T3na.

[0239] The drain node (or source node) of the first Q-discharge transistor T3n, which is one of the two first Q-discharge transistors T3n and T3na, can be electrically connected to the Q-node, and the source node (or drain node) of the first Q-discharge transistor T3na, which is the other of the two first Q-discharge transistors T3n and T3na, can be electrically connected to the second low-level voltage node Nvss2. Here, the second low-level voltage GVSS2 can be applied to the second low-level voltage node Nvss2.

[0240] refer to Figure 8 The second Q discharge circuit QDC2 may include two second Q discharge transistors T3nb and T3nc connected between the second low-level voltage node Nvss2 and the Q node.

[0241] The source node (or drain node) of the second Q discharge transistor T3nb, which is one of the two second Q discharge transistors T3nb and T3nc, can be electrically connected to the drain node (or source node) of the second Q discharge transistor T3nc, which is the other of the two second Q discharge transistors T3nb and T3nc.

[0242] The start signal VST can be applied to the gate nodes of the two second Q discharge transistors T3nb and T3nc.

[0243] The drain node (or source node) of the second Q discharge transistor T3nb, which is one of the two second Q discharge transistors T3nb and T3nc, can be electrically connected to the Q node, and the source node (or drain node) of the second Q discharge transistor T3nc, which is the other of the two second Q discharge transistors T3nb and T3nc, can be electrically connected to the second low-level voltage node Nvss2.

[0244] The connection nodes of the two second Q discharge transistors T3nb and T3nc can be electrically connected to the connection nodes of the two first Q discharge transistors T3n and T3na.

[0245] refer to Figure 8 The holding circuits QHM and QLM, which are circuits used to stably maintain the voltage state of the Q node, may include a first holding circuit QHM and a second holding circuit QLM.

[0246] refer to Figure 8 The first holding circuit QHM is used to stably maintain the voltage of the Q node at a high level, and the second holding circuit QLM is used to stably maintain the voltage of the Q node at a low level.

[0247] The holding circuit QLM may include two second holding transistors T3 and T3a connected between the second low-level voltage node Nvss2 and the Q node.

[0248] The gate nodes of the two second holding transistors T3 and T3a can be commonly connected to the QB node.

[0249] The source node (or drain node) of the second holding transistor T3, which is one of the two second holding transistors T3 and T3a, can be electrically connected to the drain node (or source node) of the second holding transistor T3a, which is the other of the two second holding transistors T3 and T3a.

[0250] The drain node (or source node) of the second holding transistor T3, which is one of the two second holding transistors T3 and T3a, can be electrically connected to the Q node, and the source node (or drain node) of the second holding transistor T3a, which is the other of the two second holding transistors T3 and T3a, can be electrically connected to the second low-level voltage node Nvss2.

[0251] The connection nodes of the two second holding transistors T3 and T3a can be electrically connected to the connection nodes of the two second Q discharge transistors T3nb and T3nc, as well as the connection nodes of the two first Q discharge transistors T3n and T3na.

[0252] The first holding circuit QHM may include two first holding transistors T3q and T3qa connected between the second drive voltage node Nvdd and the connection node of the two second holding transistors T3 and T3a.

[0253] The gate nodes of the two first holding transistors T3q and T3qa can be commonly connected to the Q node.

[0254] The source node (or drain node) of the first holding transistor T3q, which is one of the two first holding transistors T3q and T3qa, can be electrically connected to the drain node (or source node) of the first holding transistor T3qa, which is the other of the two first holding transistors T3q and T3qa.

[0255] The drain node (or source node) of the first holding transistor T3q, which is one of the two first holding transistors T3q and T3qa, can be electrically connected to the second drive voltage node Nvdd, and the source node (or drain node) of the first holding transistor T3qa, which is the other of the two first holding transistors T3q and T3qa, can be electrically connected to the connection node of the two second holding transistors T3 and T3a.

[0256] refer to Figure 8The QB charging circuit QBCC, used to charge the QB node, can be connected between the first drive voltage node Nvdd1 and the QB node. Here, the first drive voltage GVDD_o can be applied to the first drive voltage node Nvdd1.

[0257] refer to Figure 8 The QB charging circuit QBCC can be configured to provide a first drive voltage GVDD_o to the QB node. The QB charging circuit QBCC may include a QB charging transistor T4 located between the first drive voltage node Nvdd1 and the QB node.

[0258] The gate node of the QB charging transistor T4 can be connected to the QB control circuit QBC. The drain node (or source node) of the QB charging transistor T4 can be electrically connected to the first drive voltage node Nvdd1. The source node (or drain node) of the QB charging transistor T4 can be electrically connected to the QB node.

[0259] The drain node (or source node) of the QB charging transistor T4 can be connected to the QB control circuit QBC.

[0260] refer to Figure 8 The QB discharge circuits QBDC1 and QBDC2 used to discharge the QB node may include a first QB discharge circuit QBDC1 and a second QB discharge circuit QBDC2.

[0261] refer to Figure 8 The first QB discharge circuit QBDC1 can be connected between the second low-level voltage node Nvss2 and the QB node. The first QB discharge circuit QBDC1 can be a discharge circuit for the QB node that operates during normal display driving for image display during the effective time period. The first QB discharge circuit QBDC1 can be configured to provide the second low-level voltage GVSS2 to the QB node during the effective time period.

[0262] refer to Figure 8 The second QB discharge circuit QBDC2 can be connected between the second low-level voltage node Nvss2 and the QB node. The second QB discharge circuit QBDC2 can be a discharge circuit for the QB node that operates during sensing-driving in the idle period. The second QB discharge circuit QBDC2 can be configured to provide a second low-level voltage GVSS2 to the QB node during the idle period.

[0263] The second QB discharge circuit QBDC2 may include two second Q discharge transistors T5a and T5b connected between the second low-level voltage node Nvss2 and the QB node.

[0264] The source node (or drain node) of the second Q discharge transistor T5a, which is one of the two second Q discharge transistors T5a and T5b, can be electrically connected to the drain node (or source node) of the second Q discharge transistor T5b, which is the other of the two second Q discharge transistors T5a and T5b.

[0265] The drain node (or source node) of the second Q discharge transistor T5a, which is one of the two second Q discharge transistors T5a and T5b, can be electrically connected to the QB node, and the source node (or drain node) of the second Q discharge transistor T5b, which is the other of the two second Q discharge transistors T5a and T5b, can be electrically connected to the second low-level voltage node Nvss2.

[0266] A reset signal RESET can be applied to the gate node of the second Q discharge transistor T5a, which is one of the two second Q discharge transistors T5a and T5b, and a discharge control signal M_o can be applied to the gate node of the other second Q discharge transistor T5b, which is the other of the two second Q discharge transistors T5a and T5b.

[0267] refer to Figure 8 The first QB discharge circuit QBDC1 may include two first Q discharge transistors T5 and T5q connected in parallel between the second low-level voltage node Nvss2 and the QB node.

[0268] In the first Q discharge transistor T5, which is one of the two first Q discharge transistors T5 and T5q, the source node (or drain node) can be connected to the second low-level voltage node Nvss2, the drain node (or source node) can be connected to the QB node, and the previous carry signal C(n-2) can be input to the gate node.

[0269] In the first Q discharge transistor T5q, which is the other of the two first Q discharge transistors T5 and T5q, the source node (or drain node) can be connected to the second low-level voltage node Nvss2, the drain node (or source node) can be connected to the QB node, and the gate node can be electrically connected to the Q node.

[0270] refer to Figure 8 The QB control circuit QBC is a circuit used to control the QB charging circuit QBCC for charging the QB node.

[0271] refer to Figure 8 The QB control circuit QBC can control the gate node of the QB charging transistor T4 contained in the QB charging circuit QBCC.

[0272] The QB control circuit QBC may include first control transistors T41 and T41a connected between the gate node of the QB charging transistor T4 and the first drive voltage node Nvdd1, and a second control transistor T4q connected between the gate node of the QB charging transistor T4 and the third low-level voltage node Nvss3. Here, the third low-level voltage GVSS1 may be applied to the third low-level voltage node Nvss3.

[0273] In the QB control circuit QBC, the gate nodes of the first control transistors T41 and T41a can be electrically connected to the first drive voltage node Nvdd1, and the gate node of the second control transistor T4q can be electrically connected to the Q node.

[0274] refer to Figure 8 The gate drive circuit 130 may further include a carry output buffer circuit CBUF, which includes a carry pull-up transistor Tu_CR and a carry pull-down transistor Td_CR.

[0275] The carry pull-up transistor Tu_CR can be connected between the carry clock signal input node Ncrclk and the carry output node Ncrout. The carry pull-down transistor Td_CR can be connected between the carry output node Ncrout and the second low-level voltage node Nvss2.

[0276] The gate node of the carry-up pull-up transistor Tu_CR can be connected to the Q node. The gate node of the carry-down pull-down transistor Td_CR can be connected to the QB node.

[0277] The capacitor Ccr can be connected between the gate node and the source node (or drain node) of the pull-up transistor Tu_CR.

[0278] The carry-out buffer circuit CBUF can output the carry signal C(n) to the previous stage circuit and / or the next stage circuit through the carry-out output node Ncrout.

[0279] refer to Figure 8 The gate drive circuit 130 according to an embodiment of the present disclosure may further include a second gate output buffer circuit GBUF2.

[0280] The second gate output buffer circuit GBUF2 may include a second pull-up transistor Tu2 and a second pull-down transistor Td2.

[0281] The second pull-up transistor Tu2 can be connected between the second clock signal input node Nclk2 and the second gate output node Nout2. The second pull-down transistor Td2 can be connected between the second gate output node Nout2 and the first low-level voltage node Nvss1.

[0282] Here, the second clock signal SCCLK(n+1) can be input to the second clock signal input node Nclk2. The second gate line GL can be electrically connected to the second gate output node Nout2.

[0283] Capacitor C2 can be connected between the gate node of the second gate output node Nout2 and the gate node of the second pull-up transistor Tu2.

[0284] The second gate output buffer circuit GBUF2 can output the second gate signal SCOUT(n+1) to the second gate line GL through the second gate output node Nout2.

[0285] refer to Figure 8 The gate drive circuit 130 according to an embodiment of the present disclosure may further include a third gate output buffer circuit GBUF3.

[0286] The third gate output buffer circuit GBUF3 may include a third pull-up transistor Tu3 and a third pull-down transistor Td3.

[0287] The third pull-up transistor Tu3 can be connected between the third clock signal input node Nclk3 and the third gate output node Nout3. The third pull-down transistor Td3 can be connected between the third gate output node Nout3 and the first low-level voltage node Nvss1.

[0288] Here, the third clock signal SCCLK(n+2) can be input to the third clock signal input node Nclk3. The third gate line GL can be electrically connected to the third gate output node Nout3.

[0289] Capacitor C3 can be connected between the gate node of the third gate output node Nout3 and the gate node of the third pull-up transistor Tu3.

[0290] The third gate output buffer circuit GBUF3 can output the third gate signal SCOUT(n+2) to the third gate line GL through the third gate output node Nout3.

[0291] refer to Figure 8 The gate drive circuit 130 according to an embodiment of the present disclosure may further include a fourth gate output buffer circuit GBUF4.

[0292] The fourth gate output buffer circuit GBUF4 may include a fourth pull-up transistor Tu4 and a fourth pull-down transistor Td4.

[0293] The fourth pull-up transistor Tu4 can be connected between the fourth clock signal input node Nclk4 and the fourth gate output node Nout4. The fourth pull-down transistor Td4 can be connected between the fourth gate output node Nout4 and the first low-level voltage node Nvss1.

[0294] Here, the fourth clock signal SCCLK(n+3) can be input to the fourth clock signal input node Nclk4. The fourth gate line GL can be electrically connected to the fourth gate output node Nout4.

[0295] Capacitor C3 can be connected between the gate node of the fourth gate output node Nout4 and the gate node of the fourth pull-up transistor Tu4.

[0296] The fourth gate output buffer circuit GBUF4 can output the fourth gate signal SCOUT(n+3) to the fourth gate line GL through the fourth gate output node Nout4.

[0297] refer to Figure 9 In the gate drive circuit 130, the voltage level of the Q node is opposite to that of the QB node. When the voltage of the Q node is high, the voltage of the QB node is low. Conversely, when the voltage of the Q node is low, the voltage of the QB node is high.

[0298] refer to Figure 9 The voltage change at the QB node can correspond to the voltage change at the gate node T4 Gate of the QB charging transistor T4 contained in the QB charging circuit QBCC.

[0299] When the voltage at the QB node decreases, the voltage at the gate node T4 of the QB charging transistor T4 can decrease. When the voltage at the QB node increases, the voltage at the gate node T4 of the QB charging transistor T4 can increase.

[0300] When the voltage at the QB node is high, the voltage at the gate node T4 of the QB charging transistor T4 can also be high. When the voltage at the QB node is low, the voltage at the gate node T4 of the QB charging transistor T4 can also be low.

[0301] refer to Figure 9 When the threshold voltage of the second control transistor T4q included in the QB control circuit QBC undergoes a negative shift, the third low-level voltage GVSS1 can be set higher than the second low-level voltage GVSS2, thereby preventing the voltage drop of the QB node caused by the voltage drop of the gate node of the QB charging transistor T4.

[0302] In the segment where the Q node is at a high voltage level and the QB node is at a low voltage level, the second control transistor T4q, which has a gate node connected to the Q node, can be turned on, and the QB charging transistor T4, which is used to charge the QB node, can be turned off.

[0303] Accordingly, in the section where the Q node is in a high-level voltage state and the QB node is in a low-level voltage state, a third low-level voltage GVSS1, which is higher than the second low-level voltage GVSS2, can be applied to the gate node (A) of the QB charging transistor T4 through the second control transistor T4q. In this case, the second low-level voltage GVSS2 can be applied to the QB node, which serves as the source node of the QB charging transistor T4.

[0304] The potential difference Vgs between the gate and source nodes of the QB charging transistor T4 can correspond to the difference between the third low-level voltage GVSS1 and the second low-level voltage GVSS2.

[0305] As mentioned above, to prevent a voltage drop at the QB node caused by a voltage drop at the gate node of the QB charging transistor T4, when the third low-level voltage GVSS1 is set higher than the second low-level voltage GVSS2 (A), the potential difference Vgs between the gate and source nodes of the QB charging transistor T4 can have a positive value. Therefore, the QB charging transistor T4 may not remain completely off. Consequently, an undesirable leakage current may be generated in the QB charging transistor T4.

[0306] In addition, refer to Figure 9 In the section where the QB node is at a high voltage level and the Q node is at a low voltage level, the QB charging transistor T4, which is used to charge the QB node, can be turned on, and the second control transistor T4q, which has a gate node connected to the Q node, can be turned off.

[0307] refer to Figure 9 In the section where the QB node is at a high voltage level and the Q node is at a low voltage level, when ripple occurs in the Q node, the second control transistor T4q may be turned on undesirably by the ripple in the Q node.

[0308] If the second control transistor T4q is undesirably turned on due to the ripple of the Q node, a third low-level voltage GVSS1 can be undesirably applied to the gate node of the QB charging transistor T4. Accordingly, the QB charging transistor T4 may fail to remain on to charge the QB node and may be turned off. In this case, a first drive voltage GVDD_o, as a high-level voltage, can be applied to the source node of the QB charging transistor T4.

[0309] When the third low-level voltage GVSS1 is applied to the gate node of the QB charging transistor T4, the QB charging transistor T4 may be undesirably turned off by the ripple of the Q node, and the voltage of the QB node may not be able to maintain a high-level voltage state and may be reduced.

[0310] refer to Figure 9 The first phenomenon (related to part A) of undesirable leakage current in transistor T4 when QB acts as QB in the section where QB is at a high voltage level and QB is at a low voltage level, and the second phenomenon (related to part B) of the voltage of QB node decreasing due to Q node ripple in the section where QB is at a low voltage level and QB node is at a high voltage level, may reduce gate drive performance, which may lead to image quality degradation.

[0311] Accordingly, embodiments of this disclosure disclose an improved gate drive circuit 130 capable of preventing or reducing the first and second phenomena while being adapted for the sensing function of the display device 100. The improved gate drive circuit 130 according to embodiments of this disclosure will be described below.

[0312] Figure 10 An improved gate drive circuit 130 is shown, which is included in the display device 100 when the display device 100 has a sensing function according to an embodiment of the present invention. Figure 11 and Figure 12 It shows Figure 10 The voltage waveforms at the main nodes (Q node, QB node, and T4 Gate) in the improved gate drive circuit 130. However, in describing... Figure 10 When the gate drive circuit 130 is improved, the connection to the gate will be omitted. Figure 8 The configuration and details of the gate drive circuit 130 are the same as those described above. However, Figure 10 The gate drive circuit 130 shown is a partial stage of the entire gate drive circuit 130.

[0313] refer to Figure 10 The improved gate drive circuit 130 according to embodiments of the present disclosure may include a first gate output buffer circuit GBUF1 and a control circuit 700.

[0314] The first gate output buffer circuit GBUF1 may include a first pull-up transistor Tu1 and a first pull-down transistor Td1.

[0315] The control circuit 700 can control the voltage of the Q node electrically connected to the gate node of the first pull-up transistor Tu1 and control the voltage of the QB node electrically connected to the gate node of the first pull-down transistor Td1.

[0316] The first pull-up transistor Tu1 can be connected between the first clock signal input node Nclk1 and the first gate output node Nout1. The first pull-down transistor Td1 can be connected between the first gate output node Nout1 and the first low-level voltage node Nvss1.

[0317] The first gate output buffer circuit GBUF1 can output the first gate signal SCOUT(n) to the first gate line GL through the first gate output node Nout1.

[0318] refer to Figure 10 When the display device 100 according to an embodiment of the present disclosure has a sensing function (e.g., mobility sensing function), the control circuit 700 included in the improved gate drive circuit 130 according to an embodiment of the present disclosure may include a line selection circuit LSC, Q charging circuits QCC1 and QCC2 for charging Q nodes, Q discharging circuits QDC1 and QDC2 for discharging Q nodes, holding circuits QHM and QLM for stably maintaining the voltage state of Q nodes, QB charging circuit QBCC for charging QB nodes, QB discharging circuits QBDC1 and QBDC2 for discharging QB nodes, QB control circuit QBC, and so on.

[0319] Figure 10 The improved gate drive circuit 130 includes a line selection circuit LSC, Q charging circuits QCC1 and QCC2, Q discharging circuits QDC1 and QDC2, and holding circuits QHM and QLM, which can be used with... Figure 8 The gate drive circuit includes the same line selection circuit LSC, Q charging circuits QCC1 and QCC2, Q discharging circuits QDC1 and QDC2, and holding circuits QHM and QLM.

[0320] Figure 10 The improved gate drive circuit 130, which includes the QB charging circuit QBCC, QB discharging circuits QBDC1 and QBDC2, and the QB control circuit QBC, may differ from the standard gate drive circuit 130. Figure 8 The gate drive circuit 130 includes a QB charging circuit QBCC, QB discharging circuits QBDC1 and QBDC2, and a QB control circuit QBC.

[0321] The QB charging circuit QBCC may include a first transistor T4. The first transistor T4 may correspond to... Figure 8 The QB charging transistor T4.

[0322] The first QB discharge circuit QBDC1 may include two second transistors T5q and T5qa. The two second transistors T5q and T5qa may correspond to... Figure 8 The first Q-discharge transistor T5q.

[0323] The QB control circuit QBC may include a third transistor T4h, fourth transistors T41 and T41a, and two fifth transistors T4q and T4qa. The third transistor T4h may be... Figure 8 The transistors not included in the QBC control circuit. The fourth transistors T41 and T41a can correspond to... Figure 8 The QBC control circuit includes first control transistors T41 and T41a. Two fifth transistors, T4q and T4qa, can correspond to... Figure 8 The second control transistor T4q is included in the QB control circuit QBC.

[0324] refer to Figure 10 The control circuit 700 may include a first transistor T4 connected between the first driving voltage node Nvdd1 and the QB node, two second transistors T5q and T5qa connected in series between the QB node and the second low-level voltage node Nvss2, a third transistor T4h connected between the first driving voltage node Nvdd1 and the connection node Nc2 of the two second transistors T5q and T5qa, a fourth transistor T41 and T41a connected between the first driving voltage node Nvdd1 and the gate node of the first transistor T4, and two fifth transistors T4q and T4qa connected in series between the second low-level voltage node Nvss2 and the gate node of the first transistor T4.

[0325] refer to Figure 10 The connection node Nc1 of the two fifth transistors T4q and T4qa can be electrically connected to the source node or drain node of the third transistor T4h.

[0326] refer to Figure 10 The drain or source node of the third transistor T4h can be connected to the first drive voltage node Nvdd1. Here, the first drive voltage PGVDD can be applied to the first drive voltage node Nvdd1. Figure 10 The first driving voltage of node Nvdd1, PGVDD, can be applied to Figure 8 The first driving voltage of node Nvdd1 is the same as the first driving voltage GVDD_o.

[0327] refer to Figure 10 The source or drain node of the third transistor T4h can be connected to the connection node Nc1 of the two fifth transistors T4q and T4qa and the connection node Nc2 of the two second transistors T5q and T5qa.

[0328] refer to Figure 10The gate node of each of the two second transistors T5q and T5qa can be connected to the Q node.

[0329] refer to Figure 10 The gate node of each of the two fifth transistors T4q and T4qa can be connected to the Q node.

[0330] refer to Figure 10 The gate node of the third transistor T4h can be connected to the QB node.

[0331] refer to Figure 10 The third transistor T4h may include two transistors T4ha and T4hb connected in series between the first driving voltage node Nvdd1 and the connection node Nc2 of the two second transistors T5q and T5qa. In other words, the third transistor T4h may include two transistors T4ha and T4hb.

[0332] refer to Figure 10 The gate node of each of the two transistors T4ha and T4hb can be commonly connected to the QB node.

[0333] refer to Figure 10 The second low-level voltage GVSS2 applied to the second low-level voltage node Nvss2 can be lower than the first low-level voltage GVSS0 applied to the first low-level voltage node Nvss1.

[0334] refer to Figure 10 The control circuit 700 may further include a first Q charging circuit QCC1 and a first Q discharging circuit QDC1.

[0335] The first Q charging circuit QCC1 can be connected between the Q node and the second drive voltage node Nvdd and is configured to provide the second drive voltage GVDD to the Q node during the effective period.

[0336] The first Q discharge circuit QDC1 can be connected between the Q node and the second low-level voltage node Nvss2 and is configured to provide the second low-level voltage GVSS2 to the Q node during the effective period.

[0337] The transistor configuration of each of the first Q charging circuit QCC1 and the first Q discharging circuit QDC1 can be... Figure 8 The same.

[0338] refer to Figure 10 The control circuit 700 may further include a second Q charging circuit QCC2 and a second Q discharging circuit QDC2.

[0339] The second Q charging circuit QCC2 can be connected between the Q node and the second drive voltage node Nvdd and is configured to provide the second drive voltage GVDD to the Q node during the idle period.

[0340] The second Q discharge circuit QDC2 can be connected between the Q node and the second low-level voltage node Nvss2 and is configured to provide the second low-level voltage GVSS2 to the Q node during the blank period.

[0341] The transistor configuration of each of the second Q charging circuit QCC2 and the second Q discharging circuit QDC2 can be... Figure 8 The same.

[0342] refer to Figure 10 The control circuit 700 may further include a QB charging circuit QBCC and a first QB discharging circuit QBDC1.

[0343] The QB charging circuit QBCC can be connected between the first drive voltage node Nvdd1 and the QB node and is configured to provide the first drive voltage PGVDD to the QB node.

[0344] The first QB discharge circuit QBDC1 can be connected between the QB node and the second low-level voltage node Nvss2 and is configured to provide the second low-level voltage GVSS2 to the QB node during the effective period.

[0345] refer to Figure 10 The QB charging circuit QBCC may include a first transistor T4. The first QB discharging circuit QBDC1 may include two second transistors T5q and T5qa.

[0346] refer to Figure 10 The control circuit 700 may further include a second QB discharge circuit QBDC2. The second QB discharge circuit QBDC2 may be connected between the QB node and the second low-level voltage node Nvss2 and is configured to provide a second low-level voltage GVSS2 to the QB node during a blank period.

[0347] The transistor configuration of the second QB discharge circuit QBDC2 can be compared with... Figure 8 The same.

[0348] refer to Figure 10 The improved gate drive circuit 130 may further include a second gate output buffer circuit GBUF2, which includes a second pull-up transistor Tu2 and a second pull-down transistor Td2.

[0349] The second pull-up transistor Tu2 can be connected between the second clock signal input node Nclk2 and the second gate output node Nout2. The second pull-down transistor Td2 can be connected between the second gate output node Nout2 and the first low-level voltage node Nvss1.

[0350] The gate node of the second pull-up transistor Tu2 can be connected to the Q node. The gate node of the second pull-down transistor Td2 can be connected to the QB node.

[0351] The second gate output buffer circuit GBUF2 can output the second gate signal SCOUT(n+1) to the second gate line GL through the second gate output node Nout2.

[0352] refer to Figure 10 The improved gate drive circuit 130 may further include a carry output buffer circuit CBUF, which includes a carry pull-up transistor Tu_CR and a carry pull-down transistor Td_CR.

[0353] The carry pull-up transistor Tu_CR can be connected between the carry clock signal input node Ncrclk and the carry output node Ncrout. The carry pull-down transistor Td_CR can be connected between the carry output node Ncrout and the second low-level voltage node Nvss2.

[0354] The gate node of the carry-up pull-up transistor Tu_CR can be connected to the Q node. The gate node of the carry-down pull-down transistor Td_CR can be connected to the QB node.

[0355] The carry-out buffer circuit CBUF can output the carry signal C(n) to the previous stage circuit and / or the next stage circuit through the carry-out output node Ncrout.

[0356] refer to Figure 10 The improved gate drive circuit 130 may further include a third gate output buffer circuit GBUF3.

[0357] The third gate output buffer circuit GBUF3 may include a third pull-up transistor Tu3 and a third pull-down transistor Td3.

[0358] The third pull-up transistor Tu3 can be connected between the third clock signal input node Nclk3 and the third gate output node Nout3. The third pull-down transistor Td3 can be connected between the third gate output node Nout3 and the first low-level voltage node Nvss1.

[0359] Here, the third clock signal SCCLK(n+2) can be input to the third clock signal input node Nclk3. The third gate line GL can be electrically connected to the third gate output node Nout3.

[0360] Capacitor C3 can be connected between the gate node of the third gate output node Nout3 and the gate node of the third pull-up transistor Tu3.

[0361] The third gate output buffer circuit GBUF3 can output the third gate signal SCOUT(n+2) to the third gate line GL through the third gate output node Nout3.

[0362] refer to Figure 10 The improved gate drive circuit 130 may further include a fourth gate output buffer circuit GBUF4.

[0363] The fourth gate output buffer circuit GBUF4 may include a fourth pull-up transistor Tu4 and a fourth pull-down transistor Td4.

[0364] The fourth pull-up transistor Tu4 can be connected between the fourth clock signal input node Nclk4 and the fourth gate output node Nout4. The fourth pull-down transistor Td4 can be connected between the fourth gate output node Nout4 and the first low-level voltage node Nvss1.

[0365] Here, the fourth clock signal SCCLK(n+3) can be input to the fourth clock signal input node Nclk4. The fourth gate line GL can be electrically connected to the fourth gate output node Nout4.

[0366] Capacitor C4 can be connected between the gate node of the fourth gate output node Nout4 and the gate node of the fourth pull-up transistor Tu4.

[0367] The fourth gate output buffer circuit GBUF4 can output the fourth gate signal SCOUT(n+3) to the fourth gate line GL through the fourth gate output node Nout4.

[0368] refer to Figure 10 and Figure 11 In the segment where the Q node is in a high-level voltage state and the QB node is in a low-level voltage state, each of the two fifth transistors T4q and T4qa connected to the gate node of the Q node can be turned on and the first transistor T4 used to charge the QB node can be turned off.

[0369] Here, the two fifth transistors T4q and T4qa can be replaced with... Figure 8 The second control transistor T4q is the transistor. The first transistor T4 can be the transistor corresponding to... Figure 8The QB charging transistor T4 is a transistor.

[0370] In the section where the Q node is at a high voltage level and the QB node is at a low voltage level, the second low voltage level GVSS2 can be applied to the gate node of the first transistor T4 through the two conducting fifth transistors T4q and T4qa.

[0371] Here, the second low-level voltage GVSS2 is a voltage lower than the first low-level voltage GVSS0 and is lower than... Figure 8 The third low-level voltage GVSS1.

[0372] Accordingly, such as Figure 11 As shown, in the section where the Q node is at a high voltage level and the QB node is at a low voltage level, the gate voltage T4 Gate of the first transistor T4 can be lower than... Figure 8 The gate voltage of the QB charging transistor T4 is T4 Gate.

[0373] Therefore, the voltage difference between the gate and source nodes of the first transistor T4 is further reduced (Vgs=Vg-Vs=GVSS2-GVSS2). In the section where the Q node is at a high voltage level and the QB node is at a low voltage level, the first transistor T4 used to charge the QB node can remain completely off.

[0374] Accordingly, in the section where the Q node is in a high-level voltage state and the QB node is in a low-level voltage state, the first phenomenon of generating undesirable leakage current can be reduced or avoided in the first transistor T4 used for charging the QB node.

[0375] In addition, refer to Figure 10 and Figure 12 In the segment where the QB node is at a high voltage level and the Q node is at a low voltage level, the first transistor T4 used to charge the QB node can be turned on, and two fifth transistors T4q and T4qa, each connected to the gate node of the Q node, can be turned off.

[0376] The first transistor T4 is used to charge the QB node. Figure 8 The transistor is a modified QB charging transistor T4 used for charging the QB node, and the two fifth transistors T4q and T4qa are... Figure 8 The second control transistor T4q is a modified transistor.

[0377] refer to Figure 10 and Figure 12In the section where the QB node is at a high voltage level and the Q node is at a low voltage level, when ripple occurs in the Q node, the ripple of the Q node may be applied to the gate nodes of the two fifth transistors T4q and T4qa.

[0378] When the first drive voltage PGVDD is applied to the gate node of the third transistor T4h through the first transistor T4, which is turned on to implement QB charging, the third transistor T4h can be turned on. Therefore, the first drive voltage PGVDD can be output to the source node of the third transistor T4h.

[0379] The first drive voltage PGVDD (which serves as a high-level voltage input IH) output to the source node of the third transistor T4h can be applied to the connection node Nc1 of the two fifth transistors T4q and T4qa.

[0380] In this scenario, although the two fifth transistors T4q and T4qa are undesirably turned on by the ripple of the Q node, the first drive voltage PGVDD applied to the connection node Nc1 of the two fifth transistors T4q and T4qa can keep the first transistor T4 on. Here, the first transistor T4 is the transistor that remains on to implement QB charging.

[0381] Therefore, in the section where the QB node is at a high voltage level and the Q node is at a low voltage level, even if ripple occurs in the Q node, the first drive voltage PGVDD, which is output to the source node of the third transistor T4h, is also applied to the connection node Nc1 of the two fifth transistors T4q and T4qa, and thus the first transistor T4, which can be used for QB charging, remains on.

[0382] Therefore, even if ripple occurs in the Q node, the QB node can remain at a high voltage level.

[0383] At the same time, the first driving voltage PGVDD (which serves as a high-level voltage input IH) output to the source node of the third transistor T4h can be applied to the connection node Nc2 of the two second transistors T5q and T5qa.

[0384] When ripple occurs in the Q node, it may be fed to the gate nodes of the two second transistors T5q and T5qa used for QB node discharge. In this case, the two second transistors T5q and T5qa may be turned on unnecessarily.

[0385] Even under these circumstances, the first drive voltage PGVDD (which serves as a high-level voltage input IH) output to the source node of the third transistor T4h can be applied to the connection node Nc2 of the two second transistors T5q and T5qa, and thus the second low-level voltage GVSS2 cannot be applied to the QB node through the two second transistors T5q and T5qa.

[0386] Therefore, in the section where the QB node is at a high voltage level and the Q node is at a low voltage level, even if ripple occurs in the Q node, the first drive voltage PGVDD, which is output to the source node of the third transistor T4h, is also applied to the connection node Nc2 of the two second transistors T5q and T5qa, and thus the QB node can remain at a high voltage level.

[0387] refer to Figure 12 In the three waveforms 1210, 1220, and 1230 indicating the voltage state of the QB node, the first waveform 1210 occurs when ripple appears in the Q node, because... Figure 8 The waveform with the largest voltage drop at the Q node is due to the gate drive circuit 130.

[0388] refer to Figure 12 The second waveform 1120 can be a waveform that reduces the voltage drop of the Q node in the gate drive circuit 130, which applies the two fifth transistors T4q and T4qa, when ripple occurs in the Q node.

[0389] refer to Figure 12 The third waveform 1230 can be a waveform in which the voltage drop at the Q node is almost eliminated due to the gate drive circuit 130 of all the two fifth transistors T4q and T4qa and the two second transistors T5q and T5qa when ripple appears in the Q node.

[0390] refer to Figure 12 With the aid of the improved gate drive circuit 130, it is possible to reduce or prevent the second phenomenon, in the section where the QB node is in a high-level voltage state and the Q node is in a low-level voltage state, from the voltage drop of the QB node due to the ripple in the Q node.

[0391] The following is a summary of the description of the embodiments of this disclosure above.

[0392] Embodiments of this disclosure may provide a gate drive circuit comprising: a first gate output buffer circuit including a first pull-up transistor and a first pull-down transistor; and a control circuit configured to control the voltage of a QB node connected to the gate node of the first pull-down transistor and the voltage of a Q node connected to the gate node of the first pull-up transistor.

[0393] The first pull-up transistor can be connected between the first clock signal input node and the first gate output node, and the first pull-down transistor can be connected between the first gate output node and the first low-level voltage node.

[0394] The control circuit may include: a first transistor connected between a first drive voltage node and the QB node; two second transistors connected in series between the QB node and the second low-level voltage node; a third transistor connected between the connection node of the two second transistors and the first drive voltage node; a fourth transistor connected between the gate node of the first transistor and the first drive voltage node; and two fifth transistors connected in series between the gate node of the first transistor and the second low-level voltage node.

[0395] The connection nodes of the two fifth transistors can be electrically connected to the source node or drain node of the third transistor.

[0396] The drain or source node of the third transistor can be connected to the first driving voltage node, and the source or drain node of the third transistor can be connected to the connection node of the two second transistors and the connection node of the two fifth transistors.

[0397] The gate node of each of the two second transistors can be connected to the Q node.

[0398] The gate node of the third transistor can be connected to the QB node.

[0399] The gate node of each of the two fifth transistors can be connected to the Q node.

[0400] The third transistor may include two transistors connected in series between the connection node of the two second transistors and the first drive voltage node.

[0401] The second low-level voltage applied to the second low-level voltage node may be lower than the first low-level voltage applied to the first low-level voltage node.

[0402] The gate drive circuit may further include a second gate output buffer circuit, which includes a second pull-up transistor and a second pull-down transistor.

[0403] The second pull-up transistor can be connected between the second clock signal input node and the second gate output node. The gate node of the second pull-up transistor can be connected to the Q node.

[0404] The second pull-down transistor can be connected between the second gate output node and the first low-level voltage node. The gate node of the second pull-down transistor can be connected to the QB node.

[0405] The gate drive circuit may further include a carry output buffer circuit, which includes a carry pull-up transistor and a carry pull-down transistor.

[0406] The carry pull-up transistor can be connected between the carry clock signal input node and the carry output node. The gate node of the carry pull-up transistor can be connected to the Q node.

[0407] The carry-down transistor can be connected between the carry-out output node and the second low-level voltage node. The gate node of the carry-down transistor can be connected to the QB node.

[0408] The control circuit may further include: a first Q charging circuit connected between the second driving voltage node and the Q node and configured to provide a second driving voltage to the Q node during an effective period; and a first Q discharging circuit connected between the Q node and the second low-level voltage node and configured to provide a second low-level voltage to the Q node during an effective period.

[0409] The control circuit may further include: a second Q charging circuit connected between the second driving voltage node and the Q node and configured to provide a second driving voltage to the Q node during a blank period; and a second Q discharging circuit connected between the Q node and the second low-level voltage node and configured to provide a second low-level voltage to the Q node during a blank period.

[0410] The control circuit may further include: a QB charging circuit connected between the first driving voltage node and the QB node and configured to provide a first driving voltage to the QB node; and a first QB discharging circuit connected between the QB node and the second low-level voltage node and configured to provide a second low-level voltage to the QB node during an effective period.

[0411] The QB charging circuit may include a first transistor.

[0412] The first QB discharge circuit may include two second transistors.

[0413] The control circuit may further include a second QB discharge circuit connected between the QB node and the second low-level voltage node and configured to provide a second low-level voltage to the QB node during a blank period.

[0414] Embodiments of this disclosure may provide a display device comprising: a display panel including a plurality of gate lines; and a gate driving circuit configured to drive the plurality of gate lines.

[0415] The gate drive circuit may include: a first gate output buffer circuit including a first pull-up transistor and a first pull-down transistor; and a control circuit configured to control the voltage of the QB node connected to the gate node of the first pull-down transistor and the voltage of the Q node connected to the gate node of the first pull-up transistor.

[0416] The first pull-up transistor can be connected between the first clock signal input node and the first gate output node, and the first pull-down transistor can be connected between the first gate output node and the first low-level voltage node.

[0417] The control circuit may include: a first transistor connected between a first drive voltage node and the QB node; two second transistors connected in series between the QB node and the second low-level voltage node; a third transistor connected between the connection node of the two second transistors and the first drive voltage node; a fourth transistor connected between the gate node of the first transistor and the first drive voltage node; and two fifth transistors connected in series between the gate node of the first transistor and the second low-level voltage node.

[0418] The connection nodes of the two fifth transistors can be electrically connected to the source node or drain node of the third transistor.

[0419] The drain or source node of the third transistor can be connected to the first driving voltage node, and the source or drain node of the third transistor can be connected to the connection node of the two second transistors and the connection node of the two fifth transistors.

[0420] The gate node of each of the two second transistors can be connected to the Q node.

[0421] The gate node of the third transistor can be connected to the QB node.

[0422] The gate node of each of the two fifth transistors can be connected to the Q node.

[0423] The third transistor may include two transistors connected in series between the connection node of the two second transistors and the first drive voltage node.

[0424] The second low-level voltage applied to the second low-level voltage node may be lower than the first low-level voltage applied to the first low-level voltage node.

[0425] According to various embodiments, a display device includes a display panel and a gate driving circuit. The display panel includes gate lines. The gate driving circuit drives the gate lines in operation and includes a gate output buffer circuit and a control circuit. The gate output buffer circuit is coupled to the gate lines and includes a pull-up transistor and a pull-down transistor, the pull-up transistor having a gate node connected to a Q node and the pull-down transistor having a gate node connected to a QB node. The control circuit includes a first transistor coupled to the QB node. The control circuit performs the following operations in operation: when the voltage of the Q node is at a first level, applying a second low-level voltage of a second low-level voltage node to the gate node and source node of the first transistor; and electrically isolating the second low-level voltage node from the gate node of the first transistor when ripple in the voltage of the Q node is applied to the gate node of a second control transistor connected between the gate node of the first transistor and the second low-level voltage node.

[0426] The second transistor may have a gate node connected to the Q node.

[0427] The pull-up transistor can be connected between the clock signal input node and the gate output node, and the pull-down transistor can be connected between the gate output node and the first low-level voltage node. The second low-level voltage applied to the second low-level voltage node can be lower than the first low-level voltage applied to the first low-level voltage node.

[0428] According to embodiments of this disclosure, it is possible to provide a display device and a gate driving circuit configured to output a gate signal having a normal signal waveform.

[0429] According to embodiments of the present disclosure, it is possible to provide a display device and a gate driving circuit configured to output a gate signal having a normal signal waveform when performing gate driving for sensing-driving to sense the mobility of driving transistors in a sub-pixel.

[0430] The foregoing description has been provided to enable those skilled in the art to implement and use the technical concepts of the invention, and the foregoing description is provided in the context of a particular application and its requirements. Various modifications, additions, and substitutions to the described embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of the invention. The foregoing description and drawings are merely examples of the technical concepts of the invention for illustrative purposes. That is, the disclosed embodiments are intended to illustrate the scope of the technical concepts of the invention. Therefore, the scope of the invention is not limited to the illustrated embodiments, but is consistent with the widest scope consistent with the claims. The scope of protection of the invention should be understood based on the following claims, and all technical concepts within the scope of their equivalents should be understood to be included within the scope of the invention.

Claims

1. A gate driving circuit, comprising: A first gate output buffer circuit, the first gate output buffer circuit including a first pull-up transistor and a first pull-down transistor; as well as A control circuit configured to control the voltage of the Q node connected to the gate node of the first pull-up transistor and the voltage of the QB node connected to the gate node of the first pull-down transistor. in, The first pull-up transistor is connected between the first clock signal input node and the first gate output node, and the first pull-down transistor is connected between the first gate output node and the first low-level voltage node. The control circuit includes: A first transistor is connected between a first drive voltage node and the QB node; Two second transistors are connected in series between the QB node and the second low-level voltage node; A third transistor is connected between the connection node of the two second transistors and the first drive voltage node; A fourth transistor, the fourth transistor being connected between the gate node of the first transistor and the first drive voltage node; and Two fifth transistors are connected in series between the gate node of the first transistor and the second low-level voltage node, and The connection nodes of the two fifth transistors are electrically connected to the source node or drain node of the third transistor.

2. The gate driving circuit according to claim 1, wherein, The drain or source node of the third transistor is connected to the first drive voltage node, and The source or drain node of the third transistor is connected to the connection node of the two second transistors and the connection node of the two fifth transistors.

3. The gate driving circuit according to claim 1, wherein, Each of the two second transistors has a gate node connected to the Q node.

4. The gate driving circuit according to claim 1, wherein, The third transistor has a gate node connected to the QB node.

5. The gate driving circuit according to claim 1, wherein, Each of the two fifth transistors has a gate node connected to the Q node.

6. The gate driving circuit according to claim 1, wherein, The third transistor includes two transistors connected in series between the connection node of the two second transistors and the first drive voltage node.

7. The gate driving circuit according to claim 1, wherein, The second low-level voltage applied to the second low-level voltage node is lower than the first low-level voltage applied to the first low-level voltage node.

8. The gate driving circuit according to claim 1, further comprising a second gate output buffer circuit, the second gate output buffer circuit comprising a second pull-up transistor and a second pull-down transistor. in, The second pull-up transistor is connected between the second clock signal input node and the second gate output node, and the second pull-down transistor is connected between the second gate output node and the first low-level voltage node. The second pull-up transistor has a gate node connected to the Q node, and the second pull-down transistor has a gate node connected to the QB node.

9. The gate driving circuit according to claim 1, further comprising a carry output buffer circuit, the carry output buffer circuit comprising a carry pull-up transistor and a carry pull-down transistor. in, The carry pull-up transistor is connected between the carry clock signal input node and the carry output node, and the carry pull-down transistor is connected between the carry output node and the second low-level voltage node. The carry pull-up transistor has a gate node connected to the Q node, and the carry pull-down transistor has a gate node connected to the QB node.

10. The gate driving circuit according to claim 1, wherein, The control circuit further includes: A first Q-charging circuit, connected between a second driving voltage node and the Q node and configured to provide a second driving voltage to the Q node during an effective time period; and A first Q-discharge circuit is connected between the Q node and the second low-level voltage node and is configured to provide a second low-level voltage to the Q node during the effective period.

11. The gate driving circuit according to claim 1, wherein, The control circuit further includes: A second Q-charging circuit is connected between the second drive voltage node and the Q node and is configured to provide a second drive voltage to the Q node during idle periods; and A second Q-discharge circuit is connected between the Q node and the second low-level voltage node and is configured to provide a second low-level voltage to the Q node during the blank period.

12. The gate driving circuit according to claim 1, wherein, The control circuit further includes: A QB charging circuit, the QB charging circuit being connected between the first driving voltage node and the QB node and configured to provide a first driving voltage to the QB node; and A first QB discharge circuit is connected between the QB node and the second low-level voltage node and is configured to provide a second low-level voltage to the QB node during the effective period. The QB charging circuit includes the first transistor, and The first QB discharge circuit includes the two second transistors.

13. The gate driving circuit according to claim 12, wherein, The control circuit further includes: A second QB discharge circuit is connected between the QB node and the second low-level voltage node and is configured to provide a second low-level voltage to the QB node during a blank period.

14. A display device, comprising: The display panel includes multiple gate lines; as well as A gate driving circuit configured to drive the plurality of gate lines. in, The gate driving circuit includes: A first gate output buffer circuit, the first gate output buffer circuit including a first pull-up transistor and a first pull-down transistor; and A control circuit configured to control the voltage of the Q node connected to the gate node of the first pull-up transistor and the voltage of the QB node connected to the gate node of the first pull-down transistor. The first pull-up transistor is connected between the first clock signal input node and the first gate output node, and the first pull-down transistor is connected between the first gate output node and the first low-level voltage node. The control circuit includes: A first transistor is connected between a first drive voltage node and the QB node; Two second transistors are connected in series between the QB node and the second low-level voltage node; A third transistor is connected between the connection node of the two second transistors and the first drive voltage node; A fourth transistor, the fourth transistor being connected between the gate node of the first transistor and the first drive voltage node; and Two fifth transistors are connected in series between the gate node of the first transistor and the second low-level voltage node, and The connection nodes of the two fifth transistors are electrically connected to the source node or drain node of the third transistor.

15. The display device according to claim 14, wherein, The drain or source node of the third transistor is connected to the first drive voltage node, and The source or drain node of the third transistor is connected to the connection node of the two second transistors and the connection node of the two fifth transistors.

16. The display device according to claim 14, wherein, Each of the two second transistors has a gate node connected to the Q node.

17. The display device according to claim 14, wherein, The third transistor has a gate node connected to the QB node.

18. The display device according to claim 14, wherein, Each of the two fifth transistors has a gate node connected to the Q node.

19. The display device according to claim 14, wherein, The third transistor includes two transistors connected in series between the first drive voltage node and the connection node of the two second transistors.

20. The display device according to claim 14, wherein, The second low-level voltage applied to the second low-level voltage node is lower than the first low-level voltage applied to the first low-level voltage node.

21. A display device, comprising: The display panel includes gate lines; as well as A gate driving circuit that drives the gate line during operation, and the gate driving circuit includes: A gate output buffer circuit, coupled to the gate line, and comprising: A pull-up transistor having a gate node connected to a Q node; and A pull-down transistor having a gate node connected to a QB node; and Control circuit, the control circuit comprising: A first transistor is connected between a first drive voltage node and the QB node; Two second transistors are connected in series between the QB node and the second low-level voltage node; A third transistor is connected between the connection node of the two second transistors and the first drive voltage node; A fourth transistor, the fourth transistor being connected between the gate node of the first transistor and the first drive voltage node; and Two fifth transistors are connected in series between the gate node of the first transistor and the second low-level voltage node, and The connection nodes of the two fifth transistors are electrically connected to the source node or drain node of the third transistor. The control circuit is configured as follows: When the voltage of the Q node is at the first level, the second low-level voltage of the second low-level voltage node is applied to the gate node and the source node of the first transistor; and When the ripple in the voltage of the Q node is applied to the gate node of the fifth transistor, which is connected between the gate node of the first transistor and the second low-level voltage node, the second low-level voltage node is electrically isolated from the gate node of the first transistor.

22. The display device according to claim 21, wherein, The fifth transistor has a gate node connected to the Q node.

23. The display device according to claim 21, wherein, The pull-up transistor is connected between the clock signal input node and the gate output node, the pull-down transistor is connected between the gate output node and the first low-level voltage node, and the second low-level voltage applied to the second low-level voltage node is lower than the first low-level voltage applied to the first low-level voltage node.

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