Pixel circuit and driving method thereof, display panel and driving method thereof, display device

Abstract

Embodiments of the present disclosure provide a pixel circuit and a driving method thereof, a display panel and a driving method thereof, and a display device. The pixel circuit comprises a driving module configured to provide an electrical signal to a fourth node based on a signal of a first power supply end under the control of a first node; a writing module configured to provide a data signal of a data signal end to a fifth node under the control of a first scan signal end; and a frequency control module comprising a frequency control submodule and a signal gating submodule, the signal gating submodule being configured to periodically provide a signal of a second scan signal end to a sixth node under the control of a first frequency control end and a second frequency control end, so that the frequency control submodule controls the frequency of writing of the data signal of the fifth node to the first node under the control of the sixth node. The technical solution of the present disclosure can realize local area variable frequency driving or different area different frequency driving, and reduce the overall power consumption of the display panel.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a pixel circuit and its driving method, a display panel and its driving method, and a display device. Background Technology

[0002] With the development of the times and the advancement of technology, users have increasingly higher requirements for display panels. High-frequency driving of display panels can result in smoother images and an improved user experience; low-frequency driving can save power and extend standby time. To balance image quality and power saving, how to drive the display panel to effectively reduce its overall power consumption is a technical problem that needs to be solved. Summary of the Invention

[0003] This disclosure provides a pixel circuit and its driving method, a display panel and its driving method, and a display device to solve or alleviate one or more technical problems in the prior art.

[0004] As a first aspect of the present disclosure, the present disclosure provides a pixel circuit, including:

[0005] The driving module, coupled to the first node, the first power supply terminal and the fourth node, is configured to provide an electrical signal to the fourth node based on the signal of the first power supply terminal under the control of the first node, so as to drive the light-emitting element to emit light.

[0006] The write module is coupled to the first scan signal terminal, the data signal terminal and the fifth node, and is configured to provide the data signal of the data signal terminal to the fifth node under the control of the first scan signal terminal;

[0007] The frequency control module includes a frequency control submodule and a signal gating submodule. The frequency control submodule is coupled to the sixth node, the first node, and the fifth node. The signal gating submodule is coupled to the second scan signal terminal, the second power supply terminal, the first frequency control terminal, the second frequency control terminal, and the sixth node. It is configured to periodically provide the second scan signal terminal to the sixth node under the control of the first and second frequency control terminals, so that the frequency control submodule controls the frequency at which the data signal from the fifth node is written to the first node under the control of the sixth node.

[0008] In one embodiment, when the signal gating submodule provides the signal of the second scanning signal terminal to the sixth node, the frequency control submodule, under the control of the sixth node, controls the data signal of the second node to be able to be written to the first node.

[0009] When the signal gating submodule provides the second power supply signal to the sixth node, the frequency control submodule, under the control of the sixth node, prohibits the data signal of the second node from being written to the first node.

[0010] In one embodiment, the signal gating submodule includes a first transistor and a second transistor. The control terminal of the first transistor is coupled to a first frequency control terminal, the first electrode of the first transistor is coupled to a second scan signal terminal, the control terminal of the second transistor is coupled to a second frequency control terminal, the first electrode of the second transistor is coupled to a second power supply terminal, and the second electrodes of both the first transistor and the second electrode of the second transistor are coupled to a sixth node.

[0011] The frequency control submodule includes a third transistor, the control terminal of which is coupled to the sixth node, and the first and second terminals of which are coupled to the fifth and first nodes, respectively.

[0012] In one embodiment, one of the first transistor and the second transistor is an N-type transistor and the other is a P-type transistor, and the signals at the first frequency control terminal and the second frequency control terminal are the same; or...

[0013] Both the first transistor and the second transistor are either N-type transistors or both are P-type transistors. One of the signals at the first frequency control terminal and the second frequency control terminal is at a high level, and the other is at a low level.

[0014] In one embodiment, the input terminal of the driving module is coupled to the first power supply terminal, the output terminal of the driving module is coupled to the fourth node, and the pixel circuit further includes a third reset module. The third reset module is coupled to the fourth scan signal terminal, the third initial signal terminal and the input terminal of the driving module, respectively, and is configured to provide the signal of the third initial signal terminal to the input terminal of the driving module under the control of the fourth scan signal terminal.

[0015] In one embodiment, the pixel circuit further includes:

[0016] The storage module is coupled to the first power supply terminal and the first node respectively, and is used to store the signals of the first node;

[0017] The first reset module is coupled to the first initial signal terminal, the third scan signal terminal and the fifth node respectively, and is configured to provide the signal of the first initial signal terminal to the fifth node under the control of the third scan signal terminal;

[0018] The second reset module is coupled to the fourth scan signal terminal, the second initial signal terminal and the fourth node respectively, and is configured to provide the signal of the second initial signal terminal to the fourth node under the control of the fourth scan signal terminal;

[0019] The first control module is coupled to the light-emitting control terminal, the first power supply terminal, and the input terminal of the driving module, respectively, and is configured to provide the signal of the first power supply terminal to the input terminal of the driving module under the control of the light-emitting control terminal.

[0020] The second control module is coupled to the light-emitting control terminal, the output terminal of the drive module, and the fourth node, respectively, and is configured to provide the output signal of the drive module to the fourth node under the control of the light-emitting control terminal.

[0021] In one embodiment, the pixel circuitry includes at least one of the following:

[0022] The driving module includes a driving transistor, the control terminal of which is coupled to the first node, and the first and second terminals of which are coupled to the first power supply terminal and the fourth node, respectively.

[0023] The write module includes a fourth transistor and a fifth transistor. The control terminals of the fourth transistor and the fifth transistor are both coupled to the first scan signal terminal. The first and second terminals of the fourth transistor are coupled to the data signal terminal and the input terminal of the drive module, respectively. The first and second terminals of the fifth transistor are coupled to the output terminal of the drive module and the fifth node, respectively.

[0024] The first reset module includes a sixth transistor, the control terminal of the sixth transistor is coupled to the third scan signal terminal, and the first and second terminals of the sixth transistor are coupled to the first initial signal terminal and the fifth node, respectively.

[0025] The second reset module includes a seventh transistor, the control terminal of the seventh transistor is coupled to the fourth scan signal terminal, and the first and second terminals of the seventh transistor are coupled to the second initial signal terminal and the fourth node, respectively.

[0026] The first control module includes an eighth transistor, the control terminal of the eighth transistor is coupled to the light-emitting control terminal, and the first and second terminals of the eighth transistor are coupled to the first power supply terminal and the input terminal of the driving module, respectively.

[0027] The second control module includes a ninth transistor. The control terminal of the ninth transistor is coupled to the light-emitting control terminal. The first and second terminals of the ninth transistor are coupled to the output terminal of the driving module and the fourth node, respectively.

[0028] As a second aspect of the present disclosure, the present disclosure provides a display panel including a plurality of gate lines extending along a first direction, the plurality of gate lines being arranged along a second direction, the display panel including a plurality of first sub-display areas arranged along the second direction, the first sub-display areas including pixel circuits;

[0029] The pixel circuit includes a driving module, a writing module, and a frequency control module. The driving module is coupled to a first node and configured to provide a driving electrical signal under the control of the first node signal. The writing module is coupled to a first scan signal terminal, a data signal terminal, and the input terminal of the frequency control module and configured to provide a data signal from the data signal terminal to the input terminal of the frequency control module under the control of the first scan signal terminal. The frequency control module is coupled to a frequency control terminal, a second scan signal terminal, and the first node and configured to control the frequency at which the data signal from the input terminal of the frequency control module is written to the first node based on the signal from the frequency control terminal and the signal from the second scan signal terminal.

[0030] The frequency control terminal in the pixel circuit of the multiple first sub-display areas is connected to the first frequency signal line, and the second scanning signal terminal in the pixel circuit is connected to the corresponding gate line in the first sub-display area. The refresh rates of the multiple first sub-display areas are different.

[0031] The first frequency signal line is configured to provide a first signal during the refresh phase of the first sub-display area and at least during the period when the corresponding gate line provides a gate signal, so that the frequency control module in the first sub-display area writes the data signal at the input terminal of the frequency control module to the first node under the control of the first signal.

[0032] The first frequency signal line is also configured to provide a second signal during the holding phase of the first sub-display area and at least during the period when the corresponding gate line provides a gate signal, such that the frequency control module in the first sub-display area, under the control of the second signal, prohibits the data signal at the input terminal of the frequency control module from being written to the first node.

[0033] In one embodiment, it further includes at least one second sub-display area, the refresh frequency of the second sub-display area is different from the refresh frequency of the first sub-display area, and the frequency control terminal of the pixel circuit in the second sub-display area is coupled to the second frequency signal line.

[0034] The second frequency signal line is configured to provide a first signal during the refresh phase of the second sub-display area and at least during the period when the corresponding gate line provides a gate signal, and to provide a second signal during the hold phase of the second sub-display area and at least during the period when the corresponding gate line provides a gate signal.

[0035] In one embodiment, there are multiple second sub-display areas, which are arranged along a second direction. The refresh rates of the multiple second sub-display areas are different, and the frequency control terminals of the pixel circuits in each second sub-display area are coupled to different frequency signal lines.

[0036] In one embodiment, the input terminal of the driving module is coupled to the first power supply terminal, and the pixel circuit further includes a third reset module. The third reset module is coupled to the fourth scan signal terminal, the third initial signal terminal and the input terminal of the driving module, and is configured to provide the signal of the third initial signal terminal to the input terminal of the driving module under the control of the fourth scan signal terminal.

[0037] In one embodiment, the pixel circuit further includes a first reset module, a second reset module, a first control module, and a second control module, and the pixel circuit satisfies at least one of the following:

[0038] The driving module includes a driving transistor, which is coupled to the first node. The first and second terminals of the driving transistor are coupled to the first power supply terminal and the light-emitting element, respectively.

[0039] The writing module includes a fourth transistor, the control terminal of which is coupled to the first scan signal terminal, and the first and second terminals of the fourth transistor are coupled to the data signal terminal and the input terminal of the driving module, respectively.

[0040] The frequency control module includes a fifth transistor and a third transistor. The control terminal of the fifth transistor is coupled to the second scan signal terminal. The first and second terminals of the fifth transistor are coupled to the output terminal of the drive module and the first terminal of the third transistor, respectively. The control terminal of the third transistor is coupled to the frequency control terminal, and the second terminal of the third transistor is coupled to the control terminal of the first node. The input terminal of the frequency control module is the first terminal of the fifth transistor.

[0041] The first reset module includes a sixth transistor, the control terminal of the sixth transistor is coupled to the third scan signal terminal, and the first and second terminals of the sixth transistor are coupled to the first initial signal terminal and the frequency control module, respectively.

[0042] The second reset module includes a seventh transistor, the control terminal of the seventh transistor is coupled to the fourth scan signal terminal, and the first and second terminals of the seventh transistor are coupled to the second initial signal terminal and the light-emitting element, respectively.

[0043] The first control module includes an eighth transistor, the control terminal of the eighth transistor is coupled to the light-emitting control terminal, and the first and second terminals of the eighth transistor are coupled to the first power supply terminal and the input terminal of the driving module, respectively.

[0044] The second control module includes a ninth transistor, the control terminal of which is coupled to the light-emitting control terminal, and the first and second terminals of the ninth transistor are coupled to the output terminal of the driving module and the light-emitting element, respectively.

[0045] In one embodiment, the pixel circuit employs the pixel circuit of any embodiment of this disclosure.

[0046] As a third aspect of the present disclosure, the present disclosure provides a display panel including a gate line, a first sub-signal line, a second sub-signal line, and a pixel circuit as described in any embodiment of the present disclosure. The second scanning signal terminal of the pixel circuit is coupled to the gate line, the first frequency control terminal of the pixel circuit is coupled to the first sub-signal line, and the second frequency control terminal of the pixel circuit is coupled to the second sub-signal line.

[0047] In one embodiment, the display panel includes a plurality of sub-display areas, and at least one sub-display area includes pixel circuitry according to any embodiment of the present disclosure.

[0048] In one embodiment, the sub-display area including the pixel circuit in any embodiment of this disclosure is a third sub-display area, the number of third sub-display areas is at least two, the refresh frequencies of the multiple third sub-display areas are different, the first frequency control terminal of the pixel circuit in different third sub-display areas is coupled to different first sub-signal lines, and the second frequency control terminal of the pixel circuit in different third sub-display areas is coupled to different second sub-signal lines.

[0049] As a fourth aspect of the present disclosure, the present disclosure provides a driving method for a pixel circuit, characterized in that, applied to the pixel circuit in any embodiment of the present disclosure, the method includes:

[0050] During the refresh phase, at least during the period when the second scan signal is provided at the second scan signal terminal, a valid signal is provided to the first frequency control terminal and an invalid signal is provided to the second frequency control terminal, so as to provide the signal of the second scan signal terminal to the sixth node, so that the data signal of the fifth node can be written to the first node;

[0051] During the holding phase, at least during the period when the second scan signal is provided at the second scan signal terminal, an invalid signal is provided to the first frequency control terminal and an valid signal is provided to the second frequency control terminal to provide the signal of the second power supply terminal to the sixth node, and the data signal of the fifth node is prohibited from being written to the first node.

[0052] In one embodiment, the refresh phase includes a reset sub-phase and a write data sub-phase, and the method further includes:

[0053] During the reset sub-stage, scan signals are provided to the third and fourth scan signal terminals in the pixel circuit to provide a first reset signal to the fifth node and a first reset signal to the first node; a third reset signal is provided to the input terminal of the drive module; and a second reset signal is provided to the fourth node.

[0054] During the data writing sub-stage, a valid level signal is provided to the first scan signal terminal to provide the data signal to the fifth node and the data signal to the first node.

[0055] In one embodiment, the method further includes:

[0056] During the reset sub-stage of the refresh phase, a valid signal is provided to the first frequency control terminal and an invalid signal is provided to the second frequency control terminal.

[0057] During the holding phase and the period when a scan signal is provided at the third scan signal terminal, an invalid signal is provided to the first frequency control terminal and an valid signal is provided to the second frequency control terminal.

[0058] As a fifth aspect of the present disclosure, the present disclosure provides a driving method for a display panel, applied to a display panel in any embodiment of the present disclosure, the method comprising:

[0059] During the refresh phase of the first sub-display area, at least during the period when the corresponding gate line provides the gate signal, the first signal is provided to the first frequency signal line, so that the data signal at the input terminal of the frequency control module of the pixel circuit in the first sub-display area is written to the first node;

[0060] During the holding phase of the first sub-display area, at least during the period when the corresponding gate line provides the gate signal, the second signal is provided to the first frequency signal line to prevent the data signal at the input terminal of the frequency control module of the pixel circuit in the first sub-display area from being written to the first node.

[0061] In one embodiment, it also includes:

[0062] During the refresh phase of the first sub-display area, a first signal is provided to the first frequency signal line during the period when the scanning signal is provided at the third scanning signal terminal in the pixel circuit, so as to reset the first node;

[0063] During the holding phase of the first sub-display area, a second signal is provided to the first frequency signal line during the period when the third scan signal terminal in the pixel circuit provides the scan signal line, thereby prohibiting the reset of the first node.

[0064] As a sixth aspect of the present disclosure, the present disclosure provides a display device, including the pixel circuit of any embodiment of the present disclosure, or including the display panel of any embodiment of the present disclosure.

[0065] The technical solution of this disclosure applies pixel circuits to different areas of the display panel. By providing signals of different frequencies to the frequency control terminal of the pixel circuit, different frequencies can be driven in different areas. For areas with high driving frequency requirements, the frequency signal line can provide a high-frequency signal to the frequency control terminal SW; for areas with low driving frequency requirements, the frequency signal line can provide a low-frequency signal to the frequency control terminal SW. This approach combines the advantages of high-frequency and low-frequency driving, ensuring smooth image display in high-frequency areas while saving power, extending standby time, and reducing the overall power consumption of the display panel.

[0066] By applying the pixel circuit of this embodiment to a local area of ​​the display panel, the refresh frequency of the pixel circuit can be controlled by controlling the frequency of the signal provided to the frequency control terminal, thereby realizing frequency conversion display of the local area of ​​the display panel.

[0067] The above overview is for illustrative purposes only and is not intended to be limiting in any way. Further aspects, embodiments, and features of this disclosure will become readily apparent from the accompanying drawings and the following detailed description, in addition to the illustrative aspects, embodiments, and features described above. Attached Figure Description

[0068] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the various drawings denote the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings depict only some embodiments according to this disclosure and should not be construed as limiting the scope of this disclosure.

[0069] Figure 1 This is a schematic diagram of a pixel circuit;

[0070] Figure 2 This is a schematic diagram of another type of pixel circuit;

[0071] Figure 3 This is a schematic diagram of the pixel circuit structure in one embodiment of the present disclosure;

[0072] Figure 4 This is a schematic diagram of the pixel circuit structure in another embodiment of the present disclosure;

[0073] Figure 5 This is a schematic diagram of the pixel circuit structure in another embodiment of the present disclosure;

[0074] Figure 6 This is a schematic diagram of the pixel circuit structure in another embodiment of the present disclosure;

[0075] Figure 7A This is a schematic diagram of the pixel circuit structure in another embodiment of the present disclosure;

[0076] Figure 7B This is a schematic diagram of the pixel circuit structure in another embodiment of the present disclosure;

[0077] Figure 8 This is a schematic diagram of a pixel circuit driving method in another embodiment of the present disclosure;

[0078] Figure 9A for Figure 5 The shown is a timing diagram of a pixel circuit.

[0079] Figure 9B for Figure 7A The timing diagram of the pixel circuit shown;

[0080] Figure 10 This is a plan view of the display panel according to one embodiment of the present disclosure;

[0081] Figure 11 This is a plan view of the display panel in another embodiment of the present disclosure;

[0082] Figure 12 This is a plan view of the display panel according to one embodiment of the present disclosure;

[0083] Figure 13 This is a timing diagram of a display panel in one embodiment;

[0084] Figure 14 This is a plan view of the display panel in another embodiment of the present disclosure;

[0085] Figure 15 This is a plan view of the display panel in another embodiment of the present disclosure;

[0086] Figure 16 This is a plan view of the display panel in another embodiment of the present disclosure;

[0087] Figure 17 This is a schematic diagram of a driving method for a display panel according to an embodiment of the present disclosure;

[0088] Figure 18 In one embodiment of this disclosure, the display panel adopts Figure 5 The diagram shows a timing sequence of the pixel circuit. Detailed Implementation

[0089] In the following description, only certain exemplary embodiments are briefly described. As those skilled in the art will recognize, the described embodiments can be modified in various ways without departing from the spirit or scope of this disclosure. Therefore, the drawings and description are to be considered exemplary in nature and not restrictive.

[0090] In all embodiments of this invention, the transistors used can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. Based on their function in the circuit, the transistors used in these embodiments are primarily switching transistors. Since the source and drain of the switching transistors used here are symmetrical, their sources and drains are interchangeable. In these embodiments, the source (source electrode) is referred to as the first electrode, and the drain (drain electrode) as the second electrode; alternatively, the drain can be referred to as the first electrode, and the source as the second electrode. According to the configuration shown in the accompanying drawings, the middle terminal of the transistor is designated as the gate (also called the gate electrode), the signal input terminal as the source, and the signal output terminal as the drain. The switching transistors used in these embodiments can be P-type or N-type switching transistors. P-type switching transistors conduct when the gate is low and are cut off when the gate is high; N-type transistors conduct when the gate is high and are cut off when the gate is low. Furthermore, multiple signals in each embodiment of this invention correspond to a first potential and a second potential. The first potential and the second potential only represent two different potential states of the signal and do not imply that the first potential or the second potential has a specific numerical value throughout the text. In this embodiment of the invention, the first potential is used as an example for illustration.

[0091] The coupling can include direct physical contact between the two ends or indirect connection between the two ends (such as establishing a connection between the two ends through a signal line). This embodiment of the invention does not limit the coupling method between the two ends.

[0092] Figure 1 This is a schematic diagram of a pixel circuit. (Example) Figure 1As shown, the pixel circuit may include a driving transistor Td, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, and a storage capacitor Cst. The control terminal of the driving transistor Td is coupled to the first node N1, and its first and second terminals are coupled to the second node N2 and the third node N3, respectively. The control terminal of the fourth transistor T4 is coupled to the first scan signal terminal Scan1, and its first and second terminals are coupled to the data signal terminal Data and the second node N2, respectively. The control terminal of the fifth transistor T5 is coupled to the second scan signal terminal Scan2, and its first and second terminals are coupled to the third node N3 and the first node N1, respectively. The control terminal of the sixth transistor T6 is coupled to the third scan signal terminal Scan3, and its first and second terminals are coupled to the first initial signal terminal Init1 and the first node N1, respectively. The control terminal of the seventh transistor T7 is coupled to the fourth scan signal terminal Scan4. The first and second terminals of the seventh transistor T7 are coupled to the second initial signal terminal Init2 and the fourth node N4, respectively. The control terminal of the eighth transistor T8 is coupled to the light-emitting control terminal EM. The first and second terminals of the eighth transistor T8 are coupled to the third initial signal terminal Init3 and the second node N2, respectively. The control terminal of the ninth transistor T9 is coupled to the light-emitting control terminal EM. The first and second terminals of the ninth transistor T9 are coupled to the third node N3 and the fourth node N4, respectively. The control terminal of the tenth transistor T10 is coupled to the fourth scan signal terminal Scan4. The first and second terminals of the tenth transistor T10 are coupled to the third initial signal terminal Init3 and the second node N2, respectively.

[0093] like Figure 1 As shown, the fifth transistor T5 and the sixth transistor T6 can be N-type transistors, meaning that both the fifth transistor T5 and the sixth transistor T6 are active high. Figure 1 Except for transistors T5 (fifth) and T6 (sixth), all other transistors can be P-type transistors, and all are active low. Figure 1 In this configuration, the signals of the second scan signal terminal Scan2 and the first scan signal terminal Scan1 are different, and the signals of the third scan signal terminal Scan3 and the fourth scan signal terminal Scan4 are different. The display panel can adopt a dual-gate structure, and the pixel circuit can be coupled to two gate lines. The first scan signal terminal Scan1 can be coupled to the first gate line in the display panel, and the second scan signal terminal Scan2 can be coupled to the second gate line in the display panel.

[0094] Figure 2 This is a schematic diagram of another type of pixel circuit. (And...) Figure 1 The pixel circuit shown is different, Figure 2The pixel circuit shown also includes a third transistor T3, which is located between the first node N1 and the second terminal of the sixth transistor T6. The third transistor T3 is also located between the first node N1 and the second terminal of the fifth transistor T5. Figure 2 As shown, the control terminal of the third transistor T3 is coupled to the second scan signal terminal Scan2, and the first and second terminals of the third transistor T3 are coupled to the fifth node N5 and the first node N1, respectively. The control terminal of the fifth transistor T5 is coupled to the first scan signal terminal Scan1, and the first and second terminals of the fifth transistor T5 are coupled to the third node N3 and the fifth node N5, respectively. The control terminal of the sixth transistor T6 is coupled to the third scan signal terminal Scan3, and the first and second terminals of the sixth transistor T6 are coupled to the first initial signal terminal Init1 and the fifth node N5, respectively. Figure 2 The connection method of other transistors and storage capacitor Cst in the pixel circuit shown is the same as... Figure 1 The pixel circuits shown are the same, so they will not be described again here.

[0095] exist Figure 2 In this configuration, the third transistor T3 can be an N-type transistor. The fifth transistor T5 is a P-type transistor, and the control terminals of both the fifth and fourth transistors T4 are coupled to the first scan signal terminal Scan1. The sixth transistor T6 can also be a P-type transistor, and the signal at the third scan signal terminal Scan3 can be the same as the signal at the fourth scan signal terminal Scan4. The display panel can employ a dual-gate structure, where the pixel circuit can be coupled to two gate lines. The first scan signal terminal Scan1 can be coupled to the first gate line, and the second scan signal terminal Scan2 can be coupled to the second gate line.

[0096] Understandably, a pixel circuit typically includes a reset phase, a data writing phase, and a light-emitting phase. In the reset phase, an initial signal (Init1) is provided to the first node N1, an initial signal (Init2) is provided to the fourth node N4, and an initial signal (Init3) is provided to the second node N2, completing the pixel circuit reset. In the data writing phase, the data signal (Data) is written to the first node N1. In the light-emitting phase, the driving transistor Td, under the control of the data signal at the first node N1, provides a driving signal to the fourth node N4 based on the signal at the first power supply terminal (VDD), driving the light-emitting element DL to emit light. Therefore, for each refresh of the image corresponding to the pixel circuit, a data signal needs to be written to the first node N1 once. By controlling the frequency at which the data signal is written to the first node N1, the refresh frequency of the image corresponding to the pixel circuit can be controlled.

[0097] Figure 3 This is a schematic diagram of the pixel circuit structure in one embodiment of this disclosure. Figure 3As shown, the pixel circuit may include a driving module 10, a writing module 20, and a frequency control module 30. The driving module 10 is coupled to the first node N1 and is configured to provide a driving electrical signal under the control of the first node signal. For example, the output terminal of the driving module 10 may be coupled to the light-emitting element DL, so that the driving electrical signal provided by the output terminal of the driving module 10 can drive the light-emitting element DL to emit light.

[0098] The write module 20 is coupled to the first scan signal terminal Scan1, the data signal terminal Data, and the input terminal of the frequency control module 30. The write module 20 is configured to provide the data signal from the data signal terminal Data to the input terminal of the frequency control module 30 under the control of the first scan signal terminal Scan1.

[0099] The frequency control module 30 can be coupled to the frequency control terminal SW and the second scan signal terminal Scan2. The frequency control module 30 is configured to control the frequency at which the data signal at the input terminal of the frequency control module 30 is written to the first node N1 based on the signal at the frequency control terminal SW and the signal at the second scan signal terminal Scan2.

[0100] Figure 1 and Figure 2 In the pixel circuit, when the data signal is written to the first node N1, the second scan signal terminal Scan2 needs to provide an effective level signal. That is to say, the frequency at which the data signal is written to the first node N1 is determined by the frequency of the second scan signal terminal Scan2, and the frequency at which the data signal is written to the first node N1 is the same as the frequency at the second scan signal terminal Scan2.

[0101] In the pixel circuit of this embodiment, the frequency control module 30 can control the frequency at which the data signal at the input terminal of the frequency control module 30 is written to the first node N1 based on the signal at the frequency control terminal SW and the signal at the second scan signal terminal Scan2. Therefore, compared to Figure 1 and Figure 2 In the pixel circuit shown in this embodiment, the frequency at which the data signal is written to the first node N1 is no longer determined by the signal of the second scan signal terminal Scan2, but by the frequency of the frequency control terminal SW and the frequency of the second scan signal terminal Scan2. By changing the frequency of the frequency control terminal SW, the frequency at which the data signal is written to the first node N1 can be changed, thereby controlling the frequency at which the data signal is written to the first node N1 and controlling the image refresh frequency of the pixel circuit.

[0102] By applying the pixel circuits of this disclosure to different areas of the display panel, the frequency control terminals SW of the pixel circuits in different areas can be connected to different frequency signal lines. These different frequency signal lines can provide signals of different frequencies to the frequency control terminals SW, thereby achieving different refresh rates in different areas and enabling different frequency driving for different areas of the display panel. For areas with high driving frequency requirements, the frequency signal lines can provide high-frequency signals to the frequency control terminals SW; for areas with low driving frequency requirements, the frequency signal lines can provide low-frequency signals to the frequency control terminals SW. This approach combines the advantages of high-frequency and low-frequency driving, ensuring smooth image display in high-frequency areas while saving power, extending standby time, and reducing the overall power consumption of the display panel.

[0103] By applying the pixel circuit of this embodiment to a local area of ​​the display panel, the refresh frequency of the pixel circuit can be controlled by controlling the frequency of the signal provided to the frequency control terminal, thereby realizing frequency conversion display of the local area of ​​the display panel.

[0104] Figure 4 This is a schematic diagram of the pixel circuit structure in another embodiment of this disclosure. Figure 4 As shown, the drive module 10 can be coupled to the first power supply terminal VDD. The pixel circuit may also include a third reset module 60, which is coupled to the fourth scan signal terminal Scan4, the third initial signal terminal Init3, and the input terminal of the drive module 10. The third reset module 60 is configured to provide the signal of the third initial signal terminal Init3 to the input terminal of the drive module 10 under the control of the fourth scan signal terminal Scan4.

[0105] The third reset module 60 can reset the input terminal of the drive module 10. Thus, before writing the data signal into the drive module 10, the third reset module 60 can provide the signal of the third initial signal terminal Init3 to the input terminal of the drive module 10 under the control of the fourth scan signal terminal Scan4, thereby resetting the input terminal of the drive module 10, preventing the residual signal from the previous process from affecting the current data writing process, and improving the display effect.

[0106] Figure 5 This is a schematic diagram of the pixel circuit structure in another embodiment of the present disclosure. In one embodiment, such as Figure 5 As shown, the pixel circuit may also include a first reset module 40, a second reset module 50, a first control module 70, a second control module 80, and a storage module 90.

[0107] In one embodiment, such as Figure 5As shown, the driving module 10 may include a driving transistor Td. The first terminal of the driving transistor Td can be the input terminal of the driving module 10, and the second terminal of the driving transistor Td can be the output terminal of the driving module 10. The control terminal of the driving transistor Td is coupled to the first node N1, and the first and second terminals of the driving transistor Td are coupled to the first power supply terminal VDD and the light-emitting element, respectively. For example, the first and second terminals of the driving transistor Td are coupled to the second node N2 and the third node N3, respectively. The second node N2 can be coupled to the first power supply terminal VDD through the first control module 70, and the third node N3 can be coupled to the light-emitting element through the second control module 80.

[0108] The write module 20 includes a fourth transistor T4. The control terminal of the fourth transistor T4 is coupled to the first scan signal terminal Scan1, and the first and second terminals of the fourth transistor T4 are coupled to the data signal terminal Data and the input terminal of the drive module 10, respectively. For example, as shown... Figure 5 As shown, the first and second terminals of the fourth transistor T4 are coupled to the data signal terminal Data and the second node N2, respectively.

[0109] The frequency control module 30 includes a fifth transistor T5 and a third transistor T3. The control terminal of the fifth transistor T5 is coupled to the second scan signal terminal Scan2, and the first and second terminals of the fifth transistor T5 are coupled to the output terminal of the drive module 10 and the fifth node N5, respectively. The control terminal of the third transistor T3 is coupled to the frequency control terminal SW, the first terminal of the third transistor T3 is coupled to the fifth node N5, and the second terminal of the third transistor T3 is coupled to the first node N1. The input terminal of the frequency control module 30 is the first terminal of the fifth transistor T5. Exemplarily, the first and second terminals of the fifth transistor T5 are coupled to the third node N3 and the fifth node N5, respectively, and the first and second terminals of the third transistor T3 are coupled to the fifth node N5 and the first node N1, respectively.

[0110] The first reset module 40 includes a sixth transistor T6. The control terminal of the sixth transistor T6 is coupled to the third scan signal terminal Scan3. The first and second terminals of the sixth transistor T6 are coupled to the first initial signal terminal Init1 and the frequency control module 30, respectively. For example, as shown... Figure 5 As shown, the second terminal of the sixth transistor T6 can be coupled to the fifth node N5.

[0111] The second reset module 50 includes a seventh transistor T7. The control terminal of the seventh transistor T7 is coupled to the fourth scan signal terminal Scan4. The first and second terminals of the seventh transistor T7 are coupled to the second initial signal terminal Init2 and the light-emitting element, respectively. For example, as shown... Figure 5 As shown, the second terminal of the seventh transistor T7 can be coupled to the fourth node N4, and the fourth node N4 is coupled to the light-emitting element.

[0112] The first control module 70 includes an eighth transistor T8. The control terminal of the eighth transistor T8 is coupled to the light-emitting control terminal EM. The first and second terminals of the eighth transistor T8 are coupled to the first power supply terminal VDD and the input terminal of the drive module 10, respectively.

[0113] The second control module 80 includes a ninth transistor T9. The control terminal of the ninth transistor T9 is coupled to the light-emitting control terminal EM. The first and second terminals of the ninth transistor T9 are coupled to the output terminal of the driving module 10 and the light-emitting element, respectively.

[0114] The storage module 90 may include a storage capacitor Cst, which is used to store the signal of the first node N1. One plate of the storage capacitor Cst may be coupled to the first node N1, and the other plate may be coupled to the first power supply terminal VDD.

[0115] In one embodiment, such as Figure 5 As shown, the fifth transistor T5 and the sixth transistor T6 can be N-type transistors, while the other transistors can be P-type transistors. The active layer material of the N-type transistor can include oxide, and the active layer material of the P-type transistor can include low-temperature polycrystalline silicon (LTPS). In one embodiment, the third transistor T3 can be either an N-type transistor or a P-type transistor, without specific limitation.

[0116] It should be noted that, Figure 5 The diagram illustrates an exemplary structure of the driver module 10, the write module 20, the frequency control module 30, the third reset module 60, the first reset module 40, the second reset module 50, the first control module 70, the second control module 80, and the storage module 90. Those skilled in the art will understand that the modules are not limited to these specific modules. Figure 5 Any structure shown can achieve its function.

[0117] Figure 6 This is a schematic diagram of the pixel circuit structure in another embodiment of the present disclosure. In one embodiment, such as Figure 6 As shown, the input terminal of the frequency control module 30 is coupled to the fifth node N5, and the frequency control terminal SW includes a first frequency control terminal SW1 and a second frequency control terminal SW2.

[0118] The driving module 10 can be coupled to the first node N1, the first power supply terminal VDD, and the fourth node N4. The driving module 10 is configured to provide an electrical signal to the fourth node N4 based on the signal of the first power supply terminal VDD under the control of the first node N1, so as to drive the light-emitting element to emit light.

[0119] The write module 20 is coupled to the first scan signal terminal Scan1, the data signal terminal Data, and the fifth node N5. The write module 20 is configured to provide the data signal from the data signal terminal Data to the fifth node N5 under the control of the first scan signal terminal Scan1.

[0120] The frequency control module 30 includes a frequency control submodule 32 and a signal gating submodule 31. The frequency control submodule 32 is coupled to the sixth node N6, the first node N1, and the fifth node N5. The signal gating submodule 31 is coupled to the second scan signal terminal Scan2, the second power supply terminal VGL, the first frequency control terminal SW1, the second frequency control terminal SW2, and the sixth node N6. The signal gating submodule 31 is configured to periodically provide the signal from the second scan signal terminal Scan2 to the sixth node N6 under the control of the first frequency control terminal SW1 and the second frequency control terminal SW2, so that the frequency control submodule 32, under the control of the sixth node N6, controls the frequency at which the data signal from the fifth node N5 is written to the first node N1.

[0121] For example, the signal gating submodule 31 can provide the sixth node N6 with either the signal of the second scan signal terminal Scan2 or the signal of the second power supply terminal VGL under the control of the first frequency control terminal SW1 and the second frequency control terminal SW2. For instance, when the signals provided by the first frequency control terminal SW1 and the second frequency control terminal SW2 are the first signals, the signal gating submodule 31 provides the sixth node N6 with the signal of the second scan signal terminal Scan2 under the control of the first signal; when the signals provided by the first frequency control terminal SW1 and the second frequency control terminal SW2 are the second signals, the signal gating submodule 31 provides the sixth node N6 with the signal of the second power supply terminal VGL under the control of the second signal.

[0122] When the signal gating submodule 31 provides the second scan signal terminal Scan2 to the sixth node N6, the frequency control submodule 32, under the control of the sixth node N6, controls the data signal of the second node N2 to be able to be written to the first node N1. When the signal gating submodule 31 provides the second power supply terminal VGL to the sixth node N6, the frequency control submodule 32, under the control of the sixth node N6, prevents the data signal of the second node N2 from being written to the first node N1.

[0123] exist Figure 3 In the pixel circuit shown, a periodic signal needs to be provided to the frequency control terminal SW so that the signal of the frequency control terminal SW can periodically control the input and output terminals of the frequency control module 30 to conduct. For example, in Figure 5In the process, the frequency control module 30 includes a third transistor T3. Data signals are written to the first node N1 through the third transistor T3. In order to meet the requirements of data signal writing, the signal used to control the third transistor T3 needs to meet specific conditions. Therefore, the signal provided to the frequency control terminal SW is affected by the data signal.

[0124] Compared to Figure 3 The pixel circuit shown, Figure 6 The pixel circuit shown may include a first frequency control terminal SW1 and a second frequency control terminal SW2. The first frequency control terminal SW1 and the second frequency control terminal SW2 can provide different signals. The signal gating submodule 31 is configured to periodically provide the second scan signal terminal Scan2 to the sixth node N6 under the control of the first frequency control terminal SW1 and the second frequency control terminal SW2, so that the frequency control submodule 32, under the control of the sixth node N6, controls the frequency at which the data signal of the fifth node N5 is written to the first node N1. In this way, as long as a signal allowing the second scan signal terminal Scan2 to pass is provided to the first frequency control terminal SW1 and the second frequency control terminal SW2 during the write data sub-stage of the refresh phase, the signal of the second scan signal terminal Scan2 can control the frequency control submodule 32 to conduct, allowing the data signal of the fifth node N5 to be written to the first node N1. In other stages, a signal allowing the signal of the second power supply terminal VGL to pass can be provided to the first frequency control terminal SW1 and the second frequency control terminal SW2. The signal of the second power supply terminal VGL can control the frequency control submodule 32 to be cut off, preventing the data signal of the fifth node N5 from being written to the first node N1.

[0125] Therefore, the pixel circuit of this disclosure can fully utilize the signals of the second scan signal terminal Scan2 and the second power supply terminal VGL present in the pixel circuit to control the frequency control submodule 32. Furthermore, since the signals of the first frequency control terminal SW1 and the second frequency control terminal SW2 do not directly control the frequency control submodule 32, the signals provided to the first frequency control terminal SW1 and the second frequency control terminal SW2 are unaffected by the data signal; only the signal line with lower power needs to be selected according to the devices in the signal gating submodule 31. Therefore, the pixel circuit of this disclosure can further reduce the power consumption of the pixel circuit.

[0126] Figure 7A This is a schematic diagram of the pixel circuit structure in another embodiment of the present disclosure. Figure 7B This is a schematic diagram of the pixel circuit structure in another embodiment of the present disclosure. In one embodiment, such as Figure 7AAs shown, the signal gating submodule 31 includes a first transistor T1 and a second transistor T2. The control terminal of the first transistor T1 is coupled to the first frequency control terminal SW1, and the first electrode of the first transistor T1 is coupled to the second scan signal terminal Scan2. The control terminal of the second transistor T2 is coupled to the second frequency control terminal SW2, and the first electrode of the second transistor T2 is coupled to the second power supply terminal VGL. The second electrodes of both the first transistor T1 and the second electrode of the second transistor T2 are coupled to the sixth node N6.

[0127] The frequency control submodule 32 includes a third transistor T3. The control terminal of the third transistor T3 is coupled to the sixth node N6. The first and second terminals of the third transistor T3 are coupled to the fifth node N5 and the first node N1, respectively.

[0128] For example, the third transistor T3 can be an N-type transistor. The first transistor T1 and the second transistor T2 can both be transistors of the same type; for example, both can be P-type transistors, or both can be N-type transistors. To selectively provide the second scan signal terminal Scan2 and the second power supply terminal VGL to the sixth node N6, when the first transistor T1 and the second transistor T2 are of the same type, the signals of the first frequency control terminal SW1 and the second frequency control terminal SW2 are different. For example, one of the signals of the first frequency control terminal SW1 and the second frequency control terminal SW2 can be high, and the other can be low.

[0129] For example, the first transistor T1 and the second transistor T2 can be different types of transistors, such as Figure 7B As shown, one of the first transistor T1 and the second transistor T2 is a P-type transistor, and the other is an N-type transistor. In this case, the signal of the first frequency control terminal SW1 and the signal of the second frequency control terminal SW2 can be the same, thus requiring only one frequency control signal. The first frequency control terminal SW1 and the second frequency control terminal SW2 can be combined into a single frequency control terminal SW.

[0130] It should be noted that, Figure 6 The diagram illustrates an exemplary structure of the signal gating submodule 31 and the frequency control submodule 32. Those skilled in the art will understand that the signal gating submodule 31 and the frequency control submodule 32 are not limited to... Figure 6 Any structure shown can achieve its function.

[0131] In one embodiment, such as Figure 7AAs shown, the input terminal of the driving module 10 is coupled to the first power supply terminal VDD, and the output terminal of the driving module 10 is coupled to the fourth node N4. The pixel circuit may also include a third reset module 60. The third reset module 60 is coupled to the fourth scan signal terminal Scan4, the third initial signal terminal Init3, and the input terminal of the driving module 10, and is configured to provide the signal of the third initial signal terminal Init3 to the input terminal of the driving module 10 under the control of the fourth scan signal terminal Scan4.

[0132] The write module 20 can be coupled to the input and output terminals of the drive module 10. The write module 20 provides the data signal of the data signal terminal Data to the fifth node N5 through the drive module 10.

[0133] The third reset module 60 can reset the input terminal of the drive module 10. Thus, before writing the data signal into the drive module 10, the third reset module 60 can provide the signal of the third initial signal terminal Init3 to the input terminal of the drive module 10 under the control of the fourth scan signal terminal Scan4, thereby resetting the input terminal of the drive module 10, preventing the residual signal from the previous process from affecting the current data writing process, and improving the display effect.

[0134] like Figure 7A As shown, the pixel circuit may further include a storage module 90, which is coupled to the first power supply terminal VDD and the first node N1, respectively. The storage module 90 is used to store the signal of the first node N1. The storage module 90 may include a storage capacitor Cst, one plate of which is coupled to the first node N1, and the other plate is coupled to the first power supply terminal VDD.

[0135] like Figure 7A As shown, the pixel circuit may further include a first reset module 40, which is coupled to a first initial signal terminal Init1, a third scan signal terminal Scan3, and a fifth node N5. The first reset module 40 is configured to provide the signal from the first initial signal terminal Init1 to the fifth node N5 under the control of the third scan signal terminal Scan3.

[0136] The pixel circuit may further include a second reset module 50, which is coupled to the fourth scan signal terminal Scan4, the second initial signal terminal Init2, and the fourth node N4. The second reset module 50 is configured to provide the signal of the second initial signal terminal Init2 to the fourth node N4 under the control of the fourth scan signal terminal Scan4.

[0137] The pixel circuit may further include a first control module 70, which is coupled to the light-emitting control terminal EM, the first power supply terminal VDD, and the input terminal of the driving module 10. The first control module 70 is configured to provide a signal from the first power supply terminal VDD to the input terminal of the driving module 10 under the control of the light-emitting control terminal EM. The input terminal of the driving module 10 is coupled to the second node N2.

[0138] The pixel circuit may further include a second control module 80, which is coupled to the light-emitting control terminal EM, the output terminal of the driving module 10, and the fourth node N4. The second control module 80 is configured to provide the output signal of the driving module 10 to the fourth node N4 under the control of the light-emitting control terminal EM. The output terminal of the driving module 10 is coupled to the third node N3.

[0139] In one embodiment, such as Figure 7A As shown, the driving module 10 includes a driving transistor Td. The control terminal of the driving transistor Td is coupled to the first node N1, and the first and second terminals of the driving transistor Td are coupled to the first power supply terminal VDD and the fourth node N4, respectively. For example, the first terminal of the driving transistor Td is coupled to the second node N2.

[0140] The write module 20 includes a fourth transistor T4 and a fifth transistor T5. The control terminals of both transistors T4 and T5 are coupled to the first scan signal terminal Scan1. The first and second terminals of the fourth transistor T4 are coupled to the data signal terminal Data and the input terminal of the drive module 10, respectively. The first and second terminals of the fifth transistor T5 are coupled to the output terminal of the drive module 10 and the fifth node N5, respectively. For example, the first and second terminals of the fourth transistor T4 are coupled to the data signal terminal Data and the second node N2, respectively. The first and second terminals of the fifth transistor T5 are coupled to the third node N3 and the fifth node N5, respectively.

[0141] The first reset module 40 includes a sixth transistor T6. The control terminal of the sixth transistor T6 is coupled to the third scan signal terminal Scan3. The first and second terminals of the sixth transistor T6 are coupled to the first initial signal terminal Init1 and the fifth node N5, respectively.

[0142] The second reset module 50 includes a seventh transistor T7. The control terminal of the seventh transistor T7 is coupled to the fourth scan signal terminal Scan4. The first and second terminals of the seventh transistor T7 are coupled to the second initial signal terminal Init2 and the fourth node N4, respectively.

[0143] The first control module 70 includes an eighth transistor T8. The control terminal of the eighth transistor T8 is coupled to the light-emitting control terminal EM. The first and second terminals of the eighth transistor T8 are coupled to the first power supply terminal VDD and the input terminal of the driving module 10, respectively. For example, the first and second terminals of the eighth transistor T8 are coupled to the first power supply terminal VDD and the second node N2, respectively.

[0144] The second control module 80 includes a ninth transistor T9. The control terminal of the ninth transistor T9 is coupled to the light-emitting control terminal EM. The first and second terminals of the ninth transistor T9 are coupled to the output terminal of the driving module 10 and the fourth node N4, respectively. For example, the first and second terminals of the ninth transistor T9 are coupled to the third node N3 and the fourth node N4, respectively.

[0145] It should be noted that, Figure 7A The diagram illustrates exemplary structures for each module. Those skilled in the art will understand that the modules are not limited to specific modules. Figure 7A Any structure shown can achieve its function.

[0146] One embodiment of this disclosure provides a driving method for a pixel circuit, which can be applied to the pixel circuit in any embodiment of this disclosure, for example, it can be applied to the embodiment of this disclosure. Figure 3 or Figure 6 The pixel circuit is shown. The driving process of the pixel circuit may include a refresh phase and a hold phase. In the refresh phase, the data signal of the first node N1 in the pixel circuit is refreshed; in the hold phase, the data signal of the first node N1 in the pixel circuit is held and not rewritten. The driving method of the pixel circuit includes the following steps.

[0147] During the refresh phase, at least during the period when the second scan signal terminal Scan2 provides the scan signal, the first signal is provided to the frequency control terminal SW, so that the frequency control module 30 writes the data signal of the input terminal (i.e., the fifth node N5) of the frequency control module 30 to the output terminal (i.e., the first node N1) of the frequency control module 30 under the control of the first signal.

[0148] During the holding phase, at least during the period when the second scan signal terminal Scan2 provides the scan signal, a second signal is provided to the frequency control terminal SW, so that the frequency control module 30, under the control of the second signal, prohibits the data signal at the input terminal of the frequency control module 30 from being written to the output terminal of the frequency control module 30.

[0149] It is understandable that the scanning signal can be interpreted as an effective signal that turns on the first and second terminals of the transistor.

[0150] When the second scan signal terminal Scan2 provides a scan signal and the frequency control terminal SW provides a first signal, the frequency control module 30 is turned on. Data signals at the input terminal of the frequency control module 30 can be written to its output terminal, thus refreshing the image corresponding to the pixel circuit. When the frequency control terminal SW provides the second signal, regardless of whether the second scan signal terminal Scan2 provides a scan signal, data signals at the input terminal of the frequency control module 30 are prohibited from being written to its output terminal, and the image corresponding to the pixel circuit will not be refreshed.

[0151] In one embodiment, the driving method for the pixel circuit may further include: during the refresh phase, providing a first signal to the frequency control terminal SW during the period when the third scan signal terminal Scan3 provides a scan signal to achieve a reset of the pixel circuit; during the hold phase, providing a second signal to the frequency control terminal SW during the period when the third scan signal terminal Scan3 provides a scan signal to prevent the pixel circuit from being reset.

[0152] In one embodiment, the driving method for the pixel circuit may further include: during the refresh phase, providing a first signal to the frequency control terminal SW, so that during the refresh phase, the pixel circuit can realize the reset of the first node N1 and the writing of data signals to the first node N1. During the hold phase, providing a second signal to the frequency control terminal SW to disable the reset and data writing of the first node N1 of the pixel circuit.

[0153] Figure 8 This is a schematic diagram of a pixel circuit driving method according to another embodiment of this disclosure. This disclosure also provides a pixel circuit driving method that can be applied to the methods described in this disclosure, such as... Figure 6 The pixel circuit shown. In Figure 6 In the pixel circuit shown, the frequency control terminal SW includes a first frequency control terminal SW1 and a second frequency control terminal SW2. The signals provided to the frequency control terminal SW include signals provided to the first frequency control terminal SW1 and signals provided to the second frequency control terminal SW2. For example... Figure 8 As shown, the driving method of the pixel circuit may include steps S810 to S820.

[0154] In step S810, during the refresh phase, at least during the period when the second scan signal terminal Scan2 provides the scan signal, a valid signal is provided to the first frequency control terminal SW1 and an invalid signal is provided to the second frequency control terminal SW2, so as to provide the signal of the second scan signal terminal Scan2 to the sixth node N6, enabling the data signal of the fifth node N5 to be written to the first node N1. The first signal includes the valid signal provided to the first frequency control terminal SW1 and the invalid signal provided to the second frequency control terminal SW2.

[0155] In step S820, during the holding phase, at least during the period when the second scan signal terminal Scan2 provides the scan signal, an invalid signal is provided to the first frequency control terminal SW1 and a valid signal is provided to the second frequency control terminal SW2 to provide the second power supply terminal VGL signal to the sixth node N6, thereby preventing the data signal of the fifth node N5 from being written to the first node N1. The second signal includes the invalid signal provided to the first frequency control terminal SW1 and the valid signal provided to the second frequency control terminal SW2.

[0156] In one embodiment, during the refresh phase, a first signal is provided to the first frequency control terminal SW1 and the second frequency control terminal SW2; during the hold phase, a second signal is provided to the first frequency control terminal SW1 and the second frequency control terminal SW2. That is, during the refresh phase, a valid signal is provided to the first frequency control terminal SW1 and an invalid signal is provided to the second frequency control terminal SW2; during the hold phase, an invalid signal is provided to the first frequency control terminal SW1 and a valid signal is provided to the second frequency control terminal SW2.

[0157] In one embodiment, the refresh phase may include a reset sub-phase and a data write sub-phase. In the reset sub-phase, a scan signal is provided to the second scan signal terminal Scan2, and scan signals are provided to the third scan signal terminals Scan3 and Scan4 in the pixel circuit to provide a first reset signal to the fifth node N5 and the first node N1; a third reset signal is provided to the input terminal of the driving module 10; and a second reset signal is provided to the fourth node N4, thus resetting the pixel circuit during the refresh phase. In the data write sub-phase, a scan signal is provided to the second scan signal terminal Scan2, and an effective level signal is provided to the first scan signal terminal Scan1 to provide a data signal to the fifth node N5 and a data signal to the first node N1. The storage module 90 can store the signal of the first node N1, allowing the light-emitting element to continue emitting light during the holding phase.

[0158] In one embodiment, the driving method for the pixel circuit may further include: in the reset sub-stage of the refresh phase, providing a scan signal to the second scan signal terminal, providing a valid signal to the first frequency control terminal SW1, and providing an invalid signal to the second frequency control terminal SW2. At this time, under the control of the third scan signal terminal Scan3, the first reset module 40 provides a first initial signal to the fifth node N5, and the frequency control module 30, under the control of the first signal, provides a first initial signal to the first node N1, thereby resetting the first node N1.

[0159] During the hold phase, and while the third scan signal terminal Scan3 provides the scan signal, an invalid signal is provided to the first frequency control terminal SW1, and an valid signal is provided to the second frequency control terminal SW2. Therefore, during the hold phase, the first initial signal of the fifth node N5 will not be provided to the first node N1, thus preventing a reset of the first node N1 during the hold phase.

[0160] Figure 9A for Figure 5 The diagram shows a timing diagram of a pixel circuit. The following section combines... Figure 5 and Figure 9A The driving process of the pixel circuit is explained in detail.

[0161] During the refresh phase, a first signal is provided to the frequency control terminal SW, thereby turning on the third transistor T3 under the control of the first signal.

[0162] During the reset phase, the signals of the third scan signal terminal Scan3 and the fourth scan signal terminal Scan4 are the same, and both Scan3 and Scan4 provide valid signals. Under the control of the third scan signal terminal Scan3, the sixth transistor T6 provides the first initial signal terminal Init1 to the fifth node N5 and the first node N1. Under the control of the fourth scan signal terminal Scan4, the seventh transistor T7 provides the second initial signal terminal Init2 to the fourth node N4. Under the control of the fourth scan signal terminal Scan4, the tenth transistor T10 provides the third initial signal terminal Init3 to the second node N2, thereby resetting the pixel circuit.

[0163] During the data writing sub-stage, the first scan signal terminal Scan1 provides a valid signal to the second scan signal terminal Scan2. The fourth transistor T4 is turned on under the control of the first scan signal terminal Scan1, and the fifth transistor T5 is turned on under the control of the second scan signal terminal Scan2. The data signal at the data signal terminal Data is written to the first node N1, and the storage capacitor Cst stores the signal of the first node N1.

[0164] During the reset and write data sub-stages of the refresh phase, the EM control terminal provides an invalid level signal to ensure the normal operation of the reset and write data processes.

[0165] During the light-emitting stage, the light-emitting control terminal EM provides a valid signal. Under the control of the light-emitting control terminal EM, the eighth transistor T8 provides the first power supply terminal VDD signal to the second node N2. Under the control of the data signal of the first node N1, the driving transistor Td provides the driving electrical signal to the third node N3 based on the signal of the second node N2. Under the control of the light-emitting control terminal EM, the ninth transistor T9 provides the driving electrical signal of the third node N3 to the fourth node N4 to drive the light-emitting element DL to emit light.

[0166] During the hold phase, the frequency control terminal SW provides the second signal, the third transistor T3 is in the off state, and the signal of the first node N1 is not affected by the fifth node N5. The signal of the first node N1 holds the data signal of the write data sub-phase, and the light-emitting element emits light when the light-emitting control terminal EM is an active signal. Since the data signal of the first node N1 does not change during the hold phase, the image corresponding to the pixel circuit does not change during the hold phase.

[0167] Figure 9B for Figure 7A The timing diagram of the pixel circuit is shown below. (Followed by...) Figure 7A and Figure 9B The driving process of the pixel circuit is described in detail. The first signal includes a valid level signal provided to the first frequency control terminal SW1 and an invalid level signal provided to the second frequency control terminal SW2; the second signal includes an invalid level signal provided to the first frequency control terminal SW1 and a valid level signal provided to the second frequency control terminal SW2.

[0168] During the refresh phase, a valid level signal (low level signal) is provided to the first frequency control terminal SW1, and an invalid level signal (high level signal) is provided to the second frequency control terminal SW2. Thus, under the control of the valid level signal at the first frequency control terminal SW1, the first transistor T1 provides the signal of the second scan signal terminal Scan2 to the sixth node N6. The signal of the sixth node N6 is the same as the signal of the second scan signal terminal Scan2.

[0169] During the reset phase, the signals of the third scan signal terminal Scan3 and the fourth scan signal terminal Scan4 are the same, and both Scan3 and Scan4 provide valid signals. Under the control of the third scan signal terminal Scan3, the sixth transistor T6 provides the first initial signal terminal Init1 to the fifth node N5 and the first node N1. Under the control of the fourth scan signal terminal Scan4, the seventh transistor T7 provides the second initial signal terminal Init2 to the fourth node N4. Under the control of the fourth scan signal terminal Scan4, the tenth transistor T10 provides the third initial signal terminal Init3 to the second node N2, thereby resetting the pixel circuit.

[0170] During the data writing sub-stage, the first scan signal terminal Scan1 provides a valid signal. Under the control of the first scan signal terminal Scan1, the fourth transistor T4 and the fifth transistor T5 write the data signal of the data signal terminal Data to the first node N1, and the storage capacitor Cst stores the signal of the first node N1.

[0171] During the reset and write data sub-stages of the refresh phase, the EM control terminal provides an invalid level signal to ensure the normal operation of the reset and write data processes.

[0172] During the light-emitting stage, the light-emitting control terminal EM provides a valid signal. Under the control of the light-emitting control terminal EM, the eighth transistor T8 provides the first power supply terminal VDD signal to the second node N2. Under the control of the data signal of the first node N1, the driving transistor Td provides the driving electrical signal to the third node N3 based on the signal of the second node N2. Under the control of the light-emitting control terminal EM, the ninth transistor T9 provides the driving electrical signal of the third node N3 to the fourth node N4 to drive the light-emitting element DL to emit light.

[0173] During the hold phase, an invalid level signal is provided to the first frequency control terminal SW1, and an valid level signal is provided to the second frequency control terminal SW2. Thus, under the control of the valid level signal at the second frequency control terminal SW2, the second transistor T2 provides the signal of the second power supply terminal VGL to the sixth node N6. The signal of the sixth node N6 is the same as the signal of the second power supply terminal VGL. The signal of the second power supply terminal VGL is the invalid level signal of the third transistor T3. Therefore, during the hold phase, the third transistor T3 is in the off state, and the signal of the first node N1 is not affected by the fifth node N5. The signal of the first node N1 holds the data signal of the write data sub-phase. When the light emission control terminal EM is a valid signal, the light emission element emits light. Since the data signal of the first node N1 does not change during the hold phase, the image corresponding to the pixel circuit does not change during the hold phase.

[0174] The technical solution in this embodiment controls the frequency at which data signals are written to the control terminal of the driving module by controlling the frequency at which the first signal is provided to the frequency control terminal (first frequency control terminal and second frequency control terminal), thereby controlling the image display frequency corresponding to the pixel circuit. Therefore, when the display panel uses the pixel circuit of this embodiment, variable frequency driving of the free display area can be achieved, and different driving frequencies can be achieved in different display areas, reducing the overall power consumption of the display panel.

[0175] Figure 10 This is a plan view of a display panel according to one embodiment of the present disclosure. The present disclosure also provides a display panel, such as... Figure 10As shown, the display panel includes gate lines, a first sub-signal line, a second sub-signal line, and a pixel circuit 100 in this embodiment. The second scan signal terminal Scan2 in the pixel circuit is coupled to the gate lines. The first frequency control terminal SW1 of the pixel circuit is coupled to the first sub-signal line, and the second frequency control terminal SW2 of the pixel circuit is coupled to the second sub-signal line. It can be understood that when the pixel circuit 100 uses... Figure 7B In the pixel circuit shown, the first sub-signal line and the second sub-signal line can be the same signal line.

[0176] Such a display panel can control the refresh frequency of the pixel circuit by controlling the frequency of the signals provided to the first sub-signal line and the second sub-signal line, thereby realizing frequency conversion display in the area where the pixel circuit is located.

[0177] The display panel may include at least two sub-display areas, and at least one sub-display area includes a plurality of pixel circuits 100 as described in the embodiments of this disclosure. For example, at least one sub-display area includes a plurality of pixel circuits 100 as described in the embodiments of this disclosure. Figure 6 or Figure 7A The pixel circuit shown has a second scan signal terminal Scan2 coupled to a gate line. The first frequency control terminal SW1 of the pixel circuit is coupled to a first sub-signal line, and the second frequency control terminal SW2 of the pixel circuit is coupled to a second sub-signal line. In this disclosure, when the frequency control terminal SW includes both a first frequency control terminal SW1 and a second frequency control terminal SW2, the frequency signal line may include a first sub-signal line and a second sub-signal line. The first sub-signal line may be coupled to the first frequency control terminal SW1, and the second sub-signal line may be coupled to the second frequency control terminal SW2.

[0178] In one embodiment, such as Figure 10 As shown, the display panel may include two sub-display areas, one of which, A, adopts the following... Figure 2 The pixel circuit shown, another sub-display area B uses, as shown in the figure. Figure 6 or Figure 7A The pixel circuit is shown. The display panel may include multiple gate lines, and the second scan signal terminal Scan2 of each pixel circuit is connected to the corresponding gate line. For example, the display panel may adopt a dual-gate structure, that is, each row of pixel circuits corresponds to two gate lines, the first scan signal terminal in the pixel circuit can be coupled to the first gate line, and the second scan signal terminal can be coupled to the second gate line.

[0179] For example, the base frequency is 120Hz. Sub-display area A refreshes according to the base frequency, and the refresh frequency of sub-display area A is 120Hz. The refresh frequency of sub-display area B is determined by the frequencies of the first frequency control terminal SW1, the second frequency control terminal SW2, and the gate signal. To make the refresh frequency of sub-display area B 10Hz, 120Hz can be set to contain 12 subframes of 10Hz each. Then, one frame period at a refresh frequency of 120Hz can be divided into 12 subframes, including 1 refresh frame and 11 hold frames. In the refresh frame, the first frequency control terminal SW1 provides a valid signal, the second frequency control terminal SW2 provides an invalid signal, and the first transistor T1, under the signal control of the first frequency control terminal SW1, provides the gate signal of the second scan signal terminal Scan2 to the sixth node N6; the third transistor T3, under the signal control of the sixth node N6, writes the data signal of the fifth node N5 into the first node N1, thereby realizing the refresh of the image corresponding to each pixel circuit. During frame holding, the first frequency control terminal SW1 provides an invalid signal, and the second frequency control terminal SW2 provides an valid signal. Under the signal control of the second frequency control terminal SW2, the second transistor T2 provides the signal of the second power supply terminal VGL to the sixth node N6. The third transistor T3 is turned off under the control of the sixth node N6, and the first node N1 maintains the data signal written in the refresh frame, thus maintaining the image corresponding to each pixel circuit. In this method, the frequency of the first signal provided by the frequency control terminal is 10Hz. This achieves frequency division display between sub-display area A and sub-display area B, which not only ensures the smoothness of the image in sub-display area A but also reduces the overall power consumption of the display panel.

[0180] Figure 11 This is a plan view of the display panel according to another embodiment of this disclosure. Figure 11 As shown, this includes multiple embodiments as described in this disclosure. Figure 6 or Figure 7A The pixel circuit shown has a third sub-display area, and there are at least two third sub-display areas. The refresh rates of these multiple third sub-display areas are different. The first frequency control terminal SW1 of the pixel circuit in different third sub-display areas is coupled to different first sub-signal lines, and the second frequency control terminal SW2 of the pixel circuit in different third sub-display areas is coupled to different second sub-signal lines. In other words, different third sub-display areas are coupled to different frequency signal lines, thus providing different frequencies of first signals to different third sub-display areas and achieving different refresh rates for each third sub-display area.

[0181] For example, the third sub-display area C1 can be coupled to the fifth frequency signal line S5. That is, the first frequency control terminal SW1 of each pixel circuit in the third sub-display area C1 is coupled to the first sub-signal line of the fifth frequency signal line S5, and the second frequency control terminal SW2 is coupled to the second sub-signal line of the fifth frequency signal line S5. The third sub-display area C2 can be coupled to the sixth frequency signal line S6. That is, the first frequency control terminal SW1 of each pixel circuit in the third sub-display area C2 is coupled to the first sub-signal line of the sixth frequency signal line S6, and the second frequency control terminal SW2 is coupled to the second sub-signal line of the sixth frequency signal line S6. The frequency at which the first signal is provided by the fifth frequency signal line S5 is different from the frequency at which the first signal is provided by the sixth frequency signal line S6. Therefore, the refresh frequency of the third sub-display area C1 is different from the refresh frequency of the third sub-display area C2, realizing different refresh rates for different areas of the display panel.

[0182] Figure 12 This is a plan view of a display panel according to one embodiment of the present disclosure. The present disclosure also provides a display panel, such as... Figure 12 As shown, the display panel includes multiple grid lines extending along a first direction X, and these grid lines are arranged along a second direction Y. The display panel includes multiple first sub-display areas arranged along the second direction Y. The second direction is not parallel to the first direction. For example, the second direction is perpendicular to the first direction.

[0183] The first sub-display area includes the pixel circuit 100 in any embodiment of this disclosure. The pixel circuit 100 includes a driving module 10, a writing module 20, and a frequency control module 30.

[0184] like Figure 3 As shown, the driving module 10 is coupled to the first node N1. The driving module 10 is configured to provide a driving electrical signal under the control of the signal of the first node N1. Exemplarily, the output terminal of the driving module 10 can be coupled to the light-emitting element, so that the driving electrical signal provided by the output terminal of the driving module 10 can drive the light-emitting element to emit light.

[0185] The write module 20 is coupled to the first scan signal terminal Scan1, the data signal terminal Data, and the input terminal of the frequency control module 30. The write module 20 is configured to provide the data signal from the data signal terminal Data to the input terminal of the frequency control module 30 under the control of the first scan signal terminal Scan1.

[0186] The frequency control module 30 can be coupled to the frequency control terminal SW and the second scan signal terminal Scan2. The frequency control module 30 is configured to control the frequency at which the data signal at the input terminal of the frequency control module 30 is written to the first node N1 based on the signal at the frequency control terminal SW and the signal at the second scan signal terminal Scan2.

[0187] In multiple first sub-display areas, the frequency control terminal SW of the pixel circuit is connected to the first frequency signal line S1, and the second scan signal terminal Scan2 of the pixel circuit is connected to the corresponding gate line in the first sub-display area. The refresh rates of the multiple first sub-display areas are different. For example, the frequency control terminal SW of the pixel circuit in all first sub-display areas is connected to the first frequency signal line S1, so that the frequency control terminal SW of the pixel circuit in all first sub-display areas is connected to the same frequency signal line S1.

[0188] The first frequency signal line S1 is configured to provide a first signal during the refresh phase of the first sub-display area and at least during the period when the corresponding gate line provides the gate signal, so that the frequency control module 30 in the first sub-display area writes the data signal at the input terminal of the frequency control module 30 into the first node N1 under the control of the first signal.

[0189] The first frequency signal line S1 is also configured to provide a second signal during the holding phase of the first sub-display area and at least during the period when the corresponding gate line provides the gate signal, such that the frequency control module 30 in the first sub-display area prohibits the data signal at the input terminal of the frequency control module 30 from being written to the first node N1 under the control of the second signal.

[0190] like Figure 12 As shown, in this embodiment, the gate lines extend along a first direction, and multiple first sub-display areas are arranged along a second direction, which is perpendicular to the first direction. Therefore, in the first display area, multiple gate lines sequentially provide gate signals. Each first sub-display area includes at least one row of pixel circuits, and in the first sub-display area, multiple rows of pixel circuits are provided with gate signals row by row.

[0191] The refresh frequencies of the multiple first sub-display areas are different. For each first sub-display area, during the refresh phase of the first sub-display area and at least during the period when the corresponding gate line provides the gate signal, the first frequency signal line S1 provides a first signal. Under the control of the first signal, the frequency control module 30 writes the data signal at its input terminal to the first node N1 to refresh the image of the first sub-display area. During the holding phase of the first sub-display area and at least during the period when the corresponding gate line provides the gate signal, the first frequency signal line S1 provides a second signal. Under the control of the second signal, the frequency control module 30 prevents the data signal at its input terminal from being written to the first node N1, thus holding the image of the first sub-display area.

[0192] for Figure 12The three first sub-display areas are configured such that, during the refresh phase of the first sub-display area E1 and at least during the period when the corresponding gate line provides a gate signal, the frequency control module 30 in the first sub-display area E1 writes the data signal at its input terminal to the first node N1 under the control of the first signal, thereby refreshing the first sub-display area E1. Similarly, during the refresh phase of the first sub-display area E2 and at least during the period when the corresponding gate line provides a gate signal, the frequency control module 30 in the first sub-display area E2 writes the data signal at its input terminal to the first node N1 under the control of the first signal, thus refreshing the first sub-display area E2. Finally, during the refresh phase of the first sub-display area E3 and at least during the period when the corresponding gate line provides a gate signal, the frequency control module 30 in the first sub-display area E3 writes the data signal at its input terminal to the first node N1 under the control of the first signal, thus refreshing the first sub-display area E3.

[0193] The first frequency signal line S1 is also configured to provide a second signal during the holding phase of the first sub-display area E1 and at least during the period when the corresponding gate signal is provided on the gate line, during the holding phase of the first sub-display area E2 and at least during the period when the corresponding gate signal is provided on the gate line, and during the holding phase of the first sub-display area E3 and at least during the period when the corresponding gate signal is provided on the gate line, so that the frequency control module 30 in each first sub-display area prohibits the data signal at the input terminal of the frequency control module 30 from being written to the first node N1 under the control of the second signal, thereby preventing the image of each first sub-display area from being refreshed during the holding phase.

[0194] In this embodiment, the first direction X is the row direction, and the second direction Y is the column direction. Multiple first gate lines are arranged along the second direction Y, and multiple first sub-display areas are arranged along the second direction Y. Each first sub-display area includes at least one row of pixel circuitry. The pixel circuitry can only perform the data writing phase when the gate lines provide gate signals. The gate signals in the display panel are provided row by row; therefore, the refresh time of each first sub-display area is different.

[0195] In this embodiment of the display panel, the refresh time of each first sub-display area is different. The frequency control terminals SW of the pixel circuits in multiple first sub-display areas are all connected to a first frequency signal line S1. Therefore, the first frequency signal line S1 can provide a first signal during the refresh period of each first sub-display area, thereby achieving image refresh of the corresponding first sub-display area. When the gate lines in the first sub-display area do not provide a gate signal, even if the first frequency signal line S1 provides a first signal, it will not cause the pixel circuits in that first sub-display area to refresh.

[0196] The display panel of this disclosure embodiment can not only realize frequency division display of multiple first sub-display areas, but also reduce the number of frequency signal lines used, which facilitates the wiring of the display panel.

[0197] In one embodiment, the pixel circuit in the display panel may employ the pixel circuit described in any embodiment of this disclosure. For example, the pixel circuit may employ... Figures 3 to 7A The pixel circuit shown in any one of the options.

[0198] Figure 13 This is a timing diagram of a display panel in one embodiment. For example, the display panel includes three first sub-display areas, the first sub-display areas employing... Figure 7A The pixel circuits are shown. Each first sub-display area includes two rows of pixel circuits. For example, first sub-display area E1 includes a first row of pixel circuits and a second row of pixel circuits; first sub-display area E2 includes a third row of pixel circuits and a fourth row of pixel circuits; first sub-display area E3 includes a fifth row of pixel circuits and a sixth row of pixel circuits. The refresh rate of first sub-display area E1 is 120Hz, the refresh rate of second sub-display area E2 is 60Hz, and the refresh rate of third sub-display area E3 is 40Hz. The first signal includes a valid level signal (low level signal) provided to the first frequency control terminal SW1 and an invalid level signal (high level signal) provided to the second frequency control terminal SW2; the second signal includes an invalid level signal (high level signal) provided to the first frequency control terminal SW1 and a valid level signal (low level signal) provided to the second frequency control terminal SW2. Figure 7A In the pixel circuit shown, the effective level signal provided by the first frequency control terminal SW1 is a low level signal, and the invalid level signal is a high level signal; the effective level signal provided by the second frequency control terminal SW2 is a low level signal, and the invalid level signal is a high level signal. The refresh process of each first sub-display area is described in detail below. Figure 13 In the diagram, the refresh phase of the first sub-display area E1 is shown using SX1, and the time period outside of SX1 is the hold phase of the first sub-display area E1; the refresh phase of the second sub-display area E2 is shown using SX2, and the time period outside of SX2 is the hold phase of the first sub-display area E2; the refresh phase of the third sub-display area E3 is shown using SX3, and the time period outside of SX3 is the hold phase of the first sub-display area E3. From Figure 13 As can be seen, the refresh time for each first sub-display area is different.

[0199] The refresh rate of the grid lines is 120Hz. Therefore, in the first sub-display area E1, the image is refreshed once for each row of pixels when the grid lines provide a grid signal. The refresh rate of the second sub-display area E2 is 60Hz. Therefore, in the second sub-display area E2, the image is refreshed once every other grid signal for each row of pixels. The refresh rate of the third sub-display area E3 is 40Hz. Therefore, in the third sub-display area E3, the image is refreshed once every two grid signals for each row of pixels.

[0200] like Figure 13 As shown, at least when gate lines G1 and G2 provide gate signals, the first frequency control terminal SW1 provides an effective level signal (low level signal), and the second frequency control terminal SW2 provides an invalid level signal (high level signal). Under the control of the first frequency control terminal SW1 and the second frequency control terminal SW2, the frequency control module 30 provides the gate signal of G1 or G2 to the sixth node N6 of the corresponding pixel circuit to realize the refresh of the pixel circuit in the first sub-display area E1.

[0201] like Figure 13 As shown, during the refresh phase of the first sub-display area E2 and the period when gate signals are provided by gate lines G3 and G4, the first frequency control terminal SW1 provides a valid level signal (low level signal), and the second frequency control terminal SW2 provides an invalid level signal (high level signal). Under the control of the first frequency control terminal SW1 and the second frequency control terminal SW2, the frequency control module 30 provides the gate signal of G3 or G4 to the sixth node N6 of the corresponding pixel circuit, thereby refreshing the pixel circuit in the first sub-display area E2. During the holding phase of the first sub-display area E2 and the period when gate signals are provided by gate lines G3 and G4, the first frequency control terminal SW1 provides an invalid level signal, and the second frequency control terminal SW2 provides a valid level signal. Under the control of the first frequency control terminal SW1 and the second frequency control terminal SW2, the frequency control module 30 provides the signal of the second power supply terminal VGL to the sixth node N6 of the corresponding pixel circuit, preventing data signals in the pixel circuit from being written to the first node N1, thus holding the image in the first sub-display area E2.

[0202] like Figure 13As shown, during the refresh phase of the first sub-display area E3 and the period when gate signals are provided by gate lines G5 and G6, the first frequency control terminal SW1 provides a valid level signal (low level signal), and the second frequency control terminal SW2 provides an invalid level signal (high level signal). Under the control of the first frequency control terminal SW1 and the second frequency control terminal SW2, the frequency control module 30 provides the gate signal of G5 or G6 to the sixth node N6 of the corresponding pixel circuit, thereby refreshing the pixel circuit in the first sub-display area E3. During the holding phase of the first sub-display area E3 and the period when gate signals are provided by gate lines G5 and G6, the first frequency control terminal SW1 provides an invalid level signal (high level signal), and the second frequency control terminal SW2 provides a valid level signal (low level signal). Under the control of the first frequency control terminal SW1 and the second frequency control terminal SW2, the frequency control module 30 provides the signal of the second power supply terminal VGL to the sixth node N6 of the corresponding pixel circuit, preventing data signals in the pixel circuit from being written to the first node N1, thus holding the image in the first sub-display area E3.

[0203] exist Figure 13 During the holding phase of the first sub-display area E2 and the periods when grid lines G3 and G4, and the holding phase of the first sub-display area E3 and the periods when grid lines G5 and G6 provide grid signals, the first frequency control terminal SW1 provides an invalid level signal (high level signal), and the second frequency control terminal SW2 provides an valid level signal (low level signal) to prevent the first sub-display areas E2 and E3 from refreshing the image during the grid signal holding phase. During other periods, the first frequency control terminal SW1 provides a valid level signal (low level signal), and the second frequency control terminal SW2 provides an invalid level signal (high level signal).

[0204] Figure 14 This is a plan view of the display panel according to another embodiment of this disclosure. Figure 14 As shown, the display panel may further include at least one second sub-display area, the refresh rate of which is different from that of the first sub-display area. The frequency control terminal SW of the pixel circuit in the second sub-display area is coupled to the second frequency signal line S2.

[0205] The second frequency signal line S2 is configured to provide a first signal during the refresh phase of the second sub-display area and at least during the period when the corresponding gate line provides a gate signal, and to provide a second signal during the hold phase of the second sub-display area and at least during the period when the corresponding gate line provides a gate signal.

[0206] When the second frequency signal line S2 provides the first signal, the frequency control module 30 in the pixel circuit of the second sub-display area, under the control of the first signal, writes the data signal at the input terminal of the frequency control module 30 to the first node N1, thereby refreshing the image of the second sub-display area. When the second frequency signal line S2 provides the second signal, the frequency control module 30 in the pixel circuit of the second sub-display area, under the control of the second signal, prevents the data signal at the input terminal of the control module from being written to the first node N1, thus maintaining the image of the second sub-display area.

[0207] In one embodiment, such as Figure 14 As shown, there can be multiple second sub-display areas, arranged along a second direction. Each of the multiple second sub-display areas has a different refresh rate. The frequency control terminal SW of the pixel circuit in each second sub-display area is coupled to a different second frequency signal line S2. It is understood that "multiple" in this disclosure refers to at least two.

[0208] For example, Figure 14 In this configuration, there can be three second sub-display areas. The frequency control terminal SW of the pixel circuit in the second sub-display area F1 can be coupled to the second frequency signal line S2. The frequency control terminal SW of the pixel circuit in the second sub-display area F2 can be coupled to the third frequency signal line S3. The frequency control terminal SW of the pixel circuit in the second sub-display area F3 can be coupled to the fourth frequency signal line S4.

[0209] The second frequency signal line S2 is configured to provide a first signal during the refresh phase of the second sub-display area F1 and at least during the period when the corresponding gate line provides a gate signal, and to provide a second signal during the hold phase and at least during the period when the corresponding gate line provides a gate signal.

[0210] The third frequency signal line S3 is configured to provide a first signal during the refresh phase of the second sub-display area F2 and at least during the period when the corresponding gate line provides a gate signal, and to provide a second signal during the hold phase and at least during the period when the corresponding gate line provides a gate signal.

[0211] The fourth frequency signal line S4 is configured to provide a first signal during the refresh phase of the second sub-display area F3 and at least during the period when the corresponding gate line provides a gate signal, and to provide a second signal during the hold phase and at least during the period when the corresponding gate line provides a gate signal.

[0212] Figure 14 The plurality of second sub-display areas shown are located below the plurality of first sub-display areas. It is understood that the plurality of second sub-display areas may be located above the plurality of first sub-display areas, or the plurality of second sub-display areas may be located between two adjacent first sub-display areas.

[0213] In one embodiment, the input terminal of the driving module 10 is coupled to the first power supply terminal VDD. The pixel circuit also includes a third reset module 60, which is coupled to the fourth scan signal terminal Scan4, the third initial signal terminal Init3, and the input terminal of the driving module 10, and is configured to provide the signal of the third initial signal terminal Init3 to the input terminal of the driving module 10 under the control of the fourth scan signal terminal Scan4.

[0214] In one embodiment, the pixel circuit in the display panel can be adopted as follows: Figure 5 and Figure 7A The pixel circuit is shown. For each sub-display area, the frequency signal line is also configured to provide a first signal during the refresh phase of the sub-display area and at least during the period when the corresponding third scan signal terminal Scan3 provides a scan signal, so that the frequency control module 30 in the sub-display area writes the first initial signal of the input terminal of the frequency control module 30 to the first node N1 under the control of the first signal, thereby resetting the pixel circuit so that the next data signal can be written to the first node N1.

[0215] The frequency signal line is also configured to provide a second signal during the hold phase of the sub-display area and at least during the period when the corresponding third scan signal terminal Scan3 provides a scan signal, so that the frequency control module 30 in the sub-display area is prohibited from writing the first initial signal of the input terminal of the frequency control module 30 to the first node N1 under the control of the second signal, thereby avoiding reset during the hold phase.

[0216] The light-emitting signal terminal is configured to provide invalid level signals to the first control module 70 and the second control module 80 during the reset sub-stage and write data sub-stage of the pixel circuit, and to provide valid level signals during the holding stage, so that the pixel circuit can provide driving electrical signals to the light-emitting element during the holding stage to drive the light-emitting element to emit light.

[0217] Figure 15 This is a plan view of the display panel according to another embodiment of this disclosure. Figure 15 As shown, the display panel includes at least two sub-display areas, and at least one sub-display area includes a pixel circuit as described in any embodiment of this disclosure. The second scan signal terminal Scan2 in the pixel circuit is connected to a gate line. The frequency control terminal SW in the pixel circuit can be coupled to a frequency signal line. The refresh rate of the sub-display area can be controlled by the signal provided by the frequency signal line.

[0218] In one embodiment, the sub-display area of ​​the pixel circuit using this disclosure can be a fourth sub-display area, and the number of fourth sub-display areas is at least two. The refresh rates of the multiple fourth sub-display areas can be different. When the pixel circuit is... Figure 6In the pixel circuit shown, the first frequency control terminal SW1 of the pixel circuit in each fourth sub-display area is coupled to different first sub-signal lines, and the second frequency control terminal SW2 of the pixel circuit in each fourth sub-display area is coupled to different second sub-signal lines. By controlling the signals provided to the first and second sub-signal lines, the refresh frequency of the fourth sub-display area can be controlled, enabling frequency-division display of multiple fourth sub-display areas.

[0219] Figure 16 This is a plan view of a display panel according to another embodiment of the present disclosure. In one embodiment, such as Figure 16 As shown, the display panel includes multiple sub-display areas, each sub-display area including the pixel circuitry in any embodiment of this disclosure. The display panel may further include a multiplexing circuit (MUX), where frequency control terminals in the pixel circuits of the multiple sub-display areas are coupled to different frequency signal lines. The multiple frequency signal lines are coupled to multiple output terminals of the multiplexing circuit. The display panel may also include control signal lines, the number of which is less than the number of frequency signal lines, and these control signal lines are coupled to the input terminals of the multiplexing circuit.

[0220] Figure 16The display panel shown includes four sub-display areas. The frequency control terminal of the pixel circuit in each sub-display area is coupled to different frequency signal lines S10, S11, S12, and S13. A multiplexing circuit is located in the bezel area and includes transistors TA, TB, TC, and TD. Frequency signal lines S10, S11, S12, and S13 are coupled to the second terminals of transistors TA, TB, TC, and TD, respectively. The first terminals of transistors TA and TB are coupled to control signal line F1, and the first terminals of transistors TC and TD are coupled to control signal line F2. The display panel may also include control lines SA and SB. Control line SA is coupled to the gates of transistors TA and TC, and control line SB is coupled to the gates of transistors TB and TD. When frequency signal line S10 requires a first signal, control line SA provides an active level, and control signal line F1 provides the first signal, thus providing the first signal to sub-display area 1. When frequency signal line S11 requires the first signal, control line SB provides an active level, and control signal line F1 provides the first signal, thus providing the first signal to sub-display area 2. When frequency signal line S12 requires the first signal, control line SA provides an active level, and control signal line F2 provides the first signal, thus providing the first signal to sub-display area 3. When frequency signal line S13 requires the first signal, control line SB provides an active level, and control signal line F2 provides the first signal, thus providing the first signal to sub-display area 4. Using the same principle, a second signal can be provided to the sub-display area as needed. This method enables time-division control of the four sub-display areas. By using a multiplexing circuit, the four frequency signal lines provided to the display panel are replaced with two control signal lines, reducing the number of signal lines provided to the display panel. This allows for a reduction in the size of the driver chip, which is beneficial for reducing the bezel size of the display panel.

[0221] It should be noted that, Figure 16 The MUX shown is a 1:2 structure. In actual implementation, the ratio structure of the MUX can be set as needed.

[0222] Figure 17 This is a schematic diagram of a driving method for a display panel according to one embodiment of the present disclosure. The present disclosure also provides a driving method for a display panel, applicable to the display panel in any embodiment of the present disclosure. Figure 17 As shown, the driving method for the display panel includes steps S1710 to S1720.

[0223] In step S1710, during the refresh phase of the first sub-display area, a first signal is provided to the first frequency signal line S1 at least during the period when the corresponding gate line provides the gate signal, so that the data signal at the input terminal of the frequency control module 30 of the pixel circuit in the first sub-display area is written to the first node N1.

[0224] In step S1720, during the holding phase of the first sub-display area, a second signal is provided to the first frequency signal line S1 at least during the period when the corresponding gate line provides the gate signal, thereby preventing the data signal at the input terminal of the frequency control module 30 of the pixel circuit in the first sub-display area from being written to the first node N1.

[0225] In one embodiment, the driving method for the display panel may further include: during the refresh phase of the first sub-display area, providing a first signal to the first frequency signal line S1 during the period when the third scan signal terminal Scan3 in the pixel circuit provides a scan signal to reset the first node N1; and during the hold phase of the first sub-display area, providing a second signal to the first frequency signal line S1 during the period when the third scan signal terminal Scan3 in the pixel circuit provides a scan signal to prevent the first node N1 from being reset.

[0226] The first sub-display area adopts Figure 6 and Figure 7A The driving process of the display panel of the pixel circuit shown has been described above and will not be repeated here.

[0227] In one embodiment, the first sub-display area of ​​the display panel can be adopted Figure 5 The pixel circuit shown. For example, as Figure 12 As shown, the display panel includes three first sub-display areas, and the first sub-display areas adopt... Figure 5 The pixel circuits are shown. Each first sub-display area may include multiple rows of pixel circuits; for ease of explanation, only one row of pixel circuits is shown for each first sub-display area. For example, first sub-display area E1 shows the i-th row of pixel circuits; first sub-display area E2 shows the j-th row of pixel circuits; and first sub-display area E3 shows the k-th row of pixel circuits. The refresh rate of first sub-display area E1 is 120Hz, the refresh rate of second sub-display area E2 is 60Hz, and the refresh rate of third sub-display area E3 is 40Hz. The first signal is a valid level signal provided to the frequency control terminal SW; the second signal is an invalid level signal provided to the frequency control terminal SW. Figure 5 In the pixel circuit shown, the effective level signal provided by the frequency control terminal SW is a low level signal, and the invalid level signal is a high level signal. Figure 18 In one embodiment of this disclosure, the display panel adopts Figure 5 The diagram shows a timing sequence of the pixel circuit. The following is a related... Figure 5 and Figure 18 Provide a detailed explanation of the refresh process for each first sub-display area in the display panel. Figure 18In the diagram, the refresh phase of the first sub-display area E1 is shown using SX1, and the time period outside of SX1 is the holding phase of the first sub-display area E1; the refresh phase of the second sub-display area E2 is shown using SX2, and the time period outside of SX2 is the holding phase of the first sub-display area E2; the refresh phase of the third sub-display area E3 is shown using SX3, and the time period outside of SX3 is the holding phase of the first sub-display area E3.

[0228] The refresh rate of the grid lines is 120Hz. Therefore, in the first sub-display area E1, the image is refreshed once for each row of pixels when the grid lines provide a grid signal. The refresh rate of the second sub-display area E2 is 60Hz. Therefore, in the second sub-display area E2, the image is refreshed once for each row of pixels every other grid signal. The refresh rate of the third sub-display area E3 is 40Hz. Therefore, in the third sub-display area E3, the image is refreshed once for each row of pixels every two grid signals.

[0229] like Figure 18 As shown, in the first sub-display area E1, when the third scan signal terminal Scan3 of the pixel circuit provides a scan signal and the gate line G1 provides a gate signal, an effective level signal (low level signal) is provided to the frequency control terminal SW. Under the control of the frequency control terminal SW, the frequency control module 30 in the pixel circuit realizes the reset and refresh of the pixel circuit, thereby realizing the refresh of the image in the first sub-display area E1.

[0230] like Figure 18 As shown, during the refresh phase of the first sub-display area E2, when the third scan signal terminal Scan3 of the row pixel circuit provides a scan signal and the gate line G3 provides a gate signal, an effective level signal (low level signal) is provided to the frequency control terminal SW to achieve pixel reset and refresh, thereby achieving image refresh of the first sub-display area E2. During the holding phase of the first sub-display area E2, when the third scan signal terminal Scan3 of the pixel circuit provides a scan signal and the gate line G3 provides a gate signal, the frequency control terminal SW provides an ineffective level signal. Under the control of the frequency control terminal SW, the frequency control module 30 prohibits the reset and refresh of the first node N1, so that the image of the first sub-display area E2 is held.

[0231] like Figure 18As shown, during the refresh phase of the first sub-display area E3, when the third scan signal terminal Scan3 of the pixel circuit provides a scan signal and the gate line G5 provides a gate signal, an effective level signal (low level signal) is provided to the frequency control terminal SW to achieve pixel reset and refresh, thereby achieving image refresh of the first sub-display area E3. During the holding phase of the first sub-display area E3, when the third scan signal terminal Scan3 of the pixel circuit provides a scan signal and the gate line G5 provides a gate signal, and the frequency control terminal SW provides an ineffective level signal, the frequency control module 30, under the control of the frequency control terminal SW, prohibits the reset and refresh of the first node N1, so that the image of the first sub-display area E3 is held.

[0232] It should be noted that the detailed driving process of the display panel has been described above and will not be repeated here.

[0233] It should be noted that the planar schematic diagram of the display panel only exemplarily shows the number of sub-display areas and the number of pixel circuits. It is understood that those skilled in the art can divide the display panel into multiple sub-display areas according to the scheme of this disclosure, and the number of pixel rows and columns in each sub-display area can be set as needed. In the accompanying drawings, i, j, and k represent the number of rows of pixel circuits, and i, j, and k in different drawings can represent different values.

[0234] This disclosure also provides a display device, including the pixel circuit of any embodiment of this disclosure, or including the display panel of any embodiment of this disclosure. The display panel may be a liquid crystal display panel, an organic light-emitting diode (OLED) display panel, or a light-emitting diode (LED) display panel, etc.

[0235] The display device includes a display panel using the aforementioned embodiments. The display device can be any product or component with display functionality, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0236] In the description of this specification, it should be understood that the terms "center," "longitudinal," "transverse," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this disclosure.

[0237] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this disclosure, "multiple" means two or more, unless otherwise explicitly specified.

[0238] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection, an electrical connection, or a communication connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0239] In this disclosure, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0240] The foregoing disclosure provides many different implementations or examples for carrying out different structures of this disclosure. To simplify this disclosure, the components and arrangements of specific examples are described above. Of course, these are merely examples and are not intended to limit this disclosure. Furthermore, reference numerals and / or reference letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various implementations and / or arrangements discussed.

[0241] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any person skilled in the art can easily conceive of various variations or substitutions within the technical scope disclosed in this disclosure, and these should all be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A pixel circuit, characterized in that, include: The driving module, coupled to the first node, the first power supply terminal and the fourth node, is configured to provide an electrical signal to the fourth node based on the signal of the first power supply terminal under the control of the first node, so as to drive the light-emitting element to emit light. The write module, coupled to the first scan signal terminal, the data signal terminal, and the fifth node, is configured to provide the data signal from the data signal terminal to the fifth node under the control of the first scan signal terminal. A frequency control module includes a frequency control submodule and a signal gating submodule. The frequency control submodule is coupled to a sixth node, a first node, and a fifth node. The signal gating submodule is coupled to a second scan signal terminal, a second power supply terminal, a first frequency control terminal, a second frequency control terminal, and the sixth node. It is configured to periodically provide a signal from the second scan signal terminal to the sixth node under the control of the first frequency control terminal and the second frequency control terminal, so that the frequency control submodule controls the frequency at which the data signal from the fifth node is written to the first node under the control of the sixth node.

2. The pixel circuit according to claim 1, characterized in that, When the signal gating submodule provides the signal from the second scanning signal terminal to the sixth node, the frequency control submodule, under the control of the sixth node, controls the data signal of the fifth node to be able to be written to the first node; When the signal gating submodule provides the second power supply signal to the sixth node, the frequency control submodule, under the control of the sixth node, prohibits the data signal of the fifth node from being written to the first node.

3. The pixel circuit according to claim 1, characterized in that, The signal gating submodule includes a first transistor and a second transistor. The control terminal of the first transistor is coupled to the first frequency control terminal. The first electrode of the first transistor is coupled to the second scan signal terminal. The control terminal of the second transistor is coupled to the second frequency control terminal. The first electrode of the second transistor is coupled to the second power supply terminal. The second electrodes of the first transistor and the second electrode of the second transistor are both coupled to the sixth node. The frequency control submodule includes a third transistor, the control terminal of which is coupled to the sixth node, and the first and second terminals of which are coupled to the fifth node and the first node, respectively.

4. The pixel circuit according to claim 3, characterized in that, One of the first transistor and the second transistor is an N-type transistor, and the other is a P-type transistor; the signals at the first frequency control terminal and the second frequency control terminal are the same; or... Both the first transistor and the second transistor are either N-type transistors or both are P-type transistors, and one of the signals at the first frequency control terminal and the other at the second frequency control terminal is at a high level and the other is at a low level.

5. The pixel circuit according to claim 1, characterized in that, The input terminal of the driving module is coupled to the first power supply terminal, and the output terminal of the driving module is coupled to the fourth node. The pixel circuit further includes a third reset module, which is coupled to the fourth scan signal terminal, the third initial signal terminal and the input terminal of the driving module, and is configured to provide the signal of the third initial signal terminal to the input terminal of the driving module under the control of the fourth scan signal terminal.

6. The pixel circuit according to claim 1, characterized in that, The pixel circuit also includes: The storage module is coupled to the first power supply terminal and the first node respectively, and is used to store the signal of the first node; The first reset module is coupled to the first initial signal terminal, the third scan signal terminal and the fifth node respectively, and is configured to provide the signal of the first initial signal terminal to the fifth node under the control of the third scan signal terminal; The second reset module is coupled to the fourth scan signal terminal, the second initial signal terminal and the fourth node respectively, and is configured to provide the signal of the second initial signal terminal to the fourth node under the control of the fourth scan signal terminal; The first control module is coupled to the light-emitting control terminal, the first power supply terminal, and the input terminal of the driving module, respectively, and is configured to provide the signal from the first power supply terminal to the input terminal of the driving module under the control of the light-emitting control terminal. The second control module is coupled to the light-emitting control terminal, the output terminal of the driving module, and the fourth node, respectively, and is configured to provide the signal from the output terminal of the driving module to the fourth node under the control of the light-emitting control terminal.

7. The pixel circuit according to claim 6, characterized in that, The pixel circuit includes at least one of the following: The driving module includes a driving transistor, the control terminal of which is coupled to the first node, and the first and second terminals of which are coupled to the first power supply terminal and the fourth node, respectively. The writing module includes a fourth transistor and a fifth transistor. The control terminals of the fourth transistor and the fifth transistor are both coupled to the first scan signal terminal. The first and second terminals of the fourth transistor are coupled to the data signal terminal and the input terminal of the driving module, respectively. The first and second terminals of the fifth transistor are coupled to the output terminal of the driving module and the fifth node, respectively. The first reset module includes a sixth transistor, the control terminal of the sixth transistor is coupled to the third scan signal terminal, and the first and second terminals of the sixth transistor are coupled to the first initial signal terminal and the fifth node, respectively. The second reset module includes a seventh transistor, the control terminal of which is coupled to the fourth scan signal terminal, and the first and second terminals of which are coupled to the second initial signal terminal and the fourth node, respectively. The first control module includes an eighth transistor, the control terminal of which is coupled to the light-emitting control terminal, and the first and second terminals of which are coupled to the first power supply terminal and the input terminal of the driving module, respectively. The second control module includes a ninth transistor, the control terminal of which is coupled to the light-emitting control terminal, and the first and second terminals of which are coupled to the output terminal of the driving module and the fourth node, respectively.

8. A display panel, characterized in that, The display panel includes multiple gate lines extending along a first direction, the multiple gate lines being arranged along a second direction, and the display panel including multiple first sub-display areas arranged along the second direction, each of the first sub-display areas including pixel circuits. The pixel circuit includes a driving module, a writing module, and a frequency control module. The driving module is coupled to a first node and configured to provide a driving electrical signal under the control of the first node. The writing module is coupled to a first scan signal terminal, a data signal terminal, and the input terminal of the frequency control module and configured to provide the data signal from the data signal terminal to the input terminal of the frequency control module under the control of the first scan signal terminal. The frequency control module is coupled to a frequency control terminal, a second scan signal terminal, and the first node and configured to control the frequency at which the data signal from the input terminal of the frequency control module is written to the first node based on the signal from the frequency control terminal and the signal from the second scan signal terminal. The frequency control terminal in the pixel circuit of the plurality of first sub-display areas is connected to the first frequency signal line, and the second scanning signal terminal in the pixel circuit is connected to the corresponding gate line of the first sub-display area. The refresh frequencies of the plurality of first sub-display areas are different. The first frequency signal line is configured to provide a first signal during the refresh phase of the first sub-display area and at least during the period when the corresponding gate line provides a gate signal, so that the frequency control module in the first sub-display area writes the data signal at the input terminal of the frequency control module to the first node under the control of the first signal; The first frequency signal line is also configured to provide a second signal during the holding phase of the first sub-display area and at least during the period when the corresponding gate line provides a gate signal, such that the frequency control module in the first sub-display area, under the control of the second signal, prohibits the data signal at the input terminal of the frequency control module from being written to the first node.

9. The display panel according to claim 8, characterized in that, It also includes at least one second sub-display area, the refresh frequency of which is different from that of the first sub-display area, and the frequency control terminal of the pixel circuit in the second sub-display area is coupled to the second frequency signal line. The second frequency signal line is configured to provide the first signal during the refresh phase of the second sub-display area and at least during the period when the corresponding gate line provides a gate signal, and to provide the second signal during the hold phase of the second sub-display area and at least during the period when the corresponding gate line provides a gate signal.

10. The display panel according to claim 9, characterized in that, There are multiple second sub-display areas, which are arranged along the second direction. The refresh rates of the multiple second sub-display areas are different, and the frequency control terminals of the pixel circuits in each second sub-display area are coupled to different frequency signal lines.

11. The display panel according to claim 8, characterized in that, The input terminal of the driving module is coupled to the first power supply terminal. The pixel circuit further includes a third reset module, which is coupled to the fourth scan signal terminal, the third initial signal terminal and the input terminal of the driving module. The third reset module is configured to provide the signal of the third initial signal terminal to the input terminal of the driving module under the control of the fourth scan signal terminal.

12. The display panel according to any one of claims 8-11, characterized in that, The pixel circuit further includes a first reset module, a second reset module, a first control module, and a second control module, wherein the pixel circuit satisfies at least one of the following: The driving module includes a driving transistor, which is coupled to the first node. The first and second terminals of the driving transistor are coupled to a first power supply terminal and a light-emitting element, respectively. The writing module includes a fourth transistor, the control terminal of which is coupled to the first scan signal terminal, and the first and second terminals of which are coupled to the data signal terminal and the input terminal of the driving module, respectively. The frequency control module includes a fifth transistor and a third transistor. The control terminal of the fifth transistor is coupled to the second scan signal terminal. The first and second terminals of the fifth transistor are coupled to the output terminal of the driving module and the first terminal of the third transistor, respectively. The control terminal of the third transistor is coupled to the frequency control terminal. The second terminal of the third transistor is coupled to the first node. The first terminal of the fifth transistor is the input terminal of the frequency control module. The first reset module includes a sixth transistor, the control terminal of which is coupled to a third scan signal terminal, and the first and second terminals of which are coupled to a first initial signal terminal and the frequency control module, respectively. The second reset module includes a seventh transistor, the control terminal of which is coupled to a fourth scan signal terminal, and the first and second terminals of which are coupled to a second initial signal terminal and the light-emitting element, respectively. The first control module includes an eighth transistor, the control terminal of the eighth transistor is coupled to the light-emitting control terminal, and the first and second terminals of the eighth transistor are coupled to the first power supply terminal and the input terminal of the driving module, respectively. The second control module includes a ninth transistor, the control terminal of which is coupled to the light-emitting control terminal, and the first and second terminals of which are coupled to the output terminal of the driving module and the light-emitting element, respectively.

13. The display panel according to any one of claims 8-10, characterized in that, The pixel circuit adopts the pixel circuit of any one of claims 1-7.

14. A display panel, characterized in that, The system includes a gate line, a first sub-signal line, a second sub-signal line, and a pixel circuit as described in any one of claims 1-7, wherein a second scan signal terminal of the pixel circuit is coupled to the gate line, a first frequency control terminal of the pixel circuit is coupled to the first sub-signal line, and a second frequency control terminal of the pixel circuit is coupled to the second sub-signal line.

15. The display panel according to claim 14, characterized in that, The display panel includes a plurality of sub-display areas, and at least one of the sub-display areas includes a pixel circuit as described in any one of claims 1-7.

16. The display panel according to claim 14, characterized in that, The sub-display area including the pixel circuit as described in any one of claims 1-7 is a third sub-display area, the number of third sub-display areas is at least two, the refresh frequencies of the multiple third sub-display areas are different, the first frequency control terminal of the pixel circuit in different third sub-display areas is coupled to different first sub-signal lines, and the second frequency control terminal of the pixel circuit in different third sub-display areas is coupled to different second sub-signal lines.

17. A driving method for a pixel circuit, characterized in that, The method, applied to the pixel circuit of any one of claims 1-7, comprises: During the refresh phase, at least during the period when the second scan signal terminal provides the scan signal, a valid signal is provided to the first frequency control terminal and an invalid signal is provided to the second frequency control terminal, so as to provide the signal of the second scan signal terminal to the sixth node, so that the data signal of the fifth node can be written to the first node; During the holding phase, at least during the period when the second scan signal terminal provides the scan signal, an invalid signal is provided to the first frequency control terminal and an valid signal is provided to the second frequency control terminal to provide the signal of the second power supply terminal to the sixth node, thereby prohibiting the data signal of the fifth node from being written to the first node.

18. The method according to claim 17, characterized in that, The refresh phase includes a reset sub-phase and a write data sub-phase, and the method further includes: During the reset sub-stage, a scan signal is provided to the second scan signal terminal, and scan signals are provided to the third and fourth scan signal terminals in the pixel circuit to provide a first reset signal to the fifth node and a first reset signal to the first node; a third reset signal is provided to the input terminal of the drive module; and a second reset signal is provided to the fourth node. During the data writing sub-stage, a scan signal is provided to the second scan signal terminal, and an effective level signal is provided to the first scan signal terminal to provide a data signal to the fifth node and the data signal to the first node.

19. The driving method according to claim 18, characterized in that, The method further includes: In the reset sub-stage of the refresh phase, a valid signal is provided to the first frequency control terminal and an invalid signal is provided to the second frequency control terminal. During the holding phase and the period when the scanning signal is provided at the third scanning signal terminal, an invalid signal is provided to the first frequency control terminal and an valid signal is provided to the second frequency control terminal.

20. A driving method for a display panel, characterized in that, Applied to the display panel of any one of claims 8-13, the method comprises: During the refresh phase of the first sub-display area, at least during the period when the corresponding gate line provides the gate signal, a first signal is provided to the first frequency signal line, so that the data signal at the input end of the frequency control module of the pixel circuit in the first sub-display area is written to the first node; During the holding phase of the first sub-display area, at least during the period when the corresponding gate line provides the gate signal, the second signal is provided to the first frequency signal line to prevent the data signal at the input terminal of the frequency control module of the pixel circuit in the first sub-display area from being written to the first node.

21. The driving method according to claim 20, characterized in that, Also includes: During the refresh phase of the first sub-display area, the first signal is provided to the first frequency signal line during the period when the scanning signal is provided at the third scanning signal terminal in the pixel circuit, so as to reset the first node; During the holding phase of the first sub-display area, the second signal is provided to the first frequency signal line during the period when the third scan signal terminal in the pixel circuit provides the scan signal line, thereby prohibiting the reset of the first node.

22. A display device, characterized in that, It includes the pixel circuitry of any one of claims 1-7, or the display panel of any one of claims 8-16.

Images