Display driving circuit for cholesteric liquid crystal display device

Abstract

The present invention discloses a display driver circuit for a cholesteric liquid crystal display device, comprising three positive buffer groups, three negative buffer groups, a potential converter, and an output switch. The three positive buffer groups receive first to third reference voltages, respectively, and output first to third positive driving voltages, respectively. The three negative buffer groups receive fourth to sixth reference voltages, respectively, and output first to third negative driving voltages, respectively. The potential converter and the output switch are coupled to the three positive buffer groups and the three negative buffer groups, respectively, to receive the first to third positive driving voltages and the first to third negative driving voltages, and to generate output signals accordingly.

Description

Technical Field

[0001] The present invention relates to a display device, and in particular to a display driving circuit applied to a cholesteric liquid crystal display (ChLCD). Background Art

[0002] Current cholesteric liquid crystal full-color display systems utilize a three-layer stack of red (R), green (G), and blue (B) pixels. Advantages include: greater technological maturity, larger color display areas per pixel, and more saturated colors.

[0003] However, in current cholesteric liquid crystal full-color display systems, a considerable number of active and passive components must be installed on the printed circuit board (PCB) as driving voltage sources to provide driving voltage to the display driver circuit. In addition, the three-layer stacking of red (R), green (G), and blue (B) pixels further increases costs.

[0004] For example, if Figure 1 As shown, for a monochrome (e.g., red) pixel panel, at least three positive buffer groups PBF and three negative buffer groups NBF are required to be provided on the printed circuit board (PCB) to generate the first positive driving voltage VP1 to the third positive driving voltage VP3 and the first negative driving voltage VN1 to the third negative driving voltage VN3 to the display driving circuit, and as shown Figure 2A and Figure 2B As shown, each positive buffer group PBF / negative buffer group NBF requires two feedback resistors R1-R2 and one buffer BF. Therefore, a single-color (e.g., red) pixel panel requires 12 feedback resistors and 6 buffers. In other words, a three-color (i.e., red, green, and blue) pixel panel requires a total of 36 feedback resistors and 18 buffers, a considerable number. In addition, the connection wires and traces of the positive buffer group PBF and the negative buffer group NBF on the printed circuit board (PCB) must also consider their own current carrying capacity and resistance value, which will also increase the cost of the entire system.

[0005] In summary, the above problems encountered in the prior art still need to be further solved. Summary of the Invention

[0006] Therefore, the present invention proposes a display driving circuit for a cholesteric liquid crystal display device to effectively solve the above-mentioned problems encountered in the prior art.

[0007] According to a preferred embodiment of the present invention, a display driver circuit is provided for use in a cholesteric liquid crystal display device. In this embodiment, the display driver circuit includes three positive buffer groups, three negative buffer groups, a potential converter, and an output switch. The three positive buffer groups are configured to receive a first reference voltage, a second reference voltage, and a third reference voltage, respectively, and output a first positive driving voltage, a second positive driving voltage, and a third positive driving voltage, respectively. The three negative buffer groups are configured to receive a fourth reference voltage, a fifth reference voltage, and a sixth reference voltage, respectively, and output a first negative driving voltage, a second negative driving voltage, and a third negative driving voltage, respectively. The potential converter and the output switch are coupled to the three positive buffer groups and the three negative buffer groups, respectively, to receive the first positive driving voltage, the second positive driving voltage, the third positive driving voltage, the first negative driving voltage, the second negative driving voltage, and the third negative driving voltage, and generate output signals accordingly.

[0008] In one embodiment, the display driver circuit further includes a receiving circuit, a shift register, a control logic circuit, a decoder, and a data latch circuit. The receiving circuit receives an input data signal and an input clock signal, respectively. The shift register and the control logic circuit are coupled between the receiving circuit and the decoder and data latch circuit. The decoder and data latch circuit are coupled between the shift register and the control logic circuit and the level shifter and the output switch.

[0009] In one embodiment, the three positive buffer groups, the three negative buffer groups, the level shifter, and the output switch all receive a positive power voltage and a negative power voltage.

[0010] In one embodiment, the cholesteric liquid crystal display device includes a reference voltage generating circuit coupled to the display driving circuit for generating a first reference voltage, a second reference voltage, a third reference voltage, a fourth reference voltage, a fifth reference voltage, and a sixth reference voltage to the display driving circuit.

[0011] In one embodiment, the cholesteric liquid crystal display device further includes at least one display driving circuit identical to the display driving circuit. The at least one display driving circuit is coupled to the reference voltage generating circuit and receives the first reference voltage, the second reference voltage, the third reference voltage, the fourth reference voltage, the fifth reference voltage, and the sixth reference voltage.

[0012] In one embodiment, the cholesteric liquid crystal display device includes a positive power voltage generating circuit and a negative power voltage generating circuit coupled to the display driving circuit for generating a positive power voltage and a negative power voltage to the display driving circuit respectively.

[0013] In one embodiment, the cholesteric liquid crystal display device further includes at least one display driving circuit identical to the display driving circuit. The at least one display driving circuit is coupled to the positive power voltage generating circuit and the negative power voltage generating circuit and receives the positive power voltage and the negative power voltage.

[0014] In one embodiment, the reference voltage generating circuit, the positive power voltage generating circuit, and the negative power voltage generating circuit are disposed on a printed circuit board (PCB).

[0015] Another preferred embodiment of the present invention is also a display driving circuit applied to a cholesterol liquid crystal display device. In this embodiment, the cholesterol liquid crystal display device also includes at least a first display driving circuit and a second display driving circuit that are identical to the display driving circuit, and the display driving circuit, the first display driving circuit and the second display driving circuit are all coupled to a bus. The display driving circuit includes a positive buffer group, a negative buffer group, a potential converter and an output switch. The positive buffer group is used to receive a first reference voltage and output a first positive driving voltage to the bus. The negative buffer group is used to receive a fourth reference voltage and output a first negative driving voltage to the bus. The potential converter and the output switch are coupled to the bus to receive a first positive driving voltage, a first negative driving voltage, a second positive driving voltage, a third positive driving voltage, a second negative driving voltage and a third negative driving voltage from the bus and generate an output signal accordingly.

[0016] In one embodiment, a first display driver circuit, which is identical to the display driver circuit, receives the second reference voltage and the fifth reference voltage and outputs a second negative driving voltage and a second positive driving voltage to the bus. The first display driver circuit also receives a first positive driving voltage, a first negative driving voltage, a second positive driving voltage, a third positive driving voltage, a second negative driving voltage, and a third negative driving voltage from the bus and generates an output signal accordingly.

[0017] In one embodiment, a second display driving circuit that is identical to the display driving circuit receives a third reference voltage and a sixth reference voltage and outputs a third negative driving voltage and a third positive driving voltage to a bus. The second display driving circuit also receives a first positive driving voltage, a first negative driving voltage, a second positive driving voltage, a third positive driving voltage, a second negative driving voltage, and a third negative driving voltage from the bus and generates an output signal accordingly.

[0018] In one embodiment, the display driver circuit further includes a receiving circuit, a shift register, a control logic circuit, a decoder, and a data latch circuit. The receiving circuit receives an input data signal and an input clock signal, respectively. The shift register and the control logic circuit are coupled between the receiving circuit and the decoder and data latch circuit. The decoder and data latch circuit are coupled between the shift register and the control logic circuit and the level shifter and the output switch.

[0019] In one embodiment, the positive buffer set, the negative buffer set, the level shifter, and the output switch all receive a positive power voltage and a negative power voltage.

[0020] In one embodiment, the cholesterol liquid crystal display device further includes a reference voltage generating circuit, which is coupled to the display driving circuit, the first display driving circuit and the second display driving circuit respectively, for generating a first reference voltage, a second reference voltage, a third reference voltage, a fourth reference voltage, a fifth reference voltage and a sixth reference voltage.

[0021] In one embodiment, the cholesterol liquid crystal display device further includes a positive power supply voltage generating circuit and a negative power supply voltage generating circuit, which are respectively coupled to the display driving circuit, the first display driving circuit and the second display driving circuit to generate a positive power supply voltage and a negative power supply voltage to the display driving circuit, the first display driving circuit and the second display driving circuit.

[0022] In one embodiment, the reference voltage generating circuit, the positive power voltage generating circuit, and the negative power voltage generating circuit are disposed on a printed circuit board (PCB).

[0023] In one embodiment, the bus is disposed on a flexible printed circuit (FPC).

[0024] In one embodiment, the display driving circuit, the first display driving circuit, and the second display driving circuit are arranged adjacent to each other or spaced apart.

[0025] Compared to the prior art, the display driving circuit proposed in the present invention for use in a cholesterol liquid crystal display device integrates one or more driving voltage source groups having passive and active components into the interior of the device. This not only reduces design risks by utilizing the process compatibility of the original display driving circuit, but also effectively simplifies the design complexity of the printed circuit board (PCB), thereby significantly reducing its production cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 Schematic diagram of a cholesteric liquid crystal display device in the prior art.

[0027] Figure 2A and Figure 2B They are Figure 1 Schematic diagram of the positive buffer group and negative buffer group in .

[0028] Figure 3 for Figure 1 Schematic diagram of the display driver circuit in .

[0029] Figure 4 FIG. 4 is a schematic diagram of a cholesteric liquid crystal display device according to a specific embodiment of the present invention.

[0030] Figure 5 Schematic diagram of a display driving circuit used in a cholesteric liquid crystal display device.

[0031] Figure 6 FIG. 4 is a schematic diagram of a cholesteric liquid crystal display device in another embodiment of the present invention.

[0032] 7A to 7C Schematic diagrams of three display driving circuits applied to cholesteric liquid crystal display devices.

[0033] Description of main component symbols:

[0034] 1 Cholesteric Liquid Crystal Display

[0035] 11~1N display driver circuit

[0036] BOOST positive power supply voltage generation circuit

[0037] BUCK negative power supply voltage generation circuit

[0038] P-GAMMA reference voltage generation circuit

[0039] LDO low dropout voltage regulator circuit

[0040] PCB printed circuit board

[0041] FPC Flexible Printed Circuit

[0042] WOA array backplane circuit

[0043] PBF positive buffer group

[0044] NBF Negative Buffer Set

[0045] BUS bus

[0046] VPP positive supply voltage

[0047] VNN negative supply voltage

[0048] VDD operating voltage

[0049] REF1~REF6 First reference voltage to sixth reference voltage

[0050] VP1~VP3 First positive drive voltage~third positive drive voltage

[0051] VN1~VN3 First negative driving voltage~third negative driving voltage

[0052] R1~R2 feedback resistors

[0053] BF buffer

[0054] 110 Receiving Circuit

[0055] 111 Shift register and control logic circuit

[0056] 112 decoder and data latch circuit

[0057] 113 Potential Converter and Output Switch

[0058] OUT output signal

[0059] VPP positive supply voltage

[0060] VNN negative supply voltage

[0061] DAT_IN input data signal

[0062] CLK_IN input clock signal

[0063] STB / SDOE / SDOZ control signals

[0064] DIO data output and input indication signal

[0065] 4 Cholesteric Liquid Crystal Display

[0066] 41~4N display driver circuit

[0067] 410 receiving circuit

[0068] 411 Shift register and control logic circuit

[0069] 412 decoder and data latch circuit

[0070] 413 Potential Converter and Output Switch

[0071] 6 Cholesteric Liquid Crystal Display

[0072] 61~6N display driver circuit

[0073] 610 receiving circuit

[0074] 611 Shift register and control logic circuit

[0075] 612 decoder and data latch circuit

[0076] 613 Potential Converter and Output Switch

[0077] 620 receiving circuit

[0078] 621 Shift register and control logic circuit

[0079] 622 decoder and data latch circuit

[0080] 623 Potential Converter and Output Switch

[0081] 630 receiving circuit

[0082] 631 Shift register and control logic circuit

[0083] 632 decoder and data latch circuit

[0084] 633 Potential Converter and Output Switch DETAILED DESCRIPTION

[0085] A preferred embodiment of the present invention is a display driving circuit for a cholesteric liquid crystal display device. Figure 4 and Figure 5 As shown, Figure 4 This is a schematic diagram of a cholesteric liquid crystal display device 4 in this embodiment; Figure 5 FIG. 4 is a schematic diagram of a display driving circuit 41 applied to a cholesteric liquid crystal display device 4 .

[0086] like Figure 4 As shown, a cholesteric liquid crystal display device 4 includes a positive power supply voltage generator circuit BOOST, a negative power supply voltage generator circuit BUCK, a reference voltage generator circuit P-GAMMA, a low-dropout voltage regulator circuit LDO, and N display driver circuits 41-4N, where N is a positive integer. The positive power supply voltage generator circuit BOOST, the negative power supply voltage generator circuit BUCK, the reference voltage generator circuit P-GAMMA, and the low-dropout voltage regulator circuit LDO are all disposed on a printed circuit board (PCB) and coupled to a +12V power supply, but the present invention is not limited thereto. The printed circuit board PCB is coupled to the N display driver circuits 41-4N via a flexible printed circuit board (FPC) and a write-on-array (WOA) backplane.

[0087] The positive power supply voltage generating circuit BOOST is coupled to the N display driver circuits 41-4N, respectively, to generate a positive power supply voltage VPP for the N display driver circuits 41-4N. The negative power supply voltage generating circuit BUCK is coupled to the N display driver circuits 41-4N, respectively, to generate a negative power supply voltage VNN for the N display driver circuits 41-4N. The low-dropout voltage regulator circuit LDO is coupled to the N display driver circuits 41-4N, respectively, to generate an operating voltage VDD for the N display driver circuits 41-4N. The reference voltage generating circuit P-GAMMA is coupled to the N display driver circuits 41-4N, respectively, to generate a first reference voltage REF1, a second reference voltage REF2, a third reference voltage REF3, a fourth reference voltage REF4, a fifth reference voltage REF5, and a sixth reference voltage REF6 for the N display driver circuits 41-4N.

[0088] Next, the display driving circuit 41 will be taken as an example for description. Figure 5As shown, the display driving circuit 41 includes three positive buffer groups PBF, three negative buffer groups NBF, a receiving circuit 410 , a shift register and control logic circuit 411 , a decoder and data latch circuit 412 , and a level converter and output switch 413 .

[0089] The receiving circuit 410 is coupled to the shift register and control logic circuit 411 to receive the input data signal DAT_IN and the input clock signal CLK_IN. The shift register and control logic circuit 411 is coupled to the decoder and data latch circuit 412 to transmit and receive the data input / output indication signal DIO. The decoder and data latch circuit 412 is coupled to the level shifter and output switch 413 to receive the decoding and data latching control signals STB / SDOE / SDOZ and perform data decoding and latching operations.

[0090] The three positive buffer groups PBF are coupled to the potential converter and the output switch 413 to respectively receive the first reference voltage REF1, the second reference voltage REF2 and the third reference voltage REF3 from the reference voltage generating circuit P-GAMMA and respectively output the first positive driving voltage VP1, the second positive driving voltage VP2 and the third positive driving voltage VP3 to the potential converter and the output switch 413.

[0091] The three negative buffer groups NBF are coupled to the level shifter and output switch 413 to respectively receive the fourth reference voltage REF4, the fifth reference voltage REF5 and the sixth reference voltage REF6 from the reference voltage generating circuit P-GAMMA and respectively output the first negative driving voltage VN1, the second negative driving voltage VN2 and the third negative driving voltage VN3 to the level shifter and output switch 413.

[0092] In addition, the three positive buffer groups PBF, the three negative buffer groups NBF, the level converter and the output switch 413 also receive the positive power voltage VPP / negative power voltage VNN from the positive power voltage generating circuit BOOST / negative power voltage generating circuit BUCK respectively.

[0093] The level converter and output switch 413 is coupled to the three positive buffer groups PBF and the three negative buffer groups NBF respectively, and is used to receive the first positive driving voltage VP1, the second positive driving voltage VP2, the third positive driving voltage VP3, the first negative driving voltage VN1, the second negative driving voltage VN2 and the third negative driving voltage VN3 to generate the output signal OUT accordingly.

[0094] according to Figure 4 and Figure 5It can be seen that the cholesteric liquid crystal display device 4 in this embodiment utilizes the fact that the positive buffer group PBF and the negative buffer group NBF can share a common process with each of the display driver circuits 41-4N (all can use LV / HV = 3.3V / 50V). The three positive buffer groups PBF and the three negative buffer groups NBF are integrated into the display driver circuit 41, resulting in three positive buffer groups PBF and three negative buffer groups NBF embedded in the display driver circuit 41. These groups provide the first positive driving voltage VP1 to the third positive driving voltage VP3 and the first negative driving voltage VN1 to the third negative driving voltage VN3 required by the display driver circuit 41. The other display driver circuits 42-4N of the cholesteric liquid crystal display device 4 can be similarly described and are not further elaborated here.

[0095] Because the printed circuit board (PCB) in this embodiment does not require a large number of active and passive components to provide driving voltages to each display driver circuit as in the prior art, it only requires a reference voltage generation circuit P-GAMMA to provide first to sixth reference voltages REF1 to REF6 to three positive buffer groups PBF and three negative buffer groups NBF embedded in each display driver circuit. This significantly simplifies the circuit design on the PCB and effectively reduces production costs.

[0096] Another preferred embodiment of the present invention is also a display driving circuit for a cholesteric liquid crystal display device. Figure 6 and 7A to 7C As shown, Figure 6 This is a schematic diagram of a cholesteric liquid crystal display device 6 in this embodiment; 7A to 7C Schematic diagrams of three display driving circuits 61 - 63 respectively applied to the cholesteric liquid crystal display device 6 .

[0097] like Figure 6 As shown, the cholesteric liquid crystal display device 6 includes a positive power supply voltage generating circuit BOOST, a negative power supply voltage generating circuit BUCK, a reference voltage generating circuit P-GAMMA, a low-dropout voltage regulator circuit LDO, a bus BUS, and N display driver circuits 61-6N, where N is a positive integer and a multiple of 3 (i.e., three display driver circuits form a group). The positive power supply voltage generating circuit BOOST, the negative power supply voltage generating circuit BUCK, the reference voltage generating circuit P-GAMMA, and the low-dropout voltage regulator circuit LDO are all disposed on a printed circuit board (PCB) and coupled to a +12V power supply, but the present invention is not limited thereto. The printed circuit board PCB is coupled to the N display driver circuits 61-6N via a flexible printed circuit board (FPC) and an array backplane circuit WOA. The bus BUS is disposed on the flexible printed circuit board (FPC).

[0098] A positive power supply voltage generating circuit BOOST is coupled to the N display driver circuits 61-6N, respectively, to generate a positive power supply voltage VPP for the N display driver circuits 61-6N. A negative power supply voltage generating circuit BUCK is coupled to the N display driver circuits 61-6N, respectively, to generate a negative power supply voltage VNN for the N display driver circuits 61-6N. A low-dropout voltage regulator circuit LDO is coupled to the N display driver circuits 61-6N, respectively, to generate an operating voltage VDD for the N display driver circuits 61-6N. A reference voltage generating circuit P-GAMMA is coupled to the N display driver circuits 61-6N, respectively. A bus BUS is coupled to the N display driver circuits 61-6N, respectively.

[0099] Taking the display driver circuits 61-63 as an example, the reference voltage generating circuit P-GAMMA generates a first reference voltage REF1 and a fourth reference voltage REF4 for the display driver circuit 61, generates a second reference voltage REF2 and a fifth reference voltage REF5 for the display driver circuit 62, and generates a third reference voltage REF3 and a sixth reference voltage REF6 for the display driver circuit 63. The bus BUS receives the first positive driving voltage VP1 and the first negative driving voltage VN1 from the display driver circuit 61, the second positive driving voltage VP2 and the second negative driving voltage VN2 from the display driver circuit 62, and the third positive driving voltage VP3 and the third negative driving voltage VN3 from the display driver circuit 63, respectively. The bus BUS can provide the first positive driving voltage VP1 to the third positive driving voltage VP3 and the first negative driving voltage VN1 to the third negative driving voltage VN3 to each of the display driver circuits 61-63. The same applies to the other display driver circuits 64-6N, and will not be described in detail here.

[0100] Then, if Figure 7A As shown, Figure 7A for Figure 6 Schematic diagram of the display driving circuit 61 in FIG. Figure 7A As shown, the display driving circuit 61 includes a positive buffer group PBF, a negative buffer group NBF, a receiving circuit 610 , a shift register and control logic circuit 611 , a decoder and data latch circuit 612 , and a level converter and output switch 613 .

[0101] The receiving circuit 610 is coupled to the shift register and control logic circuit 611 to receive the input data signal DAT_IN and the input clock signal CLK_IN. The shift register and control logic circuit 611 is coupled to the decoder and data latch circuit 612 to transmit and receive the data input / output indication signal DIO. The decoder and data latch circuit 612 is coupled to the level shifter and output switch 613 to receive the decoding and data latching control signals STB / SDOE / SDOZ and perform data decoding and latching operations.

[0102] The positive buffer group PBF is configured to receive a first reference voltage REF1 from a reference voltage generating circuit P-GAMMA and output a first positive driving voltage VP1 to a bus BUS. The negative buffer group NBF is configured to receive a fourth reference voltage REF4 from the reference voltage generating circuit P-GAMMA and output a first negative driving voltage VN1 to a bus BUS. The level shifter and output switch 613 is coupled to the bus BUS and receives the first positive driving voltage VP1 to the third positive driving voltage VP3 and the first negative driving voltage VN1 to the third negative driving voltage VN3 from the bus BUS and generates an output signal OUT accordingly.

[0103] As for Figure 7B and Figure 7C They are Figure 6 The schematic diagram of the display driving circuit 62-63 in FIG. Figure 7A The same applies to the descriptions in the previous three paragraphs, so I will not elaborate on them here.

[0104] according to Figure 6 and 7A to 7C It can be seen that, taking the identical display driver circuits 61-63 as an example, the cholesteric liquid crystal display device 6 in this embodiment utilizes the characteristic that the positive buffer group PBF and the negative buffer group NBF can share the same process as the display driver circuit (both can use LV / HV=3.3V / 50V) to integrate the three positive buffer groups PBF and the three negative buffer groups NBF into the three display driver circuits 61-63, respectively. As a result, the three positive buffer groups PBF and the three negative buffer groups NBF are respectively embedded in the display driver circuits 61-63. Then, via a bus BUS and wiring provided on the flexible printed circuit (FPC), the first positive driving voltage VP1 and the first negative driving voltage VN1 provided by the display driver circuit 61, the second positive driving voltage VP2 and the second negative driving voltage VN2 provided by the display driver circuit 62, and the third positive driving voltage VP3 and the third negative driving voltage VN3 provided by the display driver circuit 63 are simultaneously shared by the three display driver circuits 61-63, thereby effectively reducing the area of ​​each display driver circuit 61-63. The same can be said for other display driving circuits 64 - 6N, which are not described in detail here.

[0105] Because the printed circuit board (PCB) in this embodiment does not require a large number of active and passive components to provide driving voltages to each display driver circuit as in the prior art, it only requires a reference voltage generation circuit P-GAMMA to provide different sets of reference voltages to different positive buffer groups PBF and negative buffer groups NBF embedded in each display driver circuit. The driving voltages are then shared among the display driver circuits using buses and traces on the flexible printed circuit board (FPC). This significantly simplifies the circuit design on the PCB and effectively reduces production costs.

[0106] Compared to the prior art, the display driving circuit proposed in the present invention for use in a cholesterol liquid crystal display device integrates one or more driving voltage source groups having passive and active components into the interior of the device. This not only reduces design risks by utilizing the process compatibility of the original display driving circuit, but also effectively simplifies the design complexity of the printed circuit board (PCB), thereby significantly reducing its production cost.

Claims

1. A display driving circuit, applied to a cholesteric liquid crystal display device, characterized in that: The display driving circuit includes: Three positive buffer groups, for respectively receiving a first reference voltage, a second reference voltage, and a third reference voltage and respectively outputting a first positive driving voltage, a second positive driving voltage, and a third positive driving voltage; three negative buffer groups for respectively receiving a fourth reference voltage, a fifth reference voltage, and a sixth reference voltage and respectively outputting a first negative driving voltage, a second negative driving voltage, and a third negative driving voltage; and a level converter and an output switch, respectively coupled to the three positive buffer groups and the three negative buffer groups, for receiving the first positive driving voltage, the second positive driving voltage, the third positive driving voltage, the first negative driving voltage, the second negative driving voltage, and the third negative driving voltage and generating an output signal accordingly; The device further includes a receiving circuit, a shift register, a control logic circuit, a decoder, and a data latch circuit; the receiving circuit receives an input data signal and an input clock signal respectively; the shift register and the control logic circuit are coupled between the receiving circuit and the decoder and the data latch circuit; and the decoder and the data latch circuit are coupled between the shift register and the control logic circuit and the potential converter and the output switch.

2. The display driving circuit according to claim 1, wherein: The three positive buffer groups, the three negative buffer groups, the level shifter and the output switch all receive a positive power supply voltage and a negative power supply voltage.

3. The display driving circuit according to claim 1, wherein: The cholesteric liquid crystal display device includes a reference voltage generating circuit coupled to the display driving circuit for generating the first reference voltage, the second reference voltage, the third reference voltage, the fourth reference voltage, the fifth reference voltage and the sixth reference voltage to the display driving circuit.

4. The display driving circuit according to claim 3, wherein: The cholesterol liquid crystal display device also includes at least one display driving circuit that is the same as the display driving circuit. The at least one display driving circuit is coupled to the reference voltage generating circuit and receives the first reference voltage, the second reference voltage, the third reference voltage, the fourth reference voltage, the fifth reference voltage, and the sixth reference voltage.

5. The display driving circuit according to claim 1, wherein: The cholesteric liquid crystal display device includes a positive power supply voltage generating circuit and a negative power supply voltage generating circuit, which are coupled to the display driving circuit and used to generate a positive power supply voltage and a negative power supply voltage to the display driving circuit respectively.

6. The display driving circuit according to claim 5, wherein: The cholesteric liquid crystal display device further includes at least one display driving circuit that is the same as the display driving circuit. The at least one display driving circuit is coupled to the positive power voltage generating circuit and the negative power voltage generating circuit and receives the positive power voltage and the negative power voltage.

7. The display driving circuit according to claim 5, wherein: The reference voltage generating circuit, the positive power voltage generating circuit and the negative power voltage generating circuit are arranged on a printed circuit board.

8. A display driving circuit, applied to a cholesteric liquid crystal display device, characterized in that: The cholesteric liquid crystal display device further includes at least a first display driving circuit and a second display driving circuit that are identical to the display driving circuit, and the display driving circuit, the first display driving circuit, and the second display driving circuit are all coupled to a bus. The display driving circuit includes: a positive buffer group for receiving a first reference voltage and outputting a first positive driving voltage to the bus; a negative buffer set for receiving a fourth reference voltage and outputting a first negative driving voltage to the bus; and a level converter and an output switch coupled to the bus, for receiving the first positive driving voltage, the first negative driving voltage, the second positive driving voltage, the third positive driving voltage, the second negative driving voltage and the third negative driving voltage from the bus and generating an output signal accordingly; The device further includes a receiving circuit, a shift register, a control logic circuit, a decoder, and a data latch circuit; the receiving circuit receives an input data signal and an input clock signal respectively; the shift register and the control logic circuit are coupled between the receiving circuit and the decoder and the data latch circuit; and the decoder and the data latch circuit are coupled between the shift register and the control logic circuit and the potential converter and the output switch.

9. The display driving circuit according to claim 8, wherein: The first display driving circuit, which is the same as the display driving circuit, receives the second reference voltage and the fifth reference voltage and outputs the second negative driving voltage and the second positive driving voltage to the bus. The first display driving circuit also receives the first positive driving voltage, the first negative driving voltage, the second positive driving voltage, the third positive driving voltage, the second negative driving voltage and the third negative driving voltage from the bus and generates an output signal accordingly.

10. The display driving circuit according to claim 9, wherein: The second display driving circuit, which is identical to the display driving circuit, receives a third reference voltage and a sixth reference voltage and outputs the third negative driving voltage and the third positive driving voltage to the bus. The second display driving circuit also receives the first positive driving voltage, the first negative driving voltage, the second positive driving voltage, the third positive driving voltage, the second negative driving voltage and the third negative driving voltage from the bus and generates an output signal accordingly.

11. The display driving circuit according to claim 8, wherein: The positive buffer group, the negative buffer group, the level converter and the output switch all receive a positive power supply voltage and a negative power supply voltage.

12. The display driving circuit according to claim 10, wherein: The cholesteric liquid crystal display device further includes a reference voltage generating circuit, which is respectively coupled to the display driving circuit, the first display driving circuit and the second display driving circuit for generating the first reference voltage, the second reference voltage, the third reference voltage, the fourth reference voltage, the fifth reference voltage and the sixth reference voltage.

13. The display driving circuit according to claim 10, wherein: The cholesteric liquid crystal display device also includes a positive power supply voltage generating circuit and a negative power supply voltage generating circuit, which are respectively coupled to the display driving circuit, the first display driving circuit and the second display driving circuit to generate a positive power supply voltage and a negative power supply voltage to the display driving circuit, the first display driving circuit and the second display driving circuit.

14. The display driving circuit according to claim 13, wherein: The reference voltage generating circuit, the positive power voltage generating circuit and the negative power voltage generating circuit are arranged on a printed circuit board.

15. The display driving circuit according to claim 8, wherein: The bus is arranged on the flexible circuit board.

16. The display driving circuit according to claim 8, wherein: The display driving circuit, the first display driving circuit and the second display driving circuit are arranged adjacent to each other or spaced apart.

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