Layout structure and method of data sampling circuit

Abstract

The present application provides a layout structure and method for a data sampling circuit. The layout structure includes: multiple data signal modules, multiple data signal modules are arranged at intervals along a first direction; a selection signal module, which is used to generate a selection signal, and the data sampling circuit is used to read the data signal from the data signal module according to the selection signal, or write the data signal to the data signal module; multiple signal lines, multiple signal lines correspond to multiple data signal modules one by one, one end of the signal line is connected to the selection signal module, and the other end of the signal line is connected to the corresponding data signal module; wherein, at least one signal line is provided with a compensation resistor, which is used to make the difference in the delay of the selection signal reaching any two data signal modules less than a preset threshold. The present application adjusts the transmission impedance through the compensation resistor, balances the transmission time, improves the consistency of the selection signal reaching each data signal module, and thereby ensures the accuracy of data reading and writing.

Description

Technical Field

[0001] The present application relates to layout technology, and in particular to a layout structure and method for a data sampling circuit. Background Art

[0002] In dynamic random access memory (DRAM), data signals are sampled based on the data strobe signal (DQS) to write or read data. Typically, multiple data signals are grouped together and sampled using the same DQS signal. To ensure data signal accuracy, the DQS signals corresponding to the input / output ports of each data signal must be as consistent as possible.

[0003] In actual signal line layouts, the lengths of the signal lines between each data signal input / output port and the DQS signal output port vary, inevitably leading to phase shifts in the DQS signals corresponding to different data signals. Therefore, improving the consistency of the DQS signal reaching each data signal input / output port is an urgent issue to be addressed. Summary of the Invention

[0004] The present application provides a layout structure and method of a data sampling circuit to improve the consistency of a DQS signal reaching an input / output port of each data signal.

[0005] On the one hand, the present application provides a data sampling circuit layout structure, including: multiple data signal modules, the multiple data signal modules are arranged at intervals along a first direction; a selection signal module, used to generate a selection signal, and the data sampling circuit is used to read the data signal from the data signal module according to the selection signal, or write the data signal into the data signal module; multiple signal lines, the multiple signal lines correspond one-to-one to the multiple data signal modules, one end of the signal line is connected to the selection signal module, and the other end of the signal line is connected to the corresponding data signal module; wherein, at least one signal line is provided with a compensation resistor, used to make the difference in delay of the selection signal reaching any two data signal modules less than a preset threshold.

[0006] In some embodiments, the resistance of the compensation resistor is inversely proportional to the first distance, where the first distance is the length of a signal line connecting the strobe signal module and the corresponding data signal module.

[0007] In some embodiments, the compensation resistor is a metal resistor, and the compensation resistor and the signal line are arranged in the same layer, both configured as the first metal layer.

[0008] In some embodiments, the compensation resistor is a polysilicon resistor configured as a polysilicon layer; the signal line is configured as a second metal layer, and the compensation resistor and the signal line are electrically connected via a first contact structure.

[0009] In some embodiments, the compensation resistor includes a plurality of bottom resistors and an upper resistor arranged in an array; the plurality of bottom resistors are configured as a third metal layer or a polysilicon layer; the upper resistors are arranged in the same layer as the signal line and are both configured as a fourth metal layer; contact holes are provided at both ends of the bottom resistor, and the contact holes are used to form a second contact structure for electrically connecting to the signal line or the upper resistor when the bottom resistor is selected to be connected to the signal line; the upper resistor is used to realize electrical connection between the two bottom resistors through the second contact structure provided at both ends of the upper resistor when the plurality of bottom resistors are selected to be connected to the signal line.

[0010] In some embodiments, A rows and B columns of bottom-layer resistors of the compensation resistor are selected for connection to the signal line, where A is greater than or equal to 1 and B is greater than 1; the A bottom-layer resistors in each column are connected in series through A-1 upper-layer resistors; the second ends of the B bottom-layer resistors located in the Ath row are commonly connected to the selection signal module through the signal line, and the first ends of the B bottom-layer resistors located in the first row are commonly connected to the data signal module through the signal line.

[0011] In some embodiments, C rows and D columns of the compensation resistor are selected for connection to the signal line, where C is greater than or equal to 1, D is greater than 1 and D is an odd number; the bottom resistors in each column are connected in series through C-1 upper resistors; the second end of the bottom resistor located in the first column of the Cth row is connected to the selection signal module through the signal line; the second end of the bottom resistor located in the even columns of the Cth row and the odd columns whose column number is increased by one is connected through the upper resistor; the first end of the bottom resistor located in the Dth column of the first row is connected to the data signal module through the signal line; the first end of the bottom resistor located in the odd columns of the first row and the even columns whose column number is increased by one is connected through the upper resistor.

[0012] In some embodiments, the resistance values ​​of the plurality of bottom layer resistors are the same or different.

[0013] In some embodiments, compensation resistors are provided on a plurality of signal lines, wherein the patterns of the third metal layer or polysilicon layer used to form the bottom resistors are the same.

[0014] On the other hand, the present application provides a layout method for a data sampling circuit, wherein the layout structure of the data sampling circuit includes multiple data signal modules, which are arranged at intervals along a first direction; a selection signal module, which is used to generate a selection signal, and the data sampling circuit is used to read the data signal from the data signal module according to the selection signal, or write the data signal into the data signal module; multiple signal lines, which correspond one-to-one to the multiple data signal modules, one end of the signal line is connected to the selection signal module, and the other end of the signal line is connected to the corresponding data signal module; wherein at least one signal line is provided with a compensation resistor; the layout method includes: obtaining the delay of the selection signal reaching each data signal module; adjusting the compensation resistor so that the difference in the delay of the selection signal reaching any two data signal modules is less than a preset threshold.

[0015] In some embodiments, the resistance of the compensation resistor is inversely proportional to the first distance, where the first distance is the length of a signal line connecting the strobe signal module and the corresponding data signal module.

[0016] In some embodiments, the compensation resistor is a metal resistor, and the compensation resistor and the signal line are arranged in the same layer, both configured as the first metal layer; the compensation resistor is adjusted so that the difference in delay between the selection signal and any two data signal modules is less than a preset threshold, including: by modifying the width or length of the metal resistor in the layout of the first metal layer, adjusting the compensation resistor so that the difference in delay between the selection signal and any two data signal modules is less than a preset threshold.

[0017] In some embodiments, the compensation resistor is a polysilicon resistor configured as a polysilicon layer; the signal line is configured as a second metal layer, and the compensation resistor and the signal line are electrically connected through a first contact structure; the compensation resistor is adjusted so that the difference in delay between the selection signal and any two data signal modules is less than a preset threshold, including: by modifying the width or length of the polysilicon resistor in the layout of the polysilicon layer, adjusting the compensation resistor so that the difference in delay between the selection signal and any two data signal modules is less than a preset threshold.

[0018] In some embodiments, the compensation resistor includes a plurality of bottom resistors and an upper resistor arranged in an array; the plurality of bottom resistors are configured as a third metal layer or a polysilicon layer; the upper resistors are arranged in the same layer as the signal line and are all configured as a fourth metal layer; contact holes are provided at both ends of the bottom resistor, and the contact holes are used to form a second contact structure for electrically connecting to the signal line or the upper resistor when the bottom resistor is selected to be connected to the signal line; the upper resistor is used to realize the electrical connection between the two bottom resistors through the contact structure provided at its two ends when the plurality of bottom resistors are selected to be connected to the signal line; adjusting the compensation resistor so that the difference in delay of the selection signal reaching any two data signal modules is less than a preset threshold, including: adjusting the resistance value of the compensation resistor by modifying the layout of the fourth metal layer so that the difference in delay of the selection signal reaching any two data signal modules is less than a preset threshold.

[0019] In some embodiments, the resistance of the compensation resistor is adjusted by modifying the layout of the fourth metal layer, including: adjusting the number of upper resistors and the number of selected bottom resistors, and / or the resistance, and / or the connection method by modifying the layout of the fourth metal layer to adjust the resistance of the compensation resistor.

[0020] The layout structure and method of the data sampling circuit provided by the present application include: multiple data signal modules, the multiple data signal modules are arranged at intervals along a first direction; a selection signal module, which is used to generate a selection signal, and the data sampling circuit is used to read the data signal from the data signal module or write the data signal to the data signal module according to the selection signal; multiple signal lines, the multiple signal lines correspond one-to-one to the multiple data signal modules, one end of the signal line is connected to the selection signal module, and the other end of the signal line is connected to the corresponding data signal module; wherein at least one signal line is provided with a compensation resistor, which is used to make the difference in the delay of the selection signal reaching any two data signal modules less than a preset threshold. The present application adjusts the transmission impedance through the compensation resistor, balances the transmission time, improves the consistency of the selection signal reaching each data signal module, and thus ensures the accuracy of data reading and writing. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0022] Figure 1 A first layout of a data sampling circuit provided in an embodiment of the present application;

[0023] Figure 2 A second layout of a data sampling circuit provided in an embodiment of the present application;

[0024] Figure 3A third layout of a data sampling circuit provided in an embodiment of the present application;

[0025] Figure 4 A schematic diagram showing a layout comparison of a compensation resistor provided in an embodiment of the present application;

[0026] Figure 5 A schematic diagram of a layout modification of a compensation resistor provided in an embodiment of the present application;

[0027] Figure 6 A schematic diagram of a compensation resistor array provided in an embodiment of the present application Figure 1 ;

[0028] Figure 7 A schematic diagram of a compensation resistor array provided in an embodiment of the present application Figure 2 ;

[0029] Figure 8 A flow chart of a data sampling circuit layout method provided in an embodiment of the present application;

[0030] Figure 9 The present invention provides a schematic structural diagram of an electronic device according to an embodiment of the present application.

[0031] The above drawings illustrate specific embodiments of the present application, which will be described in more detail below. These drawings and the textual description are not intended to limit the scope of the present application in any way, but rather to illustrate the concepts of the present application to those skilled in the art by reference to specific embodiments. DETAILED DESCRIPTION

[0032] Exemplary embodiments are described in detail herein, with examples illustrated in the accompanying drawings. When the following description refers to the drawings, identical numerals in different figures represent identical or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with the present application. Rather, they are merely examples of apparatuses and methods consistent with certain aspects of the present application.

[0033] In dynamic random access memory (DRAM), data signals are sampled based on the data strobe signal (DQS) to write or read data. Typically, multiple data signals are grouped together and sampled using the same DQS signal. To ensure data signal accuracy, the DQS signals corresponding to the input / output ports of each data signal must be as consistent as possible.

[0034] In actual signal line layouts, the lengths of the signal lines between each data signal input / output port and the DQS signal output port vary, inevitably leading to phase shifts in the DQS signals corresponding to different data signals. Therefore, improving the consistency of the DQS signal reaching each data signal input / output port is an urgent issue to be addressed.

[0035] Figure 1 The layout structure and method of the data sampling circuit provided in this application can be applied to Figure 1 As shown in the layout diagram. Figure 1 As shown, in the layout, taking 8 data signals referring to the same DQS signal as an example, the input / output ports of these 8 data signals can be named DQ0 to DQ7 in sequence starting from 0. DQ0 to DQ7 are arranged along the first direction, and DQ0 to DQ7 are all set on the same side of the output end of the DQS signal.

[0036] Figure 1 The equivalent resistances of the signal lines, R0y, R0x, R1y, R1x, etc., are also shown. Clearly, the impedance of the DQS signal's transmission path to each DQ is different, which results in misalignment of the DQS signal edges received by the input / output ports of each data signal, making it impossible to guarantee the accuracy of the 8-bit data. Specifically, assuming the signal lines are of uniform width, the line for transmitting the DQS signal to DQ0 is relatively long, while the line for transmitting to DQ7 is relatively short. Therefore, starting from the moment the DQS signal is output, the DQS signal will arrive at DQ0 later than at DQ7. This misalignment affects the accuracy of data reading.

[0037] Figure 2 A second layout of a data sampling circuit is provided for an embodiment of the present application. In some embodiments, DQ0 to DQ3 are arranged on one side of the output end of the DQS signal, and DQ4 to DQ7 are arranged on the other side of the output end of the DQS signal. Assuming that the widths of the signal lines are consistent, under this symmetrical wiring method, the lengths of the signal lines corresponding to DQ3 and DQ4 are consistent, which can be understood as the equivalent resistance (R3y+R3x+R8) of the signal line corresponding to DQ3 is equal to the equivalent resistance (R4y+R4x+R8) of the signal line corresponding to DQ4. Furthermore, the maximum length difference of the 8 data lines is reduced, Figure 2 relatively Figure 1 To a certain extent, the consistency of DQS signal transmission to DQ0 to DQ7 is improved.

[0038] The improvement achieved by adjusting the wiring method mentioned above is limited. In order to further improve the consistency of DQS signal transmission to multiple DQ ports, the layout structure and method of the data sampling circuit provided in this application increase the transmission impedance by adding compensation resistors on the signal lines, balance the transmission time, and improve the consistency of DQS signals reaching the input / output ports of each data signal, thereby ensuring the consistency of data signal reading and writing.

[0039] The following specific embodiments describe in detail the technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0040] Example 1

[0041] Figure 3 This is a layout of a data sampling circuit provided in an embodiment of the present application. Figure 3 As shown, the layout includes: multiple data signal modules DQ0, DQ1...DQn, and the multiple data signal modules are arranged at intervals along the first direction; a selection signal module, which is used to generate a selection signal, and a data sampling circuit is used to read the data signal from the data signal module according to the selection signal, or write the data signal into the data signal module.

[0042] Multiple signal lines, each corresponding to a plurality of data signal modules, one end of the signal line is connected to the selection signal module, and the other end of the signal line is connected to the corresponding data signal module; wherein, at least one signal line is provided with a compensation resistor, which is used to make the difference in the delay of the selection signal reaching any two data signal modules less than a preset threshold.

[0043] Specifically, the impedance on the strobe signal transmission path is composed of the compensation resistor and the signal line itself ( Figure 3 The equivalent resistance R of the signal lines is shown. When impedance differences exist between multiple signal lines, compensating resistors are added to at least some of the signal lines to minimize the impedance of each transmission path. This allows the strobe signal to be transmitted to each data signal module as simultaneously as possible after output, ensuring the stability and consistency of each bit of collected data signal.

[0044] Furthermore, a data signal can remain stable within a period of time, and the effective edge of the selection signal can collect a stable and accurate data signal within this period of time. Therefore, the value of the preset threshold can be determined based on the length of time the data signal remains stable. Among them, the smaller the value of the preset threshold, the smaller the total impedance difference of each selection signal transmission path, and the higher the actual manufacturing process precision requirement. The embodiment of the present application does not limit the value of the preset threshold, and the specific value needs to be determined in combination with factors such as the actual chip type and the manufacturing process precision.

[0045] Furthermore, Figure 3 The layout structure shown in which multiple data signal modules are arranged on the same side of the selection signal module is only for example, and the embodiments of the present application do not limit the relative positions of the data signal module and the selection signal module.

[0046] Furthermore, the present embodiment does not impose any restrictions on the resistance value of the compensation resistor. In actual applications, it can be flexibly adjusted based on the delay of each data signal module receiving the strobe signal. It should be noted that when setting the compensation resistor, the total impedance of the strobe signal transmission path should not be too large to avoid excessively long transmission time of the strobe signal, which may fail to meet the timing requirements of normal storage.

[0047] In summary, the layout structure of the data sampling circuit provided in this embodiment increases the transmission impedance by adding compensation resistors on the signal lines, balances the transmission time, improves the consistency of the selection signal reaching the input / output port of each data signal, and thus ensures the accuracy of the data signal.

[0048] In some embodiments, the resistance of the compensation resistor is inversely proportional to the first distance, where the first distance is the length of a signal line connecting the strobe signal module and the corresponding data signal module.

[0049] Specifically, refer to Figure 3 , the distance from DQ0 to DQn and the strobe signal gradually decreases, according to Figure 3 In the wiring structure shown, the length of the signal lines corresponding to DQ0 to DQn gradually decreases. Given a constant signal line width, the length of the signal line is proportional to its impedance. That is, the shorter the signal line, the lower the impedance provided on the transmission path. Accordingly, larger compensation resistors are installed on shorter signal lines to balance the impedance of the transmission paths corresponding to the data signal modules, ensuring that the difference in the delay between the selection signal reaching any two data signal modules is less than a preset threshold.

[0050] Furthermore, Figure 4A schematic diagram of a layout comparison of compensation resistors provided in an embodiment of the present application shows the layout of the compensation resistors corresponding to the data signal modules DQ0, DQ1 and DQ7 respectively. Among them, the compensation resistors of DQ1 and DQ0 are both single resistors, and the length of the compensation resistor corresponding to DQ1 is greater than the length of the compensation resistor corresponding to DQ0. The longer the length, the greater the resistance. The compensation resistor corresponding to DQ7 is a plurality of resistors arranged in parallel and connected in series, which can provide a greater impedance. The parallel arrangement saves layout space. The distances between DQ0, DQ1 and DQ7 and the selection signal module are progressive, and the resistance values ​​of the corresponding compensation resistors also increase in sequence.

[0051] In some embodiments, the compensation resistor is a metal resistor, and the compensation resistor and signal line are arranged on the same layer, both configured as the first metal layer. Specifically, the compensation resistor uses the same metal type M0 as the signal line. During layout design, the compensation resistor and signal line can be placed on the same layer to reduce the number of layout layers. Here, the compensation resistor can be regarded as a signal line with increased width.

[0052] In other embodiments, the compensation resistors are constructed from a different metal type than the signal lines. Specifically, the compensation resistors are placed in a separate layer, and the corresponding compensation resistors and signal lines are electrically connected via contact structures. This method separates the fabrication of the signal lines from the compensation resistors, facilitating flexible material selection for the compensation resistors.

[0053] In some further embodiments, the compensation resistor is a polysilicon resistor configured as a polysilicon layer; the signal line is configured as a second metal layer, and the compensation resistor and the signal line are electrically connected via a first contact structure.

[0054] Compare metal compensation resistors to polysilicon compensation resistors. Metal compensation resistors have a higher resistance per square unit than polysilicon compensation resistors. Therefore, for equivalent resistance, metal compensation resistors are shorter. Because metal compensation resistors are made of the same material as signal lines, they can be placed on the same layer without requiring contact structures. This reduces the load on the signal lines and increases transmission speeds.

[0055] Furthermore, polysilicon compensation resistors have higher process precision and smaller resistance deviation than metal compensation resistors. When using polysilicon compensation resistors, the compensation resistors are longer and electrically connected to the signal lines via the first contact structure, resulting in a greater load on the signal lines. This can improve transmission speed by increasing the drive capability of the selection signal module.

[0056] During the process development, early process development is unstable. It often takes up to a year or even several years from developing a process to finally determining various process parameters. In early products, products are generally designed based on the data at that time, and sometimes the gap with later process parameters is more than 10% or even more. This has a great impact on key data paths, so layout modification is necessary.

[0057] Layout modification is a significant undertaking. For example, modifying the resistance of compensation resistors is crucial. Different data signal modules correspond to different compensation resistor values, which can be reflected in the layout patterns as varying lengths and widths. Each data signal module typically has a separate layout for forming compensation resistors. Therefore, when modifying the layout, the layout for each data signal module's compensation resistor must be modified independently, requiring repeated iterations.

[0058] On the other hand, layout modification often requires revising multiple layers to adjust the resistance value, which brings a large workload. Figure 5 This is a schematic diagram of a layout modification for a compensation resistor provided in an embodiment of the present application. The resistance value is changed by adjusting the length of the compensation resistor. Taking a polysilicon resistor as an example, the layers involved in the actual modification include the polysilicon layer (poly), the contact structure layer (licon), and the first metal layer (M0).

[0059] In some embodiments, the compensation resistors include multiple bottom resistors and upper resistors arranged in an array; the multiple bottom resistors are configured as a third metal layer or a polysilicon layer; the upper resistors are arranged on the same layer as the signal lines and are all configured as a fourth metal layer. It is understood that when the bottom resistors are metal resistors, they are configured as the third metal layer; when the bottom resistors are polysilicon resistors, they are configured as a polysilicon layer.

[0060] Contact holes are provided at both ends of the bottom layer resistor. The contact holes are used to form a second contact structure for electrically connecting to the signal line or the upper layer resistor when the bottom layer resistor is selected to be connected to the signal line. The upper layer resistor is used to realize the electrical connection between the two bottom layer resistors through the second contact structures provided at both ends of the upper layer resistor when multiple bottom layer resistors are selected to be connected to the signal line.

[0061] Specifically, considering that the process of modifying the resistance value of the compensation resistor by adjusting the layout involves a lot of repetitive work, and layout modification often requires revising multiple layers to adjust the resistance value. This embodiment divides the compensation resistor into two parts: the bottom layer resistor and the upper layer resistor. The layout of the bottom layer resistor is kept as fixed as possible, and the resistance value of the compensation resistor is adjusted by changing the upper layer resistor and the signal line (i.e., the fourth metal layer). This reduces the workload of layout modification, reduces the number of revising layers, and saves costs.

[0062] Furthermore, a single bottom resistor may be Figure 4 and Figure 5 The figure shows a single resistor of a certain length. Multiple resistors are arranged side by side along their length and width to form an array with M rows and N columns. Contact holes are provided at both ends of each bottom resistor.

[0063] In some embodiments, when the number of selected bottom-layer resistors is at least two, it is necessary to realize the series or parallel connection between the bottom-layer resistors through the upper-layer resistor. From the perspective of the layout pattern projection, the first end of the upper-layer resistor overlaps with one end of one bottom-layer resistor, and the other end of the upper-layer resistor overlaps with one end of another bottom-layer resistor. The electrical connection between one end of the upper-layer resistor and one end of the bottom-layer resistor can be achieved through the second contact structure. Further, the electrical connection between the two bottom-layer resistors can be achieved through one upper-layer resistor. In this way, by changing the number and position of the upper-layer resistors, the resistance value of the compensation resistor can be adjusted, and at the same time, the bottom-layer resistor does not need to be revised, reducing the revision workload.

[0064] In some embodiments, when the number of selected bottom-layer resistors is one, both ends of the bottom-layer resistor are connected to the signal line via the second contact structure, and an upper-layer resistor is not required.

[0065] In some embodiments, A rows and B columns of bottom resistors of the compensation resistor are selected for connection to the signal line, where A is greater than or equal to 1 and B is greater than 1;

[0066] The A bottom-layer resistors in each column are connected in series through A-1 upper-layer resistors; the second ends of the B bottom-layer resistors in the Ath row are commonly connected to the selection signal module through a signal line, and the first ends of the B bottom-layer resistors in the first row are commonly connected to the data signal module through a signal line.

[0067] Specifically, Figure 6 A schematic diagram of a compensation resistor array provided in an embodiment of the present application Figure 1 . Figure 6 The bottom layer resistor array shown in FIG has 4 rows and 13 columns. The bottom layer resistors located in columns 5 to 9 are selected and connected to the signal line. In these 5 columns, the 4 bottom layer resistors in each column are electrically connected through three upper layer resistors, wherein a contact structure is provided in the dotted box; the upper end (i.e., the first end) of the bottom layer resistors in the first row of each column is directly connected to the signal line through the contact structure, and then connected to the data signal module; the lower end (i.e., the second end) of the bottom layer resistors in the fourth row of each column is directly connected to the signal line through the contact resistor, and then connected to the selection signal module.

[0068] in, Figure 6In the five selected columns of bottom-layer resistors, the four bottom-layer resistors in each column are connected in series, and the columns are connected in parallel. By adjusting the number and connection method of the selected bottom-layer resistors, the compensation resistor value can be flexibly adjusted. This also eliminates the need to redesign the bottom-layer and top-layer resistor layouts, reducing the redesign workload.

[0069] Furthermore, the resistance values ​​of the multiple bottom resistors are the same or different. In order to facilitate calculation and present a neat array arrangement, Figure 6 Each bottom-layer resistor shown in FIG has the same length and width, and the same resistance value. It is understood that multiple bottom-layer resistors of different lengths and / or widths can be arranged to form an array. The present embodiment does not limit the arrangement of the bottom-layer resistors or the individual resistance values, and the specific resistance values ​​of the compensation resistors can be determined based on the actual required resistance values.

[0070] For example, if the actual required compensation resistor value is estimated to be 200 ohms, then the adjustable resistance range of the bottom resistor can be determined to be 100 ohms to 300 ohms. It is known that the bottom resistors will show the maximum resistance when connected in series, and the minimum resistance when connected in parallel. According to this rule, the number of bottom resistors can be calculated. By reasonably setting the number of bottom resistors, it is beneficial to save costs and layout area. Too many bottom resistors will occupy a larger layout area and increase the difficulty and cost of the manufacturing process.

[0071] In some embodiments, C rows and D columns of bottom resistors of the compensation resistor are selected for connection to the signal line, where C is greater than or equal to 1, D is greater than 1 and D is an odd number;

[0072] The bottom layer resistors in each column are connected in series through C-1 top layer resistors; the second ends of the bottom layer resistors in the first column of the Cth row are connected to the selection signal module through a signal line; the second ends of the bottom layer resistors in the even columns in the Cth row and the odd columns (the number of columns plus one) are connected through top layer resistors; the first ends of the bottom layer resistors in the Dth column of the first row are connected to the data signal module through a signal line; the first ends of the bottom layer resistors in the odd columns in the first row and the even columns (the number of columns plus one) are connected through top layer resistors.

[0073] Specifically, Figure 7 A schematic diagram of a compensation resistor array provided in an embodiment of the present application Figure 2 . Figure 7The bottom resistor array shown in the figure is 4 rows and 13 columns. Among them, the bottom resistors in the 1st to 11th columns are selected to be connected to the signal line. In these 1-11 columns, for the 4 bottom resistors in each column, electrical connection is achieved through three upper resistors, wherein a contact structure is provided at the dotted box; the lower end (i.e., the second end) of the bottom resistor in the 4th row of the first column is directly connected to the signal line through the contact structure, and then connected to the selection signal module; the upper end (i.e., the first end) of the bottom resistor in the first row of the first column and the first row of the second column is connected through the upper resistor, and the lower end (i.e., the second end) of the bottom resistor in the fourth row of the second column and the fourth row of the third column is connected through the upper resistor... and so on, the 11 columns of bottom resistors are connected in series; the upper end (i.e., the first end) of the bottom resistor in the 11th row of the 1st column is directly connected to the signal line through the contact resistor, and then connected to the data signal module.

[0074] in, Figure 7 In the 11 selected columns of bottom-layer resistors, the four bottom-layer resistors in each column are connected in series, and the columns are also connected in series. Optionally, adjusting the number of bottom-layer resistors connected in series allows for flexible adjustment of the compensation resistor value, while also eliminating the need to redesign the bottom-layer resistor layout, reducing the redesign workload.

[0075] Furthermore, the resistance values ​​of the multiple bottom resistors are the same or different. In order to facilitate calculation and present a neat array arrangement, Figure 7 The length and width of the bottom resistors shown in the figure remain consistent, and their resistance values ​​are also the same. It is understood that multiple bottom resistors with different lengths and / or widths can be arranged to form an array. The present embodiment does not limit the arrangement of the bottom resistors or the individual resistance values, and the specific resistance value of the compensation resistor can be determined based on the actual required resistance value of the compensation resistor.

[0076] In some embodiments, the resistance values ​​of the plurality of bottom resistors are the same or different. Figure 6 、 Figure 7 As shown, the bottom resistors are set to the same resistance value. By adjusting the number of selected bottom resistors and adjusting the connection method, different compensation resistance values ​​can be obtained.

[0077] Furthermore, multiple bottom resistors are set to different resistance values. Optionally, they are set to equidistant resistance values, such as 50 ohms, 75 ohms, 100 ohms, etc. with a difference of 25 ohms. By selecting the bottom resistors with corresponding resistance values, the compensation resistance is adjusted.

[0078] In some embodiments, compensation resistors are provided on a plurality of signal lines, wherein the patterns of the third metal layer or polysilicon layer used to form the bottom resistors are the same.

[0079] Specifically, such as Figure 6 and Figure 7The bottom layer resistors of the compensation resistors on each compensated signal line use the same layout. When modifying the bottom layer resistor layout, there is no need to independently modify the layout of the compensation resistors corresponding to each data signal module, which effectively avoids repeating similar work multiple times and reduces the workload of revision.

[0080] The data sampling circuit layout structure provided in this embodiment uses compensation resistors to adjust transmission impedance, balance transmission time, and improve the consistency of the selection signal reaching each data signal module, thereby ensuring the accuracy of data reading and writing. Furthermore, the compensation resistors are divided into two parts: a bottom layer resistor and an upper layer resistor. The layout of the bottom layer resistor is fixed and unchanged. By changing the upper layer resistor, the resistance value of the compensation resistor is adjusted, thereby reducing the workload of layout modification and the number of redesigned layers.

[0081] Example 2

[0082] Figure 8 This is a flow chart of a data sampling circuit layout method provided in an embodiment of the present application. Figure 3 The layout structure of the data sampling circuit is shown.

[0083] The layout structure includes multiple data signal modules, which are arranged at intervals along a first direction; a selection signal module, which is used to generate a selection signal, and the selection signal is used to read the data signal from the data signal module according to the command signal, or to write the data signal to the data signal module; multiple signal lines, which correspond one-to-one to the multiple data signal modules, one end of the signal line is connected to the selection signal module, and the other end of the signal line is connected to the corresponding data signal module; wherein, at least one signal line is provided with a compensation resistor.

[0084] The layout method may be executed by a layout device, which may be implemented by a computer program, specifically application software, etc.; it may also be implemented by a physical device integrated or installed with a relevant computer program, such as a computer, etc. The layout method may include the following steps:

[0085] S100, obtaining the delay of the strobe signal reaching each data signal module;

[0086] S200 , adjusting the compensation resistor so that the difference in delay between the strobe signal reaching any two data signal modules is smaller than a preset threshold.

[0087] Specifically, after arranging multiple data signal modules in a certain order, the delays taken for the strobe signal to reach each data signal module are compared based on the delays obtained in step S100. In some embodiments, a pairwise comparison method is used: taking four data signal modules (DQ0 to DQ4) as an example, the delay corresponding to DQ0 is compared with the delays of DQ1, DQ2, and DQ3, the delay corresponding to DQ1 is compared with the delays of DQ2 and DQ3, and the delay corresponding to DQ2 is compared with the delay of DQ3. Based on the comparison results, repeated adjustments are made to ensure that the difference in the delays taken for the strobe signal to reach any two data signal modules is less than a preset threshold.

[0088] Furthermore, in some embodiments, the delay of the strobe signal corresponding to a data signal module is first determined as a base value, which is then sequentially subtracted from the delays of the strobe signals corresponding to other data signal modules. Data signal modules whose subtraction results exceed a preset threshold are marked to indicate that the corresponding compensation resistors should be adjusted downward during subsequent layout adjustments. It should be noted that during these adjustments, the compensation resistors on each signal line should be adjusted downward as much as possible to reduce transmission impedance and increase transmission speed.

[0089] Optionally, the delay of the strobe signal corresponding to the data signal module with the largest distance from the strobe signal module is used as the base value, because there is no need to set a compensation resistor on the signal line corresponding to the data signal module with the largest distance from the strobe signal module, or a compensation resistor with a very small resistance is set.

[0090] In some embodiments, the resistance of the compensation resistor is inversely proportional to the first distance, where the first distance is the length of a signal line connecting the strobe signal module and the corresponding data signal module.

[0091] Specifically, refer to Figure 3 , the distance from DQ0 to DQn and the strobe signal gradually decreases, according to Figure 3 In the wiring structure shown, the length of the signal lines corresponding to DQ0 to DQn gradually decreases. Given a constant signal line width, the length of the signal line is proportional to its impedance. That is, the shorter the signal line, the lower the impedance provided on the transmission path. Accordingly, larger compensation resistors are installed on shorter signal lines to balance the impedance of the transmission paths corresponding to the data signal modules, ensuring that the difference in the delay between the selection signal reaching any two data signal modules is less than a preset threshold.

[0092] In some embodiments, the compensation resistor is a metal resistor, and the compensation resistor and the signal line are arranged in the same layer, both configured as the first metal layer; step S200 specifically includes: by modifying the width or length of the compensation resistor in the layout of the first metal layer, adjusting the resistance value of the metal resistor so that the difference in the delay of the selection signal reaching any two data signal modules is less than a preset threshold.

[0093] In some embodiments, the compensation resistor is a polysilicon resistor, configured as a polysilicon layer; the signal line is configured as a second metal layer, and the compensation resistor and the signal line are electrically connected through a first contact structure; step S200 specifically includes: by modifying the width or length of the compensation resistor in the layout of the polysilicon layer, adjusting the resistance value of the compensation resistor so that the difference in delay between the selection signal reaching any two data signal modules is less than a preset threshold.

[0094] In some embodiments, the compensation resistor includes a plurality of bottom resistors and an upper resistor arranged in an array; the plurality of bottom resistors are configured as a third metal layer or a polysilicon layer; the upper resistors are arranged in the same layer as the signal line and are all configured as a fourth metal layer; contact holes are provided at both ends of the bottom resistor, and the contact holes are used to form a second contact structure for electrically connecting to the signal line or the upper resistor when the bottom resistor is selected to be connected to the signal line; the upper resistor is used to realize electrical connection between the two bottom resistors through the contact structure provided at both ends of the upper resistor when the plurality of bottom resistors are selected to be connected to the signal line; step S200 specifically includes: adjusting the resistance value of the polysilicon resistor by modifying the layout of the fourth metal layer so that the difference in delay of the selection signal reaching any two data signal modules is less than a preset threshold.

[0095] Specifically, considering that the process of modifying the resistance value of the compensation resistor by adjusting the layout involves a lot of rework, and layout modification often requires revising multiple layers to adjust the resistance value. This embodiment divides the compensation resistor into two parts: a bottom layer resistor and an upper layer resistor. The layout of the bottom layer resistor is kept as fixed as possible. The resistance value of the compensation resistor is adjusted by changing the upper layer resistor and the signal line (i.e., the fourth metal layer). This reduces the workload of layout modification to a certain extent, reduces the number of revising layers, and saves costs.

[0096] On the basis of the above embodiment, the resistance value of the compensation resistor is adjusted by modifying the layout of the fourth metal layer, specifically including: adjusting the number of upper resistors and the number of selected bottom resistors, and / or resistance value, and / or connection method by modifying the layout of the fourth metal layer to adjust the resistance value of the compensation resistor.

[0097] Specifically, refer to Figure 6 and Figure 7 The bottom resistor arrays of the two are the same, with 4 rows and 13 columns. The length and width of each bottom resistor in the array are the same, and they have the same resistance value. The difference between the two is the connection method of the bottom resistors: Figure 6 Among the five selected columns of bottom resistors, the four bottom resistors in each column are connected in series, and the columns are connected in parallel. Figure 7In the 11 selected columns of bottom-layer resistors, the four bottom-layer resistors in each column are connected in series, and the columns are also connected in series. By adjusting the number and connection method of the selected bottom-layer resistors, the compensation resistor value can be flexibly adjusted. This also eliminates the need to redesign the bottom-layer and top-layer resistor layouts, reducing the redesign workload.

[0098] Furthermore, the resistance value of each bottom resistor in the array can be set to be different. Optionally, the resistance value can be set to be equal, such as 50 ohms, 75 ohms, 100 ohms, etc., with a difference of 25 ohms. By selecting the bottom resistor with the corresponding resistance value, the compensation resistance value can be adjusted.

[0099] In addition, the resistance values ​​of the bottom resistors in the array may also be partially the same, which is not limited in the embodiment of the present application.

[0100] The data sampling circuit layout method provided in this embodiment uses compensation resistors to adjust transmission impedance, balance transmission time, and improve the consistency of the selection signal reaching each data signal module, thereby ensuring the accuracy of data reading and writing. Furthermore, the compensation resistors are divided into two parts: a bottom layer resistor and an upper layer resistor. The layout of the bottom layer resistor is fixed and unchanged. By changing the upper layer resistor, the resistance value of the compensation resistor is adjusted. This reduces the workload of layout modification to a certain extent, reduces the number of redesigned layers, and saves costs.

[0101] Example 3

[0102] Figure 9 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application is shown in FIG. Figure 9 As shown, the electronic equipment includes:

[0103] The electronic device includes a processor 291 and a memory 292; a communication interface 293, and a bus 294. The processor 291, memory 292, and communication interface 293 can communicate with each other via bus 294. Communication interface 293 can be used for information transmission. The processor 291 can invoke logic instructions in memory 292 to execute the methods of the above embodiments.

[0104] In addition, the logic instructions in the memory 292 can be implemented in the form of software functional units and can be stored in a computer-readable storage medium when sold or used as an independent product.

[0105] Memory 292, as a computer-readable storage medium, can be used to store software programs and computer-executable programs, such as program instructions / modules corresponding to the methods in the embodiments of the present application. Processor 291 executes the software programs, instructions, and modules stored in memory 292 to perform functional applications and data processing, thereby implementing the methods in the above-mentioned method embodiments.

[0106] Memory 292 may include a program storage area and a data storage area. The program storage area may store an operating system and at least one application required for a function; the data storage area may store data generated based on the use of the terminal device. Memory 292 may also include high-speed random access memory and non-volatile memory.

[0107] The present application provides a computer-readable storage medium, in which computer-executable instructions are stored. When the computer-executable instructions are executed by a processor, they are used to implement the method provided in the above method embodiment.

[0108] An embodiment of the present application provides a computer program product, including a computer program, which implements the method provided in the above embodiment when executed by a processor.

[0109] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present application that follow the general principles of the present application and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0110] It should be understood that the present application is not limited to the exact structure described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A layout structure of a data sampling circuit, characterized in that: include: a plurality of data signal modules, wherein the plurality of data signal modules are arranged at intervals along a first direction; a strobe signal module for generating a strobe signal, the data sampling circuit for reading a data signal from the data signal module or writing the data signal to the data signal module according to the strobe signal; a plurality of signal lines, the plurality of signal lines corresponding one-to-one to the plurality of data signal modules, one end of the signal line connected to the strobe signal module, and the other end of the signal line connected to the corresponding data signal module; wherein at least one of the signal lines is provided with a compensation resistor for ensuring that the difference in delay between the strobe signal reaching any two data signal modules is less than a preset threshold; The compensation resistor includes a plurality of bottom resistors and an upper resistor arranged in an array; the plurality of bottom resistors are configured as a third metal layer or a polysilicon layer; the upper resistors are arranged in the same layer as the signal line and are both configured as a fourth metal layer; contact holes are provided at both ends of the bottom resistor, and the contact holes are used to form a second contact structure for electrically connecting to the signal line or the upper resistor when the bottom resistor is selected to be connected to the signal line; the upper resistor is used to achieve electrical connection between two bottom resistors through the second contact structures provided at its two ends when the plurality of bottom resistors are selected to be connected to the signal line; A rows and B columns of the compensation resistors are selected for connection to the signal line, where A is greater than or equal to 1 and B is greater than 1; the A bottom resistors in each column are connected in series through A-1 upper resistors; the second ends of the B bottom resistors located in the Ath row are commonly connected to the selection signal module through the signal line, and the first ends of the B bottom resistors located in the first row are commonly connected to the data signal module through the signal line.

2. The layout structure according to claim 1, characterized in that: The resistance of the compensation resistor is inversely proportional to a first distance, where the first distance is the length of a signal line connecting the strobe signal module and the corresponding data signal module.

3. The layout structure according to claim 2, characterized in that: The compensation resistor is a metal resistor, and the compensation resistor and the signal line are arranged in the same layer, both configured as the first metal layer.

4. The layout structure according to claim 2, characterized in that: The compensation resistor is a polysilicon resistor configured as a polysilicon layer; the signal line is configured as a second metal layer, and the compensation resistor and the signal line are electrically connected via a first contact structure.

5. The layout structure according to claim 1, characterized in that: The bottom layer resistors in C rows and D columns of the compensation resistor are selected for connection to the signal line, wherein C is greater than or equal to 1, D is greater than 1 and D is an odd number; the bottom layer resistors in each column are connected in series through C-1 upper layer resistors; the second ends of the bottom layer resistors located in the first column of the Cth row are connected to the selection signal module through the signal line; the second ends of the bottom layer resistors located in the even columns of the Cth row and the odd columns whose column number is increased by one are connected through the upper layer resistor; the first ends of the bottom layer resistors located in the Dth column of the first row are connected to the data signal module through the signal line; the first ends of the bottom layer resistors located in the odd columns of the first row and the even columns whose column number is increased by one are connected through the upper layer resistor.

6. The layout structure according to claim 1, characterized in that: The resistance values ​​of the multiple bottom resistors are the same or different.

7. The layout structure according to claim 1, characterized in that: The compensation resistors are provided on a plurality of the signal lines, wherein the patterns of the third metal layer or the polysilicon layer used to form the bottom resistors are the same.

8. A layout method for a data sampling circuit, characterized in that: The layout structure of the data sampling circuit includes a plurality of data signal modules, the plurality of data signal modules being arranged at intervals along a first direction; a strobe signal module for generating a strobe signal, the data sampling circuit being used to read a data signal from the data signal module or write the data signal to the data signal module according to the strobe signal; a plurality of signal lines, the plurality of signal lines corresponding one-to-one to the plurality of data signal modules, one end of the signal line being connected to the strobe signal module, and the other end of the signal line being connected to the corresponding data signal module; wherein at least one of the signal lines is provided with a compensation resistor; the layout method includes: obtaining a delay of the strobe signal reaching each of the data signal modules; adjusting the compensation resistor so that the difference in the delay of the strobe signal reaching any two of the data signal modules is less than a preset threshold; The compensation resistor includes a plurality of bottom resistors and an upper resistor arranged in an array; the plurality of bottom resistors are configured as a third metal layer or a polysilicon layer; the upper resistors are arranged in the same layer as the signal line and are both configured as a fourth metal layer; contact holes are provided at both ends of the bottom resistor, and the contact holes are used to form a second contact structure electrically connected to the signal line or the upper resistor when the bottom resistor is selected to be connected to the signal line; the upper resistor is used to achieve electrical connection between two bottom resistors through the contact structures provided at its two ends when the plurality of bottom resistors are selected to be connected to the signal line; A rows and B columns of the compensation resistors are selected for connection to the signal line, where A is greater than or equal to 1 and B is greater than 1; the A bottom resistors in each column are connected in series through A-1 upper resistors; the second ends of the B bottom resistors located in the Ath row are commonly connected to the selection signal module through the signal line, and the first ends of the B bottom resistors located in the first row are commonly connected to the data signal module through the signal line.

9. The method according to claim 8, characterized in that The resistance of the compensation resistor is inversely proportional to a first distance, where the first distance is the length of a signal line connecting the strobe signal module and the corresponding data signal module.

10. The method according to claim 9, characterized in that The compensation resistor is a metal resistor, and the compensation resistor and the signal line are arranged in the same layer, both configured as the first metal layer; adjusting the compensation resistor so that the difference in delay between the selection signal and any two data signal modules is less than a preset threshold includes: adjusting the compensation resistor so that the difference in delay between the selection signal and any two data signal modules is less than a preset threshold by modifying the width or length of the metal resistor in the layout of the first metal layer.

11. The method according to claim 9, characterized in that The compensation resistor is a polysilicon resistor configured as a polysilicon layer; the signal line is configured as a second metal layer, and the compensation resistor and the signal line are electrically connected through a first contact structure; adjusting the compensation resistor so that the difference in delay between the selection signal and any two data signal modules is less than a preset threshold includes: adjusting the compensation resistor so that the difference in delay between the selection signal and any two data signal modules is less than a preset threshold by modifying the width or length of the polysilicon resistor in the layout of the polysilicon layer.

12. The method according to claim 9, characterized in that The step of adjusting the compensation resistor so that the difference in delay between the selection signal and any two data signal modules is less than a preset threshold value includes: adjusting the resistance of the compensation resistor by modifying the layout of the fourth metal layer so that the difference in delay between the selection signal and any two data signal modules is less than a preset threshold value.

13. The method according to claim 12, characterized in that The method of adjusting the resistance of the compensation resistor by modifying the layout of the fourth metal layer includes: adjusting the number of the upper resistors and the number of the selected bottom resistors, and / or the resistance, and / or the connection method by modifying the layout of the fourth metal layer to adjust the resistance of the compensation resistor.

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