Reference voltage controlled equalized input data buffer circuit

Abstract

The present invention discloses a reference voltage-controlled equalized input data buffer circuit. The reference voltage-controlled equalized input data buffer circuit includes a first amplifier, a second amplifier, a feedback signal generator, a reference voltage converter, a reference voltage multiplexing circuit, and a gain control unit. The first amplifier is configured to receive a data signal and a reference voltage. The second amplifier is coupled to the first amplifier. The feedback signal generator is coupled to the second amplifier. The reference voltage converter is configured to receive a reference voltage. The reference voltage multiplexing circuit is coupled to the second amplifier and the reference voltage converter. The gain control unit is coupled to the feedback signal generator, the first amplifier, and the reference voltage multiplexing circuit.

Description

Technical Field

[0001] The present invention relates to a reference voltage controlled equalized input data buffer circuit, and more particularly to a buffer circuit capable of automatically controlling its gain and adding equalization characteristics according to a reference voltage and input data. Background Art

[0002] With the rapid advancement of technology, various volatile and non-volatile memory types have been incorporated into computer systems. Dynamic Random Access Memory (DRAM) is a type of semiconductor memory that falls under the volatile category. Its primary function is to use the amount of charge stored in a capacitor to represent a binary bit as a 1 or 0. DRAM is a short-term data storage area in a computer system, storing information currently in use for quick access.

[0003] DRAM offers high-speed transmission and high bandwidth utilization. However, these demands on DRAM lead to increased power consumption, especially with the newer Double-Data-Rate (DDR) 4 and DDR5 specifications. Therefore, developing a DRAM data buffer circuit that automatically controls its gain and adds equalization characteristics based on the reference voltage and input data is a critical design issue. Summary of the Invention

[0004] An embodiment of the present invention provides a reference voltage controlled equalized input data buffer circuit. The reference voltage controlled equalized input data buffer circuit includes a first amplifier, a second amplifier, a feedback signal generator, a reference voltage converter, a reference voltage multiplexing circuit, and a gain control unit. The first amplifier includes a first input terminal for receiving a data signal, a second input terminal for receiving a reference voltage, a first output terminal, and a second output terminal. The second amplifier is coupled to the first output terminal of the first amplifier and the second output terminal of the first amplifier. The feedback signal generator is coupled to the second amplifier. The reference voltage converter is used to receive a reference voltage. The reference voltage multiplexing circuit is coupled to the second amplifier and the reference voltage converter. The gain control unit is coupled to the feedback signal generator, the first output terminal of the first amplifier, the second output terminal of the first amplifier, and the reference voltage multiplexing circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 It is a block diagram of the reference voltage controlled equalized input data buffer circuit of the present invention.

[0006] Figure 2 yes Figure 1FIG. 1 is a structural diagram of a first amplifier in an equalized input data buffer circuit controlled by a reference voltage.

[0007] Figure 3 yes Figure 1 FIG. 1 is a diagram showing the architecture of a second amplifier in an equalized input data buffer circuit controlled by a reference voltage.

[0008] Figure 4 yes Figure 1 Schematic diagram of the feedback signal generator in the equalized input data buffer circuit controlled by the reference voltage.

[0009] Figure 5 yes Figure 1 Schematic diagram of the reference voltage converter in the equalized input data buffer circuit controlled by the reference voltage.

[0010] Figure 6 yes Figure 1 Schematic diagram of the reference voltage multitasking circuit in the reference voltage controlled equalized input data buffer circuit.

[0011] Figure 7 yes Figure 1 Schematic diagram of the gain control unit in the equalized input data buffer circuit controlled by the reference voltage.

[0012] The description of the accompanying drawings is as follows:

[0013] 100Ω reference voltage controlled equalized input data buffer

[0014] 10 First Amplifier

[0015] 11 Second Amplifier

[0016] 12 Feedback signal generator

[0017] 13 Reference Voltage Converter

[0018] 14 Reference voltage multitasking circuit

[0019] 15 gain control unit

[0020] POUTB first output signal

[0021] POUT second output signal

[0022] DIP data signal

[0023] VERF reference voltage

[0024] PT third output signal

[0025] PB fourth output signal

[0026] P_FB feedback signal

[0027] VREF_H first potential reference voltage

[0028] VREF_DEF second potential reference voltage

[0029] VREF_L third potential reference voltage

[0030] V DD Operating voltage

[0031] BIAS bias signal

[0032] T1 first transistor

[0033] T2 second transistor

[0034] T3 third transistor

[0035] T4 fourth transistor

[0036] T5 fifth transistor

[0037] T6 sixth transistor

[0038] T7 seventh transistor

[0039] T8 eighth transistor

[0040] T9 ninth transistor

[0041] INV1 first inverter

[0042] A3 third amplifier

[0043] R1 first resistor

[0044] R2 second resistor

[0045] R3 third resistor

[0046] R4 fourth resistor

[0047] SW1 first switch

[0048] SW2 second switch

[0049] SW3 third switch

[0050] H_ENB first control signal

[0051] H_ENT second control signal

[0052] RSTB third control signal

[0053] RST fourth control signal

[0054] L_ENB fifth control signal

[0055] L_ENT sixth control signal

[0056] VREF_FB reference voltage feedback signal

[0057] NAND1 NAND gate

[0058] NOR1

[0059] INV2 second inverter

[0060] INV3 third inverter

[0061] INV4 fourth inverter

[0062] INV5 fifth inverter

[0063] INV6 sixth inverter

[0064] HF_EN start signal. DETAILED DESCRIPTION

[0065] Figure 1This is a block diagram of a reference voltage-controlled equalized input data buffer circuit 100 according to the present invention. The function of the reference voltage-controlled equalized input data buffer circuit 100 is to automatically control its gain and provide an equalization function based on the input reference voltage and input data. The reference voltage-controlled equalized input data buffer circuit 100 includes a first amplifier 10, a second amplifier 11, a feedback signal generator 12, a reference voltage converter 13, a reference voltage multiplexer circuit 14, and a gain control unit 15. The first amplifier includes a first input terminal, a second input terminal, a first output terminal, and a second output terminal. The first input terminal is used to receive a data signal DIP. The second input terminal is used to receive a reference voltage VREF. The second amplifier 11 is coupled to the first output terminal of the first amplifier 10 and the second output terminal of the first amplifier. The feedback signal generator 12 is coupled to the second amplifier 11. The reference voltage converter 13 is used to receive the reference voltage VREF. The reference voltage multiplexer circuit 14 is coupled to the second amplifier 11 and the reference voltage converter 12. The gain control unit 15 is coupled to the feedback signal generator 12, the first output terminal of the first amplifier 10, the second output terminal of the first amplifier 10, and the reference voltage multiplexer circuit 14. In the reference voltage-controlled equalized input data buffer circuit 100, the first amplifier 10, the second amplifier 11, the feedback signal generator 12, the reference voltage multiplexer circuit 14, and the gain control unit 15 form a circuit loop that automatically controls its gain based on the reference voltage and input data. For example, after being amplified by the first amplifier 10 and the second amplifier 11, the data signal DIP and the reference voltage VREF are input to the feedback signal generator 12 to generate the feedback signal P_FB. The reference voltage VREF is converted by the reference voltage converter 13 into a first reference voltage VREF_H, a second reference voltage VREF_DEF, and a third reference voltage VREF_L. The first reference voltage VREF_H, the second reference voltage VREF_DEF, and the third reference voltage VREF_L are converted into the reference voltage feedback signal VREF_FB by the reference voltage multiplexer circuit 14. The gain control unit 15 adjusts its gain by receiving the two outputs (POUT and POUTB) of the first amplifier 11, the feedback signal P_FB, and the reference voltage feedback signal VREF_FB. Because the reference voltage feedback signal VREF_FB is related to the reference voltage VREF, the gain control unit 15 can automatically control its gain using the reference voltage VREF and the data signal DIP. The circuit details of the reference voltage-controlled equalized input data buffer circuit 100 will be described in detail below.

[0066] Figure 2 FIG. 1 is a structural diagram of the first amplifier 10 in the reference voltage controlled equalized input data buffer circuit 100 . Figure 3This is a diagram of the architecture of the second amplifier 11 in the reference voltage controlled equalized input data buffer circuit 100. The first amplifier 10 and the second amplifier 11 of the reference voltage controlled equalized input data buffer circuit 100 are not limited by the amplifier circuit. For example, the first amplifier 10 and the second amplifier 11 can be voltage amplifiers, current amplifiers, or differential amplifiers. For example, Figure 2 In the embodiment, the first amplifier 10 may be a differential amplifier. The first amplifier 10 may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, and a fifth transistor T5. The first transistor T1 includes a transistor for receiving an operating voltage V DD The second transistor T2 includes a first terminal, a second terminal and a control terminal for receiving the working voltage V DDThe first transistor T1 and the second transistor T2 include a first terminal, a second terminal, and a control terminal coupled to the first transistor T1. The third transistor T3 includes a first terminal coupled to the second terminal of the first transistor T1, a second terminal, and a control terminal for receiving a data signal DIP. The fourth transistor T4 includes a first terminal coupled to the second terminal of the second transistor T2, a second terminal coupled to the second terminal of the third transistor T3, and a control terminal for receiving a reference voltage VREF. The fifth transistor T5 includes a first terminal coupled to the second terminal of the fourth transistor T4, a second terminal coupled to ground, and a control terminal for receiving a bias signal BIAS. In this description, the first transistor T1 and the second transistor T2 may be P-type metal-oxide-semiconductor field-effect transistors (P-Type Metal-Oxide-Semiconductor Field-Effect Transistors). The third transistor T3, the fourth transistor T4, and the fifth transistor T5 may be N-type metal-oxide-semiconductor field-effect transistors (N-Type Metal-Oxide-Semiconductor Field-Effect Transistors). The bias signal BIAS can be a custom or internal voltage value to control the conduction state of the fifth transistor T5. For example, when the fifth transistor T5 is an N-type metal oxide semiconductor field effect transistor, the voltage of the bias signal BIAS will affect the conduction state of the fifth transistor T5, so the current of the first amplifier 10 passing through the fifth transistor T5 can also be controlled by the bias signal BIAS. In addition, when the third transistor T3 and the fourth transistor T4 are in the linear region, and the first transistor T1 and the second transistor T2 are turned on, the two outputs of the first amplifier 10, namely the first output signal POUTB and the second output signal POUT will also be linearly amplified according to the data signal DIP and the reference voltage VREF. It should be understood that the first output signal POUTB is located at the first end of the third transistor T3, and the second output signal POUT is located at the first end of the fourth transistor T4. In addition, the first output signal POUTB and the second output signal POUT are opposite to each other. Figure 3 In the embodiment, the second amplifier 11 can also be a differential amplifier, whose inputs are the first output signal POUTB and the second output signal POUT, which are inversely proportional to each other. The second amplifier 11 includes a first input terminal coupled to the first output terminal of the first amplifier 10, a second input terminal coupled to the second output terminal of the first amplifier 10, a first output terminal coupled to the feedback signal generator 12, and a second output terminal. Therefore, after the first output signal POUTB and the second output signal POUT are operated by the second amplifier 11, they are amplified into a third output signal PT and a fourth output signal PB, respectively. The third output signal PT is output from the first output terminal. The fourth output signal PB is output from the second output terminal. Furthermore, the third output signal PT and the fourth output signal PB can be inversely proportional to each other.

[0067] Figure 4 1 is a schematic diagram of the feedback signal generator in the reference voltage controlled equalized input data buffer circuit 100. The feedback signal generator 12 includes a plurality of first inverters INV1 connected in series. The plurality of first inverters INV1 connected in series are used to delay the signal at the first output end of the second amplifier 11 to output the feedback signal P_FB. In other words, the third output signal PT output by the second amplifier 11 can be delayed by the feedback signal generator 12 to generate the feedback signal P_FB. Figure 4 There is no limit to the number of first inverters INV1 in the feedback signal generator 12. Moreover, since each inverter has its own time delay, the more inverters there are in the feedback signal generator 12, the greater the time delay will be.

[0068] Figure 5 This is a structural diagram of the reference voltage converter 13 in the reference voltage controlled equalized input data buffer circuit 100. The reference voltage converter 13 includes a third amplifier A3, at least one first resistor R1 connected in series, at least one second resistor R2 connected in series, at least one third resistor R3 connected in series, and at least one fourth resistor R4 connected in series. The third amplifier A3 is used to receive the reference voltage VREF. The at least one first resistor R1 connected in series includes a first end coupled to the third amplifier A3, and a second end for outputting the first potential reference voltage VREF_H. The at least one second resistor R2 connected in series includes a first end coupled to the second end of the at least one first resistor R1 connected in series, and a second end for outputting the second potential reference voltage VREF_DEF. The at least one third resistor R3 connected in series includes a first end coupled to the second end of the at least one second resistor R2 connected in series, and a second end for outputting the third potential reference voltage VREF_L. The at least one fourth resistor R4 connected in series includes a first end coupled to the second end of the at least one third resistor R3 connected in series, and a second end coupled to the ground end. In Figure 5As can be seen from the architecture of the reference voltage converter 13, at least one first resistor R1 connected in series, at least one second resistor R2 connected in series, at least one third resistor R3 connected in series, and at least one fourth resistor R4 connected in series form a voltage divider circuit. In other words, after the reference voltage VREF is amplified by the third amplifier A3, the voltage divider circuit can output a first potential reference voltage VREF_H, a second potential reference voltage VREF_DEF, and a third potential reference voltage VREF_L. Furthermore, the first potential reference voltage VREF_H is greater than the second potential reference voltage VREF_DEF, and the second potential reference voltage VREF_DEF is greater than the third potential reference voltage VREF_L. The first potential reference voltage VREF_H, the second potential reference voltage VREF_DEF, and the third potential reference voltage VREF_L can be calculated using the voltage divider theorem, and therefore will not be further described here.

[0069] Figure 6This is a block diagram of the reference voltage multiplexing circuit 14 in the reference voltage-controlled equalized input data buffer circuit 100. The reference voltage multiplexing circuit 14 includes a first switch SW1, a second switch SW2, and a third switch SW3. The first switch SW1 includes an input terminal for receiving a first potential reference voltage VREF_H, a first control terminal for receiving a first control signal H_ENB, a second control terminal for receiving a second control signal H_ENT, and an output terminal for outputting a reference voltage feedback signal VREF_FB. The second switch SW2 includes an input terminal for receiving a second potential reference voltage VREF_DEF, a first control terminal for receiving a third control signal RSTB, a second control terminal for receiving a fourth control signal RST, and an output terminal coupled to the output terminal of the first switch SW1. The third switch SW3 includes an input terminal for receiving a third potential reference voltage VREF_L, a first control terminal for receiving a fifth control signal L_ENB, a second control terminal for receiving a sixth control signal L_ENT, and an output terminal coupled to the output terminal of the first switch SW1. Furthermore, in the reference voltage multiplexer circuit 14, the first switch SW1, the second switch SW2, and the third switch SW3 may include a pair of an N-type metal oxide semiconductor field effect transistor and a P-type metal oxide semiconductor field effect transistor. Furthermore, the first control signal H_ENB and the second control signal H_ENT are inversely proportional to each other. The third control signal RSTB and the fourth control signal RST are inversely proportional to each other. The fifth control signal L_ENB and the sixth control signal L_ENT are inversely proportional to each other. In other words, the first control signal H_ENB and the second control signal H_ENT control the first switch SW1 to be turned on or off. The third control signal RSTB and the fourth control signal RST control the second switch SW2 to be turned on or off. The fifth control signal L_ENB and the sixth control signal L_ENT control the third switch SW3 to be turned on or off. The following describes the circuitry for generating the first control signal H_ENB, the second control signal H_ENT, the third control signal RSTB, the fourth control signal RST, the fifth control signal L_ENB, and the sixth control signal L_ENT.

[0070] like Figure 6As shown, the reference voltage multiplexer circuit 14 further includes a NAND gate NAND1, a NOR gate NOR1, a second inverter INV2, a third inverter INV3, a fourth inverter INV4, a fifth inverter INV5, and a sixth inverter INV6. The NAND gate NAND1 includes a first input coupled to the first output of the second amplifier 11 for receiving the third output signal PT, a second input for receiving the third control signal RSTB, and an output. The NOR gate NOR1 includes a first input coupled to the first output of the second amplifier 11 for receiving the third output signal PT, a second input for receiving the fourth control signal RST, and an output. The second inverter INV2 includes an input coupled to the output of the NAND gate NAND1 and an output for outputting the second control signal H_ENT. The third inverter INV3 includes an input coupled to the output of the NOR gate NOR1 and an output for outputting the fifth control signal L_ENB. The fourth inverter INV4 includes an input terminal for receiving the fourth control signal RST and an output terminal for outputting the third control signal RSTB. The fifth inverter INV5 includes an input terminal coupled to the output terminal of the second inverter INV2 and an output terminal for outputting the first control signal H_ENB. The sixth inverter INV6 includes an input terminal coupled to the output terminal of the third inverter INV3 and an output terminal for outputting the sixth control signal L_ENT. Therefore, through the NAND gate NAND1, the NOR gate NOR1, the second inverter INV2, the third inverter INV3, the fourth inverter INV4, the fifth inverter INV5, and the sixth inverter INV6, the potentials of the first control signal H_ENB, the second control signal H_ENT, the third control signal RSTB, the fourth control signal RST, the fifth control signal L_ENB, and the sixth control signal L_ENT can be changed according to the third output signal PT. Furthermore, since the first control signal H_ENB, the second control signal H_ENT, the third control signal RSTB, the fourth control signal RST, the fifth control signal L_ENB, and the sixth control signal L_ENT control the on / off states of the switches SW1 to SW3, the reference voltage feedback signal VREF_FB ultimately output by the reference voltage multiplexer circuit 14 is related to the third output signal PT, the first potential reference voltage VREF_H, the second potential reference voltage VREF_DEF, and the third potential reference voltage VREF_L (e.g., Figure 1 shown).

[0071] For example, when the first output terminal of the second amplifier 11 is high, that is, the third output signal PT is high, the output of the NAND gate NAND1 is inversely proportional to the third control signal RSTB. Therefore, the output of the second inverter INV2 is in phase with the third control signal RSTB. This causes the second control signal H_ENT to be in phase with the third control signal RSTB, and the first control signal H_ENB to be inversely proportional to the third control signal RSTB. When the third control signal RSTB is high, the first control signal H_ENB is low, and the second control signal H_ENT is high. Therefore, the first switch SW1 is turned on, and the first reference voltage VREF_H is enabled. When the third output signal PT is high, the output of the NOR gate NOR1 is low. This causes the output of the third inverter INV3 to be high, that is, the fifth control signal L_ENB is high, and the sixth control signal L_ENT is low. Therefore, the third switch SW3 is in the off state, and the third reference voltage VREF_L is disabled. Furthermore, if the first output terminal of the second amplifier 11 is at a low level, the first reference voltage VREF_H is disabled and the third reference voltage VREF_L is enabled. The derivation details are similar to the concepts described above and will not be repeated here.

[0072] Figure 7This is a schematic diagram of the gain control unit 15 in the reference voltage-controlled equalized input data buffer circuit 100. The gain control unit 15 includes a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a ninth transistor T9. The sixth transistor T6 includes a first terminal coupled to the first output terminal of the first amplifier 10 (receiving the first output signal POUTB), a second terminal, and a control terminal coupled to the feedback signal generator 12 for receiving the feedback signal P_FB. The seventh transistor T7 includes a first terminal coupled to the second output terminal of the first amplifier 10 (receiving the second output signal POUT), a second terminal coupled to the second terminal of the sixth transistor T6, and a control terminal for receiving the reference voltage feedback signal VREF_FB. The eighth transistor T8 includes a first terminal coupled to the second terminal of the seventh transistor T7, a second terminal, and a control terminal for receiving the bias signal BIAS. The bias signal BIAS can be a user-defined or preset voltage value and is used to control the conduction state of the eighth transistor T8. The ninth transistor T9 includes a first terminal coupled to the second terminal of the eighth transistor T8, a second terminal coupled to ground, and a control terminal for receiving an enable signal HF_EN. In the gain control unit 15, when the eighth transistor T8 is an N-type metal-oxide-semiconductor field-effect transistor, the voltage of the bias signal BIAS affects the conduction state of the eighth transistor T8. Therefore, the current flowing through the eighth transistor T8 in the gain control unit 15 can also be controlled by the bias signal BIAS. In the gain control unit 15, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are N-type metal-oxide-semiconductor field-effect transistors. The enable signal HF_EN can be considered a switching signal for the gain control unit 15. For example, if the enable signal HF_EN is low, the ninth transistor T9 is turned off, and no current flows through the ninth transistor T9. Therefore, the gain control unit 15 does not adjust the voltage gain and is turned off. If the enable signal HF_EN is high, the ninth transistor T9 is turned on. The gain control unit 13 can adjust the voltage gain of the gain control unit 15 based on the bias signal BIAS, the feedback signal P_FB, and the reference voltage feedback signal VREF_FB. Similar to the above, since the reference voltage feedback signal VREF_FB is received by the control terminal of the seventh transistor T7, the voltage between the reference voltage feedback signal VREF_FB and the second output signal POUT can control the conduction state of the seventh transistor T7. Similarly, since the feedback signal PT_FB is received by the control terminal of the sixth transistor T6, the voltage between the feedback signal PT_FB and the first output signal POUTB can control the conduction state of the sixth transistor T6.For example, when the seventh transistor T6 and the seventh transistor T7 are turned on, the voltages of the first output signal POUTB and the second output signal POUT are opposite, so a current flows between the first output signal POUTB and the second output signal POUT. Furthermore, because the voltage of the bias signal BIAS affects the conduction state of the eighth transistor T8, a portion of the current flowing between the first output signal POUTB and the second output signal POUT can be diverted to the ground terminal by the eighth transistor T8 and the ninth transistor T9. When the current magnitude changes, the gain control unit 15 can adjust the gain between the first output signal POUTB and the second output signal POUT.

[0073] In summary, the present invention describes a reference voltage-controlled equalized input data buffer circuit. This reference voltage-controlled equalized input data buffer circuit can automatically adjust its gain using a reference voltage and a data signal. This reference voltage-controlled equalized input data buffer circuit can automatically adjust its gain to optimize power consumption. Therefore, the reference voltage-controlled equalized input data buffer circuit of the present invention is well-suited for use in high-speed dynamic random access memories.

[0074] The foregoing description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention are intended to be within the scope of protection of the present invention.

Claims

1. A reference voltage controlled equalized input data buffer circuit, characterized in that: include: A first amplifier comprising: A first input terminal, for receiving a data signal; A second input terminal, for receiving a reference voltage; a first output terminal; and a second output terminal; A second amplifier, coupled to the first output terminal of the first amplifier and the second output terminal of the first amplifier, comprising a first output terminal and a second output terminal; a feedback signal generator coupled to the second amplifier; a reference voltage converter, configured to receive the reference voltage; a reference voltage multiplexing circuit coupled to the second amplifier and the reference voltage converter, wherein the reference voltage multiplexing circuit includes an output terminal for outputting a reference voltage feedback signal; and The gain control unit is coupled to the feedback signal generator, the first output terminal of the first amplifier, the second output terminal of the first amplifier, and the reference voltage multiplexer circuit; the gain control unit is also coupled to the second input terminal of the first amplifier.

2. The reference voltage controlled equalized input data buffer circuit according to claim 1, wherein: The first amplifier further includes: A first transistor comprising: A first terminal is used to receive an operating voltage; the second end; and Control terminal; A second transistor comprising: A first end is used to receive the operating voltage; the second end; and a control terminal coupled to the control terminal of the first transistor; A third transistor includes: a first terminal coupled to the second terminal of the first transistor; the second end; and A control terminal, configured to receive the data signal; a fourth transistor comprising: a first terminal coupled to the second terminal of the second transistor; A second terminal coupled to the second terminal of the third transistor; and A control terminal, configured to receive the reference voltage; a fifth transistor comprising: a first terminal coupled to the second terminal of the fourth transistor; The second terminal is coupled to the ground terminal; and The control terminal is used to receive a bias signal.

3. The reference voltage controlled equalized input data buffer circuit according to claim 2, wherein: The first transistor and the second transistor are P-type metal oxide semiconductor field effect transistors, and the third transistor, the fourth transistor, and the fifth transistor are N-type metal oxide semiconductor field effect transistors.

4. The reference voltage controlled equalized input data buffer circuit according to claim 1, wherein: The feedback signal generator includes: A plurality of first inverters connected in series are used to delay the signal of the first output end of the second amplifier to output a feedback signal.

5. The reference voltage controlled equalized input data buffer circuit according to claim 1, wherein: The reference voltage converter comprises: a third amplifier, configured to receive the reference voltage; At least one first resistor connected in series, comprising: A first terminal coupled to the third amplifier; and The second terminal is used to output a first potential reference voltage; At least one second resistor connected in series, comprising: A first terminal coupled to the second terminal of the at least one first resistor in series; and The second terminal is used to output a second potential reference voltage; At least one third resistor connected in series, comprising: A first terminal coupled to a second terminal of the at least one second resistor in series; and The second terminal is used to output a third potential reference voltage; and at least one fourth resistor connected in series, comprising: A first terminal coupled to a second terminal of the at least one third resistor connected in series; and The second end is coupled to the ground end.

6. The reference voltage controlled equalized input data buffer circuit according to claim 5, wherein: The reference voltage multitasking circuit includes: The first switch comprises: an input terminal, for receiving the first potential reference voltage; A first control terminal, configured to receive a first control signal; A second control terminal for receiving a second control signal; and An output terminal, used for outputting the reference voltage feedback signal; The second switch comprises: an input terminal, for receiving the second potential reference voltage; A first control terminal, configured to receive a third control signal; A second control terminal for receiving a fourth control signal; and an output terminal coupled to the output terminal of the first switch; and The third switch includes: An input terminal, for receiving the third potential reference voltage; The first control terminal is used to receive a fifth control signal; A second control terminal for receiving a sixth control signal; and The output terminal is coupled to the output terminal of the first switch.

7. The reference voltage controlled equalized input data buffer circuit according to claim 6, wherein: The first switch, the second switch, and the third switch include a pair of N-type metal oxide semiconductor field effect transistors and P-type metal oxide semiconductor field effect transistors, and the first control signal and the second control signal are opposite to each other, the third control signal and the fourth control signal are opposite to each other, and the fifth control signal and the sixth control signal are opposite to each other.

8. The reference voltage controlled equalized input data buffer circuit according to claim 6, wherein: The reference voltage multitasking circuit further includes: NAND gates, including: a first input terminal coupled to the first output terminal of the second amplifier; a second input terminal for receiving the third control signal; and Output terminal; NOR gates, including: a first input terminal coupled to the first output terminal of the second amplifier; a second input terminal, configured to receive the fourth control signal; and Output terminal; The second inverter comprises: an input terminal coupled to the output terminal of the NAND gate; and an output terminal, configured to output the second control signal; The third inverter includes: an input terminal coupled to the output terminal of the NOR gate; and an output terminal, configured to output the fifth control signal; The fourth inverter comprises: an input terminal for receiving the fourth control signal; and an output terminal, configured to output the third control signal; The fifth inverter comprises: an input terminal coupled to the output terminal of the second inverter; and an output terminal, configured to output the first control signal; and The sixth inverter comprises: an input terminal coupled to the output terminal of the third inverter; and The output terminal is used to output the sixth control signal.

9. The reference voltage controlled equalized input data buffer circuit according to claim 8, wherein: When the circuit is not in a reset state, if the first output terminal of the second amplifier is a high voltage, the first voltage reference voltage is enabled and the third voltage reference voltage is disabled; if the first output terminal of the second amplifier is a low voltage, the first voltage reference voltage is disabled and the third voltage reference voltage is enabled.

10. The reference voltage controlled equalized input data buffer circuit according to claim 1, wherein: The gain control unit includes: a sixth transistor comprising: a first terminal coupled to a first output terminal of the first amplifier; the second end; and a control terminal coupled to the feedback signal generator and configured to receive the feedback signal; A seventh transistor comprising: a first terminal coupled to the second output terminal of the first amplifier; A second terminal coupled to the second terminal of the sixth transistor; and A control terminal for receiving a reference voltage feedback signal; an eighth transistor comprising: a first terminal coupled to the second terminal of the seventh transistor; the second end; and a control terminal for receiving a bias signal; and A ninth transistor comprising: a first terminal coupled to the second terminal of the eighth transistor; The second terminal is coupled to the ground terminal; and The control terminal is used to receive a start signal.

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