Computer system and memory testing method based on wafer stacking architecture

Abstract

A memory testing method and a computer system based on wafer stacking architecture are disclosed. The memory testing method is applied to a computer system based on wafer stacking architecture. The computer system is a three-dimensional wafer product formed by a memory wafer layer, a logic circuit layer and a substrate. When performing memory testing, the memory devices in the memory wafer layer are divided into a plurality of memory sub-blocks, each of which is tested separately. First, a data table is established in one memory sub-block. Then, a plurality of different initial values prepared in advance are provided, and a proof-of-work operation is performed to generate a plurality of operation results corresponding to each initial value by performing multiple read / write operations on the data table. The judgment module obtains the operation results from the operation module and compares them with the corresponding known solutions to calculate the error rate of the tested memory sub-block.

Description

Technical Field

[0001] This application relates to an improved testing method for a memory device, and more particularly to a method for testing memory in a computer system implemented using wafer stacking technology. Background Technology

[0002] In this era, the application of artificial intelligence and blockchain has become a new business opportunity. Blockchain can be widely used in applications such as smart contracts, digital identity, and the sharing economy.

[0003] However, some blockchain platforms frequently alter their algorithms for various security considerations or vulnerability patching. In addition to increasing computational complexity, they often make deliberate design changes to reduce the computational efficiency of application-specific integrated circuits (ASICs), such as increasing memory throughput requirements or storage device capacity requirements.

[0004] Therefore, blockchain server developers must also change their hardware architecture to meet the high standards for memory throughput. Thus, a completely new hardware architecture for blockchain servers is needed. Furthermore, memory control and testing methods suitable for the new hardware architecture require corresponding improvements. Summary of the Invention

[0005] Traditional memory testing methods require a dedicated test module within the chip to perform the tests. In computer systems based on chip stacking architectures, testing all memory cells can be extremely time-consuming. However, for specific applications, sometimes it's only necessary to know whether the error rate of a certain area of ​​memory is below a certain value. If the error rate of this area meets the requirements, the memory is usable, without needing to know the location of all bad cells in that area. Therefore, this application proposes a rapid testing method that utilizes the native algorithm in the computing module, combined with different initial values ​​and known solutions, to directly determine the usability of the memory device based on the computation results of the computing module.

[0006] The memory testing method of this application is particularly applicable to computer systems based on a wafer-on-wafer architecture. A wafer-on-wafer architecture refers to a computer system consisting of a memory crystal layer, a logic circuit layer, and a substrate formed using wafer-on-wafer technology. The memory crystal layer includes at least one memory device. The logic circuit layer is connected to the memory device through multiple connection pads and includes firmware, a processing module connected to the firmware and the memory device, and a decision module connected to the processing module.

[0007] During memory testing, the memory device is typically divided into multiple memory sub-blocks, each tested individually. When testing a memory sub-block, a data table is first created within that sub-block. Then, multiple pre-prepared initial values ​​and a known solution corresponding to each initial value are provided. Each initial value is required by the computation module for proof-of-work operations. The proof-of-work operation involves multiple reads and writes to the data table, generating multiple computation results corresponding to each initial value. The judgment module obtains these computation results from the computation module and compares them with the corresponding known solutions to calculate the error rate of the tested memory sub-block.

[0008] In a further embodiment, the determination module compares the error rate and a threshold value of the memory sub-block to determine whether the memory sub-block is available or unavailable. Then, based on the availability determination result, the determination module records the number of the memory sub-block in the firmware.

[0009] In a specific embodiment, the proof-of-work operation can be an Ethash algorithm. The data table is a directed acyclic graph (DAG).

[0010] To ensure that the memory cells in each memory subblock are fully tested, a directed acyclic graph of the same size as the memory subblock can be generated in the memory subblock through programmable configuration of the arithmetic module.

[0011] In a further embodiment, the pre-prepared initial values ​​and corresponding known solutions may be pre-stored in the firmware at the factory or be values ​​input externally on the spot. During testing, the judgment module obtains the known solutions from the firmware or external sources and compares them with the test results.

[0012] This application also proposes embodiments of the above-described computer system based on a chip stacking architecture.

[0013] In summary, the memory testing method proposed in this application is applicable to computer systems with a chip stacking architecture. By utilizing the native algorithm in the computing module combined with different initial values ​​and known solutions, the availability of the memory device can be directly determined based on the computation results of the computing module. This method does not require the design of additional test logic in the computer system, and the testing efficiency is also exponentially improved. Attached Figure Description

[0014] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0015] Figure 1 This is the stereo wafer product 100 of this application embodiment.

[0016] Figure 2 This is the computer system 200 in this application embodiment.

[0017] Figure 3 This is a flowchart of a memory testing method according to an embodiment of this application. Detailed Implementation

[0018] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0019] Figure 1 This is a schematic diagram of the wafer stacking architecture of the stereochip product 100. The stereochip product 100 consists of at least one memory crystal layer 110, a logic circuit layer 120, and a substrate 130 stacked layer by layer. Multiple memory devices 112 are disposed in the memory crystal layer 110. The memory devices 112 can be memory modules composed of memory chips, such as dynamic random access memory (DRAM). The logic circuit layer 120 is a wafer layer in which multiple logic circuits 122 are disposed. These logic circuits 122 are a general term for various wafer modules, such as, but not limited to, application-specific integrated circuits (ASICs), memory controllers, or processors. The bottommost substrate 130 provides basic support and additional wiring space. Multiple connection pads 102 or 104 are configured between each layer to provide signal paths. The stereochip product 100 of this embodiment is a semi-finished product of a computer system 200, which, after being cut, can produce multiple independently operating computer systems 200. Figure 1 Although only one base 130 is shown, this is not a limitation in solid design; multiple bases 130 can be arranged in parallel. For example... Figure 1 As shown, each computer system 200 may include a plurality of memory devices 112 and a plurality of logic circuits 122, possessing the same three-dimensional chip structure. In other words, the memory devices 112 and logic circuits 122 included in each computer system 200 are pre-laid in the memory crystal layer 110 and the logic circuit layer 120, and then fabricated as a three-dimensional structure in the form of chip stacking. In the three-dimensional structure, the circuit wires between the chip groups do not need to occupy extra area, and thousands of connection pads 102 and 104 can be used directly as signal transmission paths, so that the data transmission efficiency problem is effectively solved, thereby realizing the computer system 200 of this application.

[0020] exist Figure 1 In this chip stacking architecture, the number of transmission lines is no longer limited by planar design, allowing for the use of numerous dedicated wirings to address data transmission performance issues. The smaller spacing between the memory crystal layer 110 and the logic circuit layer 120 enables the placement of more interfaces within the same area. Bandwidth is calculated by multiplying the number of interfaces by the channel frequency formula; therefore, more interfaces result in higher bandwidth. Thanks to chip stacking technology, applications requiring significant memory access, such as machine learning, artificial intelligence, or blockchain applications, can achieve exponential performance improvements.

[0021] Figure 2 This is a computer system 200 according to an embodiment of this application. The computer system 200 is composed of... Figure 1 The product is formed by stacking and then cutting the memory crystal layer 110, logic circuit layer 120, and substrate 130. The computer system 200 may include one or more memory devices 210 cut from the memory crystal layer 110, and multiple wafers cut from the logic circuit layer 120, such as firmware 202, arithmetic module 204, and decision module 206. The arithmetic module 204 may include the functions of a memory controller, through... Figure 1 The multiple connection pads 102 shown connect to the memory device 210. For example, the memory device 210 may include multiple memory arrays (BANK), each memory array containing multiple memory cells (not shown). Each memory cell is used to store bit data 0 or 1. Each row or column of memory cells can be connected to the arithmetic module 204 via corresponding multiple connection pads 102. Known standard specifications exist for the internal circuitry of the memory, therefore detailed embodiments are not described further.

[0022] The chip stacking process requires a high level of technical expertise. If the 3D chip product 100 and the logic circuit layer 120 cannot be accurately aligned during manufacturing, the resulting computer system 200 will not function properly. For example, if the connection of the arithmetic module 204 cannot transmit signals due to errors in the chip stacking process, the arithmetic module 204 will be unable to access data from the corresponding memory cell. Therefore, a method is needed to test the memory device 210 in the computer system 200.

[0023] A common memory testing method is to integrate the memory test logic into the chip. For example, when the arithmetic module 204 receives a command to execute a test, it will automatically test the memory device; this method is called a built-in self-test (BIST). However, as the number of memory devices increases, the time required to execute a complete BIST (including the time to execute the test and the time to read the results) will also increase.

[0024] The BIST test for memory is a fairly comprehensive test that can identify all bad cells in the memory. However, not all applications require finding all bad cells. Sometimes, we only need to know whether the error rate of a certain area of ​​the memory is below a certain value. If the error rate of this area of ​​the memory meets the requirements, then this memory can be used, without needing to know the location of all bad cells in this area.

[0025] The embodiments proposed in this application first divide the memory into multiple memory sub-blocks 212, and then the arithmetic module 204 directly uses each memory sub-block 212 to execute the native function of the arithmetic module 204, which can quickly predict the data error rate of all memory sub-blocks 212. The arithmetic module 204 can be a logic circuit of a specific algorithm, and its native function can be a proof-of-work algorithm. In this embodiment, if the data error rate of a memory sub-block 212 is greater than a threshold value, the memory sub-block 212 is marked as an unusable block. Conversely, if the data error rate of the memory sub-block 212 is less than the threshold value, the memory sub-block 212 is marked as a usable block. After the memory test is completed, the information of the usable blocks can be stored in the firmware 202 for subsequent applications by the computer system 200.

[0026] Generally, users are required to perform some complex calculations that take a reasonable amount of time, and the answer can be quickly verified by the service provider. The time, equipment, and energy consumed serve as collateral costs to ensure that the service and resources are used for genuine needs. This concept was first proposed in 1993, and the term Proof-of-Work was formally published in 1999, becoming the mainstream blockchain mechanism today.

[0027] Proof-of-Work (PoW) algorithms are block-solving algorithms based on hash functions. Given any initial value, the hash function generates a corresponding result. Changing even a single bit in the initial value triggers an avalanche effect, making reverse engineering virtually impossible. Therefore, by finding computation results with specific characteristics and requiring users to perform extensive brute-force calculations, PoW can be achieved. Common PoW algorithms include SHA-256, Ethash, Scrypt, Equihash, and CryptoNode. The following explanation uses Ethash as an example; other algorithms have internationally recognized standards, and their detailed operation will not be repeated here.

[0028] Ethereum Hash (Ethash) is a proof-of-work algorithm modified from the Dagger-Hashimoto algorithm. Its main principle is to increase the memory load through a large number of random table lookups, thereby hindering the speedup effect of application-specific integrated circuits (ASICs). Ethash uses a data table with an initial value of 1GB and a fake random number cache with an initial value of 16MB. Every 30,000-block interval, the data table and the fake random number cache are recalculated. This 30,000-block interval is called an epoch. The content generated in each epoch increases, so 1GB and 16MB are just basic values. The computer system in this embodiment stores the entire data table and the fake random number cache. When the computer system performs proof-of-work calculations on a block, it first fills a random number (nonce) into the block header and continuously looks up the mixed value (MIX) in SHA-3 form to calculate the solution for the block.

[0029] The data table used by the Ether Hash Algorithm during its operation is called a Directed Acyclic Graph (DAG). When performing the Proof-of-Work algorithm, the computation module 204 randomly reads data from the DAG 64 times, each data entry being 128 bytes. The computation module 204 first randomly selects an initial value, then randomly reads a data entry from the DAG. After merging the initial value with the data entry read from the DAG, the computation module 204 converts it into an intermediate product using the SHA-3 hash function. Next, the computation module 204 randomly reads another data entry from the DAG, mixes it with the intermediate product, and executes the SHA-3 hash function again. After repeating this process 64 times, the computation module 204 obtains a Proof-of-Work.

[0030] like Figure 2 As shown, the computer system 200 is a wafer stack formed by a memory crystal layer 110, a logic circuit layer 120, and a substrate 130 using wafer-on-wafer technology. The memory crystal layer 110 includes at least one memory device. The logic circuit layer 120 is connected to the memory device via multiple connection pads 102 and includes firmware 202, a computing module 204 connecting the firmware 202 and the memory device, and a decision module 206 connected to the computing module 204.

[0031] During memory testing, the memory device is typically divided into multiple memory sub-blocks 212, each tested individually. When testing one of the memory sub-blocks 212, a data table is first created within that sub-block. Then, multiple pre-prepared initial values ​​#N and a known solution #A corresponding to each initial value #N are provided. Each initial value #N is the value required by the computation module 204 for proof-of-work operations. The computation module 204 can also use an externally input hash value #H as an initial value. Each proof-of-work operation involves multiple reads and writes to the data table in the memory sub-block 212, generating multiple operation results corresponding to each initial value #N. After obtaining these operation results from the computation module 204, the judgment module 206 compares them with the corresponding known solution #A to calculate the error rate of the tested memory sub-block 212.

[0032] After calculating the error rate of the memory sub-block 212, the judgment module 206 compares it with a threshold value #T to determine whether the memory sub-block 212 is available or unavailable. Then, the judgment module 206 records the number #R of the available or unavailable memory sub-block 212 in the firmware 202. For example, in some applications, the threshold value #T only needs to be 80%. In more demanding applications, the threshold value #T may require 99% or 99.999%.

[0033] The proof-of-work operation mentioned in this embodiment can be an etheric hash algorithm. The data table is the aforementioned directed acyclic graph (DAG). To ensure that the memory cells in each memory sub-block 212 are fully tested, a directed acyclic graph (DAG) of the same size as the memory sub-block 212 can be generated in the memory sub-block 212 through the programmable configuration of the operation module 204.

[0034] Furthermore, the pre-prepared initial value #N and the corresponding known solution #A can be pre-stored in the firmware 202 at the factory, or values ​​input from an external source in real time.

[0035] In an embodiment of the computer system 200 of this application, the initial size of the directed acyclic graph (DAG) can be 1GB. However, the size of the DAG increases as the number of blocks on the blockchain increases. That is, the size of the DAG is not always a fixed value and can be increased or decreased as needed in practical applications.

[0036] Assuming the total size of the memory device in computer system 200 is 4GB, we can divide the memory device into 8192 memory sub-blocks 212, each of the same size (512 kilobytes; KB). Simultaneously, the size of the directed acyclic graph (DAG) in the Ethash algorithm is also configured to 512KB. Thus, running the Ethash algorithm once to obtain one proof-of-work step is equivalent to randomly reading 64 * 128 bytes = 8KB of data from each 512KB memory sub-block 212. In a more advanced approach, the size of each memory sub-block 212 can be flexibly adjusted. For example, if a memory sub-block 212 is found to have a high error rate after testing, it can be divided into smaller memory sub-blocks for further testing, thereby reducing the range of unusable sub-blocks and increasing usable capacity.

[0037] This embodiment can prepare multiple sets of initial values ​​with known results in advance as test samples. When the operation module 204 obtains an operation result using a memory sub-block 212, it can compare this operation result with the known results. If they are the same, it means that the 8KB of data randomly read this time is correct. This embodiment can reuse different initial values ​​to make the operation module 204 perform multiple operations on the same memory sub-block 212 to increase the number of memory cells accessed in the memory sub-block 212. It can be understood that since the memory sub-block 212 stores a directed acyclic graph (DAG), after performing multiple test operations on the same memory sub-block 212 using a certain number of different initial values, it can be confirmed that all memory cells in the memory sub-block 212 have been tested. Similarly, the above process can also be applied to 8192 regions in the memory device. After testing all usable regions in the memory sub-block 212, the memory device can be used for subsequent calculations and applications.

[0038] Figure 3 The image shows a memory testing method described in an embodiment of this application. Figure 2 The steps performed in the computer system 200 can be summarized as follows.

[0039] In step 301, computer system 200 begins memory testing. In step 303, one memory sub-block 212 in the memory device is sequentially selected for testing. Steps 305 to 309 are then repeated. In step 305, proof-of-work operations are sequentially performed on the memory sub-block 212 using multiple pre-prepared different initial values. In step 307, the result of each proof-of-work operation is compared with the corresponding known solution to determine if the result is correct. In step 309, it is determined whether the proof-of-work operations for all initial values ​​have been completed. If so, step 311 continues. If there are still unused initial values, step 305 is repeated.

[0040] In step 311, the data error rate of memory sub-block 212 is calculated. Since multiple correct and incorrect records of calculation results have been obtained in steps 305 to 309, the data error rate of memory sub-block 212 can be statistically calculated. In step 313, the judgment module 206 can mark the memory sub-block as usable or unusable based on the data error rate.

[0041] In step 315, it is confirmed whether the testing of all memory sub-blocks 212 in the memory device has been completed. If there are still memory sub-blocks 212 that have not been tested, steps 303 to 313 are repeated.

[0042] In step 317, after all memory sub-blocks 212 have completed the test, the judgment module 206 stores the marking information of the memory sub-blocks that are judged to be usable or unusable in the firmware. It is understood that the above steps are merely illustrative, and the execution order can be reasonably adjusted. This memory testing method can be performed when the computer system 200 is powered on, or when the computer system 200 is in an idle state. This memory testing method can also be triggered only upon user request.

[0043] In summary, this application provides a memory testing method and a computer system suitable for chip stacking architectures. By utilizing the native algorithm in the arithmetic module 204 with different initial values ​​and known solutions, the availability of the memory device can be directly determined based on the calculation results of the arithmetic module 204. This method eliminates the need to design additional test logic in the computer system 200, and also exponentially improves testing efficiency.

[0044] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0045] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these are within the protection scope of this application.

Claims

1. A memory testing method, characterized in that, Applied to a computer system; wherein the computer system includes at least one memory device, firmware, a computing module connecting the firmware and the memory device, and a judgment module connected to the computing module; wherein the memory testing method includes: The memory device is divided into multiple memory sub-blocks; A data table is created in one of the multiple memory sub-blocks; Provide multiple different initial values, and the known solution corresponding to each initial value; The calculation module performs multiple proof-of-work operations. Each proof-of-work operation reads and writes the data table multiple times based on one of the multiple different initial values ​​to generate the corresponding calculation result. as well as The judgment module obtains multiple calculation results from the calculation module and compares them with the corresponding known solutions to calculate the error rate of the memory sub-block.

2. The memory testing method according to claim 1, characterized in that, Further includes: The judgment module compares the error rate of the memory sub-block with the critical value to determine the availability of the memory sub-block.

3. The memory testing method according to claim 2, characterized in that, Further includes: Based on the availability determination result, the determination module records the number of the memory sub-block in the firmware.

4. The memory testing method according to claim 1, characterized in that: The proof-of-work operation is a block-solving algorithm based on a hash function; and The data table is a directed acyclic graph.

5. The memory testing method according to claim 4, characterized in that: The size of the directed acyclic graph is the same as the size of the memory sub-block; and The computer system is based on a chip stacking architecture and includes a memory crystal layer, a logic circuit layer and at least one substrate, wherein the memory crystal layer, the logic circuit layer and the at least one substrate are stacked in a three-dimensional structure.

6. A computer system based on a chip stacking architecture, characterized in that, Include: At least one memory device; firmware; The computing module connects the firmware and the memory device, and performs tests on the memory device; and The judgment module is connected to the calculation module; wherein: The computing module divides the memory device into multiple memory sub-blocks. When the computing module tests a memory sub-block, it establishes a data table in the memory sub-block and sequentially performs multiple proof-of-work operations using multiple initial values, so that the data table is read and written multiple times to generate multiple operation results corresponding to the multiple initial values, wherein each initial value corresponds to a known solution; as well as The judgment module obtains the multiple calculation results from the calculation module and compares them with the corresponding known solutions to calculate the error rate of the memory sub-block.

7. The computer system based on a chip stacking architecture according to claim 6, characterized in that, The judgment module compares the error rate of the memory sub-block with the critical value to determine the availability of the memory sub-block.

8. The computer system based on a chip stacking architecture according to claim 7, characterized in that, Based on the availability determination result, the determination module records the number of the memory sub-block in the firmware.

9. The computer system based on a chip stacking architecture according to claim 6, characterized in that: The proof-of-work operation is a block-solving algorithm based on a hash function; and The data table is a directed acyclic graph.

10. The computer system based on a chip stacking architecture according to claim 9, characterized in that: The size of the directed acyclic graph is the same as the size of the memory sub-block.

11. The computer system based on a chip stacking architecture according to claim 6, characterized in that, It further includes a memory crystal layer, a logic circuit layer, and at least one substrate, wherein the memory crystal layer, the logic circuit layer, and the at least one substrate are stacked in a three-dimensional structure; wherein: The logic circuit layer is connected to the memory device and the substrate through multiple connection pads; The firmware, the arithmetic module, and the judgment module are configured in the logic circuit layer; and The memory device is disposed in the memory crystal layer.

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