Base chip, memory system, and semiconductor structure

Abstract

Embodiments of the present disclosure provide a basic chip, a storage system, and a semiconductor structure. The basic chip is configured to receive first data and first encoded data during a write phase. The first encoded data is obtained by performing first error correction code encoding processing on the first data, and perform second error correction code encoding processing on the first data to generate second encoded data. During the write phase, the basic chip transmits second data to the storage chip. The second data includes the first data, the first encoded data, and the second encoded data. The basic chip is further configured to receive the second data from the storage chip during a read phase, perform first error detection and correction processing on the first data and the second encoded data, and transmit third data during the read phase. The third data includes the first encoded data and the first data after the first error detection and correction processing. Embodiments of the present disclosure can improve the storage performance of the storage system.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of semiconductor technologies, and particularly to a basic chip, a storage system, and a semiconductor structure. Background Art

[0002] Semiconductor storage can be divided into non-volatile storage and volatile storage. As volatile storage, Dynamic Random Access Memory (DRAM) has advantages such as high storage density and fast read / write speed, and is widely used in various electronic systems.

[0003] As the manufacturing process of DRAM becomes more and more advanced and the storage density becomes higher and higher, data stored in DRAM may be incorrect, seriously affecting the performance of DRAM. Therefore, Error Checking and Correction (ECC) technology is usually adopted in DRAM to detect or correct errors in stored data. Summary of the Invention

[0004] Embodiments of the present disclosure provide a basic chip, a storage system, and a semiconductor structure, which are at least beneficial to solving the problem of tight area of the controller or the storage chip.

[0005] According to some embodiments of the present disclosure, on the one hand, a basic chip is provided, which is applied to a storage system and includes: the basic chip is configured to receive first data and first encoded data in a write stage, the first encoded data is obtained by performing first error correction code encoding processing on the first data, and perform second error correction code encoding processing on the first data to generate second encoded data, and transmit second data to a storage chip in the write stage, the second data includes the first data, the first encoded data, and the second encoded data; the basic chip is further configured to receive the second data from the storage chip in a read stage, perform first error detection and correction processing on the first data and the second encoded data, and transmit third data in the read stage, the third data includes the first encoded data and the first data after the first error detection and correction processing.

[0006] In addition, the basic chip includes: a second encoding module configured to receive the first data and perform the second error correction code encoding processing to generate the second encoded data in the write stage; a first error detection and correction module configured to receive the first data and the second encoded data and perform the first error detection and correction processing in the read stage.

[0007] In addition, the base chip further includes: a first serial-to-parallel conversion module configured to receive the first data and the first encoded data during a write phase, perform a first serial-to-parallel conversion process on the first data and the first encoded data, and transmit the first data after the first serial-to-parallel conversion process to the second encoding module, and transmit the first encoded data after the first serial-to-parallel conversion process to the storage chip; a first parallel-to-serial conversion module configured to receive the third data during a read phase, perform a first parallel-to-serial conversion process on the third data, and transmit the third data after the first parallel-to-serial conversion process to the controller.

[0008] In addition, the base chip further includes: a second parallel-to-serial conversion module configured to receive the second data during a write phase, perform a second parallel-to-serial conversion process, and transmit the second data after the second parallel-to-serial conversion process to the storage chip; a second serial-to-parallel conversion module configured to receive the second data from the storage chip during a read phase, perform a second serial-to-parallel conversion process, and transmit the second encoded data and the first data after the second serial-to-parallel conversion process to the first error detection and correction module, and output the first encoded data after the second serial-to-parallel conversion process.

[0009] In addition, the base chip is further configured to generate a first error detection flag signal during the first error detection and correction process, and record the error conditions of the first data and the second encoded data during transmission based on the first error detection flag signal.

[0010] In addition, the base chip further includes: a first storage buffer module configured to store the error conditions of the first data and the second encoded data during transmission; a first command module that receives a polling instruction and generates a first command signal and a first clock signal; the first storage buffer module is further configured to output a first characterization signal based on the first command signal and the first clock signal, and the first characterization signal characterizes the error conditions of the first data and the second encoded data during transmission.

[0011] In addition, the first storage buffer module includes a first-in, first-out register.

[0012] In addition, the first error correction code encoding process and the second error correction code encoding process are performed using different encoding and decoding algorithms.

[0013] In addition, the number of bits of the first encoded data is different from the number of bits of the second encoded data.

[0014] According to some embodiments of the present disclosure, on the other hand, an embodiment of the present disclosure further provides a storage system, including a controller, a base chip, and a storage chip; the controller is configured to perform a first error correction code encoding process on first data in a write stage to generate first encoded data, and transmit the first data and the first encoded data to the base chip; the base chip is configured to receive the first data and the first encoded data in the write stage, perform a second error correction code encoding process on the first data to generate second encoded data, transmit second data to the storage chip in the write stage, the second data including the first data, the first encoded data, and the second encoded data, receive the second data from the storage chip in a read stage, perform a first error detection and correction process on the first data and the second encoded data, and transmit third data to the controller in the read stage, the third data including the first encoded data and the first data after the first error detection and correction process; the storage chip is configured to receive the second data and store the second data in the write stage, and transmit the second data to the base chip in the read stage; the controller is further configured to receive the third data from the base chip in the read stage, perform a second error detection and correction process on the third data, and obtain the first data after the second error detection and correction process.

[0015] In addition, the controller includes: a first encoding module configured to perform the first error correction code encoding process on the first data in the write stage to generate the first encoded data; a second error detection and correction module configured to receive the third data in the read stage and perform the second error detection and correction process on the third data.

[0016] In addition, the base chip includes: a second encoding module configured to receive the first data and perform the second error correction code encoding process on the first data to generate the second encoded data in the write stage; a first error detection and correction module configured to receive the first data and the second encoded data and perform the first error detection and correction process in the read stage.

[0017] In addition, the number of data transmission channels between the controller and the base chip is M, and the number of data transmission channels between the base chip and the storage chip is N; where M and N are both positive integers greater than 1, and N is greater than M.

[0018] In addition, the storage chip includes: a first storage module for storing the first data; a second storage module for storing the first encoded data; and a third storage module for storing the second encoded data.

[0019] In addition, the first error correction code encoding process and the second error detection and correction process are performed using a first compilation algorithm, the second error correction code encoding process and the first error detection and correction process are performed using a second compilation algorithm, and the first compilation algorithm is different from the second compilation algorithm.

[0020] In addition,

[0021] The base chip is further configured to generate a first error detection flag signal during the first error detection and correction process, and based on the first error detection flag signal, record the error conditions of the first data and the first two encoded data during transmission; the storage system further includes:

[0022] A first register configured to store the error conditions of the first data and the second encoded data during transmission.

[0023] In addition, the base chip includes: a first storage cache module configured to store the error conditions of the first data and the second encoded data during transmission; a first command module that receives a first polling instruction and generates a first command signal and a first clock signal; the first storage cache module is further configured to output a first characterization signal to the first register based on the first command signal and the first clock signal, and the first characterization signal characterizes the error conditions of the first data and the second encoded data during transmission.

[0024] In addition, the controller is further configured to generate a second error detection flag signal during the second error detection and correction process, and based on the second error detection flag signal, record the error conditions of the first data and the first encoded data during transmission; the storage system further includes: a second register configured to store the error conditions of the first data and the first encoded data during transmission.

[0025] In addition, the controller includes: a second storage buffer module configured to store the first data and the error situation of the first encoded data during transmission; a second command module that receives a second polling instruction and generates a second command signal and a second clock signal; the second storage buffer module is further configured to output a second characterization signal to the second register based on the second command signal and the second clock signal, where the second characterization signal characterizes the error situation of the first data and the first encoded data during transmission.

[0026] According to some embodiments of the present disclosure, yet another aspect of the embodiments of the present disclosure further provides a semiconductor structure, including: a carrier substrate; the above storage system, where the controller and the base chip are both located on the surface of the carrier substrate, and the memory chip is located on the surface of the base chip away from the carrier substrate.

[0027] The technical solutions provided by the embodiments of the present disclosure have the following advantages:

[0028] In the technical solution of the base chip provided by the embodiments of the present disclosure, after the base chip receives the first data and the first encoded data in the writing stage, it performs second error correction code encoding processing on the first data to generate second encoded data, and transmits the first data, the first encoded data, and the second encoded data into the memory chip; in the reading stage, the first data, the first encoded data, and the second encoded data transmitted from the memory chip are transmitted to the base chip, and the base chip can perform first error detection and correction processing on the first data and the second encoded data, transmit the first data after the first error detection and correction processing to the controller, and the base chip also transmits the first encoded data to the controller. That is to say, in the storage stage, the base chip can perform error detection and correction processing on the first data, that is, the base chip can share the encoding processing function and the error detection and correction function of the controller, which is beneficial to alleviating the problem of the tight chip area of the controller; and since the first data transmitted to the controller has been subjected to error detection and correction processing once, the accuracy of the first data after the controller performs error detection and correction processing again is improved, which is beneficial to improving the performance of the storage system. Description of the Drawings

[0029] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplary illustrations do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements, unless otherwise stated, and the drawings in the drawings do not constitute a proportional limitation.

[0030] Figure 1 It is a schematic structural diagram of a semiconductor structure;

[0031] Figure 2 isFigure 1 Schematic diagram of data transmission in the provided semiconductor structure;

[0032] Figures 3 to 6 Schematic diagram of the structure of the basic chip provided by the embodiments of the present disclosure;

[0033] Figures 7 to 10 The first schematic diagram of the structure of the storage system provided by the embodiments of the present disclosure;

[0034] Figure 11 Cross-sectional structure schematic diagram of the semiconductor structure provided by the embodiments of the present disclosure. Detailed implementation manners

[0035] Figure 1 It is a schematic diagram of the structure of a semiconductor structure, Figure 2 is Figure 1 Schematic diagram of data transmission in the provided semiconductor structure.

[0036] Referring to Figure 1 , the semiconductor structure may include: a substrate 11; a basic chip (base die) 12 and a controller (processor) 13 respectively located on the surface of the substrate 11; a plurality of core chips (core die) 14 are stacked on the basic chip 12, and the core chips 14 may be DRAM chips. Referring to Figure 2 , during the data transmission process in the semiconductor structure, it includes: in the writing stage, the controller 13 transmits data to the basic chip 12, and the basic chip 12 transmits the data into the core chip 14. The controller 13 may perform error correction code encoding processing on the data before transmitting the data; in the reading stage, the core chip 14 transmits the data to the basic chip 12, and then, the basic chip 12 transmits the data to the controller 13. The controller 13 receives the data and performs error code correction code decoding processing to detect and correct errors in the data.

[0037] It is not difficult to find that in the above semiconductor structure, the basic chip 12 does not participate in the error detection and correction processing, that is, there is no error correction code encoding function and corresponding error detection and correction function in the basic chip 12, and it is necessary for the controller 13 or the core chip 14 to complete the error detection, which makes the chip areas of the controller 13 and the core chip 14, where the chip area is already tight, even more tense. Therefore, the performance of the controller 13 and the core chip 14 is affected, and further the storage performance of the entire semiconductor structure needs to be improved.

[0038] The embodiments of the present disclosure provide a basic chip, a storage system, and a semiconductor structure, and the basic chip has an error detection and correction function. Figure 3 The first schematic diagram of the structure of the basic chip provided by the embodiments of the present disclosure, Figure 4 The second schematic diagram of the structure of the basic chip provided by the embodiments of the present disclosure,Figure 5 The third structural schematic diagram of the basic chip provided by the embodiments of the present disclosure; Figure 6 The fourth structural schematic diagram of the basic chip provided by the embodiments of the present disclosure.

[0039] The basic chip provided by the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0040] Reference Figure 3 , the basic chip 100 is applied to a storage system. Among them, the basic chip 100 is configured to receive a first data data1 and a first encoded data ecc1 during the writing stage. The first encoded data ecc1 is obtained by performing a first error correction code encoding process on the first data data1, and perform a second error correction code encoding process on the first data data1 to generate a second encoded data ecc2. During the writing stage, the second data data2 is transmitted to the storage chip. The second data data2 includes the first data data1, the first encoded data ecc1, and the second encoded data ecc2; the basic chip 100 is further configured to receive the second data data2 from the storage chip during the reading stage, and perform a first error detection and correction process on the first data data1 and the second encoded data ecc2, and transmit a third data data3 during the reading stage. The third data data3 includes the first encoded data ecc1 and the first data data1 after the first error detection and correction process.

[0041] In the embodiments of the present disclosure, the basic chip 100 participates in error correction code encoding processing and error detection and correction processing during data transmission. Specifically, in the writing stage, after receiving the first data data1 and the first encoded data ecc1, the basic chip 100 performs second error correction code encoding processing on the first data data1 to obtain the second encoded data ecc2, and the first data data1, the first encoded data ecc1, and the second encoded data ecc2 are all transmitted into the storage chip; in the reading stage, the first data data1, the first encoded data ecc1, and the second encoded data ecc2 transmitted from the storage chip are transmitted to the basic chip 100. The basic chip can perform first error detection and correction processing on the first data data1 and the second encoded data ecc2, transmit the first data data1 after the first error detection and correction processing to the controller, and the basic chip 100 also transmits the first encoded data ecc1 to the controller, so that the controller can perform second error detection and correction processing on the first data data1 after the first error detection and correction processing. That is to say, in the storage stage, the basic chip 100 can perform first error detection and correction processing on the first data data1, that is, the basic chip 100 can share the encoding processing function and the error detection and correction function of the controller, which is beneficial to alleviating the problem of the tight chip area of the controller, and can make full use of the relatively sufficient chip area of the basic chip 100. In addition, since the first data data1 transmitted to the controller has been subjected to error detection and correction processing once, the accuracy of the first data data1 after being subjected to error detection and correction processing again by the controller is improved, which is beneficial to improving the RAS performance of the storage system, that is, improving the reliability, availability, and serviceability of the storage system.

[0042] In addition, the basic chip 100 and the controller can perform error detection and correction on different data transmission paths, which is beneficial to locating the data transmission path where an error occurs.

[0043] In some embodiments, the basic chip 100 can be connected between the first port A and the second port B, where the first port A is connected to the data transmission port of the controller of the storage system, and the second port B is connected to the data transmission port of the storage chip of the storage system. It can be understood that the first port A and the second port B are general terms. The first port A includes multiple data transmission ports, and the second port B includes multiple data transmission ports. Among them, the number of data transmission ports is related to the number of data to be transmitted by the basic chip 100. For example, the number of data transmission ports can be the same as the number of data to be transmitted by the basic chip 100, and one data can be transmitted through one data transmission port.

[0044] Both the error correction code encoding process and the error detection and correction process are used to implement ECC error detection and correction, so as to detect and locate the errors occurring in the first data transmission process and correct the errors. In some embodiments, the ECC error detection and correction can adopt the error correction mechanism of Reed Solomon Code (RS), and correspondingly, the error correction code encoding process can adopt the RS encoding algorithm to generate encoded data, and the decoding process in the error detection and correction process can adopt the RS decoding algorithm. In other embodiments, the ECC error detection and correction can adopt the error correction mechanism of Hamming Code, and correspondingly, the error correction code encoding process can adopt the Hamming code encoding algorithm to generate encoded data, and the decoding process in the error detection and correction process can adopt the Hamming code decoding algorithm.

[0045] In some embodiments, the first data data1 can be data of 256 bits (bit), and correspondingly, the first encoded data ecc1 can be data of 16 bits. It can be understood that in other embodiments, due to the difference in the specific encoding algorithm adopted by the first error correction code encoding process, the number of bits of the first encoded data can also be different accordingly. In addition, the number of bits of the first data data1 can also be other quantities, such as 128, 512, etc.

[0046] In some embodiments, the first error correction code encoding process and the second error correction code encoding process can adopt different encoding algorithms, and the number of bits of the first encoded data ecc1 and the second encoded data ecc2 can be different. Correspondingly, the decoding algorithms adopted by the first error detection and correction process and the second error detection and correction process performed by the controller are also different. The encoding algorithm and the corresponding decoding algorithm are collectively referred to as the compilation algorithm. In this way, adopting different compilation algorithms for error detection and correction is beneficial to further improving the correct rate of data error correction and the data error detection and correction ability, and reducing the difficulty for the basic chip 100 to identify different encoded data. For example, the first data data1 is 256-bit data, the first encoded data ecc1 is 16-bit data, and the second encoded data ecc2 is 32-bit data.

[0047] It should be noted that in other embodiments, the first error correction code encoding process and the second error correction code encoding process can also adopt the same encoding algorithm. In addition, the encoding algorithm adopted by the second error correction code encoding process can correspond to the compilation algorithm adopted by the first error detection and correction process, where the compilation algorithm includes: the encoding algorithm adopted by the second error correction code encoding process and the decoding algorithm adopted by the first error detection and correction process, that is, the encoding algorithm corresponds to the decoding algorithm. In addition, the compilation algorithms adopted by the first error correction code encoding process and the second error detection and correction process can also correspond to each other.

[0048] Figure 4This is the second structural schematic diagram of the basic chip provided by the embodiments of the present disclosure. Refer to Figure 4 , in some embodiments, the basic chip 100 may include: a second encoding module 110, which is configured to receive the first data data1 and perform second error correction code encoding processing during the writing stage to generate second encoded data ecc2; a first error detection and correction module 120, which is configured to receive the first data data1 and the second encoded data ecc2 and perform first error detection and correction processing during the reading stage.

[0049] The second encoding module 110 is connected between the data transmission port of the controller and the data transmission port of the storage chip, and the first data data1 is transmitted to the second encoding module 110.

[0050] The first error detection and correction module 120 is connected between the data transmission port of the controller and the data transmission port of the storage chip, and the first error detection and correction module 120 performs first error detection and correction processing on the first data data1 and the second encoded data ecc2. Specifically, the paths where data errors can be detected by the first error detection and correction module 120 include: the transmission path from the second encoding module 110 to the storage chip during writing, and the transmission path from the storage chip to the first error detection and correction module 120 during reading.

[0051] It should be noted that the "first", "second", and "third" in the embodiments of the present disclosure are only for descriptive distinction, and there is no special limitation on the order in which the corresponding features appear.

[0052] The following will combine Figure 4 to describe the working principle of the basic chip 100 in detail:

[0053] During the writing stage, the first data data1 from the controller is transmitted to the second encoding module 110, and the second encoding module 110 performs second error correction code encoding processing on the first data data1 to generate second encoded data ecc2; then the first data data1 and the second encoded data ecc2 are written into the storage chip; in addition, the basic chip 100 also writes the first encoded data ecc1 into the storage chip. For example, the first data data1 is 256bit, the first encoded data ecc1 is 16bit, and the second encoded data ecc2 is 32bit. The 256bit first data data1, the 16bit first encoded data ecc1, and the 32bit second encoded data ecc2 are all stored in the storage chip.

[0054] In the reading stage, the first data data1 and the second encoded data ecc2 from the storage chip are read out and transmitted to the first error detection and correction module 120. The first error detection and correction module 120 performs the first error detection and correction process to obtain the first data data1 after the first error detection and correction process, and the first data data1 after the first error detection and correction process is transmitted to the controller. In addition, the base chip 100 also transmits the first encoded data ecc1 to the controller. For example, 256bit + 16bit + 32bit of data is read out from the storage chip. Among them, the 256bit first data data1 and the 32bit second encoded data ecc2 are processed by the first error detection and correction module 120 for the first error detection and correction process, and then 256bit of the first data data1 after the first error detection and correction process is output. The 256bit of the first data data1 after the first error detection and correction process is transmitted into the controller, and the 16bit first encoded data ecc1 is also transmitted into the controller via the base chip 100, enabling the controller to perform the second error detection and correction process. It can be understood that the objects for which the controller performs error detection and correction include: the first encoded data ecc1 and the first data data1 after the first error detection process.

[0055] Thus, in the reading stage, the base chip 100 can perform the first error detection and correction process on the first data data1 and the first encoded data ecc1, so that the first data data1 transmitted back to the controller is the data after the first error detection and correction process. That is to say, the accuracy rate of the first data data1 transmitted back to the controller is improved. Then, the controller performs the second error detection and correction process on the first data data1 after the first error detection and correction process and the first encoded data ecc1 to obtain the first data data1 after the second error detection and correction process, and the first data data1 after the second error detection and correction process will also have a high accuracy rate accordingly.

[0056] In summary, the base chip 100 is beneficial to improving the overall data error detection and correction accuracy rate of the storage system. In addition, the storage chip in the storage system does not need to have encoding processing functions and error detection and correction functions, and the base chip 100 can share the encoding processing functions and error detection and correction functions required by the controller, which is beneficial to improving the performance of the controller and the storage chip, and reasonably utilizing the chip area of the base chip 100, which is beneficial to alleviating the chip area pressure of the controller and the storage chip, and further beneficial to improving the storage performance of the storage system.

[0057] Figure 5 This is the third structural schematic diagram of the base chip provided in the embodiment of the present disclosure. Refer to Figure 5, in some embodiments, the base chip 100 may further include: a first serial-to-parallel conversion (DES, DESerializer) module 130, which is configured to receive a first data data1 and a first encoded data ecc1 during the write phase, perform a first serial-to-parallel conversion process on the first data data1 and the first encoded data ecc1, and transmit the first data after the first serial-to-parallel conversion process to the second encoding module, and transmit the first encoded data after the first serial-to-parallel conversion process to the storage chip; a first parallel-to-serial conversion (SER, SERlializer) module 140, which is configured to receive a third data data3 during the read phase, perform a first parallel-to-serial conversion process on the third data data3, and transmit the third data data3 after the first parallel-to-serial conversion process to the controller.

[0058] The settings of the first serial-to-parallel conversion module 130 and the first parallel-to-serial conversion module 140 can reduce the number of transmission channels between the base chip 100 and the controller and increase the number of bits transmitted by each transmission channel; in addition, since the number of transmission channels is reduced, the number of data transmission ports required to be set on the base chip 100 and the controller can be saved, thereby saving the chip area of the base chip 100 and the chip area of the controller. The first data data1 and the first encoded data ecc1 are transmitted to the first serial-to-parallel conversion module 130 in a serial manner. The first serial-to-parallel conversion module 130 can also be called a deserialization unit, that is, it deserializes the serial first data data1 and the first encoded data ecc1. The first parallel-to-serial conversion module 140 performs a serial processing on the third data data3 and transmits the third data data3 after the serial processing. The first parallel-to-serial conversion module 140 can also be called a serializer.

[0059] For example, if the first data data1 is 256 bits, the first data data1 is transmitted to the first serial-to-parallel conversion module 130 through 32 transmission channels. If the first encoded data ecc1 is 16 bits, the first encoded data ecc1 is transmitted to the first serial-to-parallel conversion module 130 through 2 transmission channels; after the first data data1 and the first encoded data ecc1 are deserialized by the first serial-to-parallel conversion module 130, the first data data1 is transmitted to the second encoding module 110 in parallel through 256 transmission channels, and the first encoded data ecc1 is transmitted to the storage chip through 16 transmission channels.

[0060] For example, 256 bits is the first data data1 after the first error detection and correction process, 16 bits is the first encoded data ecc1. After the third data dtat3 is serially processed by the first serial-to-parallel conversion module 140, it can be changed into 32 + 2 string data, and the 32 + 2 string data can be transmitted through 32 + 2 transmission channels. Among them, 32 string data is the first data data1 after the first error detection and correction process, and 2 string data is the first encoded data ecc1.

[0061] Reference Figure 5 , in some embodiments, in addition to the first parallel-to-serial conversion module 130 and the first serial-to-parallel conversion module 140, the base chip 100 may further include: a second serial-to-parallel conversion module 150, which is configured to receive the second data data2 and perform a second serial-to-parallel conversion process during the writing stage, and transmit the second data data2 after the second serial-to-parallel conversion process to the storage chip; a second parallel-to-serial conversion module 160, which is configured to receive the second data data2 from the storage chip and perform a second parallel-to-serial conversion process during the reading stage, and transmit the second encoded data and the first data after the second parallel-to-serial conversion process to the first error detection and correction module, and output the first encoded data after the second parallel-to-serial conversion process, and the first encoded data is transmitted to the controller.

[0062] The second serial-to-parallel conversion module 150 performs serial processing on the second data data2, which is beneficial to reducing the transmission channels between the base chip 100 and the storage chip, thereby saving the number of data transmission ports required on the base chip 100 and the storage chip, and further saving the chip area of the base chip 100 and the chip area of the storage chip. For example, if the first data is 256 bits, the first encoded data ecc1 is 16 bits, and the second encoded data is 32 bits, after the serial-to-parallel conversion process by the second serial-to-parallel conversion module 150, 128 + 8 + 16 transmission channels can be used to transmit the second data data2. Among them, 128 transmission channels transmit the first data data1, 8 transmission channels transmit the first encoded data ecc1, and 16 transmission channels transmit the second encoded data ecc2.

[0063] In addition, in some embodiments, the base chip 100 may also be configured to generate a first error detection flag signal during the first error detection and correction process, and record the error conditions of the first data data1 and the second encoded data ecc2 during the transmission process based on the first error detection flag signal. Specifically, if an error occurs in the first data data1 or the second encoded data ecc2 during the transmission process, a first error detection flag signal is generated; if no error occurs in the first data data1 and the second encoded data ecc2 during the transmission process, no first error detection flag signal is generated. In addition, in some embodiments, the first error detection flag signal may be defined as: if an error occurs in the first data data1 or the second encoded data ecc2 during the transmission process, the first error detection flag signal is 1; if no error occurs in the first data data1 and the second encoded data ecc2 during the transmission process, the first error detection flag signal is 0. In some other embodiments, the first error detection flag signal may also be defined as: if an error occurs in the first data data1 or the second encoded data ecc2 during the transmission process, the first error detection flag signal is 0; if no error occurs in the first data data1 and the second encoded data ecc2 during the transmission process, the first error detection flag signal is 1.

[0064] Through the first error detection flag signal, it is possible to obtain whether an error occurs in the first data data1 or the second encoded data ecc2 in the data transmission path from the controller to the base chip 100 during the write phase, and it is also possible to obtain whether an error occurs in the first data data11 or the second encoded data ecc2 in the data transmission path from the storage chip to the base chip during the read phase.

[0065] As Figure 6 shown, Figure 6 FIG. 4 is a schematic structural diagram of a fourth type of base chip provided by an embodiment of the present disclosure. In some embodiments, the base chip 100 may further include: a first storage buffer module 101, which is configured to store the error conditions of the first data data1 and the second encoded data ecc2 during the transmission process; a first command module 102, which receives a first polling instruction PS1 and generates a first command signal CMD1 and a first clock signal CLK1; the first storage buffer module 101 is further configured to output a first characterization signal flag1 based on the first command signal CMD1 and the first clock signal CLK1, and the first characterization signal flag1 characterizes the error conditions of the first data data1 and the second encoded data ecc2 during the transmission process.

[0066] In addition, in the case where the first polling instruction PS1 is not received, the first storage buffer module 101 only stores the error conditions of the first data data1 and the second encoded data ecc2 during the transmission process; after the first command module 102 receives the first polling instruction PS1, it controls the first storage buffer module 101 to output a first representation signal flag1 indicating the error conditions of the first data data1 or the second encoded data ecc2 during the transmission process. Based on this first representation signal flag1, the error conditions of the first data data1 and the second encoded data ecc2 can be obtained.

[0067] In some embodiments, the first representation signal flag1 can be a binary string. For example, if an error is detected in the first data data1 or the second encoded data ecc2 during the transmission process, 1 is recorded; if no error is detected in the first data data1 and the second encoded data ecc2 during the transmission process, 0 is recorded. Thus, after a period of time, the first representation signal flag1 is a binary string composed of 0 and 1. In other embodiments, the first representation signal flag1 can also be a decimal value. For example, the first storage buffer module 101 can be a counter, and if an error is detected in the first data data1 or the second encoded data ecc2 during the transmission process, it is incremented by 1. Thus, after a period of time, the first representation signal flag1 is a decimal value related to the number of errors.

[0068] In some embodiments, the first storage buffer module 101 can be a first-in-first-out (FIFO, First Input First Output) register. Using a first-in-first-out register as the first storage buffer module 101 can cache continuous data streams to prevent data loss during storage operations; in addition, the error conditions of the first data data11 and the second encoded data ecc2 during the transmission process are centralized for stacking and storage, which can avoid frequent bus operations and is beneficial to improving the data transmission speed.

[0069] In addition, in some embodiments, the first clock signal CLK1 can be independently generated by the first command module 102; in other embodiments, the first clock signal CLK1 can also be externally provided, such as being generated by the controller that generates the first polling instruction PS1.

[0070] The basic chip 100 provided in the above embodiments not only has the function of data transmission, but also has the functions of error correction code encoding processing and error detection and correction processing. Thus, the chip area of the basic chip 100 can be effectively utilized, reducing the chip area pressure on the controller and the storage chip and saving the chip area of the controller and the storage chip.

[0071] Moreover, since the base chip 100 can perform second error correction code encoding processing on the first data data1 to obtain the second encoded data ecc2, and can transmit the second encoded data ecc2, the first encoded data ecc1, and the first data data1 to the storage chip, facilitating the first error detection and correction processing of the first data data1 based on the second encoded data ecc2 during the reading stage, it is possible to detect whether errors occur in the first data data1 and the second encoded data ecc2 during the writing stage or the reading stage and correct the errors. Moreover, the first encoded data ecc1 and the first data data1 after the first error detection and correction processing can be transmitted to the controller, so that the controller can perform error detection and correction processing again, thereby improving the error detection and correction ability of the storage system and enhancing the data error detection and correction accuracy rate.

[0072] Another embodiment of the present disclosure further provides a storage system, which includes a controller, a storage chip, and a base chip as provided in the foregoing embodiment. The following will describe in detail the storage system provided in another embodiment of the present disclosure. It should be noted that for the same or corresponding parts as those in the foregoing embodiment, reference may be made to the detailed description of the foregoing embodiment, and the following will not be repeated.

[0073] Figure 7 It is a schematic diagram of the first structure of the storage system provided in the embodiment of the present disclosure.

[0074] Reference Figure 7, the storage system includes: a base chip 200, a controller 300, and a storage chip 400; the controller is configured to perform a first error correction code encoding process on the first data data1 during the write phase to generate first encoded data ecc1, and transmit the first data data1 and the first encoded data ecc1 to the base chip 200; the base chip 200 is configured to receive the first data data1 and the first encoded data ecc1 during the write phase, perform a second error correction code encoding process on the first data data1 to generate second encoded data ecc2, transmit second data data2 to the storage chip 400 during the write phase, the second data data2 includes the first data data1, the first encoded data ecc1, and the second encoded data ecc2, receive the second data data2 from the storage chip 400 during the read phase, perform a first error detection and correction process on the first data data1 and the second encoded data ecc2, and transmit third data data3 to the controller during the read phase, the third data data3 includes the first encoded data ecc1 and the first data data1 after the first error detection and correction process; the storage chip 400 is configured to receive the second data data2 and store the second data data2 during the write phase, and transmit the second data data2 to the base chip 200 during the read phase; the controller 300 is further configured to receive the third data data3 from the base chip 200 during the read phase, perform a second error detection and correction process on the third data data3, and obtain the first data data1 after the second error detection and correction process.

[0075] In the above storage system, the error correction code encoding process and the error detection and correction process performed on the data can both be implemented by the base chip 200. Thus, the storage chip 400 does not need to perform the encoding process and the error detection and correction process, and the base chip 200 can share the encoding process and the error detection and correction process required by the controller 300, so that the functions required by the controller 300 and the storage chip 400 are relatively reduced. Therefore, the pressure on the tight chip area of the controller 300 and the storage chip 400 can be alleviated, so as to better improve the performance of the controller 300 and the storage chip 400. For example, the reliability of the storage chip 400 can be improved, thereby enhancing the storage performance of the storage system. And, the base chip 200 can perform a first error detection and correction process on the first data data1, and the controller 300 can perform a second error detection and correction process on the first data data1 after the first error detection and correction process, which is beneficial to improving the error detection and correction accuracy rate of the data.

[0076] Both the base chip 200 and the controller 300 can perform error detection and correction processes on the first data data1, which is beneficial to enhancing the data error detection and correction ability of the storage system.

[0077] In some embodiments, the storage system may be a DRAM storage system, such as a DDR (double data rate) 4 DRAM storage system or a DDR5 DRAM storage system. In other embodiments, the storage system may also be an SRAM (Static Random-Access Memory) storage system, a NAND storage system, a NOR storage system, a FeRAM storage system, or a PcRAM storage system.

[0078] The controller 300 may include: a first encoding module 301 configured to perform a first error correction code encoding process on the first data data1 during the write phase to generate first encoded data ecc1; and a second error detection and correction module 302 configured to receive the third data data3 during the read phase and perform a second error detection and correction process on the third data data3.

[0079] The base chip 200 can provide a high-speed interface for data transmission in the storage system. In addition, the base chip 200 is also used to manage and control the storage chip 400. In some embodiments, the base chip 200 can be used to monitor and manage the temperature of the storage chip 400, and can also be used to perform Memory Build-In-Self Test (MBIST) and self-repair on the storage chip 400. In addition, the base chip 200 is also used to perform error detection and correction on the transmitted data.

[0080] Figure 8 This is the second structural schematic diagram of the storage system provided by the embodiments of the present disclosure. Refer to Figure 8 , in some embodiments, the base chip 200 may include: a second encoding module 210 configured to receive the first data data1 and perform a second error correction code encoding process during the write phase to generate second encoded data ecc2; and a first error detection and correction module 220 configured to receive the first data data1 and the second encoded data ecc2 and perform a first error detection and correction process during the read phase.

[0081] Regarding the working principle of the storage system, reference can be made to the corresponding descriptions in the foregoing embodiments, which will not be elaborated here. It can be understood that the controller 300 can perform a second error detection and correction process on the first data data1 after the first error detection and correction process.

[0082] The first error correction code encoding process and the second error detection and correction process are performed using a first compilation algorithm, and the second error correction code encoding process and the first error detection and correction process are performed using a second compilation algorithm. In some embodiments, the first compilation algorithm and the second compilation algorithm may be different. Using different compilation algorithms for error detection and correction of data is beneficial to further improve the accuracy rate of error detection and correction of data.

[0083] Specifically, the encoding algorithms used by the second encoding module 210 and the first encoding module 301 may be different, and the decoding algorithms used by the first error detection and correction module 220 and the second error detection and correction module 302 may be different.

[0084] It should be noted that in some other embodiments, the first compilation algorithm and the second compilation algorithm may also be the same.

[0085] Refer to Figure 8 , the storage chip 400 may include: a first storage module 410 for storing the first data data1; a second storage module 420 for storing the first encoded data ecc1; and a third storage module 430 for storing the second encoded data ecc3. For example, the first storage module 410 may store 256-bit first data data1, the second storage module 420 may store 16-bit first encoded data ecc1, and the third storage module 430 stores 16-bit second encoded data ecc2.

[0086] It can be understood that the number of data transmission channels between the controller 300 and the base chip 200 is M, and the number of data transmission channels between the base chip 200 and the storage chip 400 is N. Both M and N are positive integers greater than 1, and N is greater than M. This is because, in addition to transmitting the first data data1 and the first encoded data ecc1 between the base chip 200 and the storage chip 400, the second encoded data ecc2 also needs to be transmitted.

[0087] Figure 9 This is the third structural schematic diagram of the storage system provided by the embodiments of the present disclosure. Refer to Figure 9, in some embodiments, the storage system may further include: a first serial-to-parallel conversion module 230, configured to receive a first data data1 and a first encoded data ecc1 during a write phase, perform a first serial-to-parallel conversion process on the first data data1 and the first encoded data ecc1, and transmit the first data data1 after the first serial-to-parallel conversion process to the second encoding module 210, and transmit the first encoded data ecc1 after the first serial-to-parallel conversion process to the storage chip 400; a first parallel-to-serial conversion module 240, configured to receive a third data data3 during a read phase, perform a first parallel-to-serial conversion process on the third data data3, and transmit the third data data3 after the first parallel-to-serial conversion process to the controller 300.

[0088] Specifically, the first serial-to-parallel conversion module 230 is connected between the data transmission port of the controller 300 and the data transmission port of the second encoding module 210. In this way, the number of transmission channels between the controller 300 and the base chip 200 can be less than the sum of the bit numbers of the first data data1 and the first encoded data ecc1, thereby saving the number of transmission channels between the controller 300 and the base chip 200, saving the number of data transmission ports required to be set on the base chip 200 and the controller 300, facilitating reducing the complexity of the electrical connection structure between the controller 300 and the base chip 200, and saving the chip areas of the controller 300 and the base chip 200.

[0089] Reference Figure 9 , the base chip 200 may further include: a second parallel-to-serial conversion module 250, configured to receive a second data data2 from the second encoding module 210 during a write phase, perform a second parallel-to-serial conversion process, and transmit the second data data2 after the second parallel-to-serial conversion process to the storage chip 400; a second serial-to-parallel conversion module 260, configured to receive the second data data2 from the storage chip 400 during a read phase, perform a second serial-to-parallel conversion process, and transmit the second encoded data ecc2 and the first data data1 after the second serial-to-parallel conversion process to the first error detection and correction module 220, and output the first encoded data ecc1 after the second serial-to-parallel conversion process.

[0090] In this way, the number of transmission channels between the storage chip 400 and the base chip 200 can be less than the sum of the bit numbers of the first data data1, the first encoded data ecc1, and the second encoded data ecc2, thereby saving the number of transmission channels between the storage chip 400 and the base chip 200, which is beneficial to reducing the number of data transmission ports required to be set on the base chip 200 and the storage chip 400, beneficial to reducing the complexity of the electrical connection structure between the storage chip 400 and the base chip 200, and saving the chip areas of the storage chip 400 and the base chip 200.

[0091] For the detailed descriptions of the first serial-to-parallel conversion module 230, the first parallel-to-serial conversion module 240, the second parallel-to-serial conversion module 250, and the second serial-to-parallel conversion module 260, reference can be made to the corresponding descriptions in the foregoing embodiments, which will not be elaborated herein.

[0092] Reference Figure 10 , Figure 10 For Figure 8 a schematic structural diagram of the base, in some embodiments, the base chip 200 is further configured to generate a first error detection flag signal during the first error detection and correction process, and record the error conditions of the first data data1 and the second encoded data ecc2 during the transmission process based on the first error detection flag signal; the storage system further includes: a first register 501, and the first register 501 is configured to store the error conditions of the first data data1 and the second encoded data ecc2 during the transmission process.

[0093] Specifically, referring to Figure 10 , the base chip 200 may include: a first storage buffer module 201, and the first storage buffer module 201 is configured to store the error conditions of the first data data1 and the second encoded data ecc2 during the transmission process; a first command module 202, and the first command module 202 receives the first polling instruction PS1 and generates a first command signal CMD1 and a first clock signal CLK1; the first storage buffer module 201 is further configured to output a first characterization signal flag1 to the first register 501 based on the first command signal CMD1 and the first clock signal CLK1, and the first characterization signal flag1 characterizes the error conditions of the first data data1 and the second encoded data ecc2 during the transmission process.

[0094] In some embodiments, the controller 300 may further be configured to issue the first polling instruction PS1 to the first command module 202, that is, the controller 300 periodically issues an inquiry to control the first storage buffer module 201 to output the first characterization signal flag1 to the first register 501. It can be understood that in other embodiments, the first polling instruction may also be provided by an external circuit.

[0095] Reference Figure 10 In some embodiments, the controller 300 may further be configured to generate a second error detection flag signal during the second error detection and correction process, and record the error conditions of the first data data1 and the first encoded data ecc1 during transmission based on the second error detection flag signal. The storage system may further include: a second register 502, which is configured to store the error conditions of the first data data1 and the first encoded data ecc1 during transmission. It should be noted that the first data data1 in the first data data1 for which the controller 300 performs the second error detection and correction process refers to the first data data1 that has undergone the first error detection and correction process.

[0096] Reference Figure 10 In some embodiments, the controller 300 may further include: a second storage buffer module 271, which is configured to store the error conditions of the first data data1 and the first encoded data ecc1 during transmission; a second command module 281, which receives a second polling instruction PS2 and generates a second command signal CMD2 and a second clock signal CLK2. The second storage buffer module 271 is further configured to output a second characterization signal flag2 to the second register 502 based on the second command signal CMD2 and the second clock signal CLK2, and the second characterization signal flag2 characterizes the error conditions of the first data data1 and the first encoded data ecc1 during transmission.

[0097] It can be understood that the first register 501 and the second register 502 may be the same register.

[0098] For the storage system provided in the above embodiments, the base chip 200 can implement the error detection and correction function. Correspondingly, the storage chip 400 does not need to have the error detection and correction function, and the base chip 200 can share the error detection and correction function originally borne by the controller 300. Therefore, it is beneficial to save the space area of the controller 300 and the storage chip 400, improve the storage performance of the storage chip 400, and thus improve the storage performance of the storage system. At the same time, both the base chip 200 and the controller 300 can perform error detection and correction processing on the first data data1, and some of the first data data1 undergoes two error detection and correction processes. Therefore, the data error detection and correction accuracy rate of the storage system is high, and it is beneficial to improve the RAS performance of the storage system, that is, to improve the reliability, availability, and serviceability of the storage system.

[0099] In addition, the setting of the first error detection and correction module 220 and the second error detection and correction module 302 enables error detection and correction to be performed on different data transmission paths, improving the error detection and correction ability of the storage system and facilitating the location of the specific data transmission path where an error occurs.

[0100] Correspondingly, an embodiment of the present disclosure further provides a semiconductor structure, which may include the storage system provided in the above embodiment. The semiconductor structure provided in the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that for the same or corresponding parts as those in the foregoing embodiments, reference may be made to the detailed description of the foregoing embodiments, and details will not be repeated below.

[0101] Figure 11 It is a schematic cross-sectional structure diagram of the semiconductor structure provided in the embodiment of the present disclosure.

[0102] Referring to Figure 11 , the semiconductor structure includes: a carrier substrate 600; the storage system provided in the foregoing embodiment, and the controller 300 and the base chip 200 are both located on the surface of the carrier substrate 600, and the storage chip 400 is located on the surface of the base chip 200 away from the carrier substrate 600.

[0103] Among them, the semiconductor structure may include a plurality of storage chips 400 stacked in sequence. The semiconductor structure may be a memory such as a DARM device or an SRAM device.

[0104] In some embodiments, the carrier substrate 600 may be a PCB (Printed Circuit Board) circuit board. For a detailed description of the storage system, reference may be made to the foregoing embodiments, and details will not be repeated here.

[0105] The semiconductor structure may be a 2.5D (dimensions) device, that is, the semiconductor structure is a stacked structure, which is beneficial to saving the size in the horizontal direction, and using the base chip 200 in the semiconductor structure to implement the ECC error detection and correction function is beneficial to improving the performance of the semiconductor structure.

[0106] Those of ordinary skill in the art can understand that the above embodiments are specific embodiments for implementing the present disclosure, and in practical applications, various changes can be made in form and details without departing from the spirit and scope of the present disclosure. Any person skilled in the art can make their own changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of the present disclosure should be determined by the scope defined by the claims.

Claims

1. A basic chip is applied to a storage system. It is characterized in that it includes: The basic chip is configured to receive first data and first encoded data during a write phase. The first encoded data is obtained by performing first error correction code encoding processing on the first data, and perform second error correction code encoding processing on the first data to generate second encoded data. During the write phase, transmit second data to a storage chip. The second data includes the first data, the first encoded data, and the second encoded data; The basic chip is further configured to receive the second data from the storage chip during a read phase, perform first error detection and correction processing on the first data and the second encoded data, and transmit third data during the read phase. The third data includes the first encoded data and the first data after the first error detection and correction processing; The basic chip is further configured to generate a first error detection flag signal during the first error detection and correction processing, and record the error conditions of the first data and the second encoded data during transmission based on the first error detection flag signal.

2. The basic chip according to claim 1, It is characterized in that the basic chip includes: A second encoding module, which is configured to receive the first data and perform the second error correction code encoding processing during the write phase to generate the second encoded data; A first error detection and correction module, which is configured to receive the first data and the second encoded data and perform the first error detection and correction processing during the read phase.

3. The basic chip according to claim 2, It is characterized in that the basic chip further includes: A first serial-to-parallel conversion module, which is configured to receive the first data and the first encoded data during the write phase, perform first serial-to-parallel conversion processing on the first data and the first encoded data, and transmit the first data after the first serial-to-parallel conversion processing to the second encoding module, and transmit the first encoded data after the first serial-to-parallel conversion processing to the storage chip; A first parallel-to-serial conversion module, which is configured to receive the third data and perform first parallel-to-serial conversion processing on the third data during the read phase, and transmit the third data after the first parallel-to-serial conversion processing to a controller.

4. The basic chip according to claim 3, It is characterized in that the basic chip further includes: A second parallel-to-serial conversion module, which is configured to receive the second data and perform second parallel-to-serial conversion processing during the write phase, and transmit the second data after the second parallel-to-serial conversion processing to the storage chip; A second serial-to-parallel conversion module, which is configured to receive the second data from the storage chip during the reading phase, perform a second serial-to-parallel conversion process, and transmit the second encoded data and the first data after the second serial-to-parallel conversion process to the first error detection and correction module, and output the first encoded data after the second serial-to-parallel conversion process.

5. The base chip according to claim 1, wherein, the base chip further includes: A first storage buffer module, which is configured to store the error conditions of the first data and the second encoded data during transmission; A first command module, which receives a polling instruction and generates a first command signal and a first clock signal; The first storage buffer module is further configured to output a first characterization signal based on the first command signal and the first clock signal, and the first characterization signal characterizes the error conditions of the first data and the second encoded data during transmission.

6. The base chip according to claim 5, wherein, the first storage buffer module includes a first-in, first-out register.

7. The base chip according to claim 1, wherein, the first error correction code encoding process and the second error correction code encoding process are performed using different encoding algorithms.

8. The base chip according to claim 7, wherein, the number of bits of the first encoded data is different from the number of bits of the second encoded data.

9. A storage system, wherein, it includes a controller, a base chip, and a storage chip, and further includes: The controller is configured to perform a first error correction code encoding process on the first data during the writing phase to generate first encoded data, and transmit the first data and the first encoded data to the base chip; The base chip is configured to receive the first data and the first encoded data during the writing phase, perform a second error correction code encoding process on the first data to generate second encoded data, transmit second data to the storage chip during the writing phase, the second data includes the first data, the first encoded data, and the second encoded data, receive the second data from the storage chip during the reading phase, perform a first error detection and correction process on the first data and the second encoded data, and transmit third data to the controller during the reading phase, the third data includes the first encoded data and the first data after the first error detection and correction process; The storage chip is configured to receive the second data and store the second data during the writing phase, and transmit the second data to the base chip during the reading phase; The controller is further configured to receive the third data from the base chip during the reading phase, perform a second error detection and correction process on the third data, and obtain the first data after the second error detection and correction process; The base chip is further configured to generate a first error detection flag signal during the first error detection and correction process, and record the error conditions of the first data and the second encoded data during transmission based on the first error detection flag signal; the storage system further includes: A first register configured to store the error conditions of the first data and the second encoded data during transmission.

10. The storage system according to claim 9, wherein, the controller includes: A first encoding module configured to perform the first error correction code encoding process on the first data during the write phase to generate the first encoded data; A second error detection and correction module configured to receive the third data during the read phase and perform the second error detection and correction process on the third data.

11. The storage system according to claim 9, wherein, the base chip includes: A second encoding module configured to receive the first data and perform the second error correction code encoding process during the write phase to generate the second encoded data; A first error detection and correction module configured to receive the first data and the second encoded data during the read phase and perform the first error detection and correction process.

12. The storage system according to claim 9, wherein, the number of data transmission channels between the controller and the base chip is M, and the number of data transmission channels between the base chip and the storage chip is N; where M and N are both positive integers greater than 1, and N is greater than M.

13. The storage system according to claim 9, wherein, the storage chip includes: A first storage module for storing the first data; A second storage module for storing the first encoded data; A third storage module for storing the second encoded data.

14. The storage system according to claim 9, wherein, the first error correction code encoding process and the second error detection and correction process are performed using a first compilation algorithm, the second error correction code encoding process and the first error detection and correction process are performed using a second compilation algorithm, and the first compilation algorithm is different from the second compilation algorithm.

15. The storage system according to claim 9, wherein, the base chip includes: A first storage buffer module configured to store the error conditions of the first data and the second encoded data during transmission; A first command module that receives a first polling instruction and generates a first command signal and a first clock signal; The first storage buffer module is further configured to output a first characterization signal to the first register based on the first command signal and the first clock signal, and the first characterization signal characterizes the error conditions of the first data and the second encoded data during transmission.

16. The storage system according to claim 9, wherein, the controller is further configured to generate a second error detection flag signal during the second error detection and correction process, and record the error conditions of the first data and the first encoded data during transmission based on the second error detection flag signal; the storage system further includes: a second register configured to store the error conditions of the first data and the first encoded data during transmission.

17. The storage system according to claim 16, wherein, the controller includes: a second storage cache module configured to store the error conditions of the first data and the first encoded data during transmission; a second command module that receives a second polling instruction and generates a second command signal and a second clock signal; the second storage cache module is further configured to output a second characterization signal to the second register based on the second command signal and the second clock signal, and the second characterization signal characterizes the error conditions of the first data and the first encoded data during transmission.

18. A semiconductor structure, wherein, it includes: a carrier substrate; the storage system according to any one of claims 9-17, and the controller and the base chip are both located on the surface of the carrier substrate, and the storage chip is located on the surface of the base chip away from the carrier substrate.

Images