Method of forming a semiconductor structure

Abstract

The application provides a semiconductor structure forming method, which comprises the following steps: providing a substrate, sequentially forming a metal interconnection layer and a first dielectric layer on the substrate, and forming a plurality of first through holes in the first dielectric layer; forming a plurality of first interconnection structures, the first interconnection structures are arranged at intervals and have a pitch of 2N, each first interconnection structure covers at least one first through hole to be electrically connected with the metal interconnection layer, and N is a positive number; forming a plurality of side walls and a plurality of second through holes; forming a second interconnection structure between two adjacent side walls, the second interconnection structure is electrically connected with the metal interconnection layer, and the first interconnection structure and the second interconnection structure form an interconnection structure with a pitch of N. The first interconnection structure with a pitch of 2N is formed first, then the second interconnection structure is formed in a self-aligned manner between the first interconnection structure, thereby forming the interconnection structure with a pitch of N, the problem that the interconnection structure is difficult to form is solved, the process difficulty is reduced, and the manufacturing yield is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a method for forming a semiconductor structure. Background Art

[0002] With the rapid growth of the integrated circuit (IC) industry, semiconductor technology, driven by Moore's Law, continues to advance toward smaller process nodes. This has led to smaller ICs, higher circuit density, and greater circuit complexity. During the development of ICs, functional density (i.e., the number of interconnects per chip) has generally increased while geometric size (i.e., the minimum component size that can be produced using a specific process step) has decreased, which in turn increases the difficulty and complexity of IC manufacturing.

[0003] Among them, the formation process of the interconnection structure of the back-end process is more difficult. In order to ensure device performance and smaller process nodes, it is necessary to select materials with lower resistivity. Metal is usually used as the material of the interconnection structure, and the etching difficulty of metal is greater than that of other materials. For example, when the pitch of the interconnection structure (the sum of the minimum spacing and the minimum line width between adjacent interconnection structures) is above 32nm, an interconnection structure with a line width / line spacing of more than 15nm can be directly formed. When the pitch of the interconnection structure is reduced to below 32nm (for example, 18nm), that is, when the line width / line spacing of the interconnection structure is reduced by less than 10nm, only a small number of metals can meet the resistivity requirements, such as Ru and Mo, but these metals are difficult to directly etch to form a low-pitch interconnection structure. Summary of the Invention

[0004] An object of the present invention is to provide a method for forming a semiconductor structure to facilitate the formation of an interconnection structure.

[0005] To solve the above technical problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, sequentially forming a metal interconnection layer and a first dielectric layer on the substrate, wherein a plurality of first through-holes exposing the metal interconnection layer are formed in the first dielectric layer; forming a plurality of first interconnect structures on the first dielectric layer, wherein the first interconnect structures are spaced apart and have a pitch of 2N, each of the first interconnect structures covering the first dielectric layer and filling at least one of the first through-holes to electrically connect to the metal interconnection layer, where N is a positive number; forming sidewalls on sidewalls of the first interconnect structures, and etching the first dielectric layer between two adjacent sidewalls to form a plurality of second through-holes exposing the metal interconnection layer; and forming second interconnect structures between two adjacent sidewalls, wherein each of the second interconnect structures covers the first dielectric layer and fills at least one of the second through-holes to electrically connect to the metal interconnection layer, wherein the first interconnect structures and the second interconnect structures constitute an interconnect structure with a pitch of N.

[0006] Optionally, the step of forming a plurality of first interconnect structures on the first dielectric layer includes: sequentially forming a first conductive layer, an adhesion layer, and a second dielectric layer on the first dielectric layer; patterning the second dielectric layer to form a mask plate, wherein the pitch of the mask pattern of the mask plate is 2N; using the mask plate as a mask, etching the adhesion layer and the first conductive layer to expose the first dielectric layer, and the remaining first conductive layer, adhesion layer, and second dielectric layer constitute the first interconnect structure.

[0007] Optionally, the step of forming a sidewall on the sidewall of the first interconnect structure includes: conformally forming a third dielectric layer, wherein the third dielectric layer covers the surface of the first dielectric layer and the outer wall of the first interconnect structure; and etching to remove the third dielectric layer on the surface of the first dielectric layer and the top wall of the first interconnect structure, wherein the remaining third dielectric layer constitutes the sidewall.

[0008] Optionally, when forming the first interconnect structure or after forming the first interconnect structure, a portion of the first interconnect structure is etched to form a first isolation gap exposing the first dielectric layer; when forming the third dielectric layer, the third dielectric layer also fills the first isolation gap to form a first isolation structure for isolating the first interconnect structure.

[0009] Optionally, the second interconnect structure is formed by a self-alignment process.

[0010] Optionally, the step of forming the second interconnect structure includes: filling a second conductive layer in the area between the corresponding two sidewalls; etching the second conductive layer until it is flush with the top surface of the first conductive layer; forming a second dielectric layer on the second conductive layer, wherein the top surface of the second dielectric layer is flush with the top surface of the first interconnect structure, and the second conductive layer and the second dielectric layer constitute the second interconnect structure.

[0011] Optionally, before forming the second dielectric layer, a portion of the second conductive layer is etched to form a second isolation gap exposing the first dielectric layer; the second dielectric layer fills the second isolation gap to form a second isolation structure for isolating the second interconnect structure.

[0012] Optionally, the first dielectric layer, the second dielectric layer, and the third dielectric layer are made of different materials.

[0013] Optionally, the materials of the first conductive layer and the second conductive layer include molybdenum and / or ruthenium.

[0014] Optionally, it is characterized in that the material of the side wall is a medium with a low dielectric constant.

[0015] In summary, the method for forming a semiconductor structure provided by the present invention has the following beneficial effects:

[0016] 1) By first forming a first interconnect structure with a pitch of 2N, forming sidewalls on the sidewalls of the first interconnect structure, etching a second through hole between the sidewalls using the first interconnect structure and the sidewalls as a mask, and forming a second interconnect structure between the sidewalls, the first interconnect structure and the second interconnect structure together constitute an interconnect structure with a pitch of N, thereby solving the problem of difficulty in forming interconnect structures (e.g., interconnect structures below 32nm);

[0017] 2) In the process of forming the first interconnect structure, the first interconnect structure has a double pitch (2N), which expands the process window during photolithography and etching, reduces process difficulty, reduces the risk of short circuits, and improves manufacturing yield;

[0018] 3) The second interconnect structure is formed by a self-alignment process, which reduces the process difficulty. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Those skilled in the art should understand that the drawings are provided for a better understanding of the present invention, but do not constitute any limitation on the scope of the present invention.

[0020] Figures 1 to 13 A schematic structural diagram corresponding to the corresponding steps of the method for forming a semiconductor structure provided by the present invention;

[0021] Figure 14 This is a flow chart of a method for forming a semiconductor structure provided in an embodiment of the present application.

[0022] In the attached figure:

[0023] 10-substrate;

[0024] 21-first dielectric layer; 211-first through hole; 212-second through hole;

[0025] 22-adhesion layer; 23-second dielectric layer; 24-third dielectric layer;

[0026] 31-first conductive layer; 32-second conductive layer; 33-first interconnect structure; 34-second interconnect structure;

[0027] 41-first partition gap; 411-first partition structure; 42-second partition gap; 421-second partition structure. DETAILED DESCRIPTION

[0028] To make the objects, advantages, and features of the present invention more clearly apparent, the present invention is further described below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale. They are only used to conveniently and clearly assist in illustrating the purposes of the embodiments of the present invention. In addition, the structures shown in the drawings are often part of the actual structure. In particular, different drawings may need to illustrate different focuses and sometimes use different scales.

[0029] As used in the present invention, the singular forms "a", "an", and "the" include plural objects, the term "or" is generally used to include the meaning of "and / or", the term "several" is generally used to include the meaning of "at least one", and the term "at least two" is generally used to include the meaning of "two or more". In addition, the terms "first", "second", and "third" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features specified as "first", "second", and "third" may explicitly or implicitly include one or at least two of the features, unless the content clearly indicates otherwise.

[0030] The present invention provides a method for forming a semiconductor structure, so as to facilitate the formation of an interconnection structure.

[0031] Figure 14 1 is a flow chart of a method for forming a semiconductor structure provided by an embodiment of the present application. This flow chart only shows the relevant part of the method for forming a semiconductor structure. It should be understood that in the method of forming a semiconductor structure by Figure 14 Additional operations may be provided before, during, and after the illustrated processes.

[0032] like Figure 14 As shown, the method for forming a semiconductor structure provided in this embodiment includes the following steps:

[0033] S01: providing a substrate, on which a metal interconnection layer and a first dielectric layer are sequentially formed, wherein a plurality of first through holes exposing the metal interconnection layer are formed in the first dielectric layer;

[0034] S02: forming a plurality of first interconnect structures on the first dielectric layer, wherein the first interconnect structures are arranged at intervals with a pitch of 2N, each of the first interconnect structures covers the first dielectric layer and fills at least one first through hole to be electrically connected to the metal interconnect layer, where N is a positive number;

[0035] S03: forming sidewalls on the sidewalls of the first interconnect structure, and etching the first dielectric layer between two adjacent sidewalls to form a plurality of second through holes exposing the metal interconnect layer;

[0036] S04: forming a second interconnect structure between two adjacent sidewalls, wherein each second interconnect structure covers the first dielectric layer and fills at least one second through hole to be electrically connected to the metal interconnect layer, wherein the first interconnect structure and the second interconnect structure constitute an interconnect structure with a pitch of N.

[0037] Figures 1 to 13 The structural diagram corresponding to the corresponding steps of the method for forming a semiconductor structure provided in this embodiment is shown below. Figures 1 to 13 The method for forming the semiconductor structure is described in detail.

[0038] First, please refer to Figure 1 , step S01 is performed to provide a substrate 10 , on which a metal interconnection layer (not shown) is formed, and a first dielectric layer 21 is formed on the substrate 10 , the first dielectric layer 21 covering the surface of the substrate 10 .

[0039] In this embodiment, the substrate 10 is used to provide a process platform for subsequent processes, and the subsequent processes may be to form a first metal interconnection line or other layers of metal interconnection lines (Mth metal interconnection line, M is a positive integer greater than 1).

[0040] The substrate 10 may be any suitable base material known to those skilled in the art, for example, at least one of the following materials: silicon, silicon-on-insulator (SOI), stacked silicon-on-insulator (SSOI), stacked silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), and germanium-on-insulator (GeOI). In this embodiment, the substrate 10 is described as a silicon substrate.

[0041] In other embodiments, when the formed semiconductor device is a FINFET (Fin Field Effect Transistor), the substrate 10 includes a protruding fin portion.

[0042] The substrate 10 may further include other structures, such as a gate structure, a local interconnect structure, a contact plug (CT), an active region, a shallow trench isolation (STI), and an interlayer dielectric layer, etc. The gate structure may be a metal gate structure or a polysilicon gate structure.

[0043] The first dielectric layer 21 is used to electrically isolate the substrate 10 from the interconnect structure to be formed thereon. When used to form a first metal interconnect, the first dielectric layer 21 may be a first metal interlayer dielectric layer (PMD). When used to form an Mth metal interconnect, the first dielectric layer 21 may be an Mth metal interlayer dielectric layer. In this embodiment, the provided method for forming a semiconductor structure can form a lower-level interconnect structure, such as the first, second, or third metal interconnect layer. In practice, other dielectric layers, such as a barrier layer, an adhesion layer, or a low-k dielectric layer, may also be present on the substrate 10 below the first dielectric layer 21.

[0044] In this embodiment, the interconnect structure to be formed is arranged orthogonally to the metal interconnect layer in substrate 10 to reduce their facing area, thereby reducing RC delay. Preferably, the first dielectric layer is made of carbon-doped silicon nitride (silicon carbonitride) to provide better isolation and lower dielectric constant.

[0045] Please refer to Figure 2 , a plurality of first through holes 211 exposing the substrate 10 are formed on the first dielectric layer 21 .

[0046] The formed first vias 211 are used to expose a portion of the metal interconnect layer on the substrate 10 to be electrically connected (this region is not shown in the schematic diagram). The first vias 211 can be used to electrically connect the first interconnect structure to different regions of the metal interconnect layer on the substrate 10 when forming the first interconnect structure. Thus, the size and arrangement of the first vias 211 can match the first interconnect structure. It should be understood that in practice, multiple first vias 211 are used to form the first interconnect structure. For ease of illustration, only one is shown in this embodiment for illustrative purposes.

[0047] Next, please refer to Figure 3 , step S02 is performed to sequentially form a first conductive layer 31, an adhesion layer 22, and a second dielectric layer 23 on the surface of the first dielectric layer 21. The first conductive layer 31 fills the first through hole 211 and covers the surface of the first dielectric layer 21. The adhesion layer 22 covers the first conductive layer 31. The second dielectric layer 23 covers the adhesion layer 22.

[0048] The first conductive layer 31 can be any suitable low-resistivity conductive material, such as molybdenum (Mo) and / or ruthenium (Ru). The adhesion layer 22 is used to enhance the adhesion between the second dielectric layer 23 and the first conductive layer 31 and prevent the second dielectric layer 23 from diffusing into the first conductive layer 31. For example, it can be titanium nitride or tantalum nitride. The second dielectric layer 23 can also serve as a hard mask for forming the subsequent first and second interconnect structures. For example, it can be silicon nitride.

[0049] See also Figure 4The second dielectric layer 23 is patterned to form a mask, wherein the pitch of the mask pattern is 2N, where N is the pitch of the interconnect structure to be formed. A mask pattern with a pitch of 2N here means that the pitch of the mask openings used to form the first interconnect structure is 2N, that is, the width of the openings plus the spacing between adjacent openings is 2N. For example, if the pitch N of the interconnect structure to be formed is 18nm, then the second dielectric layer 23 is patterned to form a mask with a pitch of 36nm. The mask pattern has a width of, for example, 9nm for forming the first interconnect structure, and an opening with a width of 27nm for subsequently forming the second interconnect structure located between the first interconnect structures.

[0050] Please continue reading Figure 4 Using the patterned second dielectric layer 23 as a mask, the adhesion layer 22 and the first conductive layer 31 are etched to expose the first dielectric layer 21. The remaining first conductive layer 31, adhesion layer 22, and second dielectric layer 23 form first interconnect structures 33. The first interconnect structures 33 are arranged at intervals with a pitch of 2N. Each first interconnect structure 33 covers the first dielectric layer 21 and fills at least one first via 211 to electrically connect to the metal interconnect layer.

[0051] It is worth mentioning that compared with forming an interconnect structure with a pitch of N, especially when N is a pitch less than 32nm, the process window for lithography and etching is twice as large when forming the first interconnect structure 33 with a pitch of 2N, which can significantly reduce the process difficulty of the corresponding process, reduce the risk of short circuit, and improve the manufacturing yield.

[0052] Please refer to Figure 5a and Figure 5b After forming the first interconnect structure 33, a first isolation gap 41 may be formed in the first interconnect structure 33 to isolate the first interconnect structure 33. The specific process may include, for example, re-patterning the second dielectric layer 23 to form an opening, and then sequentially etching the adhesion layer 22 and the first conductive layer 31 to expose the first dielectric layer 21 to form the first isolation gap 41, which completely cuts off the first interconnect structure 33. As a preferred embodiment, the first isolation gap 41 may be formed by etching simultaneously with the first interconnect structure 33. It should be understood that to facilitate the simultaneous filling of the first isolation gap 41 during the subsequent formation of the sidewall spacer, the opening width of the first isolation gap 41 along the extension direction of the first interconnect structure 33 should be smaller than the spacing between the first interconnect structures 33, preferably less than 0.5N.

[0053] Please refer to Figures 6a to 6b , executing step S03, conformally forming a third dielectric layer 24 to cover the entire surface of the substrate 10, the third dielectric layer 24 not only covers the outer wall (including the side wall and the top wall) of the first interconnect structure and the first dielectric layer 21, but also fills the first isolation gap 41.

[0054] Furthermore, to improve the uniformity and step coverage of the third dielectric layer 24, ALD (Atomic Layer Deposition) is preferably used to form the third dielectric layer 24. Since the opening width of the first isolation gap 41 is relatively small (e.g., less than 0.5N), the thickness of the third dielectric layer 24 is appropriately controlled. For example, the thickness of the third dielectric layer 24 located on the sidewalls of the first interconnect structure 33 is approximately 0.3N. This allows the third dielectric layer 24 to completely fill the first isolation gap 41, while also ensuring that the spacing between the third dielectric layers 24 located on the sidewalls of adjacent first interconnect structures 33 is the width of the second interconnect structure. It should be understood that the second interconnect structure will be formed between the third dielectric layers 24 on the sidewalls of adjacent first interconnect structures 33 in subsequent processing steps. To reduce resistance fluctuations of the interconnect structures, the first and second interconnect structures 33 can have the same width.

[0055] Please refer to Figures 7a and 7b , etching the third dielectric layer 24. Since the third dielectric layer 24 located on the top wall of the first interconnect structure 33 and on the first dielectric layer 21 has a faster etching rate, only the third dielectric layer 24 located on the sidewall of the first interconnect structure 33 and within the first isolation gap 41 can be retained. The third dielectric layer 24 located on the sidewall of the first interconnect structure 33 constitutes a sidewall, while the third dielectric layer 24 located within the first isolation gap 41 constitutes a first isolation structure 411. The first isolation structure 411 is used to completely isolate the first interconnect structure 33. It should be noted that the sidewall will be used to isolate the first interconnect structure 33 from the second interconnect structure. Since the two have a large facing area, in order to reduce the capacitance value and reduce RC delay, the material of the sidewall (third dielectric layer) can be a low-k dielectric.

[0056] Please refer to Figure 8 Using the first interconnect structure 33 as a mask, the first dielectric layer 21 is etched to form a second through-hole 212 exposing the substrate 10. The second through-hole 212 is used to expose the metal interconnect layer on the substrate 10. Because the first dielectric layer 21, the third dielectric layer 24, and the second dielectric layer 23 are made of different materials, and in particular, the second dielectric layer 23 also serves as a hard mask, a self-alignment effect can be achieved when the first interconnect structure 33 is used as a mask and an appropriate etching process is selected for etching.

[0057] Please continue to refer to Figure 8The second through-hole 212 is located between adjacent first interconnect structures 33, and is separated from the first through-hole 211 by only the first dielectric layer 21 and the third dielectric layer 24. In practice, other masks are required when forming the second through-hole 212, while only the portion of the first dielectric layer 21 located between adjacent first interconnect structures 33 needs to be etched. In addition, to reduce the risk of short circuits, the through-holes (first through-hole 211 and second through-hole 212) of two adjacent interconnect structures (e.g., adjacent first and second interconnect structures) are staggered. In this embodiment, the first through-hole 211 and the second through-hole 212 are shown side by side for ease of illustration only.

[0058] Please refer to Figure 9 , step S04 is executed to form a second conductive layer 32 to fill the area between the second through hole 212 and the adjacent sidewall (third dielectric layer 24).

[0059] The second conductive layer 32 may be made of metal molybdenum and / or ruthenium. To reduce the resistance fluctuation of the interconnection structure, preferably, the first conductive layer 31 and the second conductive layer 32 are both made of one of metal molybdenum or ruthenium.

[0060] Please refer to Figure 10 , the second conductive layer 32 is etched until it is flush with the top surface of the first conductive layer 31. Specifically, the second conductive layer 32 can be CMPed or etched until it is flush with the top surface of the third dielectric layer 24 (sidewall), and then the second conductive layer 32 is etched until it is flush with the top surface of the first conductive layer 31.

[0061] Please refer to Figure 11a and 11b , a portion of the second conductive layer 32 is continuously etched to form a second isolation gap 42 exposing the first dielectric layer 21 for isolating the second conductive layer 32 .

[0062] Please refer to Figure 12 , forming a second dielectric layer 23 , filling the second isolation gap 42 and covering the second conductive layer 32 , and extending to cover the third dielectric layer 24 .

[0063] Please refer to Figure 13 The second dielectric layer 23 is then CMPed or etched until it is flush with the top surface of the first interconnect structure 33. The second conductive layer 32 and the second dielectric layer 23 thereon form a second interconnect structure 34. Simultaneously, the second dielectric layer 23 fills the second isolation gap 42 to form a second isolation structure 421 for isolating the second interconnect structure 34.

[0064] Thus, an interconnect structure consisting of the first interconnect structures 33 and the second interconnect structures 34 arranged alternately is formed, ie, a semiconductor structure.

[0065] During the above formation process, the second interconnect structure 34 is directly inlaid using the space formed by the previously formed second through hole 212 and the third dielectric layer 24 located on both side walls of the first interconnect structure 33 using a self-alignment process. The process difficulty is low, the manufacturing yield is high, and the short circuit risk is extremely low.

[0066] In this embodiment, to form an interconnect structure with a pitch of N, first interconnect structures 33 with a pitch of 2N are first formed by etching. Then, second interconnect structures 34 are formed between the first interconnect structures 33 using a self-aligned process (Damascene method). This results in a semiconductor (interconnect) structure with a pitch of N, formed by alternating first and second interconnect structures 33 and 34. During the formation of the entire semiconductor structure, the process limits of the existing interconnect process can be further improved, while also enhancing the manufacturing yield.

[0067] In summary, this embodiment provides a method for forming a semiconductor structure:

[0068] By first forming a first interconnect structure with a pitch of 2N, forming sidewalls on the sidewalls of the first interconnect structure, etching a second through hole between the sidewalls using the first interconnect structure and the sidewalls as a mask, and forming a second interconnect structure between the sidewalls, the first interconnect structure and the second interconnect structure together constitute an interconnect structure with a pitch of N, thereby solving the problem of difficulty in forming interconnect structures (e.g., interconnect structures below 32nm);

[0069] Furthermore, in the process of forming the first interconnect structure, the first interconnect structure has a double pitch (2N), which expands the process window during photolithography and etching, reduces process difficulty, reduces the risk of short circuits, and improves manufacturing yield;

[0070] Furthermore, the second interconnect structure is formed using a self-alignment process, which reduces the difficulty of the process.

[0071] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, on which a metal interconnection layer and a first dielectric layer are sequentially formed, wherein the first dielectric layer is formed with a plurality of first through holes exposing the metal interconnection layer; forming a plurality of first interconnect structures on the first dielectric layer, wherein the first interconnect structures are arranged at intervals with a pitch of 2N, each of the first interconnect structures covering the first dielectric layer and filling at least one first through hole to be electrically connected to the metal interconnect layer, where N is a positive number; forming sidewalls on the sidewalls of the first interconnect structure, and etching the first dielectric layer between two adjacent sidewalls to form a plurality of second through holes exposing the metal interconnect layer; and A second interconnect structure is formed between two adjacent sidewalls, each of the second interconnect structures covers the first dielectric layer and fills at least one second through hole to be electrically connected to the metal interconnect layer, wherein the first interconnect structure and the second interconnect structure constitute an interconnect structure with a pitch of N.

2. The method for forming a semiconductor structure according to claim 1, wherein: The step of forming a plurality of first interconnect structures on the first dielectric layer includes: forming a first conductive layer, an adhesion layer and a second dielectric layer in sequence on the first dielectric layer; Patterning the second dielectric layer to form a mask plate, wherein the pitch of the mask pattern of the mask plate is 2N; Using the mask plate as a mask, the adhesion layer and the first conductive layer are etched to expose the first dielectric layer. The remaining first conductive layer, adhesion layer and second dielectric layer constitute the first interconnect structure.

3. The method for forming a semiconductor structure according to claim 2, wherein: The step of forming a spacer on the sidewall of the first interconnect structure comprises: Conformally forming a third dielectric layer, wherein the third dielectric layer covers a surface of the first dielectric layer and an outer wall of the first interconnect structure; The surface of the first dielectric layer and the third dielectric layer on the top wall of the first interconnect structure are removed by etching, and the remaining third dielectric layer constitutes the sidewall.

4. The method for forming a semiconductor structure according to claim 3, wherein: When or after forming the first interconnect structure, etching a portion of the first interconnect structure to form a first isolation gap exposing the first dielectric layer; When forming the third dielectric layer, the third dielectric layer also fills the first isolation gap to form a first isolation structure for isolating the first interconnect structure.

5. The method for forming a semiconductor structure according to claim 3, wherein: The second interconnect structure is formed by a self-aligned process.

6. The method for forming a semiconductor structure according to claim 5, wherein: The step of forming the second interconnect structure includes: Filling the second conductive layer in the area between the two corresponding sidewalls; Etching the second conductive layer until it is flush with the top surface of the first conductive layer; A second dielectric layer is formed on the second conductive layer, wherein the top surface of the second dielectric layer is flush with the top surface of the first interconnect structure, and the second conductive layer and the second dielectric layer constitute the second interconnect structure.

7. The method for forming a semiconductor structure according to claim 6, wherein: Before forming the second dielectric layer, etching a portion of the second conductive layer to form a second isolation gap exposing the first dielectric layer; The second dielectric layer fills the second isolation gap to form a second isolation structure for isolating the second interconnect structure.

8. The method for forming a semiconductor structure according to claim 7, wherein: The first dielectric layer, the second dielectric layer, and the third dielectric layer are made of different materials.

9. The method for forming a semiconductor structure according to claim 7, wherein: Materials of the first conductive layer and the second conductive layer include molybdenum and / or ruthenium.

10. The method for forming a semiconductor structure according to any one of claims 1 to 9, wherein: The sidewall is made of a medium with a low dielectric constant.

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