A method for manufacturing a semiconductor structure and a semiconductor structure

Abstract

The embodiment of the present disclosure provides a preparation method of a semiconductor structure and the semiconductor structure, wherein the preparation method comprises the following steps: providing a substrate, forming a plurality of functional structures on the substrate, and defining an area between the plurality of functional structures as a to-be-filled area; introducing a first gas into a reaction chamber to form a first sub-layer, the first sub-layer covering at least a surface of the functional structure; performing a first processing process to prevent migration of elements contained in the first sub-layer; introducing a second gas into the reaction chamber to form a second sub-layer on the surface of the first sub-layer; and performing a second processing process to prevent migration of elements contained in the second sub-layer; wherein the first sub-layer and the second sub-layer partially fill the to-be-filled area on the side surface of the functional structure.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of semiconductor manufacturing, and in particular, to a method for manufacturing a semiconductor structure and the semiconductor structure. BACKGROUND

[0002] In the process of manufacturing a semiconductor structure, in order to obtain a desired function or structure, it is often necessary to perform an operation of filling various materials into a trench or a hole, and the types of these materials often involve conductive materials or insulating materials, etc.

[0003] However, as the integration of semiconductor structures continues to improve, the size of semiconductor structures is gradually miniaturized, which means that in some scenarios, the aspect ratio of the trench or hole structure becomes larger and larger, which increases the difficulty of filling the trench or hole, and easily reduces the performance of the finally obtained semiconductor structure. SUMMARY

[0004] Embodiments of the present disclosure provide a method for manufacturing a semiconductor structure, comprising:

[0005] providing a substrate, forming a plurality of functional structures on the substrate, and defining an area between the plurality of functional structures as a to-be-filled area;

[0006] introducing a first gas into a reaction chamber to form a first sub-layer, the first sub-layer covering at least the surface of the functional structure;

[0007] performing a first processing process to prevent the elements contained in the first sub-layer from migrating;

[0008] introducing a second gas into the reaction chamber to form a second sub-layer on the surface of the first sub-layer;

[0009] performing a second processing process to prevent the elements contained in the second sub-layer from migrating;

[0010] wherein the first sub-layer and the second sub-layer partially fill the to-be-filled area on the side surface of the functional structure.

[0011] In some embodiments, after forming the plurality of functional structures, before introducing the first gas into the reaction chamber, the method further comprises:

[0012] placing the substrate containing the plurality of functional structures into the reaction chamber under a nitrogen-containing atmosphere;

[0013] heating the reaction chamber to a preset temperature in an atmosphere containing nitrogen and silane to improve the cleanliness of the substrate containing the plurality of functional structures;

[0014] removing the waste gas generated in the above operation process.

[0015] In some embodiments, the first gas comprises a germanium-containing gas, and forming the first sub-layer comprises:

[0016] introducing a germanium-containing gas into the reaction chamber to form a first sub-layer, the first sub-layer covering at least a surface of the functional structure, and the first sub-layer comprising at least elemental germanium.

[0017] In some embodiments, the first gas comprises a germanium-containing gas and a boron-containing gas, and forming the first sub-layer comprises:

[0018] introducing a germanium-containing gas and a boron-containing gas into the reaction chamber to form a first sub-layer, the first sub-layer covering at least a surface of the functional structure, and the first sub-layer comprising at least elemental germanium.

[0019] In some embodiments, performing the first processing procedure comprises:

[0020] introducing a third hydrogen-containing gas into the reaction chamber, the third hydrogen-containing gas preventing migration of elements included in the first sub-layer.

[0021] In some embodiments, performing the first processing procedure comprises:

[0022] performing a first vacuuming process on the reaction chamber;

[0023] introducing a fourth hydrogen-containing gas into the reaction chamber, the fourth hydrogen-containing gas preventing migration of elements included in the first sub-layer;

[0024] performing a second vacuuming process on the reaction chamber.

[0025] In some embodiments, the second gas comprises a germanium-containing gas and a silicon-containing gas, and forming the second sub-layer comprises:

[0026] introducing a germanium-containing gas and a silicon-containing gas into the reaction chamber to form a second sub-layer on a surface of the first sub-layer.

[0027] In some embodiments, the second gas comprises a silicon-containing gas and a boron-containing gas, and forming the second sub-layer comprises:

[0028] introducing a silicon-containing gas and a boron-containing gas into the reaction chamber to form a second sub-layer on a surface of the first sub-layer.

[0029] In some embodiments, performing the second processing procedure comprises:

[0030] introducing a fifth hydrogen-containing gas into the reaction chamber, the fifth hydrogen-containing gas preventing migration of elements included in the second sub-layer.

[0031] In some embodiments, after performing the second processing procedure, the preparation method further comprises:

[0032] The first gas is introduced into the reaction chamber again to form a first sub-layer on the surface of a second sub-layer;

[0033] The first processing procedure is performed again to prevent the elements contained in the first sub-layer from migrating;

[0034] The second gas is introduced into the reaction chamber again to form a second sub-layer on the surface of the first sub-layer;

[0035] The second processing procedure is performed again to prevent the elements contained in the second sub-layer from migrating;

[0036] The above operations are repeated multiple times until the plurality of first sub-layers and the plurality of second sub-layers fill the to-be-filled region on the part of the side surface of the functional structure.

[0037] In some embodiments, before the first gas is introduced into the reaction chamber again, the preparation method comprises:

[0038] A sixth gas containing nitrogen is introduced into the reaction chamber, and the sixth gas is used to exhaust the reaction gas.

[0039] The disclosure embodiments also provide a semiconductor structure, comprising:

[0040] a substrate:

[0041] a plurality of functional structures, the functional structures being located on the substrate, and a region between the plurality of functional structures being defined as a to-be-filled region;

[0042] at least one first sub-layer and at least one second sub-layer, the first sub-layer covering at least the surface of the functional structure, and the second sub-layer covering the surface of the first sub-layer;

[0043] wherein the first sub-layer and the second sub-layer fill the to-be-filled region on the part of the side surface of the functional structure.

[0044] The method for manufacturing a semiconductor structure provided by the embodiments of the present disclosure comprises the following steps: providing a substrate, forming a plurality of functional structures on the substrate, and defining an area between the plurality of functional structures as a to-be-filled area; introducing a first gas into a reaction chamber to form a first sub-layer, the first sub-layer covering at least a surface of the functional structure; performing a first processing process to prevent the elements contained in the first sub-layer from migrating; introducing a second gas into the reaction chamber to form a second sub-layer on the surface of the first sub-layer; performing a second processing process to prevent the elements contained in the second sub-layer from migrating; and wherein the first sub-layer and the second sub-layer fill part of the to-be-filled area on the side surface of the functional structure.

[0045] During the filling operation of the embodiments of the present disclosure, the steps of the first processing process and the second processing process are added after the formation of the first sub-layer and the second sub-layer, respectively, so that the materials contained in the first sub-layer and the second sub-layer can remain in the initial deposition distribution state, and the occurrence of voids caused by clustering due to element migration can be avoided, thereby effectively improving the filling effect of the part of the first sub-layer and the second sub-layer on the side surface of the functional structure on the filling area, and being conducive to the improvement of the stability and other performances of the semiconductor structure. Meanwhile, in the embodiments of the present disclosure, compared with the conventional process, the filling is not completed at one time, but is completed by obtaining a plurality of sub-layers. When the to-be-filled area is of a high aspect ratio, the filling method provided by the embodiments of the present disclosure can ensure that the bottom of the to-be-filled area can also obtain a relatively ideal filling effect, which is further conducive to the improvement of the stability and other performances of the semiconductor structure.

[0046] The details of one or more embodiments of the present disclosure are presented in the following drawings and description. Other features and advantages of the present disclosure will become apparent from the drawings, the description, and the claims. BRIEF DESCRIPTION OF DRAWINGS

[0047] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings needed in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and other drawings can also be obtained by those skilled in the art without creative labor.

[0048] Figure 1 The flow chart of the method for manufacturing a semiconductor structure provided by the embodiments of the present disclosure is shown in the figure.

[0049] Figures 2 to 12 The process flow chart of the method for manufacturing a semiconductor structure provided by the embodiments of the present disclosure is shown in the figure.

[0050] Figure 13 And Figure 14A process flow chart of a method for manufacturing a semiconductor structure is provided for another embodiment of the present disclosure.

[0051] Figure 15 A structural schematic diagram of a semiconductor structure is provided for an embodiment of the present disclosure. DETAILED DESCRIPTION

[0052] Exemplary embodiments of the present disclosure will be described herein below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art.

[0053] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it should be apparent to one skilled in the art that the present disclosure can be implemented without one or more of these details. In other instances, some well-known features are not described in detail in order to avoid obscuring the present disclosure. That is, not all features of actual implementations are described in detail; well-known functions and structures are not described in detail in order to avoid obscuring the present disclosure.

[0054] In the drawings, the size of layers, regions, elements and their relative sizes can be exaggerated for clarity. The same reference numbers represent the same elements throughout.

[0055] In the process of manufacturing a semiconductor structure, it is often necessary to perform an operation of filling various materials into a trench or hole to obtain a structure with desired performance.

[0056] As the market continues to demand new requirements for semiconductor structures, the integration of semiconductor structures is becoming higher and higher, which leads to the miniaturization of semiconductor structures, so that the aspect ratio of the trench or hole structure faced in the above operation becomes larger and larger, and voids and other defects are easily generated during the filling operation. If the filling material is a conductive material, poor contact is also likely to occur, which greatly reduces the stability and conductivity of the semiconductor structure.

[0057] Based on this, the following technical solutions of the embodiments of the present disclosure are proposed:

[0058] The embodiments of the present disclosure provide a method for manufacturing a semiconductor structure, as shown in Figure 1 The manufacturing method includes the following steps:

[0059] Step S101: providing a substrate, forming a plurality of functional structures on the substrate, and defining an area between the plurality of functional structures as a to-be-filled area;

[0060] Step S102: introducing a first gas into the reaction chamber to form a first sub-layer, the first sub-layer covering at least the surface of the functional structure;

[0061] Step S103: performing a first processing process to prevent migration of elements contained in the first sub-layer;

[0062] Step S104: introducing a second gas into the reaction chamber to form a second sub-layer on the surface of the first sub-layer;

[0063] Step S105: performing a second processing process to prevent migration of elements contained in the second sub-layer; wherein the first sub-layer and the second sub-layer fill the part of the side surface of the functional structure in the to-be-filled region.

[0064] Thus, in the filling operation of the embodiment of the present disclosure, the steps of the first processing process and the second processing process are added after the formation of the first sub-layer and the second sub-layer, respectively, so that the materials contained in the first sub-layer and the second sub-layer can be maintained in the initial deposition distribution state, and the voids caused by the clustering of the elements due to the migration of the elements can be avoided, effectively improving the filling effect of the part of the first sub-layer and the second sub-layer on the side surface of the functional structure in the to-be-filled region, and being conducive to the improvement of the stability and other properties of the semiconductor structure. At the same time, in the embodiment of the present disclosure, compared with the conventional process, the filling of the embodiment of the present disclosure is not completed at one time, but is completed by obtaining a plurality of sub-layers. When the to-be-filled region has a high aspect ratio, the filling method provided by the embodiment of the present disclosure can ensure that the bottom of the to-be-filled region can also obtain a relatively ideal filling effect, which is further conducive to the improvement of the stability and other properties of the semiconductor structure.

[0065] To make the above-mentioned purposes, features and advantages of the present disclosure more obvious and easy to understand, the specific embodiments of the present disclosure will be described in detail below with reference to the drawings. In the detailed description of the embodiments of the present disclosure, the schematic diagrams will be partially enlarged without the general proportion for the convenience of description, and the schematic diagrams are only examples, which should not limit the protection scope of the present disclosure.

[0066] Figure 1 The flow chart of the preparation method of the semiconductor structure provided by the embodiment of the present disclosure is shown in the figure; Figures 2 to 12 The process flow chart of the preparation method of the semiconductor structure provided by one embodiment of the present disclosure is shown in the figure; Figure 13 And Figure 14 The process flow chart of the preparation method of the semiconductor structure provided by another embodiment of the present disclosure is shown in the figure; Figure 15 The structure schematic diagram of a semiconductor structure provided by the embodiment of the present disclosure is shown in the figure.

[0067] The preparation method of the semiconductor structure provided by the embodiment of the present disclosure will be described in further detail below with reference to the drawings.

[0068] First, step S101 is performed, as shown in Figures 2 to 5 A substrate 10 is provided, and a plurality of functional structures 12 are formed on the substrate 10, with the regions between the plurality of functional structures 12 being defined as the to-be-filled regions 21.

[0069] Here, the substrate can be a semiconductor substrate, and the material of the semiconductor substrate specifically includes elemental semiconductor materials (e.g., silicon (Si) substrates, germanium (Ge) substrates, etc.), or III-V compound semiconductor materials (e.g., gallium nitride (GaN) substrates, gallium arsenide (GaAs) substrates, indium phosphide (InP) substrates, etc.), or II-VI compound semiconductor materials, or organic semiconductor materials, or other semiconductor materials known in the art. In a specific embodiment, the substrate is a silicon substrate.

[0070] It can be understood that, in actual operations, the functional structures can include, but are not limited to, capacitor structures, bit line structures, or other suitable structures, etc., and the regions between these functional structures and which need to be filled with materials later are defined as the to-be-filled regions.

[0071] In some specific embodiments, the semiconductor structure can further include other structures between the substrate and the functional structures, including but not limited to transistor structures or other structures, etc.

[0072] Optionally, in some embodiments, as shown in Figure 3 , Figure 4 and Figure 5 A plurality of functional structures 12 are formed on the substrate 10, including:

[0073] A stack structure ST is formed on the substrate, and the stack structure ST includes sacrificial layers 111 and support layers 112 which are alternately stacked;

[0074] An etching process is performed to remove part of the stack structure ST to form a plurality of hole-like structures H;

[0075] A lower electrode layer 121 is formed, and the lower electrode layer 121 fills the hole-like structures H;

[0076] The remaining stack structure ST between the lower electrode layer 121 is removed;

[0077] A first dielectric layer 122 is formed, and the first dielectric layer 122 covers at least the surface of the lower electrode layer 121;

[0078] An upper electrode layer 123 is formed, and the upper electrode layer 123 covers at least the surface of the first dielectric layer 122;

[0079] The lower electrode layer 121, the first dielectric layer 122, and the upper electrode layer 123 constitute the functional structures 12, and the regions between the plurality of functional structures 12 are defined as the to-be-filled regions 21.

[0080] Optionally, the semiconductor structure can further include a second dielectric layer (not labeled in the figure) between the substrate 10 and the stack structure ST, and a node contact plug 15 separately disposed in the second dielectric layer (not labeled in the figure). In some embodiments, the hole-like structure H formed by removing part of the stack structure ST exposes the node contact plug 15, and after the step of forming the lower electrode layer 121 is performed, the lower electrode layer 121 formed can form an electrical connection with the node contact plug 15.

[0081] Here, the material constituting the lower electrode layer includes but is not limited to one or more of tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicide, metal alloy. Optionally, the material of the lower electrode layer can be titanium nitride (TiN).

[0082] The material of the first dielectric layer can include but is not limited to at least one or a combination of oxides, nitrides, oxynitrides, etc., such as at least one of silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), etc. Optionally, in some embodiments, the first dielectric layer includes a high dielectric constant material. x N y ) and / or praseodymium oxide (Pr2O3), etc.

[0083] In actual operation, the high dielectric constant material can include but is not limited to aluminum oxide (Al2O3), tantalum oxide (Ta2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSi x O y ), hafnium oxide (HfO2), hafnium silicon oxide (HfSi x O y ), hafnium silicon oxynitride (HfSiON), hafnium zirconate (HfZrO4), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAl x O y ), lanthanum hafnium oxide (LaHf x O y ), hafnium aluminum oxide (HfAl x O y ) and / or praseodymium oxide (Pr2O3), etc.

[0084] It can be understood that in some embodiments, the material of the upper electrode layer can be the same as the material of the lower electrode layer. However, in some other embodiments, the material of the upper electrode layer can also be different from the material of the lower electrode layer, which can be flexibly selected according to actual conditions, and is not specifically limited here. Optionally, in some embodiments, the material of the upper electrode layer can include titanium nitride (TiN).

[0085] It can be seen that in this embodiment, the capacitor structure composed of the lower electrode layer, the first dielectric layer and the upper electrode layer is taken as the functional structure. In the following, the preparation method provided by the embodiment of the present disclosure will be further described in detail by taking the case where the functional structure is the capacitor structure as an example.

[0086] It should be noted that the capacitor structure is in a columnar structure in the drawings. In actual operation, other capacitor structures, such as a cylindrical capacitor structure and other shaped structures, are also applicable to the scheme provided by the embodiment of the present disclosure.

[0087] Further, it should be noted that the preparation method provided by the embodiment of the present disclosure is not limited to the case where the functional structure is the capacitor structure. When the functional structure is other structure and there is a region between the functional structures that needs to be filled, especially when the region with a high aspect ratio needs to be filled, the method provided by the embodiment of the present disclosure can be used to obtain a semiconductor structure with a better filling effect, so as to effectively improve the stability, reliability and other performances of the semiconductor structure.

[0088] Next, step S102 is performed, as shown in FIG. 1, a first gas is introduced into the reaction chamber to form a first sub-layer 13, and the first sub-layer 13 covers at least the surface of the functional structure 12. Figure 6

[0089] In some embodiments, after the plurality of functional structures 12 are formed, before the first gas is introduced into the reaction chamber, the preparation method further comprises:

[0090] Placing the substrate 10 containing the plurality of functional structures 12 into the reaction chamber in a nitrogen-containing atmosphere;

[0091] Raising the temperature of the reaction chamber to a preset temperature in an atmosphere containing nitrogen and silane (SiH4) to improve the cleanliness of the substrate 10 containing the plurality of functional structures 12;

[0092] Removing the exhaust gas generated in the above operation process.

[0093] Since the environment generally has a high oxygen content, in this embodiment, the introduction of nitrogen can effectively reduce the oxygen content in the area where the wafer is loaded when the wafer is loaded. When the oxygen content is reduced to a certain value, the operation of placing the wafer into the reaction chamber is started, so as to maximize the adverse effects of the residual oxygen on the surface of the wafer on the subsequent material deposition process.

[0094] Optionally, in some embodiments, before the operation of placing the wafer into the reaction chamber is performed, the oxygen content in the area where the wafer is loaded needs to be below 10 ppm, for example, 9 ppm, 8 ppm, 5 ppm, 3 ppm, etc., which can be determined according to actual conditions and is not limited herein.​

[0095] In addition, during the process of heating the reaction chamber to the preset temperature, the chamber contains a mixed gas of nitrogen and silane (SiH4). At this time, because silane (SiH4) has a large molecular weight and part of the gas can generate a large number of gas molecules due to decomposition during the process, compared with the process without containing silane atmosphere, the process can more effectively remove the impurity gas adsorbed on the surface of the wafer, which is beneficial to the smooth execution of the subsequent operation steps. At the same time, the atmosphere contained in the process can also perform a pretreatment operation on the surface of the functional structure to reduce the adsorption of impurities on the surface of the functional structure, thereby helping the gas contained in the subsequent first sub-layer forming process to be more effectively adsorbed to the surface of the functional structure.

[0096] In some specific embodiments, the waste gas generated in the above operation process is removed, including:

[0097] Performing a vacuum pumping operation and a purge treatment to remove the waste gas on the surface of the wafer.

[0098] Optionally, in some embodiments, before performing the vacuum pumping operation and the purge treatment, the method further includes: confirming whether the equipment containing the reaction chamber has a side leakage abnormality. When it is confirmed that there is no side leakage abnormality, the equipment can be started to perform the vacuum pumping operation and the purge treatment process to remove the waste gas generated in the operation process.

[0099] It can be understood that the operation of removing the waste gas generated in the above operation process is helpful for the smooth execution of the subsequent material deposition process.

[0100] After completing the above series of operations, the operation of depositing the first sub-layer can be started. Optionally, in some embodiments, after removing the waste gas generated in the above operation process, before forming the first sub-layer, the preparation method can further include: stabilizing the temperature of the reaction chamber.

[0101] In some embodiments, the first gas includes a germanium-containing gas, and forming the first sub-layer 13 includes:

[0102] The reaction chamber is supplied with a germanium-containing gas to form the first sub-layer 13, the first sub-layer 13 at least covers the surface of the functional structure 12, and the first sub-layer 13 at least contains elemental germanium.

[0103] In other embodiments, the first gas includes a germanium-containing gas and a boron-containing gas, and forming the first sub-layer 13 includes:

[0104] The reaction chamber is supplied with a germanium-containing gas and a boron-containing gas to form the first sub-layer 13, the first sub-layer 13 at least covers the surface of the functional structure 12, and the first sub-layer 13 at least contains elemental germanium.

[0105] Here, the first sub-layer can be a boron-doped or non-boron-doped germanium layer or a seed layer containing germanium. It can be understood that when the first sub-layer is a seed layer, the presence of the seed layer facilitates the subsequent deposition of the second sub-layer to be successfully attached to the surface of the functional structure and the bottom surface of the to-be-filled region.

[0106] Optionally, the formation of the first sub-layer can be achieved by using a low-pressure chemical vapor deposition process (LPCVD).

[0107] In some specific embodiments, when the first gas includes a germanium-containing gas or a germanium-containing gas plus a boron-containing gas, the temperature range used to form the first sub-layer can be between 270°C and 450°C, inclusive. It can be understood that in some specific embodiments, the temperature range used to form the first sub-layer can be between 340°C and 450°C, inclusive, for example: 360°C, 370°C, 380°C, 400°C, 430°C, etc.; the pressure range can be between 0.005 Torr and 1 Torr, inclusive, for example: 0.05 Torr, 0.2 Torr, 0.5 Torr, 0.8 Torr, 0.9 Torr, etc.; the deposition time range can be between 5S and 60S, inclusive, for example: 8S, 15S, 30S, 50S, etc.

[0108] In addition, when the first gas includes a germanium-containing gas or a germanium-containing gas plus a boron-containing gas, the flow rate range of the germanium-containing gas can be between 0.2 slm and 1 slm, inclusive, for example: 0.4 slm, 0.5 slm, 0.8 slm, 0.9 slm, etc.; the flow rate range of the boron-containing gas can be between 10 sccm and 50 sccm, inclusive, for example: 20 sccm, 30 sccm, 40 sccm, etc. However, it is not limited to this, and in actual operation, the above-mentioned parameter settings for the flow rate range can also be flexibly adjusted according to the specific gas composition and doping concentration ratio, which is not limited here.

[0109] It can be understood that in some embodiments, as shown in FIG. 1B, in addition to covering the surface of the functional structure 12, the first sub-layer 13 can also cover the bottom surface of the to-be-filled region 21. Compared with the situation in conventional technology that the filling material is difficult to reach the to-be-filled region due to the limitation of the high aspect ratio of the to-be-filled region 21, the method provided in the embodiments of the present disclosure provides favorable conditions for obtaining better filling effect subsequently. Figure 6

[0110] ​It can be seen that, in the embodiments of the present disclosure, the first sub-layer is formed in a low-temperature and low-pressure environment, at which time the first gas introduced can have a larger diffusion coefficient and mean free path. Therefore, the first sub-layer obtained by the preparation method of the embodiments of the present disclosure can have better film formation quality and can better cover the surface of the functional structure and the bottom of the region to be filled, thereby facilitating the realization of a better filling effect, while also effectively reducing the manufacturing cost.

[0111] Next, step S103 is performed, as shown in Figure 7 The first processing process is performed to prevent the elements contained in the first sub-layer 13 from migrating.

[0112] In some embodiments, the first processing process includes:

[0113] A third gas containing hydrogen is introduced into the reaction chamber, and the third gas can prevent the elements contained in the first sub-layer 13 from migrating.

[0114] In other embodiments, the first processing process includes:

[0115] The first vacuumization process is performed on the reaction chamber;

[0116] A fourth gas containing hydrogen is introduced into the reaction chamber, and the fourth gas can prevent the elements contained in the first sub-layer 13 from migrating;

[0117] The second vacuumization process is performed on the reaction chamber.

[0118] Referring to Figure 8 It can be seen that, by setting the operation of the first processing process, the first sub-layer can always remain in the initial material deposition state (as shown in Figure 6 ) and does not have the phenomenon of element migration.

[0119] It can be understood that, since the elements contained in the first sub-layer, such as germanium, have many dangling bonds, when there is no first processing process, the dangling bonds between the germanium elements adjacent to each other will combine with each other to form clusters, and the formation of clusters will cause the roughness of the surface of the first sub-layer to increase. When the subsequent material deposition process is continued, the increase in the roughness of the surface of the first sub-layer will hinder the diffusion of the gas to a certain extent, increasing the possibility of defects such as voids in the filling material, resulting in poor filling effect, and further, it can also reduce the stability, conductivity or other performance of the semiconductor structure obtained finally.

[0120] In the embodiments of the present disclosure, after the first sub-layer is formed, the step of performing the first processing process is added, which can effectively prevent the cluster phenomenon from occurring on the surface of the first sub-layer, so that the first sub-layer can remain in the initial deposition distribution state, thereby effectively avoiding the occurrence of defects such as voids in the subsequently deposited material, and providing favorable conditions for obtaining a better filling effect for the to-be-filled region.

[0121] In addition, in the embodiments including the vacuumizing process, in addition to the above-mentioned effects, the previous vacuumizing process can enhance the effect of preventing element migration of the first processing process, and the subsequent vacuumizing process can provide a relatively pure deposition environment for the execution of the subsequent process, which is beneficial to the smooth execution of the subsequent material deposition process, and further helps to obtain a semiconductor structure with a better filling effect.

[0122] In actual operation, the third gas and the fourth gas can have the same gas composition, but are not limited thereto. The third gas and the fourth gas can also have different gas compositions, which can be flexibly selected according to actual conditions, and are not specifically limited herein.

[0123] In some specific embodiments, the third gas and the fourth gas can both be hydrogen. When the third gas and the fourth gas are both hydrogen, the temperature range of the first processing process can be between 340°C and 450°C (including the end values), for example, 360°C, 380°C, 390°C, 400°C, 430°C, etc.; the pressure range can be between 50 Torr and 100 Torr (including the end values), for example, 60 Torr, 70 Torr, 80 Torr, 90 Torr, etc.; the processing time range can be between 2 min and 5 min (including the end values), for example, 2.5 min, 3 min, 4 min, 4.5 min, etc.; and the gas flow range can be between 0.5 slm and 2 slm (including the end values), for example, 0.8 slm, 1 slm, 1.5 slm, 1.8 slm, etc.

[0124] However, the parameter settings during the execution of the first processing process are not limited to the above-mentioned cases, and can be flexibly adjusted according to actual conditions, and are not specifically limited herein.

[0125] Then, step S104 is performed, as shown in Figure 9 and Figure 13 The second gas is introduced into the reaction chamber to form a second sub-layer on the surface of the first sub-layer.

[0126] In some embodiments, as shown in Figure 9 The second gas includes a germanium-containing gas and a silicon-containing gas, and the formation of the second sub-layer includes:

[0127] The reaction chamber is supplied with a germanium-containing gas and a silicon-containing gas to form a second sub-layer on the surface of the first sub-layer.

[0128] In this embodiment, the material of the second sub-layer can include a silicon germanium material, which can have good filling performance. Optionally, in some embodiments, the silicon germanium material can be a doped material or an undoped material, which can be selected according to actual conditions and is not limited herein.

[0129] In some other embodiments, as shown in Figure 13 The second gas includes a silicon-containing gas and a boron-containing gas, and the second sub-layer is formed by the following steps:

[0130] The reaction chamber is supplied with a silicon-containing gas and a boron-containing gas to form a second sub-layer on the surface of the first sub-layer.

[0131] In this embodiment, the material of the second sub-layer can include a boron-doped polysilicon material, which can effectively improve the conductivity of the second sub-layer.

[0132] In some other embodiments, as shown in Figure 15 The material of the second sub-layer can also include a silicon germanium material and a polysilicon material at the same time, and the distance of the two materials from the first sub-layer can be selected as desired and is not limited herein.

[0133] It can be seen that, in the embodiments of the present disclosure, the filling operation on the to-be-filled region is not completed at one time, but is obtained by forming multiple sub-layers respectively. Compared with the conventional single filling mode, the operation mode of filling in batches has higher process controllability and better material distribution state. When necessary, the filling state in the to-be-filled region can be monitored, and the parameter settings during subsequent material deposition can be adjusted as necessary to obtain the desired filling effect. Therefore, even in the case of high aspect ratio, the filling mode provided by the embodiments of the present disclosure can ensure that the bottom of the to-be-filled region has a relatively ideal filling effect, which is further helpful to improve the stability and other performance of the semiconductor structure.

[0134] Optionally, the formation of the second sub-layer can be obtained by using a low-pressure chemical vapor deposition process (LPCVD).

[0135] In some embodiments, the temperature range for forming the second sub-layer can be between 270°C and 450°C, inclusive. It can be appreciated that in some embodiments, the temperature range for forming the second sub-layer can be between 340°C and 450°C, inclusive, such as 360°C, 370°C, 380°C, 400°C, 420°C, 430°C, etc.; the pressure range can be between 0.5 Torr and 3 Torr, inclusive, such as 0.8 Torr, 1 Torr, 1.5 Torr, 2.0 Torr, 2.5 Torr, 2.8 Torr, etc.; the gas introduction time range can be between 5 min and 10 min, inclusive, such as 6 min, 7 min, 8 min, 9 min, etc.; the gas flow rate range for introducing the silicon-containing gas or the germanium-containing gas can be between 0.2 slm and 1 slm, inclusive, such as 0.4 slm, 0.5 slm, 0.8 slm, 0.9 slm, etc.; the flow rate range for introducing the boron-containing gas can be between 10 sccm and 50 sccm, inclusive, such as 20 sccm, 30 sccm, 40 sccm, etc. However, the above-mentioned parameters for the flow rate range can be adjusted flexibly according to the specific gas composition and doping concentration ratio in actual operation, which is not limited herein.

[0136] As can be seen, the second sub-layer is formed in a low-temperature and low-pressure environment, at which time the introduced second gas can have a larger diffusion coefficient and mean free path. Therefore, the second sub-layer obtained by the preparation method of the embodiments of the present disclosure can have better film formation quality and can better cover the functional structure and the surface of the bottom of the to-be-filled region, thereby facilitating the realization of a better filling effect, while also effectively reducing the manufacturing cost.

[0137] Finally, step S105 is performed, as shown in Figure 10 and Figure 13 A second processing process is performed to prevent the elements contained in the second sub-layer 14 from migrating; wherein the first sub-layer 13 and the second sub-layer 14 are located on the part of the functional structure 12 side surface filling the to-be-filled region 21.

[0138] In this embodiment, when the second sub-layer is a case of simultaneously containing silicon-germanium material and polycrystalline silicon material as shown in Figure 15 , a second processing process can be performed after the formation of the silicon-germanium material and the polycrystalline silicon material to better prevent the phenomenon of element migration caused by the mutual combination of dangling bonds of germanium elements or silicon elements contained in the second sub-layer.

[0139] In some embodiments, the second processing process includes:

[0140] The fifth gas containing hydrogen is introduced into the reaction chamber, and the fifth gas can prevent the elements contained in the second sub-layer 14 from migrating.

[0141] In some embodiments, when the second processing procedure is performed, the reaction chamber can be vacuumized before and after the fifth gas containing hydrogen is introduced. The vacuumization before the fifth gas containing hydrogen is introduced can enhance the effect of preventing the elements from migrating. The vacuumization after the fifth gas containing hydrogen is introduced can provide a purer operation environment for the subsequent process, which is beneficial to the subsequent material deposition process.

[0142] In actual operation, the fifth gas can be the same as the third gas or the fourth gas, or can be different, which is not specifically limited herein.

[0143] In some embodiments, the fifth gas can be hydrogen. When the fifth gas is hydrogen, the parameters used in the second processing procedure can be the same as or different from those used in the first processing procedure.

[0144] Optionally, in some embodiments, when the second processing procedure is performed, the temperature can be in the range of 340-450°C (including the end values), for example, 360°C, 380°C, 390°C, 400°C, 430°C, etc.; the pressure can be in the range of 50-100 Torr (including the end values), for example, 60 Torr, 70 Torr, 80 Torr, 90 Torr, etc.; the processing time can be in the range of 2-5 min (including the end values), for example, 2.5 min, 3 min, 4 min, 4.5 min, etc.; and the gas flow rate can be in the range of 0.5-2 slm (including the end values), for example, 0.8 slm, 1 slm, 1.5 slm, 1.8 slm, etc.

[0145] However, the parameters used when the second processing procedure is performed can be flexibly adjusted according to actual conditions, which is not specifically limited herein.

[0146] In addition to the above scheme, in order to obtain a more ideal filling effect in the to-be-filled region, the present disclosure also provides some other embodiments, in which the operation method of steps S102-S105 is performed multiple times to achieve a better filling effect in the to-be-filled region.

[0147] Specifically, in some embodiments, as shown in Figure 11 and Figure 12 、 Figure 13 and Figure 14 and Figure 15 After the second processing procedure is performed, the preparation method further includes:

[0148] The first gas is introduced into the reaction chamber again to form the first sub-layer 13 on the surface of the second sub-layer 14;

[0149] The first processing procedure is performed again to prevent the elements contained in the first sub-layer 13 from migrating;

[0150] The second gas is introduced into the reaction chamber again to form the second sub-layer 14 on the surface of the first sub-layer 13;

[0151] The second processing procedure is performed again to prevent the elements contained in the second sub-layer 14 from migrating;

[0152] The above operation is repeated for multiple cycles until the multiple first sub-layers 13 and the multiple second sub-layers 14 fill the part of the to-be-filled region 21 on the side surface of the functional structure 12.

[0153] Optionally, the thickness of the material formed after each cycle can range from 0.5 nm to 5 nm, for example, 1 nm, 1.5 nm, 2 nm, 3 nm, 4 nm, etc. However, the thickness of the material formed after each cycle can also be flexibly adjusted according to actual conditions in actual operations, which is not specifically limited herein.

[0154] In addition, the first sub-layer and the second sub-layer can be formed by using a low-pressure chemical vapor deposition (LPCVD) method in the multiple cycles. The gas composition and parameter settings used can refer to the information provided in any of the above embodiments. However, the gas composition and parameter settings used in the multiple cycles can also be other conditions, which can be determined according to actual conditions, and are not specifically limited herein.

[0155] It can be understood that compared with the method without the multiple cycles, the method provided in the above embodiments can further improve the distribution state of the filling material in the to-be-filled region, that is, a better filling effect can be obtained even at the bottom of the to-be-filled region or other positions where the material is difficult to deposit, thereby further improving the stability, conductivity, and other properties of the semiconductor structure obtained finally.

[0156] In addition, the method with the multiple cycles is also largely adaptable to the case where the size of the to-be-filled region changes. Since the thickness of the material obtained in each cycle can be a relatively stable value after the process parameters are determined, the optimal filling effect can be obtained in a plurality of size ranges by controlling the number of cycles without changing other process parameters during the material deposition process. In addition, the method has good controllability, so that the properties of the semiconductor structures obtained in different batches can also have good consistency.

[0157] In some embodiments, before the first gas is introduced into the reaction chamber again, the preparation method comprises:

[0158] The sixth gas containing nitrogen is introduced into the reaction chamber, and the sixth gas is used to exhaust the reaction gas.

[0159] In this embodiment, after the second processing procedure is performed in each cycle, the operation of introducing the sixth gas containing nitrogen is performed before the operation of introducing the first gas again into the reaction chamber, which is contained in the next cycle operation, can help to exhaust the waste gas generated in the previous process operation of the reaction chamber, prevent the adverse effects of excess waste gas on the next cycle operation, and effectively improve the filling effect of the next cycle operation.

[0160] The present disclosure also provides a semiconductor structure, as shown in Figure 12 、 Figure 14 and Figure 15 , comprising:

[0161] a substrate 10:

[0162] a plurality of functional structures 12, the functional structures 12 being located on the substrate 10, and the area between the plurality of functional structures 12 being defined as a to-be-filled area 21;

[0163] at least one first sub-layer 13 and at least one second sub-layer 14, the first sub-layer 13 covering at least the surface of the functional structure 12, and the second sub-layer 14 covering the surface of the first sub-layer 13;

[0164] wherein the first sub-layer 13 and the second sub-layer 14 fill the to-be-filled area 21 at the part of the side surface of the functional structure 12.

[0165] In some embodiments, the functional structure can be a capacitor structure, which specifically can include a lower electrode layer 121, a first dielectric layer 122, and an upper electrode layer 123.

[0166] In some embodiments, the material of the first sub-layer includes a germanium layer, and the material of the second sub-layer includes silicon germanium (specifically refer to Figure 12 ), or polycrystalline silicon (specifically refer to Figure 14 ), or a combination of silicon germanium and polycrystalline silicon (specifically refer to Figure 15 ).

[0167] With reference to Figure 12 、 Figure 14 and Figure 15As shown, it can be seen that, in some embodiments, the first sub-layers and the second sub-layers can be arranged alternately within the to-be-filled region. Compared with the conventional arrangement, this arrangement can effectively improve the distribution state of the filling material within the to-be-filled region, especially the to-be-filled region with a high aspect ratio, so that a better filling effect can be obtained even at the bottom of the to-be-filled region or other positions where the material is difficult to deposit, and the stability, conductivity and other performances of the finally obtained semiconductor structure can be effectively improved.

[0168] Optionally, in some embodiments, the material thickness range formed by the adjacent first sub-layers and second sub-layers can be between 0.5 nm and 5 nm, for example, 1 nm, 1.5 nm, 2 nm, 3 nm, 4 nm, etc. However, it is not limited thereto, and in actual operation, the material thickness range formed by the adjacent first sub-layers and second sub-layers can also be flexibly adjusted according to actual conditions, which is not specifically limited herein.

[0169] It can be understood that the semiconductor structure provided by the embodiments of the present disclosure is also largely adapted to the case where the size of the to-be-filled region changes. Since the material thickness formed by the adjacent first sub-layers and second sub-layers can be a relatively stable value after the process parameters are determined, when the material is deposited, only the number of the first sub-layers and the second sub-layers needs to be controlled without changing other process parameters, so that a better filling effect can be obtained in a plurality of size ranges, and because the method has greater controllability, the performances of the semiconductor structures of different batches obtained finally can also have better consistency.

[0170] It should be noted that the formation method of the functional structure provided in the above embodiments is an example of the application of the functional structure as a capacitor structure (columnar capacitor structure), which cannot be the only limitation of the application scenarios of the embodiments of the present disclosure. It can be understood that the functional structure involved in the preparation method and structure provided by the embodiments of the present disclosure can also be a cylindrical capacitor structure and other shapes of capacitor structures, bit line structures or other suitable structure types, and these functional structures can be obtained by conventional techniques or any possible method, which is not specifically limited herein.

[0171] It should be noted that the preparation method of the semiconductor device provided by the embodiments of the present disclosure can be applied to a DRAM structure or other semiconductor devices, which is not limited herein. The embodiments of the semiconductor device preparation method provided by the present disclosure belong to the same concept as the embodiments of the semiconductor device; the technical features in the technical solutions described in each embodiment can be combined arbitrarily without conflict.

[0172] It should be noted that the sequence of the above steps can be changed by those skilled in the art without departing from the protection scope of the present disclosure, the above is only an optional embodiment of the present disclosure, and is not used to limit the protection scope of the present disclosure, and any modification, equivalent replacement and improvement made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A method of fabricating a semiconductor structure, characterized by, The method comprises the following steps: providing a substrate, forming a plurality of functional structures on the substrate, and defining an area between the plurality of functional structures as a filling area; introducing a first gas into a reaction chamber to form a first sub-layer, the first sub-layer covering at least a surface of the functional structure; performing a first processing process to prevent migration of elements contained in the first sub-layer; introducing a second gas into the reaction chamber to form a second sub-layer on the surface of the first sub-layer; performing a second processing process to prevent migration of elements contained in the second sub-layer; wherein the first sub-layer and the second sub-layer partially fill the filling area on the side surface of the functional structure.

2. The production method according to claim 1, characterized by, After forming the plurality of functional structures, before introducing the first gas into the reaction chamber, the preparation method further comprises: placing the substrate containing the plurality of functional structures into the reaction chamber in a nitrogen-containing atmosphere; heating the reaction chamber to a preset temperature in an atmosphere containing nitrogen and silane to improve the cleanliness of the substrate containing the plurality of functional structures; removing the waste gas generated in the above operation process.

3. The preparation method according to claim 1, characterized in that, The first gas comprises a germanium-containing gas, and the formation of the first sub-layer comprises: introducing a germanium-containing gas into the reaction chamber to form a first sub-layer, the first sub-layer covering at least a surface of the functional structure, and the first sub-layer containing at least elemental germanium.

4. The method of claim 1, wherein, The first gas comprises a germanium-containing gas and a boron-containing gas, and the formation of the first sub-layer comprises: introducing a germanium-containing gas and a boron-containing gas into the reaction chamber to form a first sub-layer, the first sub-layer covering at least a surface of the functional structure, and the first sub-layer containing at least elemental germanium.

5. The preparation method according to claim 1, characterized in that, The first processing process comprises: introducing a third gas containing hydrogen into the reaction chamber, the third gas being capable of preventing migration of elements contained in the first sub-layer.

6. The method of claim 1, wherein, The first processing process comprises: performing a first vacuumizing process on the reaction chamber; introducing a fourth gas containing hydrogen into the reaction chamber, the fourth gas being capable of preventing migration of elements contained in the first sub-layer; performing a second vacuumizing process on the reaction chamber.

7. The preparation method according to claim 1, characterized in that, The second gas comprises a germanium-containing gas and a silicon-containing gas, and the formation of the second sub-layer comprises: introducing a germanium-containing gas and a silicon-containing gas into the reaction chamber to form a second sub-layer on the surface of the first sub-layer.

8. The method of claim 1, wherein, The second gas comprises a silicon-containing gas and a boron-containing gas, and the formation of the second sub-layer comprises: introducing a silicon-containing gas and a boron-containing gas into the reaction chamber to form a second sub-layer on the surface of the first sub-layer.

9. The method of claim 1, wherein, The second processing process comprises: introducing a fifth gas containing hydrogen into the reaction chamber, the fifth gas being capable of preventing migration of elements contained in the second sub-layer.

10. The method of claim 1, wherein, After performing the second processing process, the preparation method further comprises: introducing the first gas into the reaction chamber again to form a first sub-layer on the surface of the second sub-layer; performing the first processing process again to prevent migration of elements contained in the first sub-layer; introducing the second gas into the reaction chamber again to form a second sub-layer on the surface of the first sub-layer; performing the second processing process again to prevent migration of elements contained in the second sub-layer; The above operation is repeated multiple times until the portions of the functional structures on the side surface are filled with the first sub-layers and the second sub-layers.

11. The method of claim 10, wherein, Before the first gas is introduced into the reaction chamber again, the preparation method comprises: A sixth gas containing nitrogen is introduced into the reaction chamber, and the sixth gas is used to exhaust the reaction gas.

12. A semiconductor structure obtainable by the process according to any one of claims 1 to 11, characterized in that Comprise: A substrate; A plurality of functional structures on the substrate, and an area between the plurality of functional structures is defined as a to-be-filled area; At least one first sub-layer and at least one second sub-layer, the first sub-layer at least covers the surface of the functional structure, and the second sub-layer covers the surface of the first sub-layer; Wherein, the first sub-layer and the second sub-layer fill the to-be-filled area on the side surface of the functional structure.

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