Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a forming method thereof, the forming method comprising: providing a substrate, including a device unit area, wherein a stack structure is formed in the device unit area, the stack structure including a first channel layer, a sacrificial layer and a second channel layer, first and second pre-embedded power layers are formed on both sides of the device unit area, and a dummy gate structure is formed on the substrate; forming a first source-drain doping layer in the stack structure on both sides of the dummy gate structure; forming a first source-drain interconnection layer covering the first source-drain doping layer, extending to and electrically connected to the top of the first pre-embedded power layer; forming an isolation layer on the first source-drain interconnection layer; forming a second source-drain doping layer on the isolation layer; forming a protection wall on the sidewall of the second source-drain doping layer closest to the second pre-embedded power layer; forming a second source-drain interconnection layer covering the second source-drain doping layer and the protection wall, extending to and electrically connected to the top of the second pre-embedded power layer. The application reduces the probability of short circuit between the second source-drain interconnection layer and the first source-drain doping layer or the first source-drain interconnection layer.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a forming method thereof. BACKGROUND

[0002] In semiconductor manufacturing, with the development trend of ultra-large scale integrated circuits, the feature size of integrated circuits continues to decrease, and in order to adapt to smaller feature sizes, the channel length of Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is also shortened accordingly. However, as the device channel length is shortened, the distance between the source and the drain of the device is also shortened, so the control ability of the gate structure on the channel is also deteriorated, and the difficulty of the gate voltage to pinch off the channel is also increasing, making the subthreshold leakage phenomenon, i.e. the so-called short-channel effects (SCE) more likely to occur.

[0003] Therefore, in order to better adapt to the decrease of feature size, semiconductor processes gradually begin to transition from planar MOSFET to three-dimensional transistors with higher efficiency.

[0004] Among them, the complementary field effect transistor (complementary FET, CFET) composed of vertical stacking is a revolutionary three-dimensional transistor. In the CFET structure, the PMOS transistor and the NMOS transistor vertically stacked with each other form a complementary device, but the working performance of the CFET still needs to be further improved. SUMMARY

[0005] The problem solved by embodiments of the present application is to provide a semiconductor structure and a forming method thereof, to improve the working performance of the semiconductor structure.

[0006] To solve the above problems, the embodiment of the present application provides a semiconductor structure, comprising: a substrate, comprising a device unit area for forming a first transistor and a second transistor stacked from bottom to top; a pre-embedded power supply layer located in the substrate on both sides of the device unit area in a second direction, comprising a first pre-embedded power supply layer located on one side of the device unit area and a second pre-embedded power supply layer located on the other side of the device unit area; a first transistor located on the substrate of the device unit area, the first transistor comprising a first channel layer extending along a first direction, a first gate structure crossing the first channel layer and covering the top and sidewall of the first channel layer, and a first source-drain doped layer located on the substrate on both sides of the first gate structure, the first source-drain doped layer being in contact with the end of the first channel layer located below the first gate structure, the first direction being perpendicular to the second direction; a first source-drain interconnection layer covering the first source-drain doped layer, the first source-drain interconnection layer also extending from the side of the first source-drain doped layer to the top of the corresponding first pre-embedded power supply layer in the longitudinal direction and being electrically connected with the pre-embedded power supply layer; an isolation layer located on the top of the first source-drain interconnection layer; a second transistor stacked above the first transistor, the second transistor comprising a second channel layer extending along the first direction, a second gate structure crossing the second channel layer and covering the second channel layer, and a second source-drain doped layer located on the isolation layer on both sides of the second gate structure, the second source-drain doped layer being in contact with the end of the second channel layer located below the second gate structure; a protection wall located on the sidewall of the second source-drain doped layer closest to the second pre-embedded power supply layer; a second source-drain interconnection layer covering the second source-drain doped layer and the protection wall, the second source-drain interconnection layer also extending from the side of the protection wall to the top of the corresponding second pre-embedded power supply layer in the longitudinal direction and being electrically connected with the second pre-embedded power supply layer.

[0007] Correspondingly, the embodiment of the present application also provides a forming method of a semiconductor structure, comprising: providing a substrate, including a device unit area for forming a first transistor and a second transistor stacked from bottom to top in sequence, a stack structure extending in a first direction is formed on the substrate of the device unit area, the stack structure includes a first channel layer, a sacrificial layer located on the first channel layer, and a second channel layer located on the sacrificial layer, a first pre-embedded power supply layer and a second pre-embedded power supply layer are respectively formed in the substrate on both sides of the device unit area in a second direction, the second direction is perpendicular to the first direction, a pseudo gate structure is also formed on the substrate and crosses the stack structure, the pseudo gate structure covers part of the sidewall and part of the top of the stack structure; a first source-drain doped layer is formed in the stack structure on both sides of the pseudo gate structure, the first source-drain doped layer is in contact with the end of the first channel layer under the pseudo gate structure; a first source-drain interconnection layer covering the first source-drain doped layer is formed on both sides of the pseudo gate structure, the first source-drain interconnection layer also extends from the side of the first source-drain doped layer to the top of the corresponding first pre-embedded power supply layer in the longitudinal direction and is electrically connected with the first pre-embedded power supply layer; an isolation layer is formed on the first source-drain interconnection layer, the isolation layer exposes the end of the second channel layer; a second source-drain doped layer is formed on the isolation layer on both sides of the pseudo gate structure, the second source-drain doped layer is in contact with the end of the second channel layer under the pseudo gate structure; a protection wall is formed on the sidewall of the second pre-embedded power supply layer closest to the second source-drain doped layer; a second source-drain interconnection layer covering the second source-drain doped layer and the protection wall is formed on both sides of the pseudo gate structure, the second source-drain interconnection layer also extends from the side of the protection wall to the top of the corresponding second pre-embedded power supply layer in the longitudinal direction and is electrically connected with the second pre-embedded power supply layer.

[0008] Compared with the prior art, the technical scheme of the embodiment of the present application has the following advantages:

[0009] The first transistor and the second transistor are stacked, which is beneficial to save the area occupied by the semiconductor structure, and the first source-drain interconnection layer extends to the top of the corresponding first pre-embedded power supply layer in the longitudinal direction and is electrically connected with the first pre-embedded power supply layer, the second source-drain interconnection layer extends to the top of the corresponding second pre-embedded power supply layer in the longitudinal direction and is electrically connected with the second pre-embedded power supply layer, and the protective wall is located on the sidewall of the second source-drain doped layer closest to the second pre-embedded power supply layer; when the second source-drain interconnection layer is electrically connected with the second pre-embedded power supply layer, the second source-drain interconnection layer extends downward from the outside of the protective wall, thereby increasing the distance between the part of the second source-drain interconnection layer extending downward and the first source-drain doped layer or the first source-drain interconnection layer, reducing the probability that the second source-drain interconnection layer contacts the first source-drain doped layer or the first source-drain interconnection layer due to the too-close distance, thereby reducing the probability that the second source-drain interconnection layer is short-circuited with the first source-drain doped layer or the first source-drain interconnection layer, and further ensuring the working performance of the semiconductor structure.

[0010] In the forming method, the protective wall is formed on the sidewall of the second source-drain doped layer closest to the second pre-embedded power supply layer, and then the second source-drain interconnection layer covering the second source-drain doped layer and the protective wall is formed, the second source-drain interconnection layer extends to the top of the corresponding second pre-embedded power supply layer in the longitudinal direction and is electrically connected with the second pre-embedded power supply layer, the protective wall is formed on the sidewall of the second source-drain doped layer closest to the second pre-embedded power supply layer, and when the second source-drain interconnection layer is electrically connected with the second pre-embedded power supply layer, the second source-drain interconnection layer extends downward from the outside of the protective wall, thereby increasing the distance between the part of the second source-drain interconnection layer extending downward and the first source-drain doped layer or the first source-drain interconnection layer, reducing the probability that the second source-drain interconnection layer contacts the first source-drain doped layer or the first source-drain interconnection layer due to the too-close distance, thereby reducing the probability that the second source-drain interconnection layer is short-circuited with the first source-drain doped layer or the first source-drain interconnection layer, and further ensuring the working performance of the semiconductor structure. BRIEF DESCRIPTION OF DRAWINGS

[0011] Figures 1-3 It is a structure schematic diagram corresponding to each step in a forming method of a semiconductor structure.

[0012] Figures 4-5 It is a structure schematic diagram corresponding to an embodiment of the semiconductor structure of the application.

[0013] Figures 6-24 It is a structure schematic diagram corresponding to each step in an embodiment of the forming method of the semiconductor structure of the application. DETAILED DESCRIPTION

[0014] The performance of current semiconductor structures needs improvement. This paper analyzes the reasons for this performance improvement by examining a semiconductor structure formation method.

[0015] Figures 1-3 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0016] Reference Figure 1 and Figure 2 , Figure 1 This is a top view of the channel layer and pseudo-gate structure. Figure 2 (a) is Figure 1 Cross-sectional view along the AA direction. Figure 2 (b) is Figure 1 A cross-sectional view along the BB direction provides a substrate 10, including a device cell region 10Q for forming a first transistor and a second transistor stacked sequentially from bottom to top. The substrate 10 of the device cell region 10Q has a structure formed along a first direction (e.g., ...). Figure 1 A stacked structure 20 extending in the X direction (as shown in the middle X direction) includes a first channel layer 21, a sacrificial layer 23 located on the first channel layer 21, and a second channel layer 22 located on the sacrificial layer 23, in the second direction (as shown in the middle X direction). Figure 1 On the Y-direction, a first embedded power layer 14 and a second embedded power layer 15 are formed in the substrates 10 on both sides of the device cell region 10Q, respectively. The second direction is perpendicular to the first direction. A pseudo gate structure 16 that spans the stacked structure 20 is also formed on the substrate 10. The pseudo gate structure 16 covers part of the sidewalls and part of the top of the stacked structure 20.

[0017] Continue to refer to Figure 1 and Figure 2 A first source / drain doped layer 41 is formed in the stacked structure 20 on both sides of the dummy gate structure 16, and the first source / drain doped layer 41 is in contact with the end of the first channel layer 21 below the dummy gate structure 16; a first source / drain interconnect layer 42 is formed on both sides of the dummy gate structure 16, covering the first source / drain doped layer 41, and the first source / drain interconnect layer 42 is also formed in the vertical direction (e.g., Figure 2 (As shown in the Z direction) Extends upward to the top of the corresponding first embedded power layer 14 and is electrically connected to the first embedded power layer 14.

[0018] refer to Figure 3 , Figure 3 (a) is based on Figure 2 (a) is a sectional view. Figure 3 (b) is based on Figure 2(b) is a sectional view of (a), forming an isolation layer 17 on the first source-drain interconnection layer 42, the isolation layer 17 exposing the end of the second channel layer 22; forming a second source-drain doped layer 61 on the isolation layer 17 on both sides of the pseudo-gate structure 16, the second source-drain doped layer 61 being in contact with the end of the second channel layer 22 under the pseudo-gate structure 16; forming a second source-drain interconnection layer 62 on both sides of the pseudo-gate structure 16, the second source-drain interconnection layer 62 covering the second source-drain doped layer 61, the second source-drain interconnection layer 62 also extending in the longitudinal direction to the top of the corresponding second pre-embedded power supply layer 15 and being in electrical connection with the second pre-embedded power supply layer 15.

[0019] The second source-drain interconnection layer 62 extends downward from the side of the second source-drain doped layer 61, and since the first transistor and the second transistor are stacked one above the other, the second source-drain interconnection layer 62 also extends downward from the side of the first source-drain interconnection layer 42 and the first source-drain doped layer 41, so that when the second source-drain interconnection layer 62 is formed, the part of the second source-drain interconnection layer 62 that extends downward is likely to be too close to the first source-drain interconnection layer 61 or the first source-drain doped layer 41, thus causing the second source-drain interconnection layer 62 to be short-circuited with the first source-drain doped layer 41 or the first source-drain interconnection layer 42, and further affecting the working performance of the semiconductor structure.

[0020] To solve the technical problem, the embodiment of the present application provides a forming method of a semiconductor structure, a protection wall is formed on the side wall of the second pre-embedded power supply layer closest to the second source-drain doped layer, and then a second source-drain interconnection layer is formed to cover the second source-drain doped layer and the protection wall, the second source-drain interconnection layer extending in the longitudinal direction to the top of the corresponding second pre-embedded power supply layer and being in electrical connection with the second pre-embedded power supply layer, the protection wall being formed on the side wall of the second pre-embedded power supply layer closest to the second source-drain doped layer, so that when the second source-drain interconnection layer is in electrical connection with the second pre-embedded power supply layer, the second source-drain interconnection layer extends downward from the outside of the protection wall, thus increasing the distance between the part of the second source-drain interconnection layer that extends downward and the first source-drain doped layer or the first source-drain interconnection layer, reducing the probability that the second source-drain interconnection layer is in contact with the first source-drain doped layer or the first source-drain interconnection layer due to being too close to the first source-drain doped layer or the first source-drain interconnection layer when the second source-drain interconnection layer is formed, thus reducing the probability that the second source-drain interconnection layer is short-circuited with the first source-drain doped layer or the first source-drain interconnection layer, and further ensuring the working performance of the semiconductor structure.

[0021] In order to make the above objectives, characteristics and advantages of the present application more apparent and understandable, specific embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0022] Figures 4-5 is a structure schematic diagram of an embodiment of the semiconductor structure of the present application, Figure 4 is a top view of the gate structure and the source-drain doped layer, Figure 5 (a) is Figure 4 a sectional view based on the AA direction, Figure 5 (b) is Figure 4Sectional view based on the BB direction.

[0023] The semiconductor structure includes: a substrate 101, including device cell regions 101Q for forming a first transistor and a second transistor stacked sequentially from bottom to top; and a buried power layer (not shown) located in the device cell region 101Q in a second direction (e.g., Figure 4 The substrates 101 on both sides of the device cell region 101Q (as shown in the Y direction) include a first buried power layer 141 located on one side of the device cell region 101Q and a second buried power layer 151 located on the other side of the device cell region 101Q; a first transistor is located on the substrate 101 of the device cell region 101Q, and the first transistor includes components along a first direction (as shown in the Y direction). Figure 4 The first channel layer 211 extends (as shown in the X direction), the first gate structure 711 spans the first channel layer 211 and covers the top and sidewalls of the first channel layer 211, and the first source / drain doped layer 421 is located on the substrate 101 on both sides of the first gate structure 711. The first source / drain doped layer 421 is in contact with the end of the first channel layer 211 located below the first gate structure 711, and the second direction is perpendicular to the first direction; the first source / drain interconnect layer 421 covers the first source / drain doped layer 411, and the first source / drain interconnect layer 421 also extends from the side of the first source / drain doped layer 411 in the longitudinal direction (as shown in the X direction). Figure 5 (As shown in the Z-direction) Extends upward to the top of the corresponding first buried power layer 141 and is electrically connected to the first buried power layer 141; Isolation layer 171 is located on top of the first source-drain interconnect layer 421; Second transistor is stacked above the first transistor, the second transistor includes a second channel layer 221 extending along the first direction, a second gate structure 721 spanning the second channel layer 221 and covering the second channel layer 221, and a second source-drain doped layer 6 located on the isolation layer 171 on both sides of the second gate structure 721. 11. The second source / drain doped layer 611 is in contact with the end of the second channel layer 221 located below the second gate structure 721; the guard wall 311 is located on the sidewall of the second source / drain doped layer 611 closest to the second buried power layer 151; the second source / drain interconnect layer 621 covers the second source / drain doped layer 611 and the guard wall 311, and the second source / drain interconnect layer 611 also extends longitudinally from the side of the guard wall 311 to the top of the corresponding second buried power layer 151 and is electrically connected to the second buried power layer 151.

[0024] In this embodiment, the first transistor and the second transistor are stacked one on top of the other, which helps to save the area occupied by the semiconductor structure.

[0025] The semiconductor structure is a complementary field effect transistor structure, in which a PMOS transistor and an NMOS transistor stacked vertically to each other form a complementary device. The first transistor is a bottom transistor in the CFET structure, and the second transistor is a top transistor in the CFET structure. The channel conductivity types of the first transistor and the second transistor are different, and as an example, the first transistor is an NMOS transistor and the second transistor is a PMOS transistor. According to the structure type of the first transistor and the second transistor, the first transistor and the second transistor each include a fin field effect transistor (FinFET) or a gate-all-around (GAA) transistor. Specifically, the GAA transistor can be a horizontal nanosheet transistor. This embodiment takes the first transistor and the second transistor as examples of FinFETs.

[0026] The substrate 101 is used to provide a process platform for forming the semiconductor structure.

[0027] The substrate 101 includes a device unit region 101Q for forming the stacked first transistor and the second transistor.

[0028] In this embodiment, the substrate 101 includes a substrate 111, a bottom fin 121 protruding from the substrate 111 in the device unit region 101Q, and an isolation layer 131 located on the substrate 111 and surrounding the bottom fin 121.

[0029] In this embodiment, the material of the substrate 111 is silicon. In other embodiments, the material of the substrate can also be germanium, silicon germanium, silicon carbide, gallium arsenide, or other materials, and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates. As an example, the bottom fin 121 and the substrate 111 are in an integrated structure.

[0030] In this embodiment, the isolation layer 131 can be a shallow trench isolation structure (STI). The material of the isolation layer 131 is an insulating material. As an example, the material of the isolation layer 131 is silicon oxide.

[0031] The buried power rail (BPR) layer is used to electrically connect the first source-drain interconnection layer 421 and the second source-drain interconnection layer 621, and to load corresponding voltages for the first source-drain interconnection layer 421 and the second source-drain interconnection layer 621. The buried power rail layer includes an embedded power supply wiring (VDD) and an embedded ground wiring (VSS).

[0032] In this embodiment, the buried power rail layer is located in the substrate 111 and is covered by the isolation layer 131, so that the buried power rail layer is buried in the substrate, thereby achieving good isolation between the buried power rail layer and other film layers above the buried power rail layer.

[0033] In the first transistor, the first channel layer 211 is configured to provide a channel of the first transistor. In this embodiment, the first channel layer 211 is a first fin standing on the bottom fin 121.

[0034] In this embodiment, the material of the first channel layer 211 includes silicon, germanium, silicon germanium, or a group III-V semiconductor material. As an example, the material of the first channel layer 211 is silicon. In other embodiments, the material of the first channel layer is determined according to the type and performance of the first transistor.

[0035] The first gate structure 711 is configured to control the turn-on and turn-off of the channel of the first transistor.

[0036] The first gate structure 711 includes a gate dielectric layer (not shown) and a gate electrode layer (not shown) on the gate dielectric layer.

[0037] The gate dielectric layer is configured to isolate the gate electrode layer from the first channel layer 211 and the substrate 101.

[0038] The material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3. In this embodiment, the gate dielectric layer includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer includes a high-k dielectric material. Here, the high-k dielectric material refers to a dielectric material with a relative dielectric constant greater than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer includes HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3, etc.

[0039] It should be noted that the gate dielectric layer can also include a gate oxide layer between the high-k gate dielectric layer and the first channel layer 211. Specifically, the material of the gate oxide layer can be silicon oxide.

[0040] In this embodiment, the first gate structure 711 is a metal gate structure, and thus the material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC.

[0041] Specifically, the gate electrode layer includes a work function layer (not shown) and an electrode layer (not shown) on the work function layer. Here, the work function layer is configured to adjust the threshold voltage of the transistor, and the electrode layer is configured to lead out the electrical property of the metal gate structure.

[0042] In other embodiments, the gate electrode layer can also include only the work function layer.

[0043] In other embodiments, the first gate structure can also be a polysilicon gate structure according to process requirements.

[0044] The first source-drain doped layer 411 is used as a source region or a drain region of the first transistor.

[0045] Specifically, the doping type of the first source-drain doped layer 411 is the same as the channel conduction type of the corresponding first transistor. In the embodiment, the first transistor is an NMOS transistor, and the doping ions in the first source-drain doped layer 411 are N-type ions, including P ions, As ions or Sb ions.

[0046] In the second transistor, the second channel layer 221 is used to provide a channel of the second transistor. In the embodiment, the second channel layer 221 is a second fin.

[0047] In the embodiment, the material of the second channel layer 221 includes silicon, germanium, silicon germanium or a III-V semiconductor material. As an example, the material of the second channel layer 221 is silicon. In other embodiments, the material of the second channel layer is determined according to the type and performance of the second transistor.

[0048] The second gate structure 721 is used to control the opening and closing of the channel of the second transistor.

[0049] The second gate structure 721 includes a gate dielectric layer (not shown) and a gate electrode layer (not shown) located on the gate dielectric layer.

[0050] The gate dielectric layer is used to isolate the gate electrode layer from the second channel layer 221 and the gate electrode layer from the first gate structure 711.

[0051] For specific description of the second gate structure 721, reference can be made to the related description of the aforementioned first gate structure 711, which will not be repeated here.

[0052] The second source-drain doped layer 611 is used as a source region or a drain region of the second transistor.

[0053] Specifically, the doping type of the second source-drain doped layer 611 is the same as the channel conduction type of the corresponding second transistor. In the embodiment, the second transistor is a PMOS transistor, and the doping ions in the second source-drain doped layer 611 are P-type ions, including B ions, Ga ions or In ions.

[0054] In the embodiment, the semiconductor structure further includes a first interlayer dielectric layer 501 located on the substrate 101 and covering the sidewalls of the first source-drain interconnection layer 421, the sidewalls of the first gate structure 711 and the sidewalls of the second gate structure 721.

[0055] The first interlayer dielectric layer 501 is used to isolate adjacent devices, and also provides a process base for forming the first gate structure 711, the second gate structure 721, the first source-drain interconnection layer 421, and the second source-drain interconnection layer 621.

[0056] The material of the first interlayer dielectric layer 501 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.

[0057] The first source-drain interconnection layer 421 is used to electrically connect the first pre-embedded power supply layer 141 and the first source-drain doped layer 411, and to apply a voltage to the first source-drain doped layer 411.

[0058] The first source-drain interconnection layer 421 is electrically connected to the pre-embedded power supply layer (not shown) on one side of the device unit area 101Q. In this embodiment, according to the design of the circuit layout, the first source-drain interconnection layer 421 extends to the top of the corresponding first pre-embedded power supply layer 141 and is electrically connected to the first pre-embedded power supply layer 141. Specifically, the first source-drain interconnection layer 421 extends from the side of the first source-drain doped layer 411 facing the first pre-embedded power supply layer 141 to the top of the first pre-embedded power supply layer 141 in the longitudinal direction.

[0059] In other embodiments, the first source-drain interconnection layer can also extend to the top of the second pre-embedded power supply layer and be electrically connected to the second pre-embedded power supply layer according to process requirements.

[0060] In this embodiment, the first source-drain interconnection layer 421 includes a first lateral portion 441 extending in the second direction, located in the first interlayer dielectric layer 501, and covering the first source-drain doped layer 411; and a first longitudinal portion 431 extending in the longitudinal direction, located in the base 101 on the side of the first source-drain doped layer 411, with the top of the first longitudinal portion 431 connected to the bottom of the first lateral portion 441 and the bottom of the first longitudinal portion 431 connected to the top of the first pre-embedded power supply layer 141.

[0061] The first lateral portion 441 electrically connects the first source-drain doped layer 411, the first longitudinal portion 431 is located between the bottom of the first lateral portion 441 and the top of the first pre-embedded power supply layer 141, the first longitudinal portion 431 electrically connects the first lateral portion 441 and the first pre-embedded power supply layer 141, and the first pre-embedded power supply layer 141 is located in the base 101, so that the first source-drain interconnection layer 421 is electrically connected to the first pre-embedded power supply layer 141 through the first longitudinal portion 431 extending in the longitudinal direction.

[0062] To this end, in this embodiment, the first source-drain interconnection layer 421 penetrates the isolation layer 131 on the top of the first pre-embedded power supply layer 141 in the longitudinal direction.

[0063] In this embodiment, the material of the first source-drain interconnection layer 421 includes W or Co.

[0064] W or Co is a metal material, which has good electrical conductivity and is conducive to the electrical connection between the first source-drain doped layer 411 and the first pre-embedded power supply layer 141.

[0065] In this embodiment, the isolation layer 171 is located on the top of the first source-drain interconnection layer 421, and is used to isolate the first source-drain interconnection layer 421 and the second source-drain doped layer 611 located on the isolation layer 171, and to isolate the first source-drain interconnection layer 421 and the second source-drain interconnection layer 621 located on the isolation layer 171.

[0066] In this embodiment, the first source-drain interconnection layer 421 is located in the first interlayer dielectric layer 501, and correspondingly, the isolation layer 171 is located in the first interlayer dielectric layer 501 and covers the top of the first source-drain interconnection layer 421.

[0067] In this embodiment, the material of the isolation layer 171 includes SiN, SiON, SiOCN, SiOC or SiOCH.

[0068] SiN, SiON, SiOCN, SiOC or SiOCH has good insulation and can have good isolation effect.

[0069] The second source-drain interconnection layer 621 is used to electrically connect the second pre-embedded power supply layer 151 and the second source-drain doped layer 611, and to apply voltage to the second source-drain doped layer 611.

[0070] The second source-drain interconnection layer 621 is electrically connected with the pre-embedded power supply layer (not labeled) on the other side of the device unit area 101Q. In this embodiment, according to the design of the circuit layout, the second source-drain interconnection layer 621 extends to the top of the corresponding second pre-embedded power supply layer 151 and is electrically connected with the second pre-embedded power supply layer 151. Specifically, the second source-drain interconnection layer 621 extends from the side of the second source-drain doped layer 611 facing the second pre-embedded power supply layer 151 to the top of the second pre-embedded power supply layer 151 in the longitudinal direction.

[0071] In other embodiments, according to the process requirements, the second source-drain interconnection layer can also extend to the top of the first pre-embedded power supply layer and be electrically connected with the first pre-embedded power supply layer, and correspondingly, the protection wall is located on the sidewall of the second source-drain doped layer closest to the first pre-embedded power supply layer and extends downward to cover the sidewall of the first source-drain doped layer.

[0072] In this embodiment, the protection wall 311 covers the sidewall of the second source-drain doped layer 611 closest to the second pre-embedded power supply layer 151, and therefore, the second source-drain interconnection layer 621 correspondingly covers the sidewall of the protection wall 311.

[0073] Therefore, the second source-drain interconnection layer 621 extends downward along the longitudinal direction from the side of the protection wall 311 opposite to the second source-drain doped layer 611 to the top of the second pre-embedded power supply layer 151.

[0074] In this embodiment, the second source-drain interconnection layer 621 includes a second lateral part 641 extending along the second direction, located in the first interlayer dielectric layer 501, and covering the second source-drain doped layer 611 and the protection wall 311; and a second longitudinal part 631 extending along the longitudinal direction, located in the first interlayer dielectric layer 501 and the substrate 101 at the bottom of the second lateral part 641, and connected to the top of the second pre-embedded power supply layer 151 at the bottom.

[0075] The second lateral part 641 electrically connects the second source-drain doped layer 611, and the second longitudinal part 631 is located between the bottom of the second lateral part 641 and the top of the second pre-embedded power supply layer 151, and electrically connects the second lateral part 641 and the second pre-embedded power supply layer 151, which is located in the substrate 101. Therefore, the second source-drain interconnection layer 621 is electrically connected to the second pre-embedded power supply layer 151 through the second longitudinal part 631 extending along the longitudinal direction.

[0076] To this end, in this embodiment, the second source-drain interconnection layer 621 penetrates the isolation layer 131 at the top of the second pre-embedded power supply layer 151 and the first interlayer dielectric layer 501 along the longitudinal direction.

[0077] In this embodiment, the semiconductor structure further includes a second interlayer dielectric layer 521 located between the second lateral part 641 and the first interlayer dielectric layer 501, and at the top of the isolation layer 171.

[0078] The second interlayer dielectric layer 521 is used to isolate adjacent devices, and is also used to provide a process basis for forming the second gate structure 721 and the second source-drain interconnection layer 621.

[0079] The material of the second interlayer dielectric layer 521 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.

[0080] The protection wall 311 is used to protect the sidewall of the first source-drain doped layer 411.

[0081] In the semiconductor structure provided by the embodiment, the first source-drain interconnection layer 421 extends to the top of the corresponding first pre-buried power supply layer 141 in the longitudinal direction and is electrically connected with the first pre-buried power supply layer 141, the second source-drain interconnection layer 621 covers the protection wall 311 and extends to the top of the corresponding second pre-buried power supply layer 151 in the longitudinal direction and is electrically connected with the second pre-buried power supply layer 151, the protection wall 311 is located on the sidewall of the second source-drain doped layer 611 closest to the second pre-buried power supply layer 151 and extends downward to cover the sidewall of the first source-drain doped layer 411, when the second source-drain interconnection layer 621 is electrically connected with the second pre-buried power supply layer 151, the second source-drain interconnection layer 621 extends downward from the outside of the protection wall 311, thereby increasing the distance between the part of the second source-drain interconnection layer 621 extending downward and the first source-drain doped layer 411 or the first source-drain interconnection layer 421, reducing the probability that the second source-drain interconnection layer 621 contacts the first source-drain doped layer 411 or the first source-drain interconnection layer 421 due to the too close distance, thereby reducing the probability that the second source-drain interconnection layer 621 is short-circuited with the first source-drain doped layer 411 or the first source-drain interconnection layer 421, and further ensuring the working performance of the semiconductor structure.

[0082] In the embodiment, in order to increase the distance between the second longitudinal part 631 and the first source-drain doped layer 411 and the first source-drain interconnection layer 421, further reduce the probability that the second source-drain interconnection layer 621 contacts the first source-drain doped layer 411 or the first source-drain interconnection layer 421 due to the too close distance, thereby further reduce the probability that the second source-drain interconnection layer 621 is short-circuited with the first source-drain doped layer 411 or the first source-drain interconnection layer 421, the second longitudinal part 631 is spaced apart from the protection wall 311.

[0083] In the embodiment, the forming step of the protection wall 311 includes: forming a protection material layer covering the second source-drain doped layer 611; and then removing the protection material layer located on the top of the second source-drain doped layer 611, and retaining the protection material layer located on the sidewall of the second source-drain doped layer 611 as the protection wall 311. Therefore, the protection wall 311 is also located on the remaining sidewall of the second source-drain doped layer 611.

[0084] In the embodiment, the material of the protection wall 311 is SiN.

[0085] SiN has high hardness, which is beneficial to better maintain the sidewall of the first source-drain doped layer 411 and the second source-drain doped layer 621 during the manufacturing process, and SiN has good insulation, which can better isolate the second source-drain interconnection layer 621 from the first source-drain doped layer 411 or the first source-drain interconnection layer 421.

[0086] It should be noted that the width of the protection wall 311 along the second direction should not be too large or too small. If the width of the protection wall 311 along the second direction is too large, the second source-drain interconnection layer 621 extends too far along the second direction, which is easy to cause the overall volume of the semiconductor structure to be too large, and the occupation area of the semiconductor structure is wasted. If the width of the protection wall 311 along the second direction is too small, it is easy to cause the second source-drain interconnection layer 621 to extend too small along the second direction, thereby easily causing the second source-drain interconnection layer 621 to be too close to the first source-drain doped layer 411 and the first source-drain interconnection layer 421 to contact, affecting the working performance of the semiconductor structure. Therefore, in the embodiment, the width of the protection wall along the second direction is 2nm to 10nm.

[0087] In the embodiment, the semiconductor structure further comprises a gate side wall 321 located on the side wall of the second gate structure 721.

[0088] The gate side wall 321 is used to protect the side wall of the second gate structure 721, and plays an isolating role for the second gate structure 721 and the second source-drain doped layer 611 and the second source-drain interconnection layer 621.

[0089] The material of the gate side wall 321 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbon nitride, silicon carbon nitrogen oxide, silicon nitrogen oxide, boron nitride and boron carbon nitride.

[0090] In the embodiment, the semiconductor structure further comprises an inner side wall (not marked) located on the side wall of the first gate structure 711, which is used to protect the side wall of the first gate structure 711, and plays an isolating role for the first gate structure 711 and the first source-drain doped layer 411 and the first source-drain interconnection layer 421.

[0091] Figures 6-24 is the structure schematic diagram corresponding to each step in an embodiment of the forming method of the semiconductor structure of the application.

[0092] Combined with reference Figure 6 and Figure 7 , Figure 6 is a cross-sectional view of the laminated structure and the dummy gate structure, Figure 7 (a) is Figure 6 is a cross-sectional view along the AA direction, Figure 7 (b) is Figure 6 is a cross-sectional view along the BB direction, a substrate 100 is provided, including a device unit area 100Q for forming a first transistor and a second transistor stacked from bottom to top in sequence. The substrate 100 of the device unit area 100Q is formed with a first gate structure 711 and a second gate structure 721 along a first direction (such as a horizontal direction) and a second direction (such as a vertical direction) perpendicular to the first direction. Figure 9The stack structure 200 extends in the X direction (as indicated by the arrow in the X direction), and includes a first channel layer 210, a sacrificial layer 230 located on the first channel layer 210, and a second channel layer 220 located on the sacrificial layer 230. The device unit region 100Q is located between the first channel layer 210 and the second channel layer 220 in the Y direction (as indicated by the arrow in the Y direction), and the first pre-embedded power supply layer 140 and the second pre-embedded power supply layer 150 are respectively formed in the substrate 100 on both sides of the device unit region 100Q in the Y direction. The Y direction is perpendicular to the X direction. The substrate 100 further includes a dummy gate structure 160 crossing the stack structure 200, and the dummy gate structure 160 covers part of the sidewall and part of the top of the stack structure 200. Figure 9 The stack structure 200 extends in the X direction (as indicated by the arrow in the X direction), and includes a first channel layer 210, a sacrificial layer 230 located on the first channel layer 210, and a second channel layer 220 located on the sacrificial layer 230. The device unit region 100Q is located between the first channel layer 210 and the second channel layer 220 in the Y direction (as indicated by the arrow in the Y direction), and the first pre-embedded power supply layer 140 and the second pre-embedded power supply layer 150 are respectively formed in the substrate 100 on both sides of the device unit region 100Q in the Y direction. The Y direction is perpendicular to the X direction. The substrate 100 further includes a dummy gate structure 160 crossing the stack structure 200, and the dummy gate structure 160 covers part of the sidewall and part of the top of the stack structure 200.

[0093] In this embodiment, the first transistor and the second transistor are stacked vertically, which is beneficial to saving the area occupied by the semiconductor structure.

[0094] The semiconductor structure is a complementary field effect transistor (CFET) structure. In the CFET structure, a PMOS transistor and an NMOS transistor are vertically stacked and form a complementary device. The first transistor is a bottom transistor in the CFET structure, and the second transistor is a top transistor in the CFET structure. The channel conductivity type of the first transistor is different from that of the second transistor. As an example, the first transistor is an NMOS transistor, and the second transistor is a PMOS transistor. According to the structure type of the first transistor and the second transistor, the first transistor and the second transistor each include a fin field effect transistor (FinFET) or a gate-all-around (GAA) transistor. Specifically, the GAA transistor can be a horizontal nanosheet transistor. In this embodiment, the first transistor and the second transistor are both FinFETs.

[0095] The substrate 100 is used to provide a process platform for forming the semiconductor structure.

[0096] The substrate 100 includes the device unit region 100Q, which is used to form the stacked first transistor and the second transistor.

[0097] In this embodiment, the substrate 101 includes a substrate 110, a bottom fin 120 protruding from the substrate 110 in the device unit region 100Q, and an isolation layer 130 located on the substrate 110 and surrounding the bottom fin 120.

[0098] In this embodiment, the material of the substrate 110 is silicon. In other embodiments, the material of the substrate can also be germanium, silicon germanium, silicon carbide, gallium arsenide, or other materials. The substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates. As an example, the bottom fin 120 and the substrate 110 are in an integrated structure.

[0099] In this embodiment, the isolation layer 130 can be a shallow trench isolation (STI) structure. The material of the isolation layer 130 is an insulating material. As an example, the material of the isolation layer 130 is silicon oxide.

[0100] The substrate 100 on both sides of the device unit region 100Q is formed with a pre-embedded power supply layer, which is a first pre-embedded power supply layer 140 and a second pre-embedded power supply layer 150, respectively.

[0101] The pre-embedded power supply layer is used for subsequent electrical connection of the first source-drain interconnection layer and the second source-drain interconnection layer, respectively, and loading of corresponding voltages for the first source-drain interconnection layer and the second source-drain interconnection layer. The pre-embedded power supply layer includes an embedded power supply wiring (VDD) and an embedded ground wiring (VSS).

[0102] In this embodiment, according to the design of the circuit layout, the first pre-embedded power supply layer 140 is subsequently electrically connected with the first source-drain interconnection layer, and the second pre-embedded power supply layer 150 is subsequently electrically connected with the second source-drain interconnection layer. In other embodiments, according to process requirements, the first pre-embedded power supply layer can also be electrically connected with the second source-drain interconnection layer, and the second pre-embedded power supply layer can also be electrically connected with the first source-drain interconnection layer.

[0103] In this embodiment, the first pre-embedded power supply layer 140 and the second pre-embedded power supply layer 150 are located in the substrate 110 and covered by the isolation layer 130, so that the pre-embedded power supply layer is buried in the substrate 100, and the pre-embedded power supply layer has a good isolation effect with other film layers above the pre-embedded power supply layer.

[0104] The stack structure 200 is used to form the first channel layer 210 and the second channel layer 220 which are spaced apart in the longitudinal direction.

[0105] In this embodiment, a plurality of stack structures 200 can be formed in a plurality of regions at the same time, which simplifies the process flow, improves the process efficiency, and saves the process cost.

[0106] In this embodiment, the stack structure 200 is formed in the same process as the bottom fin 120, and for this reason, the stack structure 200 is formed on the bottom fin 120.

[0107] The first channel layer 210 is used to provide a channel of the first transistor.

[0108] In this embodiment, the first channel layer 210 is a first fin which stands on the bottom fin 120.

[0109] In this embodiment, the material of the first channel layer 210 includes silicon, germanium, silicon germanium, or a group III-V semiconductor material. As an example, the material of the first channel layer 210 is silicon. In other embodiments, the material of the first channel layer is determined according to the type and performance of the first transistor.

[0110] The second channel layer 220 is used to provide a channel of the second transistor.

[0111] In this embodiment, the second channel layer 220 is a second fin.

[0112] In this embodiment, the material of the second channel layer 220 includes silicon, germanium, silicon germanium, or a group III-V semiconductor material. As an example, the material of the second channel layer 220 is silicon. In other embodiments, the material of the second channel layer is determined according to the type and performance of the second transistor.

[0113] The sacrificial layer 230 is used to set the spacing between the first channel layer 210 and the second channel layer 220 for subsequent formation of the stacked first transistor and second transistor, and to occupy a space position for subsequent formation of the first gate structure.

[0114] In this embodiment, the material of the sacrificial layer 230 includes silicon germanium.

[0115] Silicon germanium and silicon can form a large etching selectivity ratio, which is beneficial for subsequent removal of the sacrificial layer 230 and reduces damage to the first channel layer 210 and the second channel layer 220.

[0116] In other embodiments, according to the materials of the first channel layer and the second channel layer, the sacrificial layer can be selected to have a suitable material with etching selectivity ratio with the channel layer, so as to reduce damage to the first channel layer and the second channel layer when the sacrificial layer is subsequently removed.

[0117] The dummy gate structure 160 is used to occupy a space position for subsequent formation of the second gate structure.

[0118] Specifically, the dummy gate structure 260 is a laminated structure including a dummy gate oxide layer (not shown) and a dummy gate layer (not shown) covering the dummy gate oxide layer.

[0119] As an example, the material of the dummy gate oxide layer is silicon oxide, and the material of the dummy gate layer is polysilicon.

[0120] In this embodiment, the sidewall of the dummy gate structure 160 is further formed with a gate sidewall (not labeled).

[0121] The gate sidewall is used to protect the sidewall of the dummy gate structure 160, so as to ensure the formation quality of the subsequent second gate structure, and to protect the sidewall of the second gate structure after the second gate structure is formed.

[0122] The material of the gate sidewall includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbon nitride, silicon carbon nitrogen oxide, silicon nitrogen oxide, boron nitride, and boron carbon nitride.

[0123] In combination with reference to Figures 8-13 , Figures 8-12 based on Figure 7 (b) is a sectional view, Figure 13 (a) is a sectional view based on Figure 7 (a), Figure 13(b) is based on Figure 7 (b) is based on

[0124] The first source-drain doped layer 410 is used as a source region or a drain region of the first transistor.

[0125] The end of the first channel layer 210 refers to an end of the first channel layer 210 along the first direction. In the source-drain recess 240, the first source-drain doped layer 410 is epitaxially grown on the basis of the first channel layer 210. Therefore, in the step of forming the first source-drain doped layer 410, the first source-drain doped layer 410 is in contact with the end of the first channel layer 210.

[0126] The doping type of the first source-drain doped layer 410 is the same as the channel conduction type of the corresponding transistor. Specifically, the first transistor is an NMOS transistor, and the doping ions in the first source-drain doped layer 410 are N-type ions, including P ions, As ions, or Sb ions.

[0127] Specifically, referring to Figure 8 The step of forming the first source-drain doped layer 410 includes forming a source-drain recess 240 in the stack structure 200 on both sides of the dummy gate structure 160.

[0128] The source-drain recess 240 provides a spatial position for forming the first source-drain doped layer 410 and the first source-drain interconnection layer.

[0129] In this embodiment, an anisotropic etching process is used to remove the stack structure 200 on both sides of the dummy gate structure 160.

[0130] The anisotropic etching process is an anisotropic dry etching process. By selecting the anisotropic dry etching process, it is beneficial to reduce the damage to the bottom substrate 100 of the source-drain recess 240. At the same time, the anisotropic dry etching process has better directionality, which is beneficial to make the removal of the source-drain recess 240 have better morphology quality and size precision.

[0131] In this embodiment, after forming the source-drain recess 240, an inner sidewall (not labeled) is formed on the sidewall of the sacrificial layer 230 through the source-drain recess 240, which is used to protect the sidewall of the sacrificial layer 230, thereby ensuring the formation quality of the subsequent first gate structure, and after forming the first gate structure, the sidewall of the first gate structure is protected.

[0132] In combination with reference to Figures 9-13 The sacrificial sidewall 310 is formed to cover the end of the second channel layer 220 exposed by the source-drain recess 240.

[0133] The sacrificial side wall 310 is used to protect the sidewall of the second channel layer 220 in the process of forming the first source-drain doped layer 410, so that the first source-drain doped layer 410 will not be formed by mistake on the sidewall of the second channel layer 220.

[0134] In this embodiment, the sacrificial side wall 310 will be subsequently removed to form the second source-drain doped layer, so the material of the sacrificial side wall 310 needs to be selected to have a large etching selectivity with the second channel layer 220. For this purpose, in this embodiment, the material of the sacrificial side wall 310 includes SiCO.

[0135] Specifically, the step of forming the sacrificial side wall 310 covering the sidewall of the second channel layer 220 includes: forming a filling layer 180 covering the end of the first channel layer 210 on the substrate 100.

[0136] The filling layer 180 is used to occupy the space on the side of the end of the first channel layer 210, so that the sacrificial side wall 310 will not be formed on the end of the first channel layer 210, thereby facilitating the smooth formation of the first source-drain doped layer 410.

[0137] In this embodiment, the filling layer 180 is formed by a chemical vapor deposition (CVD) process.

[0138] The filling property of the chemical vapor deposition process is good, which is conducive to forming a filling layer 180 with a relatively uniform film layer.

[0139] In this embodiment, the filling layer 180 also needs to be removed subsequently, so the material of the filling layer 180 needs to be selected to be easily removed. For this purpose, in this embodiment, the material of the filling layer 180 includes an advanced patterning film (APF) material, which is easy to remove the filling layer 180 subsequently and is conducive to reducing damage to the first channel layer 210 in the removal process.

[0140] Reference Figure 10 The sacrificial side wall material layer 300 is formed on the top of the filling layer 180, the top and sidewall of the dummy gate structure 160 which is higher than the top of the filling layer 180, and the sidewall of the laminated structure 200.

[0141] The sacrificial side wall material layer 300 is used to directly form the sacrificial side wall 310.

[0142] In this embodiment, the sacrificial side wall material layer 300 is formed by an atomic layer deposition process.

[0143] The thickness uniformity of the sacrificial sidewall material layer 300 formed by the atomic layer deposition process is good, and the sacrificial sidewall material layer 300 has good step coverage capability, so that the sacrificial sidewall material layer 300 can well conformally cover the top and sidewall of the dummy gate structure 160 and the sidewall of the stack structure 200.

[0144] Correspondingly, in the embodiment, the material of the sacrificial sidewall material layer 300 includes SiCO.

[0145] Referring to Figure 11 , the sacrificial sidewall material layer 300 on the top of the filling layer 180 and the top of the dummy gate structure 160 is removed, and the sacrificial sidewall material layer 300 at the end of the second channel layer 220 is reserved as a sacrificial sidewall 310.

[0146] Correspondingly, in the embodiment, the sacrificial sidewall 310 also covers the sidewall of the dummy gate structure 160.

[0147] In the embodiment, the anisotropic etching process is used to remove the sacrificial sidewall material layer 300 on the top of the filling layer 180 and the top of the dummy gate structure 160.

[0148] The anisotropic etching process is an anisotropic dry etching process. By selecting the anisotropic dry etching process, damage to the dummy gate structure 160 can be reduced.

[0149] Referring to Figure 12 , after the sacrificial sidewall 310 is formed, the filling layer 180 is removed.

[0150] The removal of the filling layer 180 exposes the sidewall of the first channel layer 210, preparing for the formation of the first source / drain doped layer 410.

[0151] In the embodiment, the isotropic etching process is used to remove the filling layer 180.

[0152] The isotropic etching process includes an isotropic wet etching process. The isotropic wet etching process has relatively low cost and simple operation steps, and can also achieve a large etching selectivity, which is beneficial to reducing damage to the first channel layer 210 in the process of removing the filling layer 180.

[0153] Referring to Figure 13 , after the sacrificial sidewall 310 is formed, the first source / drain doped layer 410 is formed in a partial depth region of the source / drain recess 240, and the first source / drain doped layer 410 covers the end of the first channel layer 210.

[0154] In the source-drain recess 240, the first source-drain doped layer 410 is epitaxially grown with the first channel layer 210 as the epitaxial growth base, and the end of the second channel layer 220 is covered by the sacrificial side wall 310, so that the first source-drain doped layer 410 will not grow on the end of the second channel layer 220.

[0155] In this embodiment, after the first source-drain doped layer 410 is formed, before the first source-drain interconnection layer is subsequently formed, it further includes: removing the sacrificial side wall 310.

[0156] The sacrificial side wall 310 is removed to expose the end of the second channel layer 220, preparing for the subsequent formation of the second source-drain doped layer.

[0157] Reference Figure 14 , Figure 14 (a) is a cross-sectional view based on Figure 13 (a), Figure 14 (b) is a cross-sectional view based on Figure 13 (b),After the first source-drain doped layer 410 is formed, before the first source-drain interconnection layer is subsequently formed, it further includes: forming a first interlayer dielectric layer 500 on the substrate 100, covering the first source-drain doped layer 410, and the first interlayer dielectric layer 500 also covers the sidewall of the dummy gate structure 160.

[0158] The first interlayer dielectric layer 500 serves to isolate adjacent devices, and the first interlayer dielectric layer 500 also serves as a process basis for the subsequent formation of the first gate structure, the second gate structure, the first source-drain interconnection layer, and the second source-drain interconnection layer.

[0159] The material of the first interlayer dielectric layer 500 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.

[0160] Reference Figures 15-16 , Figure 15 (a) is a cross-sectional view based on Figure 14 (a), Figure 15 (b) is a cross-sectional view based on Figure 14 (b), Figure 16 (a) is a cross-sectional view based on Figure 15 (a), Figure 16 (b) is a cross-sectional view based on Figure 15 (b), The first source-drain interconnection layer 420 is formed on both sides of the dummy gate structure 160, covering the first source-drain doped layer 410, and the first source-drain interconnection layer 420 also extends from the side of the first source-drain doped layer 410 to the top of the corresponding first pre-embedded power supply layer 140 in the longitudinal direction (as shown in the Z direction in FIG. 12), and is electrically connected with the first pre-embedded power supply layer 140. Figure 16

[0161] The first source-drain interconnection layer 420 is used to electrically connect the first pre-embedded power supply layer 140 and the first source-drain doped layer 410, and to apply voltage to the first source-drain doped layer 410.

[0162] In this embodiment, according to the design of the circuit layout, the first source-drain interconnection layer 420 extends to the top of the corresponding first pre-embedded power supply layer 140 and is electrically connected to the first pre-embedded power supply layer 140. In other embodiments, according to the process requirements, the first source-drain interconnection layer can also extend to the top of the second pre-embedded power supply layer and be electrically connected to the second pre-embedded power supply layer.

[0163] In this embodiment, the material of the first source-drain interconnection layer 420 includes W or Co.

[0164] W or Co is a metal material, which has good electrical conductivity and is conducive to better electrical connection between the first source-drain doped layer 410 and the first pre-embedded power supply layer 140.

[0165] Specifically, referring to Figure 15 , the step of forming the first source-drain interconnection layer 420 includes: forming an interconnection trench 510 located in the first interlayer dielectric layer 500 and extending in the second direction on both sides of the dummy gate structure 160, and a first interconnection via hole 540 located on the side of the first source-drain doped layer 410, the top of the first interconnection via hole 540 being in communication with the bottom of the interconnection trench 510, the interconnection trench 510 exposing the first source-drain doped layer 410, and the first interconnection via hole 540 exposing the top of the first pre-embedded power supply layer 140.

[0166] The interconnection trench 510 and the first interconnection via hole 540 provide a spatial position for forming the first source-drain interconnection layer 420, and the interconnection trench 510 exposes the first source-drain doped layer 410, so that the first source-drain interconnection layer 420 formed can be in contact with the first source-drain doped layer 410.

[0167] In this embodiment, the first pre-embedded power supply layer 140 is located in the substrate 100, and the first interconnection via hole 540 is located on the first pre-embedded power supply layer 140, so that the first pre-embedded power supply layer 140 is exposed by forming the first interconnection via hole 540 extending longitudinally, so that the first source-drain interconnection layer 420 can be in contact with the first pre-embedded power supply layer 140.

[0168] In this embodiment, the interconnection trench 510 extends in the second direction and extends above the top of the first pre-embedded power supply layer 140, so that the first source-drain interconnection layer 420 formed can extend longitudinally to the top of the first pre-embedded power supply layer 140.

[0169] In this embodiment, the first interconnection trench 510 is formed by patterning the first interlayer dielectric layer 500 first, and then the first interconnection via hole 540 is formed by patterning the isolation layer 130.

[0170] In the embodiment, the first interlayer dielectric layer 500 is patterned by an anisotropic etching process.

[0171] The anisotropic etching process includes an isotropic dry etching process. The isotropic dry etching process can better control process parameters, has higher process controllability, is easy to obtain more accurate pattern transfer, and can achieve a larger etching selectivity by controlling process parameters, which is conducive to reducing damage to the first source-drain doped layer 410 in the process of removing part of the first interlayer dielectric layer 500.

[0172] In the embodiment, the isolation layer 130 is patterned by an anisotropic dry etching process.

[0173] In the embodiment, the isolation layer 130 is patterned by an anisotropic dry etching process. By selecting an anisotropic dry etching process, damage to the first embedded power supply layer 140 can be reduced. In addition, the anisotropic dry etching process has directionality, which is conducive to obtaining better topography quality and size accuracy of the first interconnection via hole.

[0174] Reference Figure 15 In the embodiment, after the interconnection trench 510 is formed, the first interlayer dielectric layer 500 also covers the top and sidewall of the dummy gate structure 160, which is conducive to protecting the sidewall and top of the dummy gate structure 160 during the formation of the first source-drain interconnection layer 420, and lays a foundation for the subsequent formation of the second gate structure.

[0175] In other embodiments, according to process requirements, the first interlayer dielectric layer covering the top and sidewall of the dummy gate structure can also be completely removed.

[0176] Reference Figure 16 The first source-drain interconnection layer 420 covering the first source-drain doped layer 410 is formed in part of the depth region of the interconnection trench 510, and the first source-drain interconnection layer 420 also fills the first interconnection via hole 540.

[0177] The first source-drain interconnection layer 420 is in contact with the first embedded power supply layer 140 by filling the first interconnection via hole 540, so that the first source-drain interconnection layer 420 is electrically connected to the first embedded power supply layer 140.

[0178] To this end, in the embodiment, the first source-drain interconnection layer 420 longitudinally penetrates the isolation layer 130 on the top of the first embedded power supply layer 140.

[0179] Reference Figure 17 , Figure 17 (a) is a sectional view based on Figure 16 (a), Figure 17 (b) is a sectional view based on Figure 16(b) is a sectional view of (a), forming an isolation layer 170 on the first source-drain interconnect layer 420, the isolation layer 170 exposing the end of the second channel layer 220.

[0180] The end of the second channel layer 220 refers to the end of the second channel layer 220 along the first direction.

[0181] The isolation layer 170 is used to isolate the first source-drain interconnect layer 420 and the second source-drain doped layer formed subsequently on the isolation layer 170, and is also used to isolate the first source-drain interconnect layer 420 and the second source-drain interconnect layer formed subsequently on the isolation layer 170.

[0182] The isolation layer 170 exposes the end of the second channel layer 220, which is beneficial for the subsequent formation of the second source-drain doped layer in contact with the end of the second channel layer 220.

[0183] In this embodiment, the first source-drain interconnect layer 420 is formed in the interconnection trench 510, and accordingly, the isolation layer 170 is formed on the top of the first source-drain interconnect layer 420 exposed by the first opening 510.

[0184] In this embodiment, the material of the isolation layer 170 includes SiN, SiON, SiOCN, SiOC, or SiOCH.

[0185] SiN, SiON, SiOCN, SiOC, or SiOCH has good insulating properties and can achieve good isolation effect.

[0186] Specifically, the step of forming the isolation layer 170 on the top of the first source-drain interconnect layer 420 exposed by the interconnection trench 510 includes: forming an isolation material layer (not shown) covering the bottom and sidewall of the interconnection trench 510 and the top of the first interlayer dielectric layer 500; removing the isolation material layer located on the sidewall of the interconnection trench 510 and the top of the first interlayer dielectric layer 500, and retaining the isolation material layer located on the top of the first source-drain interconnect layer 420 exposed by the interconnection trench 510 as the isolation layer 170.

[0187] Reference Figure 18 , Figure 18 (a) is based on Figure 17 (a) is a sectional view of (a), Figure 18 (b) is based on Figure 17 (b) is a sectional view of (a), after forming the isolation layer 170, before subsequently forming the second source-drain doped layer, further comprising: forming a second interlayer dielectric layer 520 in the remaining space of the interconnection trench 510.

[0188] The second interlayer dielectric layer 520 is used to isolate adjacent devices, and the second interlayer dielectric layer 520 is also used to provide a process basis for the subsequent formation of the second gate structure and the second source-drain interconnect layer.

[0189] The material of the second interlayer dielectric layer 520 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.

[0190] Reference Figure 19 , Figure 19 (a) is based on Figure 18 (a) is a sectional view, Figure 19 (b) is based on Figure 18 (b) is a sectional view, on both sides of the dummy gate structure 160, the first interlayer dielectric layer 500 located on top of the second embedded power supply layer 150 and higher than the top surface of the first source-drain interconnection layer 420, and the part of the second interlayer dielectric layer 520 in contact with the first interlayer dielectric layer 500 are removed, exposing the end of the second channel layer 220.

[0191] On both sides of the dummy gate structure 160, the first interlayer dielectric layer 500 located on top of the second embedded power supply layer 150 and higher than the top surface of the first source-drain interconnection layer 420, and the part of the second interlayer dielectric layer 520 in contact with the first interlayer dielectric layer 500 are removed, forming an opening 590 to provide a spatial position for the subsequent formation of the second source-drain doped layer and the second source-drain interconnection layer, and the opening 590 exposes the end of the second channel layer 220, preparing for the subsequent formation of the second source-drain doped layer.

[0192] In this embodiment, an anisotropic etching process is used to remove the first interlayer dielectric layer 500 located on top of the second embedded power supply layer 150 and higher than the top surface of the first source-drain interconnection layer 420, and the part of the second interlayer dielectric layer 520 in contact with the first interlayer dielectric layer 500.

[0193] The anisotropic etching process includes an anisotropic dry etching process, which can better control the process parameters, has higher process controllability, is easy to obtain more accurate pattern transfer, and can also achieve a larger etching selectivity by controlling the process parameters, which is conducive to reducing damage to the second channel layer 220 during etching.

[0194] In this embodiment, the opening 590 extends along the second direction and extends above the top of the second embedded power supply layer 150, so that the second source-drain interconnection layer formed subsequently can extend vertically to the top of the second embedded power supply layer 150.

[0195] In this embodiment, the interconnection trench 510 extends along the second direction and extends above the top of the first embedded power supply layer 140, and the opening 590 extends along the second direction and extends above the top of the second embedded power supply layer 150. In this embodiment, the interconnection trench 510 and the opening 590 can be formed using the same mask, saving process cost.

[0196] ReferenceFigure 20 , Figure 20 (a) is based on Figure 19 (a) is a sectional view, Figure 20 (b) is based on Figure 19 (b) is a sectional view, the second source-drain doped layer 610 is formed on the isolation layer 170 on both sides of the dummy gate structure 160, and the second source-drain doped layer 610 is in contact with the end of the second channel layer 220 located below the dummy gate structure 160.

[0197] The second source-drain doped layer 610 is used as a source region or a drain region of the second transistor.

[0198] In the opening 590, the second source-drain doped layer 610 is epitaxially grown with the second channel layer 220 as an epitaxial growth base, and therefore, in the step of forming the second source-drain doped layer 610, the second source-drain doped layer 610 is in contact with the end of the second channel layer 220.

[0199] The doping type of the second source-drain doped layer 610 is the same as the channel conduction type of the corresponding transistor, and specifically, the second transistor is a PMOS transistor, and the doping ions in the second source-drain doped layer 610 are P-type ions, including B ions, Ga ions or In ions.

[0200] In this embodiment, in the opening 590, the second source-drain doped layer 610 is formed on the isolation layer 170 exposed by the remaining second interlayer dielectric layer 520 and the first interlayer dielectric layer 500, and the second source-drain doped layer 610 is formed to stand on the isolation layer 170.

[0201] For reference Figure 21 and Figure 22 , Figure 21 and Figure 22 is based on Figure 20 (a) is a sectional view, a protective wall 330 is formed on the sidewall of the second source-drain doped layer 610 closest to the second pre-embedded power supply layer 150.

[0202] The protective wall 330 is formed on the sidewall of the second source-drain doped layer 420 closest to the second pre-embedded power supply layer 150, and when the second source-drain interconnection layer 620 is electrically connected to the second pre-embedded power supply layer 150, the second source-drain interconnection layer 620 extends downward from the outside of the protective wall 330, thereby increasing the distance between the part of the second source-drain interconnection layer 620 extending downward and the first source-drain doped layer 410 or the first source-drain interconnection layer 420, reducing the probability of contact between the second source-drain interconnection layer 620 and the first source-drain doped layer 410 or the first source-drain interconnection layer 420 due to being too close to each other when the second source-drain interconnection layer 620 is formed, thereby reducing the probability of short circuit between the second source-drain interconnection layer 620 and the first source-drain doped layer 410 or the first source-drain interconnection layer 420, and further ensuring the working performance of the semiconductor structure.

[0203] Correspondingly, in other embodiments, the second source-drain interconnection layer is electrically connected with the first pre-buried power supply layer, and the protection wall is formed on the sidewall closest to the first pre-buried power supply layer in the stack structure.

[0204] In this embodiment, the material of the protection wall 330 is SiN.

[0205] SiN has a large hardness, which is conducive to better maintaining the sidewall of the second source-drain doped layer 610.

[0206] It should be noted that the width of the protection wall 330 along the second direction should not be too large or too small. If the width of the protection wall 330 along the second direction is too large, the distance of the subsequently formed second source-drain interconnection layer extending along the second direction is too large, which is easy to cause the overall volume of the semiconductor structure to be too large, and the occupied area of the semiconductor structure is wasted. If the width of the protection wall 330 along the second direction is too small, it is easy to cause the distance of the subsequently formed second source-drain interconnection layer extending along the second direction to be too small, thereby easily causing the second source-drain interconnection layer to be too close to the first source-drain doped layer 410 and the first source-drain interconnection layer 420 to contact, affecting the working performance of the semiconductor structure. Therefore, in this embodiment, the width of the protection wall 330 along the second direction is 2nm to 10nm.

[0207] Specifically, referring to Figure 21 The step of forming the protection wall 330 on the sidewall of the second source-drain doped layer 610 closest to the second pre-buried power supply layer 150 includes: forming a protection material layer 320 covering the top and sidewall of the second source-drain doped layer 610 and the top of the isolation layer 170.

[0208] The protection material layer 320 is used to directly form the protection wall 330.

[0209] In this embodiment, the protection material layer 320 also covers the sidewall and the top of the bottom of the first interlayer dielectric layer 500 and the second interlayer dielectric layer 520 exposed by the interconnection trench 510.

[0210] In this embodiment, the protection material layer 320 is formed by using an atomic layer deposition process.

[0211] The thickness uniformity of the protection material layer 320 formed by using the atomic layer deposition process is good, and the protection material layer 320 has good step coverage capability, so that the protection material layer 320 can be well conformally covered on the top and sidewall of the second source-drain doped layer 610 and the top of the isolation layer 170.

[0212] Correspondingly, in this embodiment, the material of the protection material layer 320 includes SiN.

[0213] Referring to Figure 22Remove the protective material layer 320 located on top of the second source / drain doped layer 610 and on top of the isolation layer 170, and retain the protective material layer 320 located on the sidewall of the second source / drain doped layer 610 as a protective wall 330.

[0214] Accordingly, in this embodiment, the protective material layer 320 located at the bottom of the opening 590 is also removed.

[0215] Therefore, in this embodiment, the protective wall 330 is also formed on the remaining sidewall of the second source / drain doped layer 610.

[0216] In this embodiment, the protective wall 330 formed on the remaining sidewalls of the second source / drain doped layer 610 is retained to avoid damage to the second source / drain doped layer 610 due to the subsequent removal of the protective wall 330 on the remaining sidewalls of the second source / drain doped layer 610. Moreover, the removal is relatively difficult, thus avoiding increased process complexity and unnecessary process waste.

[0217] In this embodiment, an anisotropic etching process is used to remove the protective material layer 320 located on top of the second source / drain doped layer 610 and the isolation layer 170.

[0218] The anisotropic etching process is an anisotropic dry etching process. By selecting anisotropic dry etching process, it is beneficial to reduce the damage to the second source / drain doped layer 610. At the same time, anisotropic dry etching is more directional, which is beneficial to improve the sidewall morphology quality and dimensional accuracy of the protective wall 310.

[0219] refer to Figure 23 , Figure 23 (a) is based on Figure 22 sectional view, Figure 23 (b) is based on Figure 20 (b) Cross-sectional view, a second source-drain interconnect layer 620 is formed on both sides of the pseudo-gate structure 160, covering the second source-drain doped layer 610 and the guard wall 330. The second source-drain interconnect layer 620 also extends longitudinally from the side of the guard wall 330 to the top of the corresponding second embedded power layer 150 and is electrically connected to the second embedded power layer 150.

[0220] The second source-drain interconnect layer 620 is used to electrically connect the second buried power layer 150 and the second source-drain doped layer 610, thereby applying voltage to the second source-drain doped layer 610 through the second buried power layer 150.

[0221] In this embodiment, according to the design of the circuit layout, the second source-drain interconnection layer 620 extends to the top of the corresponding second embedded power supply layer 150 and is electrically connected with the second embedded power supply layer 150. In other embodiments, according to the process requirement, the second source-drain interconnection layer can also extend to the top of the first embedded power supply layer and be electrically connected with the first embedded power supply layer. Correspondingly, the protection wall is located in the sidewall of the second source-drain doped layer closest to the first embedded power supply layer and extends downward to cover the sidewall of the first source-drain doped layer.

[0222] In this embodiment, the protection wall 310 covers the sidewall of the second source-drain doped layer 610, and therefore the second source-drain interconnection layer 620 covers the protection wall 310 correspondingly.

[0223] In this embodiment, the material of the second source-drain interconnection layer 620 includes W or Co.

[0224] W or Co is a metal material and has good electrical conductivity, which is conducive to the good electrical connection between the second source-drain doped layer 610 and the second embedded power supply layer 150.

[0225] In this embodiment, the step of forming the second source-drain interconnection layer 620 includes: forming a second interconnection through hole (not shown) through the top of the second embedded power supply layer 150 and the first interlayer dielectric layer 500 and the substrate 100 on the side of the first source-drain interconnection layer 410 through the interconnection groove 510; forming the second source-drain interconnection layer 620 covering the second source-drain doped layer 610 in the remaining space of the interconnection groove 510, and the second source-drain interconnection layer 620 also fills in the second interconnection through hole.

[0226] Specifically, the step of forming the second source-drain interconnection layer 620 includes: forming the second interlayer dielectric layer 520 through the interconnection groove 510; etching the second interlayer dielectric layer 520 and the first interlayer dielectric layer 500 to form the opening 590.

[0227] The second embedded power supply layer 150 is located in the substrate 100, so that the second embedded power supply layer 150 is exposed by forming the second interconnection through hole extending longitudinally, and the second source-drain interconnection layer 620 is filled in the second interconnection through hole to make the second source-drain interconnection layer 620 contact with the second embedded power supply layer 150 and be electrically connected with the second embedded power supply layer 150.

[0228] Therefore, in this embodiment, the second source-drain interconnection layer 620 longitudinally extends through the isolation layer 130 and the first interlayer dielectric layer 500 on the top of the second embedded power supply layer 150.

[0229] In the embodiment, when the second interconnection via is formed, the second interconnection via needs to extend in the longitudinal direction from the outside of the protection wall 330, so as to reduce the probability of exposing the first source / drain doping layer 410 or the first source / drain interconnection layer 420 due to being too close to the first source / drain doping layer 410 or the first source / drain interconnection layer 420 when the second interconnection via is formed, thereby reducing the probability of short circuiting with the first source / drain doping layer 410 or the first source / drain interconnection layer 420 when the second source / drain interconnection layer 620 is formed, and further ensuring the working performance of the semiconductor structure.

[0230] In the embodiment, the second interconnection via is formed by using an anisotropic dry etching process.

[0231] In the embodiment, the second interconnection via is formed by using an anisotropic dry etching process. By selecting the anisotropic dry etching process, the damage to the second pre-embedded power supply layer 150 can be reduced. In addition, the anisotropic dry etching process has directionality, which is beneficial to the second interconnection via having good morphology quality and size precision.

[0232] Reference Figure 24 , Figure 24 (a) is a sectional view based on Figure 23 (a), Figure 24 (b) is a sectional view based on Figure 23 (b), after the second source / drain interconnection layer 620 is formed, the forming method further includes: removing the dummy gate structure 160 to form a gate opening (not shown in the figure) exposing the sacrificial layer 230.

[0233] The gate opening provides a spatial position for the subsequent formation of the second gate structure and prepares for the removal of the sacrificial layer 230.

[0234] In the embodiment, the sacrificial layer 230 is removed through the gate opening to form a through slot (not shown in the figure) surrounded by the first channel layer 210 and the second channel layer 220.

[0235] The through slot provides a spatial position for the subsequent formation of the first gate structure.

[0236] In the embodiment, the first gate structure 710 spanning the first channel layer 210 is formed through the gate opening and the through slot, and the first gate structure 710 covers the top and sidewall of the first channel layer 210. The second gate structure 720 spanning the second channel layer 220 is formed on the first gate structure 710 through the gate opening, and the second gate structure 720 covers the top and sidewall of the second channel layer 220.

[0237] Specifically, a first gate structure material layer is filled in the gate opening and the via, and the first gate structure material layer spans the first channel layer 210; a partial thickness of the first gate structure material layer is etched to expose the second channel layer 220, and a remaining first gate structure material layer is reserved as a first gate structure 710, a top surface of the first gate structure 710 is lower than a bottom surface of the second channel layer 220; a second gate structure 720 is formed on the first gate structure 710, and the second gate structure 720 spans the second channel layer 220.

[0238] The first gate structure 710 is configured to control opening and closing of a channel of the first transistor, and the second gate structure 720 is configured to control opening and closing of a channel of the second transistor.

[0239] The first gate structure 710 and the second gate structure 720 each include a gate dielectric layer (not shown) and a gate electrode layer (not shown) located on the gate dielectric layer.

[0240] The gate dielectric layer is configured to isolate the gate electrode layer from the first channel layer 210 and the substrate 100, and to isolate the gate electrode layer from the second channel layer 220 and the first gate structure 710.

[0241] The material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3. In this embodiment, the gate dielectric layer includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer includes a high-k dielectric material. The high-k dielectric material refers to a dielectric material with a relative dielectric constant greater than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer includes HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3, etc.

[0242] It should be noted that the gate dielectric layer can further include a gate oxide layer, and the gate oxide layer is located between the high-k gate dielectric layer and the first channel layer 210, and the gate oxide layer is also located between the high-k gate dielectric layer and the second channel layer 220. Specifically, the material of the gate oxide layer can be silicon oxide.

[0243] In this embodiment, the first gate structure 710 and the second gate structure 720 are metal gate structures, and therefore, the material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC.

[0244] Specifically, the gate electrode layer includes a work function layer (not shown) and an electrode layer (not shown) located on the work function layer. The work function layer is configured to adjust the threshold voltage of the transistor, and the electrode layer is configured to lead out the electrical property of the metal gate structure.

[0245] In other embodiments, the gate electrode layer can also include only the work function layer.

[0246] In other embodiments, the first gate structure can also be a polysilicon gate structure according to process requirements.

[0247] Although the present application has been disclosed with reference to the above embodiments, the above embodiments are not intended to limit the present application. Any person skilled in the art, without departing from the spirit and scope of the present application, can make various modifications and changes, and the scope of protection of the present application should be limited by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized by, The semiconductor structure comprises: a substrate comprising a device unit region for forming a first transistor and a second transistor stacked in sequence from bottom to top; a pre-embedded power supply layer located in the substrate on both sides of the device unit region in a second direction, comprising a first pre-embedded power supply layer located on one side of the device unit region and a second pre-embedded power supply layer located on the other side of the device unit region; a first transistor located on the substrate in the device unit region, the first transistor comprising a first channel layer extending along a first direction, a first gate structure crossing the first channel layer and covering the top and sidewall of the first channel layer, and a first source-drain doped layer located on the substrate on both sides of the first gate structure, the first source-drain doped layer being in contact with the end of the first channel layer located below the first gate structure, the first direction being perpendicular to the second direction; a first source-drain interconnection layer covering the first source-drain doped layer, the first source-drain interconnection layer further extending from the side of the first source-drain doped layer to the top of the corresponding first pre-embedded power supply layer in the longitudinal direction and being electrically connected with the pre-embedded power supply layer; an insulating layer located on the top of the first source-drain interconnection layer; a second transistor stacked above the first transistor, the second transistor comprising a second channel layer extending along the first direction, a second gate structure crossing the second channel layer and covering the second channel layer, and a second source-drain doped layer located on the insulating layer on both sides of the second gate structure, the second source-drain doped layer being in contact with the end of the second channel layer located below the second gate structure; a protection wall located on the sidewall of the second source-drain doped layer closest to the second pre-embedded power supply layer; a second source-drain interconnection layer covering the second source-drain doped layer and the protection wall, the second source-drain interconnection layer further extending from the side of the protection wall to the top of the corresponding second pre-embedded power supply layer in the longitudinal direction and being electrically connected with the second pre-embedded power supply layer.

2. The semiconductor structure of claim 1, wherein, The substrate comprises a substrate, a bottom fin of the substrate protruding in the device unit region, and an isolation layer located on the substrate and surrounding the bottom fin; The pre-embedded power supply layer is located in the substrate and covered by the isolation layer; The first channel layer is located on the bottom fin; The first source-drain interconnection layer penetrates the isolation layer on the top of the first pre-embedded power supply layer in the longitudinal direction; The second source-drain interconnection layer penetrates the isolation layer on the top of the second pre-embedded power supply layer in the longitudinal direction.

3. The semiconductor structure of claim 1 or 2, wherein, The semiconductor structure further comprises a first interlayer dielectric layer located on the substrate and covering the sidewall of the first source-drain interconnection layer and the sidewall of the first gate structure and the second gate structure; The first source-drain interconnection layer comprises a first lateral part extending along the second direction located in the first interlayer dielectric layer, the first lateral part covering the first source-drain doped layer; a first longitudinal part extending in the longitudinal direction located in the substrate on the side of the first source-drain doped layer, the top of the first longitudinal part being connected with the bottom of the first lateral part, and the bottom of the first longitudinal part being connected with the top of the first pre-embedded power supply layer; The insulating layer is located in the first interlayer dielectric layer and covers the top of the first source-drain interconnection layer; The second source-drain interconnection layer comprises a second lateral part extending along the second direction, located in the first interlayer dielectric layer, covering the second source-drain doped layer and the protection wall; a second longitudinal part extending longitudinally, located in the first interlayer dielectric layer at the bottom of the second lateral part and the substrate, and connected to the top of the second pre-embedded power supply layer.

4. The semiconductor structure of claim 3, wherein, The semiconductor structure further comprises a second interlayer dielectric layer located between the second lateral part and the first interlayer dielectric layer and on the top of the isolation layer.

5. The semiconductor structure of claim 3, wherein, The second longitudinal part is spaced apart from the protection wall.

6. The semiconductor structure of claim 1, wherein, The material of the isolation layer comprises SiN, SiON, SiOCN, SiOC or SiOCH.

7. The semiconductor structure of claim 1, wherein, The material of the protection wall is SiN.

8. The semiconductor structure of claim 1, wherein, The width of the protection wall along the second direction is 2-10 nm.

9. The semiconductor structure of claim 1, wherein, The material of the first source-drain interconnection layer comprises W or Co; and the material of the second source-drain interconnection layer comprises W or Co.

10. The semiconductor structure of claim 1, wherein, The material of the first channel layer comprises silicon, germanium, silicon germanium or group III-V semiconductor material; and the material of the second channel layer comprises silicon, germanium, silicon germanium or group III-V semiconductor material.

11. The semiconductor structure of claim 1, wherein, The first gate structure and the second gate structure each comprise a gate dielectric layer and a gate electrode layer located on the gate dielectric layer. The material of the gate dielectric layer comprises one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2 and La2O3; and the material of the gate electrode layer comprises one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN and TiAlC.

12. A method of forming a semiconductor structure, comprising: The method comprises: providing a substrate comprising a device unit area for forming a first transistor and a second transistor stacked from bottom to top, the substrate of the device unit area is formed with a stack structure extending along a first direction, the stack structure comprises a first channel layer, a sacrificial layer located on the first channel layer, and a second channel layer located on the sacrificial layer, in a second direction, the substrate on both sides of the device unit area is formed with a first pre-embedded power supply layer and a second pre-embedded power supply layer respectively, the second direction is perpendicular to the first direction, and the substrate is further formed with a pseudo gate structure across the stack structure, the pseudo gate structure covers part of the sidewall and part of the top of the stack structure; forming a first source-drain doped layer in the stack structure on both sides of the pseudo gate structure, the first source-drain doped layer is in contact with the end of the first channel layer under the pseudo gate structure; forming a first source-drain interconnection layer covering the first source-drain doped layer on both sides of the pseudo gate structure, the first source-drain interconnection layer further extends longitudinally from the side of the first source-drain doped layer to the top of the corresponding first pre-embedded power supply layer and is electrically connected to the first pre-embedded power supply layer; forming an isolation layer on the first source-drain interconnection layer, the isolation layer exposes the end of the second channel layer; forming a second source-drain doped layer on the isolation layer on both sides of the pseudo gate structure, the second source-drain doped layer is in contact with the end of the second channel layer under the pseudo gate structure; forming a protection wall on the sidewall of the second source-drain doped layer closest to the sidewall of the second pre-embedded power supply layer; forming a second source-drain interconnection layer covering the second source-drain doped layer and the protection wall on both sides of the pseudo-gate structure, the second source-drain interconnection layer further extends from the side of the protection wall to the top of the corresponding second pre-embedded power supply layer in the longitudinal direction and is electrically connected with the second pre-embedded power supply layer.

13. The method of forming a semiconductor structure of claim 12, wherein, The step of forming the protection wall on the sidewall of the second source-drain doped layer closest to the sidewall of the second pre-embedded power supply layer comprises: forming a protection material layer covering the top and sidewall of the second source-drain doped layer and the top of the isolation layer; The protection material layer on the top of the second source-drain doped layer and the top of the isolation layer is removed, and the protection material layer on the sidewall of the second source-drain doped layer is reserved as the protection wall.

14. The method of forming a semiconductor structure of claim 12, wherein, The step of forming the first source-drain doped layer comprises: forming a source-drain recess in the stacked structure on both sides of the pseudo-gate structure; forming a sacrificial sidewall covering the exposed end of the second channel layer in the source-drain recess; After forming the sacrificial sidewall, a first source-drain doped layer is formed in a partial depth region of the source-drain recess, the first source-drain doped layer covering the end of the first channel layer; After forming the first source-drain doped layer, before forming the first source-drain interconnection layer, it further comprises: removing the sacrificial sidewall.

15. The method of forming a semiconductor structure of claim 14, wherein, The step of forming the sacrificial sidewall covering the sidewall of the second channel layer comprises: forming a filling layer covering the end of the first channel layer on the substrate; forming a sacrificial sidewall material layer on the top of the filling layer, on the top and sidewall of the pseudo-gate structure higher than the top of the filling layer, and on the sidewall of the stacked structure; The sacrificial sidewall material layer on the top of the filling layer and on the top of the pseudo-gate structure is removed, and the sacrificial sidewall material layer on the end of the second channel layer is reserved as the sacrificial sidewall; After forming the sacrificial sidewall, the filling layer is removed.

16. The method of forming a semiconductor structure of claim 12, wherein, In the step of providing the substrate, the substrate comprises a substrate, a bottom fin of the substrate standing in the device unit area, and an isolation layer on the substrate and surrounding the bottom fin, the first pre-embedded power supply layer and the second pre-embedded power supply layer are formed in the substrate and covered by the isolation layer; The stacked structure is formed on the bottom fin; In the step of forming the first source-drain interconnection layer, the second source-drain interconnection layer penetrates the isolation layer on the top of the second pre-embedded power supply layer; In the step of forming the second source-drain interconnection layer, the second source-drain interconnection layer penetrates the isolation layer on the top of the second pre-embedded power supply layer.

17. The method of forming a semiconductor structure of claim 12 or 16, wherein, After forming the first source-drain doped layer, before forming the first source-drain interconnection layer, it further comprises: forming a first interlayer dielectric layer covering the first source-drain doped layer on the substrate, the first interlayer dielectric layer also covering the sidewall of the pseudo-gate structure; The step of forming the first source-drain interconnection layer includes: forming an interconnection trench in the first interlayer dielectric layer and extending along the second direction on both sides of the dummy gate structure, and a first interconnection via on the side of the first source-drain doped layer, the top of the first interconnection via being in communication with the bottom of the interconnection trench, the interconnection trench exposing the first source-drain doped layer, and the first interconnection via exposing the top of the first pre-embedded power supply layer. A first source-drain interconnection layer covering the first source-drain doped layer is formed in a partial depth region of the interconnection trench, and the first source-drain interconnection layer also fills the first interconnection via. The second source-drain doped layer is formed to stand on the isolation layer through the interconnection trench. The step of forming the second source-drain interconnection layer includes: forming a second interconnection via through the first interlayer dielectric layer and the substrate on the side of the first source-drain interconnection layer and penetrating the top of the second pre-embedded power supply layer through the interconnection trench; and forming a second source-drain interconnection layer covering the second source-drain doped layer in the remaining space of the interconnection trench, the second source-drain interconnection layer also filling the second interconnection via.

18. The method of forming a semiconductor structure of claim 17, wherein, After the isolation layer is formed and before the second source-drain doped layer is formed, a second interlayer dielectric layer is formed in the remaining space of the interconnection trench. The step of forming the second source-drain doped layer to stand on the isolation layer includes: removing the first interlayer dielectric layer on the top of the second pre-embedded power supply layer and higher than the top surface of the first source-drain interconnection layer, and the second interlayer dielectric layer in contact with the second interlayer dielectric layer on both sides of the dummy gate structure, to expose the end of the second channel layer; and forming the second source-drain doped layer on the remaining second interlayer dielectric layer and the isolation layer exposed by the first interlayer dielectric layer.

19. The method of forming a semiconductor structure of claim 13, wherein, The process of forming the protective material layer includes an atomic layer deposition process.

20. The method of forming a semiconductor structure of claim 13, wherein, An anisotropic etching process is used to remove the protective material layer on the top of the second source-drain doped layer and the top of the isolation layer.

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