A semiconductor device and an integrated circuit

Abstract

The application discloses a semiconductor device and an integrated circuit. The semiconductor device comprises an N-type semiconductor substrate, a drift layer, a semiconductor layer, a first trench in the semiconductor layer, a gate in the first trench, a P-well, a source region and an N-type second semiconductor region in the semiconductor layer, and a source and a drain. The drift layer comprises N-type column regions and P-type column regions arranged alternately and side by side. In the semiconductor device, an electrode is further arranged below the gate, a P-type first semiconductor region is arranged at the bottom end of the first trench, the first semiconductor region is in contact with the electrode and the P-type column region below the gate, and the electrode is electrically connected with the source. Thus, the P-type column region below the gate can be connected to the source through the electrode, and good electrical contact is realized between the electrode and the first semiconductor region, thereby realizing the grounding function.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and in particular, to a semiconductor device and an integrated circuit. BACKGROUND

[0002] SiC material has advantages of wide band gap, high critical breakdown field, high thermal conductivity and high electron saturation drift speed compared with Si material. The Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) made of SiC has high breakdown voltage and low on-state voltage drop compared with the Insulated Gate Bipolar Transistor (IGBT) made of Si. The unipolar conduction characteristic makes the SiC MOSFET have faster switching speed, lower on-state loss and lower switching loss compared with the Si IGBT. Therefore, the SiC MOSFET has replaced the Si IGBT in some fields. However, with the increase of voltage level, the drift region resistance of the SiC MOSFET increases continuously, which leads to a significant increase of the on-state resistance of the device.

[0003] In order to reduce the on-state resistance of the SiC MOSFET, the Super junction (SJ) drift region technology can be used, that is, the N-type column region and the P-type column region are alternately arranged in the drift region of the SiC MOSFET, so as to break through the theoretical limit between the on-state resistance and the breakdown voltage of the device by using the charge coupling principle, thereby further reducing the on-state resistance of the SiC MOSFET and improving the performance of the device and reducing the chip loss.

[0004] In the SiC MOSFET using the SJ drift region technology, in order to realize the charge coupling principle, the P-type column region in the drift region needs to be grounded (connected to zero potential) to make the P-type column region and the N-type column region deplete each other to form a lateral electric field, so as to play the advantages of the SJ drift region structure. Therefore, how to ground the P-type column region in the drift region is a technical problem to be solved by those skilled in the art. SUMMARY

[0005] The present application provides a semiconductor device and an integrated circuit for grounding the P-type column region in the SJ drift region of the SiC MOSFET.

[0006] In a first aspect, the present application provides a semiconductor device, which can include an N-type semiconductor substrate (N++), a drift layer, a semiconductor layer, a gate, a source, a drain, a gate insulating film and an electrode. The drift layer is disposed on the semiconductor substrate, and the drift layer includes N-type column regions (N) and P-type column regions (P) arranged in parallel and alternately. Here, "arranged in parallel and alternately" means that the N-type column regions (N) and the P-type column regions (P) are arranged in parallel in the order of N, P, N, P, … or P, N, P, N, … The semiconductor layer is disposed on the drift layer, and the semiconductor layer includes a first trench for disposing the gate, and the first trench is disposed in a region corresponding to the P-type column region. The gate is disposed in the first trench through the gate insulating film. The electrode is disposed in the first trench and between the gate and the P-type column region, and the electrode and the gate are separated by the gate insulating film, and the electrode is electrically connected to the source. The semiconductor layer can include a first semiconductor region (P+) at the bottom of the first trench, and a P-well, a source region (N+) and a second semiconductor region (N) on the sidewall of the first trench. The first semiconductor region is a P-type semiconductor region, the second semiconductor region is an N-type semiconductor region, the source region is on the P-well, the second semiconductor region is between the P-well and the N-type column region, the first semiconductor region is between the electrode and the P-type column region, and the first semiconductor region contacts the electrode and the P-type column region, the doping concentration of the first semiconductor region is greater than that of the P-type column region, and the first semiconductor region is used to electrically connect the electrode and the P-type column region. The source is disposed on the semiconductor layer, and the source contacts the source region and is electrically connected to the electrode. The drain is disposed on the side of the semiconductor substrate away from the drift layer.

[0007] In the semiconductor device provided in the embodiments of the present application, the electrode is disposed below the gate, the first semiconductor region of the P-type is disposed at the bottom end of the first trench, the first semiconductor region contacts the electrode and the P-type column region below the gate, and the electrode is electrically connected to the source. Therefore, the P-type column region below the gate can be connected to the source through the electrode, and good electrical contact is achieved between the electrode and the first semiconductor region, thereby achieving the grounding function. Moreover, since the electrode and the first semiconductor region are both below the gate, compared with the related art, the MOS conductive channel on the sidewall of the first trench can not be sacrificed, that is, the conductive channel is increased, thereby reducing the on-resistance of the device. In addition, the grounded electrode can shield the gate-drain capacitance, thereby reducing the Miller capacitance of the device and improving the switching speed. In addition, the grounded electrode can also effectively reduce the electric field in the gate insulating film at the bottom of the first trench, thereby improving the robustness of the device.

[0008] The first semiconductor region (P+) in the semiconductor layer, the P well, the source region (N+), the second semiconductor region (N) and the third semiconductor region (P++) mentioned later, the fourth semiconductor region (P+) and the fifth semiconductor region (P+) in the present application can be formed by doping the semiconductor layer. Among them, the source region (N+) is an N-type semiconductor region, the P well is a P-type semiconductor region, and the main impurity doped in the N-type semiconductor region is N-type impurity, such as phosphorus (P) or arsenic (As) and the like, and the main impurity doped in the P-type semiconductor region is P-type impurity, such as boron (B) or gallium (Ga) and the like. The P well refers to the P-type impurity doped in the N-type semiconductor layer with a concentration sufficient to neutralize the N-type semiconductor layer and make it have P-type characteristics.

[0009] It needs to be clearly stated that in the present application, in the layers and regions prefixed with N, electrons are the majority carriers, and in the layers and regions prefixed with P, holes are the majority carriers. In addition, the "+" marked with N or P indicates that the doping concentration is higher than that of the layer or region without the "+" mark, and the more "+" marks, the higher the doping concentration. N or P containing the same number of "+" marks indicates that the doping concentrations are similar and are not limited to the same doping concentration.

[0010] In addition, it also needs to be explained that the comparison of the doping concentrations of two regions in the present application only refers to the comparison of the concentrations of the impurities doped in the two regions, and the composition of the impurities is not limited to the substrate used for doping the impurities, that is, the composition of the impurities can be the same or different, and the material of the substrate used for doping the impurities can be the same or different.

[0011] The thickness of the electrode in the present application is not limited, and can be set according to the requirements of the device.

[0012] In the present application, the material of the electrode can be heavily doped polysilicon, or other materials with good conductive properties such as metal, which is not limited here.

[0013] The semiconductor device provided by the embodiment of the present application is mainly provided for the P-type column region located below the gate. In specific implementation, only a part of the P-type column region in the drift layer is located below the gate, and the remaining P-type column region is not disposed below the gate. The P-type column region located below the gate is the first P-type column region, and the remaining P-type column region is the second P-type column region, and the present application does not limit the way in which the second P-type column region is electrically connected to the source.

[0014] In an example, the semiconductor device can further include a third semiconductor region (P++) disposed in the semiconductor layer, the third semiconductor region (P++) being a P-type semiconductor region, and the third semiconductor region being located between the second P-type pillar region and the source; the third semiconductor region being in contact with the source and the second P-type pillar region; and the third semiconductor region having a doping concentration greater than a doping concentration of the second P-type pillar region. Thus, the second P-type pillar region is in good electrical connection with the source through the third semiconductor region.

[0015] In a specific implementation, in order to make the third semiconductor region in the semiconductor layer in contact with the second P-type pillar region and the source, the thickness of the third semiconductor region needs to be the same as the thickness of the semiconductor layer, thus increasing the process difficulty of the third semiconductor region.

[0016] Therefore, in order to reduce the process difficulty, in an example, the semiconductor device can further include a fourth semiconductor region (P+) disposed in the semiconductor layer, the fourth semiconductor region being a P-type semiconductor region, and the fourth semiconductor region being located between the second P-type pillar region and the third semiconductor region; the fourth semiconductor region being in contact with the third semiconductor region and the second P-type pillar region; and the fourth semiconductor region having a doping concentration less than a doping concentration of the third semiconductor region and greater than a doping concentration of the P-type pillar region. Thus, the fourth semiconductor region can be formed first, and then the third semiconductor region can be formed, thus reducing the process difficulty.

[0017] In a specific implementation, the doping concentration of the fourth semiconductor region can be similar to the doping concentration of the first semiconductor region, but is not limited to the same doping concentration.

[0018] In an example, the doping concentration of the fourth semiconductor region is the same as the doping concentration of the first semiconductor region, thus the fourth semiconductor region and the first semiconductor region can be simultaneously prepared, thus simplifying the process steps.

[0019] In another example, the semiconductor device further includes a second trench disposed in the semiconductor layer, the source filling the second trench, and the third semiconductor region including a first extension located at a bottom of the second trench and a second extension located at a sidewall of the second trench. Thus, by disposing the second trench, the thickness of the third semiconductor region can be reduced, thus reducing the process difficulty.

[0020] In the present application, the P-well and the source region are disposed on both sides of the gate to ensure that there is a MOS conduction channel on both sides of the gate of the SiC MOSFET.

[0021] The shape of the first trench is not limited in the present application. For example, the cross section of the first trench perpendicular to the semiconductor substrate is rectangular, or the cross section of the first trench perpendicular to the semiconductor substrate is trapezoidal, and the area of the cross section of the first trench parallel to the semiconductor substrate increases with the distance from the semiconductor substrate, i.e. the area of the top surface of the first trench (the cross section on the side far from the semiconductor substrate) is larger than the area of the bottom surface of the first trench (the cross section on the side close to the semiconductor substrate).

[0022] To improve the electrical contact between the electrode and the first P-type pillar region, the first semiconductor region can be located at the first extension of the bottom of the first trench and the second extension of the sidewall of the first trench. In this way, when multiple gates are included in the semiconductor device, part of the first semiconductor region can be arranged to include the first extension and the second extension, i.e. only part of the MOS conductive channel on one side of the gate is sacrificed, compared to the related art in which the MOS conductive channel on one side of each gate is sacrificed, the electrical contact between the electrode and the first P-type pillar region can be improved, and the on-resistance of the semiconductor device can be reduced.

[0023] In a specific implementation, in the semiconductor device provided by the embodiments of the present application, the semiconductor layer can have multiple first trenches; to improve the electrical contact between the electrode and the first P-type pillar region, the semiconductor layer further has at least one second trench located between two adjacent first trenches; the semiconductor layer further includes a P-type fifth semiconductor region (P+) located at the bottom of the second trench, the doping concentration of the fifth semiconductor region is greater than the doping concentration of the P-type pillar region; and the fifth semiconductor region is in contact with the source electrode and the P-type pillar region.

[0024] In a specific implementation, the doping concentration of the fifth semiconductor region can be similar to the doping concentration of the first semiconductor region, but is not limited to the same doping concentration.

[0025] For example, the doping concentration of the fifth semiconductor region is the same as the doping concentration of the first semiconductor region, so that the fifth semiconductor region and the first semiconductor region can be prepared at the same time during preparation, thereby simplifying the process steps.

[0026] For example, the fifth semiconductor region is in communication with the first semiconductor region adjacent thereto, i.e. the fifth semiconductor region and the first semiconductor region are integrated.

[0027] Further, to increase the contact area between the source electrode and the fifth semiconductor region, the second trench is in communication with two first trenches adjacent thereto. That is, the two first trenches adjacent to each other and the second trench located between the two first trenches are in communication, so that the two gates and part of the source electrode are arranged in the same trench, and the gates and the source electrode are isolated by a gate insulating film.

[0028] In a second aspect, there is provided an integrated circuit including a circuit board, and a semiconductor device as in the first aspect or various embodiments of the first aspect disposed on the circuit board.

[0029] The technical effects achieved by the second aspect described above can be explained with reference to the technical effects achieved by any possible design of the first aspect described above, which will not be repeated here. BRIEF DESCRIPTION OF DRAWINGS

[0030] Figure 1 Structure diagram of SiC MOSFET;

[0031] Figure 2 Structure diagram of SiC SJ-MOSFET in the related art;

[0032] Figure 3 Structure diagram of a semiconductor device provided by an embodiment of the present application;

[0033] Figure 4 Structure diagram of another semiconductor device provided by an embodiment of the present application;

[0034] Figure 5 Structure diagram of another semiconductor device provided by an embodiment of the present application;

[0035] Figure 6 Structure diagram of another semiconductor device provided by an embodiment of the present application;

[0036] Figure 7 Structure diagram of another semiconductor device provided by an embodiment of the present application;

[0037] Figure 8 Structure diagram of another semiconductor device provided by an embodiment of the present application;

[0038] Figure 9 Structure diagram of another semiconductor device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0039] In order to make the purposes, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the drawings. However, the example embodiments can be implemented in various forms, and should not be understood as being limited to the embodiments set forth herein; on the contrary, these embodiments are provided so that the present application is more comprehensive and complete, and the ideas of the example embodiments are fully conveyed to those skilled in the art. The same reference signs in the drawings represent the same or similar structures, and thus repeated descriptions thereof will be omitted. The expressions of position and direction described in the present application are described with reference to the drawings, but can be changed as needed, and the changes made are included in the protection scope of the present application. The drawings of the present application are only used to show the relative positional relationship and do not represent the true proportions.

[0040] It should be noted that specific details are set forth in the following description in order to provide a thorough understanding of the present application. However, the present application can be practiced in a variety of ways beyond those described herein, and those skilled in the art can make similar substitutions without departing from the spirit of the present application. Therefore, the present application is not limited by the specific embodiments disclosed below. The subsequent description of the specification is a preferred embodiment for implementing the present application, and is intended to illustrate the general principles of the present application, rather than to limit the scope of the present application. The protection scope of the present application is defined by the appended claims.

[0041] In order to facilitate the understanding of the ring gate transistor provided by the embodiments of the present application, the application scenarios thereof will be introduced first as follows.

[0042] SiC material has advantages such as wide band gap, high critical breakdown field, high thermal conductivity and high electron saturation drift speed compared with Si material. The metal-oxide-semiconductor field-effect transistor (MOSFET) made of SiC has characteristics such as high breakdown voltage and low on-state voltage drop compared with the insulated gate bipolar transistor (IGBT) made of Si. And the unipolar conduction characteristics make the SiC MOSFET have faster switching speed, lower on-state loss and lower switching loss compared with Si IGBT. Therefore, the SiC MOSFET has been widely applied in fields such as switching power supply, power amplifier, electric vehicle on-board power supply, photovoltaic inverter, server power supply and rail transit.

[0043] Need to say, in this application, in the layer and area with prefix N or P, respectively, indicates that the majority carrier is electron or hole. In addition, the "+" marked on N or P indicates that the doping concentration is higher than that of the layer or area without "+" mark, and the more "+" marks, the higher the doping concentration. N or P containing the same number of "+" marks indicates similar doping concentration and is not limited to the same doping concentration.

[0044] Referring to Figure 1 , Figure 1 is a schematic diagram of a SiC MOSFET structure, which includes: source 1, drain 2, gate 3, drain region (N++) 4, source region (N+) 5, drift region (N) 6, N-type first semiconductor region (N) 7, P-well (P) 8, P-type first semiconductor region (P++) 9 and gate insulating film 10. Among them, the drift region 6 is an N-type semiconductor region, mainly used for carrying high voltage. The N-type first semiconductor region 7 is mainly used to reduce the on-resistance of the SiC MOSFET, and its doping concentration is generally higher than that of the drift region 6. The P-type first semiconductor region 9 is used to contact the P-well 8 with the source 1, so as to short the PN junction of the P-well 8 and the source region 5, and avoid the opening of the PN junction.

[0045] But with the increase of voltage level, the drift region resistance of SiC MOSFET increases continuously, resulting in a significant increase in the on-resistance of the device. In order to reduce the on-resistance of SiC MOSFET, super junction drift region technology can be used, as shown in Figure 2 , that is, in the SiC MOSFET, the drift region has alternating N-type column region 61 and P-type column region 62, so as to break through the theoretical limit between the on-resistance and the breakdown voltage of the device by using the principle of charge coupling, and further reduce the on-resistance of the SiC MOSFET, and improve the performance of the device and reduce the chip loss. In this SiC MOSFET, in order to realize the principle of charge coupling, the P-type column region 62 in the drift region needs to be grounded (connected to zero potential), and for the P-type column region 62 located below the gate 3, a P-type second semiconductor region 11 is arranged at the bottom end and one side wall of the gate 3 trench, so that the P-type column region 62 and the N-type column region 61 are mutually depleted to form a lateral electric field, thereby taking advantage of the super junction drift region structure.

[0046] Continuing to refer to Figure 2 , in this SiC MOSFET, the MOS conductive channel originally generated on both side walls of the gate 3 trench is unable to form due to the arrangement of the P-type second semiconductor region 11, that is, only one side wall can generate the MOS conductive channel, so that nearly half of the MOS conductive channel is sacrificed, resulting in a decrease in the current carrying capacity of the device and an increase in the on-resistance.

[0047] To this end, the application provides a semiconductor device and integrated circuit capable of reducing on-resistance of the device, which will be described in detail below in combination with specific drawings and embodiments.

[0048] Referring to Figure 3 , Figure 3 A structure diagram of a semiconductor device provided by an embodiment of the application is shown. The semiconductor device is a SiC SJ-MOSFET, which is schematically shown by taking two gates as an example in the following. Figure 3 The semiconductor device can include an N-type semiconductor substrate (N++) 101, a drift layer 102, a semiconductor layer 103, a gate 104, a source 105, a drain 106, a gate insulating film 107, and an electrode 108. The drift layer 102 is arranged on the semiconductor substrate 101, and the drift layer 102 includes N-type column regions (N) 1021 and P-type column regions (P) 1022 arranged in parallel and alternately. Here, "arranged in parallel and alternately" means that the N-type column regions (N) and the P-type column regions (P) are arranged in parallel in the order of N, P, N, P, … or P, N, P, N, … The semiconductor layer 103 is arranged on the drift layer 102, and the semiconductor layer 103 includes a first trench V1 for arranging the gate 104, and the first trench V1 is arranged in a region corresponding to the P-type column region 1022. The gate 104 is arranged in the first trench V1 through the gate insulating film 107. The electrode 108 is arranged in the first trench V1 between the gate 104 and the P-type column region 1022, and the electrode 108 and the gate 104 are separated by the gate insulating film 107, and the electrode 108 is electrically connected to the source 105. The semiconductor layer 103 can include a first semiconductor region (P+) 1034 at the bottom of the first trench V1, a P-well (P) 1031, a source region (N+) 1032, and a second semiconductor region (N) 1033 on the sidewall of the first trench V1. The first semiconductor region 1034 is a P-type semiconductor region, the second semiconductor region 1033 is an N-type semiconductor region, the source region 1032 is on the P-well 1031, the second semiconductor region 1033 is between the P-well 1031 and the N-type column region 1021, the first semiconductor region 1034 is between the electrode 108 and the P-type column region 1022, and the first semiconductor region 1034 contacts the electrode 108 and the P-type column region 1022, the doping concentration of the first semiconductor region 1034 is greater than that of the P-type column region 1022, and the first semiconductor region 1034 is used to electrically connect the electrode 108 and the P-type column region 1022. The source 105 is arranged on the semiconductor layer 103, and the source 105 contacts the source region 1032 and is electrically connected to the electrode 108. The drain 106 is arranged on the side of the semiconductor substrate 101 away from the drift layer 102.

[0049] The semiconductor device provided in the embodiments of the present application has the electrode 108 arranged below the gate 104, the first semiconductor region 1034 of P type arranged at the bottom end of the first trench V1, the first semiconductor region 1034 in contact with the electrode 108 and the P type column region 1022 below the gate 104, and the electrode 108 electrically connected with the source 105. Thus, the P type column region 1022 below the gate 104 can be connected to the source 105 through the electrode 108, and good electrical contact is achieved between the electrode 108 and the first semiconductor region 1034, thereby achieving the grounding function. Moreover, since the electrode 108 and the first semiconductor region 1034 are both below the gate 104, compared with the related art, the MOS conductive channel of the sidewall of the first trench V1 can not be sacrificed, that is, the conductive channel is increased, thereby reducing the on-resistance of the device. In addition, the electrode 108 grounded can shield the gate-drain capacitance, thereby reducing the Miller capacitance of the device and improving the switching speed. In addition, the electrode 108 grounded can also effectively reduce the electric field in the gate insulating film 107 at the bottom of the first trench V1, thereby improving the working robustness of the device.

[0050] Specifically, in the present application, since the electrode 108 is arranged between the gate 104 and the drain 106, it is equivalent to inserting the electrode 108 grounded in the middle of the parallel-plate capacitor (gate-drain capacitance), so that the electric field lines emitted by the gate 104 and the drain 106 will all terminate on the electrode 108 in the middle, that is, the electrode 108 shields the original gate-drain capacitance. When the gate-drain capacitance is shielded, the Miller capacitance (mainly the gate-drain capacitance) will be reduced, and since the switching process of the device is essentially a capacitance charging and discharging process, the switching speed will be improved.

[0051] In the practical application of SiC MOSFET, there is a high electric field in the drift region in the blocking state. According to the principle of continuous potential displacement vector, the electric field lines will enter the gate insulating film. The curvature effect at the bottom of the first trench V1 will cause the electric field at this position to be particularly concentrated, thereby causing the electric field in the gate insulating film 107 at the bottom of the first trench V1 to be extremely high. Long-term high electric field stress will cause the quality of the gate insulating film 107 to degrade, and the reliability of the device to fail. In the semiconductor device provided in the present application, the electrode 108 grounded is arranged below the gate insulating film 107, and the zero potential of the electrode 108 will make most of the electric field lines terminate at the electrode 108, thereby reducing the electric field lines entering the gate insulating film 107, and thus effectively reducing the electric field in the gate insulating film 107 at the bottom of the first trench V1, and improving the long-term working reliability (robustness) of the device.

[0052] The thickness of the electrode is not limited in the present application, and can be set according to the requirements of the device.

[0053] In the present application, the material of the electrode can be heavily doped polysilicon, or other materials with good conductive properties such as metal, which is not limited herein.

[0054] In the present application, the semiconductor substrate can be a silicon carbide single crystal substrate doped with a pentavalent element. The drift layer can be formed by ion implantation in an N-type semiconductor layer to form P-type pillar regions, wherein the ion implantation depth of the P-type pillar regions can be less than the thickness of the N-type semiconductor layer, and the regions between adjacent P-type pillar regions are N-type pillar regions. In the drift layer, the doping concentration of the N-type pillar regions is generally less than the doping concentration of the semiconductor substrate.

[0055] In the present application, the first semiconductor region (P+) in the semiconductor layer, the P-well, the source region (N+), the second semiconductor region (N), and the third semiconductor region (P++) mentioned later, the fourth semiconductor region (P+), and the fifth semiconductor region (P+) can be formed by doping the semiconductor layer. Among them, the source region (N+) is an N-type semiconductor region, the P-well is a P-type semiconductor region, the main impurity doped in the N-type semiconductor region is N-type impurity, such as phosphorus (P) or arsenic (As) and the like, and the main impurity doped in the P-type semiconductor region is P-type impurity, such as boron (B) or gallium (Ga) and the like. The P-well refers to the P-type impurity doped in the N-type semiconductor layer with a concentration sufficient to neutralize the N-type semiconductor layer and make it have P-type characteristics.

[0056] It should be noted that the comparison of the doping concentrations of two regions in the present application only refers to the comparison of the concentrations of the impurities doped in the two regions, and the composition of the impurities is not limited, that is, the composition of the impurities can be the same or different; the material of the substrate used for doping the impurities can be the same or different.

[0057] In the present application, for each N-type semiconductor region: the semiconductor substrate (N++), the N-type pillar region (N), the second semiconductor region (N), and the source region (N+); the doping concentration of the general semiconductor substrate (N++) is the highest, the doping concentration of the source region (N+) is the second, and the doping concentration of the N-type pillar region (N) and the second semiconductor region (N) is the lowest. The doping concentrations of the N-type pillar region (N) and the second semiconductor region (N) are similar, but are not limited to the same doping concentration. For example, in order to reduce the on-resistance of the SiC MOSFET, the doping concentration of the second semiconductor region (N) is generally higher than that of the N-type pillar region (N).

[0058] In the present application, for each P-type semiconductor region: the P-type pillar region (P), the first semiconductor region (P+), and the P-well (P); the doping concentration of the first semiconductor region (P+) is generally greater than the doping concentration of the P-type pillar region (P) and the doping concentration of the P-well (P). Among them, the doping concentrations of the P-type pillar region (P) and the P-well (P) are similar, but are not limited to the same doping concentration.

[0059] The semiconductor device provided by the embodiments of the present application is mainly provided for the P-type column region under the gate 104. In the specific implementation, only part of the P-type column region 1022 in the drift layer 102 is under the gate 104, and the other part of the P-type column region 1022 is not under the gate 104. The P-type column region 1022 under the gate 104 is the first P-type column region 1022a, and the other P-type column region 1022 is the second P-type column region 1022b. The present application does not limit the way of electrically connecting the second P-type column region 1022b and the source 105.

[0060] Continuing to refer to Figure 3 , the semiconductor device can further include a third semiconductor region (P++) 1035. The third semiconductor region 1035 is a P-type semiconductor region, which is arranged in the semiconductor layer 103 and is between the second P-type column region 1022b and the source 105; the third semiconductor region 1035 is in contact with the source 105 and the second P-type column region 1022b; and the doping concentration of the third semiconductor region 1035 is greater than the doping concentration of the second P-type column region 1022b. Thus, the second P-type column region 1022b is in good electrical connection with the source 105 through the third semiconductor region 1035.

[0061] In the specific implementation, in order to make the third semiconductor region 1035 in the semiconductor layer 103 in contact with the second P-type column region 1022b and the source 105, the thickness of the third semiconductor region 1035 needs to be the same as the thickness of the semiconductor layer 103, thereby increasing the process difficulty of the third semiconductor region 1035.

[0062] Therefore, optionally, in order to reduce the process difficulty, in an embodiment, referring to Figure 4 , Figure 4 Fig. 8 shows a structure diagram of a semiconductor device provided by another embodiment of the present application. The semiconductor device can further include a fourth semiconductor region (P+) 1036. The fourth semiconductor region 1036 is a P-type semiconductor region, which is arranged in the semiconductor layer 103 and is between the second P-type column region 1022b and the third semiconductor region 1035; the fourth semiconductor region 1036 is in contact with the third semiconductor region 1035 and the second P-type column region 1022b; and the doping concentration of the fourth semiconductor region 1036 is less than the doping concentration of the third semiconductor region 1035 and greater than the doping concentration of the P-type column region 1022. Thus, the fourth semiconductor region 1036 can be formed first, and then the third semiconductor region 1035 can be formed, thereby reducing the process difficulty.

[0063] In the specific implementation, the doping concentration of the fourth semiconductor region 1036 can be similar to the doping concentration of the first semiconductor region 1034, but is not limited to the same doping concentration.

[0064] For example, the fourth semiconductor region 1036 has the same doping concentration as the first semiconductor region 1034, so that the fourth semiconductor region 1036 and the first semiconductor region 1034 can be prepared at the same time, thereby simplifying the process steps.

[0065] In another embodiment, referring to Figure 5 , Figure 5 A structure diagram of a semiconductor device provided by another embodiment of the present application is shown. The semiconductor device further includes a second trench V2 arranged in the semiconductor layer 103, the source 105 fills the second trench V2, and the third semiconductor region 1035 includes a first extension 1035a at the bottom of the second trench V2 and a second extension 1035b at the sidewall of the second trench V2. In this way, by arranging the second trench V2, the thickness of the third semiconductor region 1035 can be reduced, thereby reducing the process difficulty.

[0066] In the present application, referring to Figures 3 to 5 , the P-well 1031 and the source region 1032 are arranged on both sides of the gate 104 to ensure that there are MOS conductive channels on both sides of the gate of the SiC MOSFET.

[0067] The present application does not limit the shape of the first trench, for example, as shown in Figures 3 to 5 , the first trench V1 is rectangular in the cross section perpendicular to the semiconductor substrate 101, or as shown in Figure 6 , the first trench V1 is trapezoidal in the cross section perpendicular to the semiconductor substrate 101, and the farther the first trench V1 is from the semiconductor substrate 101 in the cross section parallel to the semiconductor substrate 101, the larger the area of the cross section, that is, the area of the top surface of the first trench V1 (the cross section located on the side far from the semiconductor substrate 101) is larger than the area of the bottom surface of the first trench V1 (the cross section located on the side close to the semiconductor substrate 101).

[0068] In order to improve the electrical contact between the electrode 108 and the first P-type pillar region 1022a, referring to Figure 7 , Figure 7 A structure diagram of a semiconductor device provided by another embodiment of the present application is shown. The first semiconductor region 1034 can include a first extension 1034a at the bottom of the first trench V1 and a second extension 1034b at the sidewall of the first trench V1. In this way, when the semiconductor device includes multiple gates, part of the first semiconductor region 1034 can be arranged to include the first extension 1034a and the second extension 1034b, that is, only the MOS conductive channel on one side of part of the gate is sacrificed, compared with the related art in which the MOS conductive channel on one side of each gate is sacrificed, the electrical contact between the electrode 108 and the first P-type pillar region 1022a can be improved, and the on-resistance of the semiconductor device can be reduced.

[0069] In a specific implementation, in the semiconductor device provided by the embodiments of the present application, the semiconductor layer 103 can have a plurality of first grooves V1; in order to improve the electrical contact between the electrode 108 and the first P-type column region 1022a, as shown, the semiconductor layer 103 further has at least one second groove V2 between two adjacent first grooves V1; the semiconductor layer 103 further includes a P-type fifth semiconductor region (P+) 1037 at the bottom of the second groove V2, the fifth semiconductor region 1037 has a doping concentration greater than that of the P-type column region 1022; the fifth semiconductor region 1037 is in contact with the source electrode 105 and the P-type column region 1022. Figure 8

[0070] In a specific implementation, the doping concentration of the fifth semiconductor region can be similar to that of the first semiconductor region, but is not limited to the same doping concentration.

[0071] For example, the doping concentration of the fifth semiconductor region is the same as that of the first semiconductor region, so that the fifth semiconductor region and the first semiconductor region can be prepared at the same time during preparation, thereby simplifying the process steps.

[0072] In a specific implementation, the second groove can be arranged only between part of the two adjacent first grooves.

[0073] For example, as shown, the fifth semiconductor region 1037 and the first semiconductor region 1034 adjacent thereto are in communication, i.e., the fifth semiconductor region 1037 and the first semiconductor region 1034 are in an integrated structure. Figure 9

[0074] Further, in order to increase the contact area between the source electrode 104 and the fifth semiconductor region 1037, the second groove V2 is in communication with the two first grooves V1 adjacent thereto. That is, the two adjacent first grooves V1 and the second groove V2 between the two adjacent first grooves V1 are in communication, so that the two gate electrodes 104 and part of the source electrode 105 are arranged in the same groove, and the gate electrode 104 and the source electrode 105 are isolated by the gate insulating film 107.

[0075] Correspondingly, the embodiments of the present application further provide an integrated circuit, which can include a circuit board and any one of the semiconductor devices provided by the above-mentioned embodiments of the present application, and the semiconductor device is arranged on the circuit board. Since the principle of solving the problem of the electronic circuit is similar to that of the above-mentioned semiconductor device, the implementation of the electronic circuit can be referred to the implementation of the above-mentioned semiconductor device, and the repeated parts will not be described herein.

[0076] ​​Obviously, many modifications and variations of the present application are possible in light of the above teachings. It is, therefore, to be understood that within the scope of the appended claims and their equivalents, the application can be practiced otherwise than as specifically described.

Claims

1. A semiconductor device, characterized by, Comprising: a semiconductor substrate of N type; a drift layer provided on the semiconductor substrate, the drift layer including N type column regions and P type column regions arranged in parallel alternately and repeatedly; a semiconductor layer provided on the drift layer; a first trench provided in the semiconductor layer and in a region corresponding to the P type column region; a gate electrode provided in the first trench with a gate insulating film interposed therebetween; an electrode provided in the first trench between the gate electrode and the P type column region with the gate insulating film interposed therebetween; a first semiconductor region of P type provided in the semiconductor layer between the electrode and the P type column region, in contact with the electrode and the P type column region, and having a higher doping concentration than the P type column region; a P well provided in the semiconductor layer on a side wall of the first trench; a source region provided in the semiconductor layer on the P well; a second semiconductor region of N type provided in the semiconductor layer between the P well and the N type column region; a source electrode provided on the semiconductor layer, in contact with the source region and electrically connected to the electrode; a drain electrode provided on a side of the semiconductor substrate distal from the drift layer.

2. The semiconductor device of claim 1, wherein, The P type column region below the gate electrode is a first P type column region, and the other P type column regions are second P type column regions. The semiconductor device further comprises: a third semiconductor region of P type provided in the semiconductor layer between the second P type column region and the source electrode; the third semiconductor region is in contact with the source electrode and the second P type column region; the third semiconductor region has a higher doping concentration than the second P type column region.

3. The semiconductor device of claim 2, wherein, The semiconductor device further comprises: a fourth semiconductor region of P type provided in the semiconductor layer between the second P type column region and the third semiconductor region; the fourth semiconductor region is in contact with the third semiconductor region and the second P type column region; the fourth semiconductor region has a lower doping concentration than the third semiconductor region and a higher doping concentration than the P type column region.

4. The semiconductor device of claim 3, wherein, The fourth semiconductor region has the same doping concentration as the first semiconductor region.

5. The semiconductor device of claim 2, wherein, The semiconductor device further comprises a second trench provided in the semiconductor layer, the source electrode filling the second trench; the third semiconductor region includes a first extension at a bottom of the second trench and a second extension at a side wall of the second trench.

6. The semiconductor device according to any one of claims 1 to 5, wherein The first trench is trapezoidal in cross section perpendicular to the semiconductor substrate, and the farther the first trench is from the semiconductor substrate in cross section parallel to the semiconductor substrate, the larger the area of the cross section of the first trench parallel to the semiconductor substrate.

7. The semiconductor device according to any one of claims 1 to 6, wherein The first semiconductor region includes a first extension at the bottom of the first trench and a second extension at a sidewall of the first trench.

8. The semiconductor device of claim 1, wherein, The semiconductor layer has a plurality of the first trenches therein; and the semiconductor layer also has at least one second trench therein, the second trench being between two adjacent first trenches. The semiconductor layer also includes a fifth semiconductor region at the bottom of the second trench, the fifth semiconductor region being a P-type semiconductor region, and the fifth semiconductor region having a doping concentration greater than that of the P-type pillar region. The fifth semiconductor region is in contact with the source and the P-type pillar region.

9. The semiconductor device of claim 8, wherein, The second trench is in communication with two adjacent first trenches.

10. The semiconductor device according to claim 8 or 9, wherein The fifth semiconductor region has the same doping concentration as the first semiconductor region.

11. The semiconductor device of claim 10, wherein, The fifth semiconductor region and the first semiconductor region adjacent thereto are in one-piece structure.

12. An integrated circuit, characterized by A semiconductor device as claimed in any one of claims 1 to 11 is provided on a circuit board.

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