Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a method for forming the same, the method comprising: forming a dummy gate dielectric layer on the surface of a fin; forming a dummy gate structure spanning the fin on the dummy gate dielectric layer, the dummy gate structure including a dummy gate and a first sidewall of the dummy gate sidewall, the dummy gate structure being located on a portion of the top surface and a portion of the sidewall surface of the fin; forming source / drain layers within the fins on both sides of the dummy gate structure; forming an interlayer dielectric layer on the substrate and the surface of the source / drain layers, the interlayer dielectric layer also being located on the sidewall of the dummy gate structure and exposing the top surface of the dummy gate; removing the dummy gate and a portion of the fin at the bottom of the dummy gate, forming an opening within the interlayer dielectric layer; forming a second sidewall on the sidewall surface of the opening; and forming a gate within the opening after forming the second sidewall, thereby reducing the probability of leakage current and improving production yield and device performance stability.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] In the existing semiconductor field, the FinFET is an emerging multi-gate device. Compared with the planar metal-oxide-semiconductor field-effect transistor (MOSFET), the FinFET has stronger short-channel rejection capability and higher operating current, and is now widely used in various semiconductor devices.

[0003] Metal interconnect structures are indispensable in semiconductor devices, used to interconnect active regions, transistors, or different metal lines to achieve signal transmission and control. Generally, in the back-end interconnect process of semiconductor device manufacturing, the first conductive layer (M1) needs to form an electrical connection with the underlying active device structure (including source / drain regions and gate structure regions). Therefore, before forming the first conductive layer, a local interconnect structure of the semiconductor device is usually pre-formed. This local interconnect structure includes a zeroth conductive layer (MO) electrically connected to the underlying source / drain regions, and a zeroth gate conductive layer (MOG) electrically connected to the gate structure.

[0004] With the further development of semiconductor technology, transistor dimensions have shrunk to below a few nanometers. The size of the FinFET itself has been reduced to its limit, and the distance between the zeroth gate conductive layer and the zeroth conductive layer has also decreased accordingly. Existing FinFET technology has long been plagued by the failure mode of short circuit between the zeroth gate conductive layer and the zeroth conductive layer. That is, a channel is generated on the surface of the source / drain region, connecting the zeroth gate conductive layer and the zeroth conductive layer, thereby creating a short circuit between the source / drain and the gate.

[0005] The semiconductor structures formed by existing fin field-effect transistor technology need further improvement. Summary of the Invention

[0006] The technical problem solved by this invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of the formed semiconductor structure.

[0007] To address the aforementioned technical problems, the present invention provides a semiconductor structure comprising: a substrate, the substrate including a base and a fin located on a portion of the base; an interlayer dielectric layer located on the substrate, the interlayer dielectric layer having an opening that spans the fin and is located within a portion of the fin, the bottom surface of the opening being lower than the top surface of the fin; a first sidewall located between the sidewall of the opening and the interlayer dielectric layer, the first sidewall spanning the fin and located on the surface of the sidewall of the fin; a second sidewall located on the surface of the sidewall of the opening; a gate located within the opening, the gate structure including the first sidewall and the gate; and source / drain layers located within the fins on both sides of the gate structure.

[0008] Optionally, the gate includes a gate oxide layer located within the opening, a work function layer located on the surface of the gate oxide layer, and a gate layer located on the surface of the work function layer.

[0009] Optionally, the depth of the opening within the fin is less than or equal to 200 angstroms.

[0010] Optionally, the thickness of the second sidewall in the direction perpendicular to the opening sidewall is less than or equal to 50 angstroms.

[0011] Optionally, it may also include: a contact hole located within the interlayer dielectric layer, the contact hole exposing the source / drain layer surface; and a conductive layer located within the contact hole.

[0012] Accordingly, the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a base, a fin located on the base, and an isolation structure, the isolation structure being located on a portion of the sidewall of the fin, and the top surface of the isolation structure being lower than the top surface of the fin; forming a dummy gate dielectric layer on the surface of the fin; forming a dummy gate structure spanning the fin on the dummy gate dielectric layer, the dummy gate structure including a dummy gate and a first sidewall of the dummy gate sidewall, the dummy gate structure being located on a portion of the top surface and a portion of the sidewall surface of the fin; forming source / drain layers in the fins on both sides of the dummy gate structure; forming an interlayer dielectric layer on the substrate and the surface of the source / drain layers, the interlayer dielectric layer also being located on the sidewall of the dummy gate structure and exposing the top surface of the dummy gate; removing the dummy gate and a portion of the fin at the bottom of the dummy gate, forming an opening in the interlayer dielectric layer; forming a second sidewall on the sidewall surface of the opening, the bottom surface of the second sidewall being lower than the top surface of the fin; and forming a gate in the opening after forming the second sidewall.

[0013] Optionally, the method for forming the second sidewall is as follows: forming a first dielectric material layer inside the opening and on the surface of the interlayer dielectric layer; etching back the first dielectric material layer until the bottom of the opening and the top surface of the interlayer dielectric layer are exposed.

[0014] Optionally, the method for forming the opening includes: removing the dummy gate, forming an initial opening in the interlayer dielectric layer, the initial opening exposing a portion of the fin and the first sidewall; etching the fin exposed by the initial opening to form the opening.

[0015] Optionally, after forming the second sidewall and before forming the gate, the method further includes: removing the dummy gate dielectric layer from the fin surface exposed by the opening.

[0016] Optionally, after forming the gate, the method further includes: forming a contact hole in the interlayer dielectric layer, the contact hole exposing the source / drain layer surface; and forming a conductive layer within the contact hole.

[0017] Optionally, the material of the second sidewall includes a dielectric material, which includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbon oxynitride.

[0018] Optionally, the gate includes a gate oxide layer and a gate layer located on the surface of the gate oxide layer; the method of forming the gate includes: forming a gate oxide layer on the surface of the fin exposed by the opening; and forming a gate layer in the opening after forming the gate oxide layer.

[0019] Optionally, the material of the dummy gate dielectric layer includes silicon oxide; the material of the gate oxide layer includes a high-k dielectric material.

[0020] Optionally, the formation process of the second sidewall includes atomic layer deposition.

[0021] Optionally, the dummy gate may be made of silicon; the gate may be made of metal.

[0022] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0023] In the semiconductor structure formation method provided by the present invention, the dummy gate and a portion of the fins at the bottom of the dummy gate are removed, an opening is formed in the interlayer dielectric layer, and a second sidewall is formed on the sidewall surface of the opening. The second sidewall can block the penetration of etching solution into the source / drain layer surface during subsequent etching processes, reducing the occurrence of interconnected channels between the gate and the source / drain layer surfaces. This reduces the filling of the gate material in the channels during subsequent gate formation, making the gate and source / drain layers conductive, reducing the probability of leakage, and improving production yield and device performance stability.

[0024] Furthermore, after forming the second sidewall and before forming the gate, the process further includes: removing the dummy gate dielectric layer from the fin surface exposed by the opening. The process of removing the dummy gate dielectric layer occurs after forming the second sidewall. The second sidewall can prevent the etching solution in the process of removing the dummy gate dielectric layer from penetrating into the source / drain layer surface, reducing the possibility of interconnecting channels between the gate and the source / drain layer surfaces. This reduces the filling of the gate material in the channels during subsequent gate formation, making the gate and source / drain layers conductive, reducing the probability of leakage, and improving production yield and device performance stability.

[0025] Furthermore, after forming the gate, the method further includes: forming a contact hole in the interlayer dielectric layer, the contact hole exposing the source / drain layer surface; forming a conductive layer in the contact hole, thereby reducing the probability of a short circuit between the gate and the conductive layer, thereby improving production yield and device performance stability. Attached Figure Description

[0026] Figures 1 to 5 This is a schematic diagram of a semiconductor structure formation process;

[0027] Figures 6 to 13 This is a schematic diagram of the steps in the method for forming a semiconductor structure according to an embodiment of the present invention. Detailed Implementation

[0028] It should be noted that the terms "surface" and "on" in this specification are used to describe the relative spatial position and are not limited to whether there is direct contact.

[0029] As described in the background section, the performance of semiconductor structures formed using existing fin field-effect transistor technology urgently needs improvement. This paper will now illustrate and analyze one such semiconductor structure.

[0030] Figures 1 to 5 This is a schematic diagram of the semiconductor structure formation process.

[0031] Please refer to Figure 1 and Figure 2 , Figure 2 yes Figure 1A cross-sectional structural schematic diagram obtained along the dashed line shows a substrate, the substrate including a base 100 and a fin 101 located on a portion of the base 100, an isolation structure 102 located on the base 100, the isolation structure 102 also located on a portion of the sidewall of the fin 101, and the top surface of the isolation structure 102 being lower than the top surface of the fin 101; a dummy gate dielectric layer 103 forming on the surface of the fin 101; and a dummy gate structure forming across the fin 101, the dummy gate structure including a dummy gate 104 and a protective layer 105, the dummy gate structure being located on a portion of the top surface and a portion of the sidewall surface of the fin 101, and on a portion of the top surface of the isolation structure 102.

[0032] Please refer to Figure 2 and Figure 3 , Figure 2 yes Figure 3 The structural diagram of the interlayer dielectric layer is omitted. Figure 3 yes Figure 2 A cross-sectional view of the EE1 shows openings (not shown) formed in the fins 101 on both sides of the dummy gate structure; a source / drain layer 106 is formed in the openings; an interlayer dielectric layer 107 is formed on the substrate and on the surface of the source / drain layer 106, the interlayer dielectric layer 107 is also located on the sidewall of the dummy gate structure and exposes the top surface of the dummy gate 104.

[0033] Please refer to Figure 4 , Figure 4 Same view direction Figure 3 Remove the dummy gate 104 to form an initial opening (not shown in the figure) in the interlayer dielectric layer 106; remove the portion of the dummy gate dielectric layer 103 exposed by the initial opening to form a first opening 108.

[0034] Please refer to Figure 5 A gate 109 is formed within the opening 108; a dielectric layer 110 is formed on the surface of the interlayer dielectric layer 106 and the surface of the gate 109; a second opening (not shown in the figure) is formed within the dielectric layer 110 and the interlayer dielectric layer 106, the second opening exposing the surface of the source / drain layer 106; and a conductive layer 111 is formed within the second opening.

[0035] In the above method, the protective layer 105 and the fin 101 are not tightly bonded, resulting in a gap surface A. During the process of removing part of the dummy gate dielectric layer 103 exposed by the initial opening to form the first opening 108, the etching solution can easily enter the surface of the source / drain layer 106 through the gap surface A. Furthermore, the dummy gate dielectric layer between the protective layer 105 and the fin 101 is also easily etched away, making it easier for the etching solution to enter the surface of the source / drain layer 106 through the gap surface A, forming a channel B connecting the source / drain layer 106 and the first opening 108. Subsequently, a gate 109 is formed within the first opening 108. During the formation of the gate 109, metal material is filled into the channel B. This metal material can cause leakage current in the device, adversely affecting its performance. After the conductive layer 111 is formed on the surface of the source / drain layer 106, the metal material increases the risk of the gate 109 and the conductive layer 111 becoming conductive, leading to device leakage or even failure.

[0036] To address the aforementioned issues, this invention provides a method for forming a semiconductor structure by removing the dummy gate and a portion of the fins at the bottom of the dummy gate, forming an opening within the interlayer dielectric layer, and forming a second sidewall on the sidewall surface of the opening. The second sidewall can block the penetration of etching solution into the source / drain layer surface during subsequent etching processes, reducing the likelihood of interconnected channels between the gate and source / drain layer surfaces. This, in turn, reduces the filling of the gate material within the channels during subsequent gate formation, ensuring conduction between the gate and source / drain layers, reducing the probability of leakage current, and improving production yield and device performance stability.

[0037] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0038] Figures 6 to 13 This is a schematic diagram of the steps in the method for forming a semiconductor structure according to an embodiment of the present invention.

[0039] Please refer to Figure 6 and Figure 7 A substrate is provided, the substrate including a base 200, a fin 201 located on the base 200, and an isolation structure 202, the isolation structure 202 being located on a portion of the sidewall of the fin 201, and the top surface of the isolation structure 202 being lower than the top surface of the fin 201; a dummy gate dielectric layer 203 is formed on the surface of the fin 201; a dummy gate structure is formed on the dummy gate dielectric layer 203 spanning the fin, the dummy gate structure including a dummy gate 204 and a first sidewall 205 of the sidewall of the dummy gate 204, the dummy gate structure being located on a portion of the top surface and a portion of the sidewall surface of the fin 201.

[0040] In this embodiment, the first sidewall 205 is also located on the top surface of the dummy gate 204.

[0041] In this embodiment, the dummy gate 204 is located on the top surface of a portion of the isolation structure 202.

[0042] The material of the pseudo-gate dielectric layer 203 includes silicon oxide.

[0043] The dummy gate 204 is made of silicon. In this embodiment, the dummy gate 204 is made of polycrystalline silicon. In other embodiments, the dummy gate 204 can be made of amorphous silicon, silicon carbide, etc. The dummy gate 204 occupies space for the subsequent formation of the gate.

[0044] Please refer to Figure 8 Source / drain layers 206 are formed in the fins 201 on both sides of the dummy gate structure; an interlayer dielectric layer 207 is formed on the substrate and the surface of the source / drain layers 206, the interlayer dielectric layer 207 is also located on the sidewall of the dummy gate structure and exposes the top surface of the dummy gate 204.

[0045] In this embodiment, the surface of the source / drain layer 206 is flat. In other embodiments, the surface of the source / drain layer 206 may be V-shaped. The morphology of the source / drain layer surface is related to the material and growth process of the source / drain layer.

[0046] Subsequently, the dummy gate 204 and a portion of the fin 201 at the bottom of the dummy gate 204 are removed, and an opening is formed within the interlayer dielectric layer 207. The method for forming the opening is described in [reference needed]. Figures 9 to 10 .

[0047] Please refer to Figure 9 Remove the dummy gate 204 and form an initial opening 208 in the interlayer dielectric layer 207, the initial opening 208 exposing part of the fin 201 and the first sidewall 205.

[0048] Specifically, the initial opening 208 exposes a portion of the pseudo-gate dielectric layer 203 on the surface of the fin 201.

[0049] The process for removing the dummy gate 204 includes one or a combination of dry etching and wet etching. In this embodiment, the process for removing the dummy gate 204 is a wet etching process. The solution used in the wet etching process includes tetramethylammonium hydroxide or potassium hydroxide solution, thereby enabling the dummy gate 204 to have a large etching selectivity relative to the substrate during the etching process for removing the dummy gate 204.

[0050] Please refer to Figure 10The fin portion 201 exposed by the initial opening 208 is etched to form the opening 209.

[0051] The etching process for exposing the fin 201 through the initial opening 208 includes one or a combination of wet etching and dry etching. In this embodiment, the etching process for exposing the fin 201 through the initial opening 208 is a dry etching process. The dry etching process is beneficial for forming a better opening morphology.

[0052] The depth of the opening 209 within the fin 201 is less than or equal to 200 angstroms. This depth refers to the dimension along the normal direction of the substrate 200 surface. The range of the opening 209 is chosen such that if the depth of the opening 209 is too large, it will affect the performance of the formed device, such as the device channel length. The depth of the opening 209 is at least the dimension of the dummy gate dielectric layer 203 along the normal direction of the substrate, so that the formed second sidewall 210 can prevent the etching solution from flowing into the gap between the first sidewall 205 and the fin 201 during subsequent etching.

[0053] The thickness of the second sidewall 210 in the direction perpendicular to the sidewall of the opening 209 is less than or equal to 50 angstroms. The reason for choosing the thickness range of the second sidewall 210 is that if the second sidewall 210 is too thick, it will be detrimental to the performance of the gate formed subsequently, and if the second sidewall 210 is too thin, it may be etched and damaged during subsequent etching, thus failing to play a blocking role.

[0054] Please refer to Figure 11 A second sidewall 210 is formed on the sidewall surface of the opening 209.

[0055] The method for forming the second sidewall 210 is as follows: a first dielectric material layer (not shown in the figure) is formed inside the opening 209 and on the surface of the interlayer dielectric layer 207; the first dielectric material layer is etched back until the bottom of the opening 209 and the top surface of the interlayer dielectric layer 207 are exposed.

[0056] The material of the second sidewall 210 includes a dielectric material, which includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbon oxynitride.

[0057] The formation process of the second sidewall 210 includes atomic layer deposition (ALD). ALD facilitates the provision of uniformity in the formed material film, thereby improving the performance of the second sidewall 210.

[0058] The second sidewall 210 can block the etching solution from penetrating into the surface of the source / drain layer 206 during the subsequent etching process, reducing the possibility of a communication channel being formed between the gate and the surface of the source / drain layer 206. This reduces the filling of the gate material in the channel during the subsequent gate formation process, thus reducing the possibility of the gate and the source / drain layer 206 being connected, reducing the probability of leakage, and improving production yield and device performance stability.

[0059] Subsequently, after the second sidewall 210 is formed, a gate is formed within the opening 209.

[0060] In this embodiment, after the second sidewall 210 is formed and before the gate is formed, the method further includes: removing the dummy gate dielectric layer 203 from the surface of the fin 201 exposed by the opening 209.

[0061] After the formation of the second sidewall 210, the process of removing the dummy gate dielectric layer 203 can prevent the etching solution in the process of removing the dummy gate dielectric layer 203 from penetrating into the surface of the source / drain layer 206, reducing the possibility of interconnecting channels between the gate and the source / drain layer 206. This reduces the filling of the gate material in the channels during subsequent gate formation, making the gate and source / drain layer 206 conductive, reducing the probability of leakage, and improving production yield and device performance stability.

[0062] In other embodiments, the pseudo-gate dielectric layer on the surface of the fin is etched away during etching processes such as the etch-back process for forming the second sidewall.

[0063] Please refer to Figure 12 After the second sidewall 210 is formed, a gate 211 is formed in the opening 209.

[0064] The gate 211 includes a gate oxide layer (not shown in the figure) and a work function layer (not shown in the figure) located on the surface of the gate oxide layer, and a gate layer located on the surface of the work function layer; the method of forming the gate 211 includes: forming a gate oxide layer on the surface of the fin 201 exposed by the opening 209; and forming a gate layer in the opening 209 after forming the gate oxide layer.

[0065] The gate 211 is made of metal. In this embodiment, the gate layer is made of tungsten. In other embodiments, the gate layer can be made of copper, aluminum, cobalt, etc.

[0066] The gate oxide layer is made of a high-k dielectric material. The high-k (i.e., dielectric constant K ≥ 3.9) dielectric material significantly reduces the quantum tunneling effect of the gate dielectric layer, thereby effectively improving gate leakage current and the resulting power consumption. In this embodiment, the high-k dielectric material is hafnium oxide. In other embodiments, the gate dielectric layer further includes a silicon nitride layer, the silicon nitride layer being formed using an in-situ water vapor generation process. The silicon nitride layer is located between the high-k dielectric layer and the trench surface to improve the interface states between the high-k dielectric material and the substrate silicon.

[0067] Please refer to Figure 13 After forming the gate 211, the method further includes: forming a contact hole (not shown in the figure) in the interlayer dielectric layer 207, the contact hole exposing the surface of the source / drain layer 206; and forming a conductive layer 212 in the contact hole.

[0068] In the technical solution described in this embodiment, the second sidewall 210 helps to reduce the occurrence of interconnected channels between the gate 211 and the source / drain layer 206, further reducing the probability of short circuits between the gate 211 and the conductive layer 212, thereby improving production yield and device performance stability.

[0069] In this embodiment, before the conductive layer 212 is formed and after the gate 211 is formed, a dielectric layer 213 is also formed on the surface of the gate 211 and the interlayer dielectric layer 207, and the contact hole is also located in the dielectric layer 213.

[0070] Accordingly, this invention also provides a semiconductor structure, please refer to [the relevant documentation]. Figure 13 The system includes: a substrate, the substrate comprising a base 200, a fin 201 located on the base 200, and an isolation structure 202, the isolation structure 202 being located on a portion of the sidewall of the fin 201, and the top surface of the isolation structure 202 being lower than the top surface of the fin 201; and an interlayer dielectric layer 207 located on the substrate, the interlayer dielectric layer 207 having an opening 209 therein, the opening 209 spanning the fin 201 and located within a portion of the fin 201, the bottom surface of the opening 209 being lower than the top surface of the fin 201. The fin 201 includes: a first sidewall 205 located between the sidewall of the opening 209 and the interlayer dielectric layer 207, the first sidewall 205 spanning the fin 201 and located on a portion of the sidewall surface of the fin 201; a second sidewall 210 located on the sidewall surface of the opening 209, the bottom surface of the second sidewall 210 being lower than the top surface of the fin 201; a gate 211 located within the opening 209, the gate structure including the first sidewall 205 and the gate 211; and source / drain layers 206 located within the fins 201 on both sides of the gate structure.

[0071] The gate 211 includes a gate oxide layer (not shown in the figure) located within the opening 209, a work function layer (not shown in the figure) located on the surface of the gate oxide layer, and a gate layer (not shown in the figure) located on the surface of the work function layer.

[0072] The depth of the opening 209 within the fin 201 is less than or equal to 200 angstroms.

[0073] The thickness of the second sidewall 210 in the direction perpendicular to the sidewall of the opening 209 is less than or equal to 50 angstroms.

[0074] The semiconductor structure further includes: a contact hole (not shown in the figure) located in the interlayer dielectric layer 207, the contact hole exposing the surface of the source / drain layer 206; and a conductive layer 212 located in the contact hole.

[0075] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: A substrate, the substrate including a base, a fin located on the base and an isolation structure, the isolation structure being located on a sidewall of the fin portion, and the top surface of the isolation structure being lower than the top surface of the fin; An interlayer dielectric layer is located on the substrate, the interlayer dielectric layer having an opening that spans the fin and is located within a portion of the fin, the bottom surface of the opening being lower than the top surface of the fin; A first sidewall is located between the opening sidewall and the interlayer medium layer, the first sidewall spans the fin and is located on a portion of the fin sidewall surface; A second sidewall located on the surface of the opening sidewall, the bottom surface of the second sidewall being lower than the top surface of the fin; A gate located within the opening, the gate structure including the first sidewall, the second sidewall, and the gate; The source / drain layers are located in the fins on both sides of the gate structure.

2. The semiconductor structure as described in claim 1, characterized in that, The gate includes a gate oxide layer located within the opening, a work function layer located on the surface of the gate oxide layer, and a gate layer located on the surface of the work function layer.

3. The semiconductor structure as described in claim 1, characterized in that, The depth of the opening within the fin is less than or equal to 200 angstroms.

4. The semiconductor structure as described in claim 1, characterized in that, The thickness of the second sidewall in the direction perpendicular to the opening sidewall is less than or equal to 50 angstroms.

5. The semiconductor structure as described in claim 1, characterized in that, Also includes: A contact hole located within the interlayer dielectric layer, the contact hole exposing the source / drain layer surface; The conductive layer located within the contact hole.

6. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including a base and fins located on a portion of the base; A pseudo-gate dielectric layer is formed on the surface of the fin; A pseudo-gate structure is formed across the fin on the pseudo-gate dielectric layer. The pseudo-gate structure includes a pseudo-gate and a first sidewall of the pseudo-gate sidewall. The pseudo-gate structure is located on a portion of the top surface and a portion of the sidewall surface of the fin. Source and drain layers are formed in the fins on both sides of the pseudo-gate structure; An interlayer dielectric layer is formed on the substrate and the source / drain layer surfaces. The interlayer dielectric layer is also located on the sidewall of the dummy gate structure and exposes the top surface of the dummy gate. Remove the dummy gate and a portion of the fin at the bottom of the dummy gate to form an opening within the interlayer dielectric layer; A second sidewall is formed on the surface of the opening sidewall; After the second sidewall is formed, a gate is formed within the opening.

7. The method for forming a semiconductor structure as described in claim 6, characterized in that, The method for forming the second sidewall is as follows: a first dielectric material layer is formed inside the opening and on the surface of the interlayer dielectric layer; The first dielectric material layer is etched back until the bottom of the opening and the top surface of the interlayer dielectric layer are exposed.

8. The method for forming a semiconductor structure as described in claim 6, characterized in that, The method for forming the opening includes: removing the dummy gate, forming an initial opening in the interlayer dielectric layer, the initial opening exposing a portion of the fin and the first sidewall; etching the fin exposed by the initial opening to form the opening.

9. The method for forming a semiconductor structure as described in claim 6, characterized in that, After forming the second sidewall and before forming the gate, the method further includes: removing the dummy gate dielectric layer from the fin surface exposed by the opening.

10. The method for forming a semiconductor structure as described in claim 6, characterized in that, After forming the gate, the method further includes: forming a contact hole in the interlayer dielectric layer, the contact hole exposing the source / drain layer surface; and forming a conductive layer within the contact hole.

11. The method for forming a semiconductor structure as described in claim 6, characterized in that, The material of the second sidewall includes a dielectric material, which includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbon oxynitride.

12. The method for forming a semiconductor structure as described in claim 6, characterized in that, The gate includes a gate oxide layer and a gate layer located on the surface of the gate oxide layer; the method of forming the gate includes: forming a gate oxide layer on the surface of the fin exposed by the opening; and forming a gate layer in the opening after forming the gate oxide layer.

13. The method for forming a semiconductor structure as described in claim 12, characterized in that, The material of the pseudo-gate dielectric layer includes silicon oxide; the material of the gate oxide layer includes a high-k dielectric material.

14. The method for forming a semiconductor structure as described in claim 6, characterized in that, The formation process of the second sidewall includes atomic layer deposition.

15. The method for forming a semiconductor structure as described in claim 6, characterized in that, The dummy gate is made of silicon; the gate is made of metal.

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