Clock recovery circuit, corresponding device and method

Abstract

Embodiments of the present disclosure relate to clock recovery circuits, corresponding devices, and methods. The clock recovery circuit includes an input node that receives a data signal having a data rate and a digital oscillator that generates a local clock signal having a frequency higher than the data rate. A counter, clocked by the local clock signal, samples and resets its count value at rising and falling edges of the data signal, and a storage block coupled to the counter stores an updated count value in response to the current sampled count value of the counter within an update range between a lower limit and an upper limit. A threshold set is generated based on the updated count value stored in the storage block. Sampling circuitry receives and samples the data signal and provides a sampled version of the data signal in response to the counter count value reaching any threshold value.

Description

[0001] Priority claim

[0002] This application claims the benefit of Italian Patent Application No. 102021000002779, filed on October 29, 2021, which is incorporated herein by reference. Technical Field

[0003] This description relates to clock recovery circuits.

[0004] One or more embodiments may be advantageously employed in various arrangements where data is transmitted over a channel without the need for a clock signal to be transmitted along with the data.

[0005] Automatic toll payment equipment is a possible example of such an application, where simplicity, low cost and reduced power absorption are important factors. Background Art

[0006] In some communication systems, when data is received from a wireless / wired connection, no clock signal is received over the channel. The receiver samples the incoming data using the "same" clock from the transmitter, which is somehow recovered from the data.

[0007] For these applications, clock recovery circuits with (very) low current draw (low power characteristics) and good noise rejection are required.

[0008] A precise local oscillator (eg, a phase-locked loop or PLL arrangement) suitable for tuning (ie, locking) on ​​the edges of the incoming data, and a local oscillator adjusted to correctly sample the incoming data may represent an option for these purposes.

[0009] The disadvantage of these solutions is the circuit complexity, which may involve a mix of analog and digital circuits. This may draw high current, which is a penalty, for example, for systems with limited power capabilities. Summary of the Invention

[0010] It is an aim of one or more embodiments to help solve the above-mentioned problems.

[0011] According to one or more embodiments, this object is achieved by a circuit having the features described in the claims.

[0012] One or more embodiments relate to corresponding devices.A receiver for automatic toll payment may be an example of such a device.

[0013] One or more embodiments are directed to corresponding methods.

[0014] The claims are an integral part of the technical teaching provided herein with respect to the embodiments.

[0015] The circuits as illustrated herein may optionally include a coarse data detector configured to check whether the received input data has a frequency that falls within an expected range. If the received frequency is allowed, a local oscillator, such as a delay-locked loop or DLL (and possibly an associated clock divider), is activated to generate a clock based on the input data.

[0016] In the circuits illustrated herein (possibly in response to a data rate being checked to be consistent with an expected range), a phase alignment feature is activated, wherein a new clock is generated based on analysis of the edges of the input signal; based on checking for the best edge, the input data is analyzed and useful data is selected and used for clock reconstruction. The reconstructed clock is used for reception by a receiver device.

[0017] The examples shown here have very low power consumption.

[0018] In these examples, clock recovery is activated only in response to a recognized input signal indicative of received data.The clock remains in the "off" state for the remainder of the time when the switch power absorption is (at least theoretically) zero.

[0019] Furthermore, the examples shown herein are based on a delay line circuit that does not involve a calibration procedure, while a phase alignment procedure helps in detecting sufficient sampling points of the input data (Data_in).

[0020] Thus, a simple, fully digital clock recovery circuit suitable for use in, for example, wireless / wired low data rate communication systems (hundreds of Kbit / s) is provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] One or more embodiments will now be described, by way of example only, with reference to the accompanying drawings, in which:

[0022] Figure 1 is a block diagram of a conventional clock recovery circuit;

[0023] Figure 2 includes various example diagrams of signals that may be advantageously used with clock recovery circuits according to embodiments of the present description;

[0024] Figure 3 is a block diagram of a clock recovery circuit according to an embodiment of this specification;

[0025] Figure 4 is a circuit diagram of a portion of a clock recovery circuit according to an embodiment of this specification;

[0026] Figure 5A and 5B Pictured Figure 4 Auxiliary parts of the circuit and the possible temporal behavior of the signals generated therefrom;

[0027] Figure 6 Includes various example diagrams of possible temporal behavior of signals that may occur in a clock recovery circuit according to embodiments of this specification;

[0028] Figure 7 is an exemplary block diagram of a possible implementation of a portion of a clock recovery circuit according to an embodiment of the present specification;

[0029] Figure 8 yes Figure 6 Flowchart examples of possible operations to be implemented; and

[0030] Figure 9 is an example of a timing diagram for sampling an input signal according to an embodiment of the present description.

[0031] The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale.

[0032] The edges of features drawn in the figure do not necessarily indicate the end of the feature's extent. DETAILED DESCRIPTION

[0033] In the following description, various specific details are shown to provide a thorough understanding of various examples according to the described embodiments. The embodiments may be obtained without one or more of the specific details, or using other methods, components, materials, etc. In other cases, well-known structures, materials, or operations are not described or illustrated in detail so as not to obscure aspects of the embodiments.

[0034] References to "an embodiment" or "one embodiment" in the framework of this specification are intended to indicate that a particular configuration, structure, or feature associated with the embodiment is included in at least one embodiment. Therefore, phrases such as "in one embodiment" or "in an embodiment" that may appear in various points in this specification do not necessarily refer to the same embodiment. Furthermore, in one or more embodiments, particular configurations, structures, or features may be combined in any appropriate manner.

[0035] The headings / references used herein are provided for convenience only and do not define the scope of protection or the scope of the embodiments.

[0036] Furthermore, for simplicity and ease of explanation, the same reference numerals / names may be used in this specification to designate circuit nodes or lines and signals appearing on such nodes or lines.

[0037] Figure 1 is a block diagram of a conventional clock recovery circuit CR, which is configured to receive an input data signal stream Data_in at an input node from a wireless / wired connection (not visible in the figure).

[0038] The clock recovery circuit CR is intended to sample the input data Data_in at the sampling block 14 with the "same" clock as the input data is recovered from the data.

[0039] In order to achieve the above effect, input data Data_in is provided to an edge detector 16 , which in turn is provided to a phase locked loop PPL arrangement 18 .

[0040] The PLL device 18 includes an input combining node (multiplier) 180 , followed by a low-pass filter (LPF) 181 and a voltage-controlled oscillator (VCO) 182 .

[0041] On the one hand, the output signal from the VCO 182 is returned to the combining node 180 to be combined (phase compared) with the output signal from the edge detector 16 , and on the other hand, it is provided to the sampling block 14 as a sampling signal.

[0042] Figure 1 The structure and operation of the PLL arrangement 16 schematically shown in FIG. 1 are conventional in the art, such that a more detailed description need not be provided here.

[0043] like Figure 1 The illustrated clock recovery circuit CR relies on a precise local oscillator (eg, a PLL) that is “tuned” based on the edges of the input data Data_in and adjusts the local oscillator (VCO 182 ) to correctly sample the input data.

[0044] Despite its apparent simplicity, Figure 1 The clock recovery circuit CR shown ends up being rather complex, with a mix of analog and digital components having a rather high current sink.

[0045] It has been observed that, particularly (but not exclusively) in communication (wired / wireless) systems exchanging data at low rates (e.g., hundreds of kilobits per second), a local oscillator (e.g., a PLL device) on the receiver side can dispense with reconstructing the sampling clock with a simple all-digital solution.

[0046] This may be the case in particular if, even in the absence of a suitable clock component, the received data signal Data_in contains transitions (edges) of such a degree that sufficient information about the clock of the incoming data is conveyed that it can be recovered from the received data.

[0047] Figure 2 is an exemplary representation of various types of signals that may be advantageously used with clock recovery circuits according to the examples described herein.

[0048] Figure 2The signals given in (by way of non-limiting example) include signals that are scrambled (so that they do not include long sequences of zeros or ones) and / or encoded as NRZ (Non Return to Zero), NRZI (Non Return to Zero Inversion), FMO or Manchester encoded signals.

[0049] like Figure 3 As shown, the clock recovery circuit 10 according to the example of this document includes:

[0050] a coarse data detector 20 configured to receive an input data stream Data_in at an input node IN, and

[0051] The local oscillator 22 may advantageously be implemented as a delay locked loop (DLL) circuit block, possibly with a clock divider 24 cascaded thereto.

[0052] The input data stream Data_in from node IN and the output from the local oscillator (DLL block 22 / clock divider 24) are provided to the phase alignment circuit block 26. This signal can have 1 to N components (edge ​​sets): two components, namely edge 1 and edge 2, will be mainly combined by Figure 6 and 7 Non-limiting examples of

[0053] The sampling block 14 in turn generates a sampled Data_in signal at an output node OUT for use by the user equipment UD, the sampled Data_in signal being obtained by sampling the input data stream Data_in received at the input node IN under the control of the sampling signal SS (eg, Edge 1 , Edge 2 ).

[0054] As mentioned above, the arrangement exemplified herein may be advantageously applied in an automatic toll collection device configured to detect and record the passage of a vehicle V through a toll booth. Reference to this possible application is made by way of example only and not limitation of the embodiments.

[0055] It is also important to note that although the coarse data detector 20 is advantageous, it is Figure 3 An optional feature of the clock recovery circuit 10.

[0056] The coarse data detector 20 may actually help to check whether "useful" input data is received at a frequency having an expected data rate range.

[0057] For example, the input data Data_in can be generated by a crystal oscillator having an oscillation frequency Fosc=32768 Hz (this is of course a purely exemplary value).

[0058] The coarse data detector 20 can therefore be configured (in a manner known per se to a person skilled in the art) to count the data edges of Data_in present within the 1 / Fosc time (assuming the input data rate is above 32 Kbit / s) and confirm that the input data rate is within the expected frequency range (e.g. between F1 and F2).

[0059] Coarse data detector 20 may thus identify the Data_in signal in the bandwidth and trigger operation of (only) circuit blocks cascaded to coarse data detector 20 in response to the Data_in signal received in the bandwidth.

[0060] This reduces power consumption.

[0061] As previously mentioned, the coarse data detector 20 is an optional feature (e.g., it can be avoided if the crystal oscillator is not functional). If the coarse data detector 20 is not present, it can be assumed that Figure 3 The other circuit blocks in the MCU are always operational.

[0062] The local oscillator 22 may advantageously be implemented as a delay locked loop (DLL) circuit configured to generate a (new) local clock. The frequency of the generated clock depends on the implemented delay.

[0063] exist Figure 4 In the possible implementation shown, the delay locked loop (DLL) circuit 22 can be realized as a chain (cascade) of delay cells 220, which are configured to apply a corresponding delay time Td (e.g., 16 ns to 32 ns: of course, these values ​​are only exemplary and non-limiting).

[0064] The combinatorial logic coupled to the delay unit 220 generates a clock signal CLK having a (half) period depending on the delay Td.

[0065] As shown, the combinational logic includes AND gates 222 and AND gates 224 coupled to every other delay cell 220 in the chain (cascade) from the first delay cell 220 to the second-to-last delay cell 220. Each AND gate 222 has a first input coupled to an input (DIN, DLL1, DLL3, DLL5, etc.) of the associated delay cell 220 and a second, negative input coupled to an output (DLL0, DLL2, DLL4, DLL6, etc.) of the associated delay cell 220.

[0066] The output of the AND gate 222 is provided as an input to the OR gate 224, and the OR gate 222 generates a clock signal CLK as an output.

[0067] That is, gates 222 , 224 provide logic circuitry configured to generate a local clock signal CLK depending on the input signal applied to the delay cells 220 in the chain.

[0068] like Figure 4 As shown, such a logic circuit arrangement thus comprises a set of AND gates 222 coupled to alternating ones of the delay cells in the chain, wherein each AND gate in the set has a first input coupled to an input of the respective delay cell 220 to which it is coupled (e.g. DIN, DLL1, DLL3, DLL5) and a second input coupled to the (inverting) input of the delay cell following the respective delay cell 220 in the chain (e.g. DLL0, DLL2, DLL14, DLL6).

[0069] Thus, the OR gate 224 coupled to the output of the AND gate generates the local clock signal CLK.

[0070] The OR gate 226 at the input of the DLL circuit 22 receives:

[0071] As the first input, pulse input / start signal, and

[0072] As a second input, the output of AND gate 228 receives, in turn, the output of the last delay cell 220 in the delay cell chain / cascade (here, DLL7) and an enable signal EN (e.g., from coarse data detector 20). As previously mentioned, while coarse data detector 20 is advantageous, it is not a mandatory feature. In those embodiments where coarse data detector 20 is not considered, other (logic) circuitry, such as a simple finite state machine (FSM), can be provided to implement the loopback arrangement.

[0073] The output of the OR gate 226 at the input of the DLL circuit 22 is applied as input DIN to the first delay cell 220 in the chain / cascade of delay cells.

[0074] The pulse input / enable signal is a pulse signal having an "on" time Tpulse and a period between Td (the delay time of delay cell 220) and M*Td, where M is the number of delay cells 22 in the delay cell chain / cascade in the DLL circuit.

[0075] That is: Tpulse<M*Td and Tpulse>Td.

[0076] For instance, in the example shown, M=8 (eight).

[0077] Figure 5A A possible circuit diagram of a logic circuit arrangement 22A is shown, which may be associated with the DLL local oscillator 22 .

[0078] In the exemplary case shown, the start signal is fed to a delay line comprising, for example, three delay cells 220A (each applying a delay Td).

[0079] AND gate 222A receives:

[0080] On the first input, the start signal, and

[0081] At the second input, the start signal delayed by the delay unit 220A is received after logical inversion.

[0082] Figure 5B Included are various timing diagrams sharing a common time (abscissa) scale t. These timing diagrams are examples of possible temporal behavior for the following signals (from top to bottom):

[0083] Start signal;

[0084] The start signal delayed by the delay unit 220A; and

[0085] The pulse input / enable signal at the output of AND gate 222A.

[0086] As long as the enable signal EN is activated, the clock pulse (signal CLK) is continuously generated with a clock period of 2*Td, where Td is the delay time of the delay unit 220 .

[0087] Figure 6 Included are various timing diagrams sharing a common time (abscissa) scale that are examples of possible temporal behavior for the following signals (from top to bottom):

[0088] Enable signal EN,

[0089] The signals at the input / output of the delay unit 220, such as DIN, DLL0, DLL1, ..., DLL7, and

[0090] Clock signal CLK.

[0091] As described above, the delay time Td is defined to depend on the data rate of the input data Data_in.

[0092] For example, the input data Data_in may be (over)sampled at the sampling circuitry 14 at a frequency that is at least 16 times greater than the data rate.

[0093] In this case, the delay Td may be chosen to have a maximum value Tdmax equal to 1 / (Fdata*32), where Fdata is the input data rate in Hz, so the maximum oversampling is 32*Fdata.

[0094] The clock divider 24 may be implemented as a simple flip-flop divider (of any type known to a person skilled in the art) whose purpose is to divide the clock signal CLK if its frequency is higher than the maximum desired oversampling rate at, for example, 32*Fdata.

[0095] In the arrangement as illustrated herein, the phase alignment block 26 has the purpose of searching for the “optimal” sampling edge for actuating the sampling circuit 14 in order to sample the input data Data_in.

[0096] like Figure 7 As shown, the phase alignment block 26 may cooperate with the sampling circuitry 14; Figure 8 The corresponding flow chart is reproduced.

[0097] exist Figure 7 In a possible implementation, the phase alignment block 26 comprises a counter 260 which receives the clock signal CLK (eg divided in the clock divider 24) and the output of a (rising and falling) edge detector 262 which receives the data Data_in to be sampled.

[0098] Logic circuitry including blocks or nodes 264 , 266 , 268A, 268B, and 270 processes the output from counter 260 to produce a set of signals (eg, two signals, Edge 1 and Edge 2 ) that activate sampling circuitry 14 to sample Sampled Data_in.

[0099] Recall that the sampled signal SS may include a set of 1 to N components: for simplicity, two components, Edge 1 and Edge 2, are discussed here by way of non-limiting example.

[0100] At each rising and falling edge of the signal Data_in, the internal counter 260 (clocked by the clock signal CLK) is sampled and then reset.

[0101] In block 264, the sampled counter value is compared to the previous value stored in storage block 266, and if (and only if)

[0102] The counter value is higher than the previous counter value divided by 2 minus the "delta" margin (the lower limit of the update range),

[0103] AND

[0104] The current value is lower than the previous value plus the "delta" margin (update range upper limit);

[0105] In response to the sampling enable signal SE, the value stored in the block 266 is updated with a new value.

[0106] A set of sampling edges to be provided to sampling circuitry 14 is calculated in blocks 268A, 268B and node 270 .

[0107] For example, in the exemplary, non-limiting case of a set consisting of two sampling edges, Edge 1 and Edge 2, the edge calculations provided to sampling circuitry 14 in blocks 268A, 268B and node 270 may be as follows:

[0108] Edge 1 is half the counter value stored in block 266, i.e., the counter value stored in block 266 is divided by 2 (shifted right one bit); and

[0109] Edge 2 is the sum (generated in adder node 270) of the counter value stored in block 266 divided by 2 (output of block 268A) plus the counter value stored in block 266 (here shown as loaded in block 268B).

[0110] As another example, four edges, Edge 1, Edge 2, Edge 3, and Edge 4, can be calculated as follows:

[0111] Edge 1 = one quarter (1 / 4) of the counter value, i.e., the counter value stored in block 266 divided by four;

[0112] Edge 2 = one quarter (1 / 4) of the counter value plus one half (1 / 2) of the counter value, i.e., plus the counter value stored in block 266 divided by two;

[0113] Edge 3 = one quarter (1 / 4) of the counter value plus one half (1 / 2) of the counter value stored in block 266 divided by two times two (in short, the counter value stored in block 266); and

[0114] Edge 4 = one quarter (1 / 4) of the counter value plus one half (1 / 2) of the counter value stored in block 266 divided by three times two.

[0115] That is, in the case of N edges, where N = 2^p, p = 1, 2, 3, 4, ... the nth edge (n = 1, ..., N) can be calculated as follows: edge n = 1 / N count + (n-1) x (1 / (N / 2 count)).

[0116] Those skilled in the art can design Figure 7 Corresponding adaptation of the exemplary circuit.

[0117] Furthermore, it will be appreciated that choosing N to be a power of 2 is advantageous as this facilitates the computation of edges via bit shift operations.

[0118] Whenever the counter 260 reaches one of the 1 to N edges counted (e.g., edge 1, edge 2), the Data_in signal may be sampled: Note that (as follows Figure 9 As shown in FIG. 2 , depending on the symbol sequence in the input signal Data_in, the counter 260 may reach the “other” edge, such as edge 2, only in certain cases.

[0119] The value of the “delta” margin used when updating the stored counter value may be determined (e.g., calculated or experimentally) taking into account process, voltage, temperature (PVT) variations in the DLL oscillator 22 and / or the type of modulation used for transmission (e.g., NRZ, NRZI, FMO, or Manchester).

[0120] For example, a good choice of the incremental margin may be approximately 20% of the expected data sampling rate of the input data Data_in.

[0121] After startup, Figure 8 The boxes in the flowchart represent the following steps / stages:

[0122] The internal counter 260 (clocked by the clock signal CLK) is sampled and then reset at each rising and falling edge of the signal Data_in;

[0123] comparing the sampled counter value with the previously stored value and, in response to a sampling enable signal SE, if (and only if) the current counter value is higher than the previous counter value divided by 2 minus the "delta" margin (the lower limit of the update range), and (AND) if the current value is lower than the previous value plus the "delta" margin (the upper limit of the update range);

[0124] Checking the counter 260 may be considered locking to the data input signal (block 104);

[0125] In response to a positive result ("Y") of the check in block 104, the confirmation counter 260 is locked (block 106);

[0126] In response to a negative result ("N") of the check in block 104, the program is aborted (block 108);

[0127] A set of edge signals Edge1, ..., EdgeN (e.g., Edge1 and Edge2) is generated depending on the stored counter value (block 110);

[0128] The sampling circuit device 14 is activated by edge signals (eg, edge 1 and edge 2 ) to generate sampled data Data_in.

[0129] Figure 9is an example of a timing diagram for sampling the input signal Data_in at the sampling instant SI according to an embodiment of the present description.

[0130] It should be noted that it is advantageous to choose Edge 1, ... Edge N depending on the storage count, since (besides being easy to calculate by bit shifting) these values ​​result in the sampling instant SI being effectively "centered" with respect to the input data stream Data_in, both in the case of "0" and "1" symbols and in the case of repeated symbols.

[0131] It will be appreciated that the number N and values ​​of edge signal sets discussed above by way of example are not strictly mandatory.

[0132] It should also be noted that in the examples discussed herein, in which a threshold set of at most N thresholds (including N) is generated, increasing the number of edges Edge 1, ..., Edge N will lead to improved sampling results.

[0133] The arrangement as exemplified herein has a startup transition where the sampled values ​​are useless and ignored. A simple lock counter can be used to detect the end of this transient phase.

[0134] Examples as shown herein facilitate implementation in a simpler manner than prior art solutions.

[0135] The example shown in this article can be implemented in a fully digital form with (very) low power consumption: for example, clock reconstruction can be activated only when a “valid” Data_in signal is recognized, and is disabled the rest of the time, reducing the switching power to zero.

[0136] The DLL circuit 22 as exemplified herein spares on logic, timing and the associated costs of an accurate reference clock and allowed Td variations (even by a factor of 2 or 3). Figure 6 and Figure 7 The phase alignment function shown can adjust the sampling edge to accommodate variations in Td (and DLL clock CLK) due to PVT (process, voltage, temperature) factors.

[0137] Without affecting the basic principles, the details and embodiments may be described by way of example only and may even vary significantly without departing from the scope of the embodiments.

[0138] The scope of protection is determined by the appended claims.

Claims

1. A circuit comprising: An input node configured to receive a data signal having a data rate and including a rising edge and a falling edge; a digital oscillator configured to generate a local clock signal having a frequency higher than the data rate, wherein the rising edge and the falling edge in the data signal are separated by a plurality of cycles of the local clock signal; a sampling signal generator circuit device comprising a counter clocked by the local clock signal, the counter being configured to sample a count value of the counter at the rising edge and the falling edge of the data signal and then reset, and a storage block coupled to the counter to receive the sampled count value of the counter, the storage block being configured to store the count value of the counter, wherein the count value stored in the storage block is updated in response to a current sampled count value of the counter being within an update range, the update range being between a lower limit depending on half of the count value previously stored in the storage block and an upper limit depending on the count value previously stored in the storage block; and The sampling signal generator circuit arrangement is configured to generate a threshold value set of at most N threshold values, wherein the nth threshold value in the threshold value set is calculated as: 1 / N counts + (n-1) x (1 / (N / 2 counts)), wherein n=1, ..., N, and count is the update count value stored in the storage block; a sampling circuitry configured to receive the data signal at the input node, the sampling circuitry coupled to the sampling signal generator circuitry and configured to be actuated thereby and, in response to the count value of the counter reaching any threshold value in the set of threshold values, sample the data signal at the input node and provide a sampled version of the data signal at the input node at an output node; wherein the lower limit is half of the count value previously stored in the storage block minus a count value margin, and the upper limit is the count value previously stored in the storage block plus the count value margin.

2. The circuit of claim 1 , comprising a data detector coupled to the input node and configured to activate the digital oscillator, the sampling signal generator circuitry, and the sampling circuitry in response to the data rate of the data signal being within a given frequency range.

3. The circuit of claim 1, wherein the digital oscillator comprises a delay locked loop.

4. The circuit of claim 3 , wherein the delay locked loop comprises: a cascade arrangement of N delay cells in a chain, each delay cell having an input-to-output delay time Td, wherein a first delay cell in the chain is configured to receive a logical sum of an input pulse signal and an output signal from a last delay cell in the chain, the input pulse signal having an activation time between the input-to-output delay time (Td) and N times N*Td of the input-to-output time; as well as Logic circuitry is configured to generate the local clock signal in dependence on input signals applied to the delay cells in the chain.

5. The circuit of claim 4 , wherein the logic circuit device comprises: a set of AND gates coupled to alternating ones of the delay cells in the chain, wherein each AND gate in the set of AND gates has a first input coupled to a non-inverting input of a corresponding delay cell to which it is coupled and an inverting input coupled to a delay cell subsequent to the corresponding delay cell in the chain; as well as An OR gate is coupled to the output of the AND gate in the set of AND gates, and the OR gate generates the local clock signal.

6. The circuit of claim 4, comprising a logic gate configured to selectively gate the supply of an output signal from a last delay cell in the chain to the logical sum received by the first delay cell in the chain.

7. The circuit of claim 1 , wherein the digital oscillator has a clock divider coupled thereto, the clock divider configured to divide the frequency of the local clock signal, wherein the counter is clocked by the local clock signal divided at the clock divider.

8. The circuit of claim 1, wherein N is a power of 2.

9. A receiver comprising: Circuit, including: An input node configured to receive a data signal having a data rate and including a rising edge and a falling edge; a digital oscillator configured to generate a local clock signal having a frequency higher than the data rate, wherein the rising edge and the falling edge in the data signal are separated by a plurality of cycles of the local clock signal; a sampling signal generator circuit device comprising a counter clocked by the local clock signal, the counter being configured to sample a count value of the counter at the rising edge and the falling edge of the data signal and then reset, and a storage block coupled to the counter to receive the sampled count value of the counter, the storage block being configured to store the count value of the counter, wherein the count value stored in the storage block is updated in response to a current sampled count value of the counter being within an update range, the update range being between a lower limit depending on half of the count value previously stored in the storage block and an upper limit depending on the count value previously stored in the storage block; The sampling signal generator circuit arrangement is configured to generate a threshold value set of at most N threshold values, wherein the nth threshold value in the threshold value set is calculated as: 1 / N counts + (n-1) x (1 / (N / 2 counts)), wherein n=1, ..., N, and count is the update count value stored in the memory block; and a sampling circuitry configured to receive the data signal at the input node, the sampling circuitry being coupled to the sampling signal generator circuitry and configured to be actuated thereby and, in response to the count value of the counter reaching any threshold value in the set of threshold values, sample the data signal at the input node and provide a sampled version of the data signal at the input node at an output node; and a user device coupled to the output node and configured to receive a sampled version of the data signal from the output; wherein the lower limit is half of the count value previously stored in the storage block minus a count value margin, and the upper limit is the count value previously stored in the storage block plus the count value margin.

10. A method for clock recovery, comprising: receiving a data signal having a data rate and including rising and falling edges at an input node; generating a local clock signal having a frequency higher than the data rate, the rising edge and the falling edge in the data signal being separated by a plurality of cycles of the local clock signal; generating, by a counter, a count value clocked by the local clock signal, the count value being sampled at the rising edge and the falling edge of the data signal and then reset, and storing the sampled count value in a storage block, the stored count value being updated in response to a currently sampled count value being within an update range, the update range being between a lower limit depending on half of the count value previously stored in the storage block and an upper limit depending on the count value previously stored in the storage block; A threshold set of at most N thresholds is generated, and the nth threshold in the threshold set is calculated as: 1 / N counts + (n-1) x (1 / (N / 2 counts)), wherein n=1, ..., N, and count is an updated count value stored in the memory block; as well as sampling the data signal at the input node and providing a sampled version of the data signal at the input node at an output node in response to the count value reaching any threshold in the set of thresholds; The lower limit is half of the previously stored count value minus a count value margin, and the upper limit is the previously stored count value plus the count value margin. The method of claim 10 , wherein N is a power of 2.

12. The method according to claim 10, further comprising: Before generating the local clock signal, the data rate of the data signal is detected within a given frequency range.

13. The method of claim 10 , wherein the generation of the local clock signal is performed by a digital oscillator comprising a delay locked loop having logic circuitry and a cascade arrangement of N delay cells in a chain, each delay cell having an input-to-output delay time (Td), and the method further comprising: receiving, by a first delay unit in the chain, a logical sum of an input pulse signal and an output signal of a last delay unit in the chain, the input pulse signal having an activation time between the input-to-output delay time (Td) and N times the input-to-output delay time (N*Td); and The local clock signal is generated by the logic circuitry in dependence on input signals applied to the delay cells in the chain.

14. The method of claim 13 , wherein the logic circuitry comprises a set of AND gates coupled to alternating ones of the delay cells in the chain, and OR gates coupled to outputs of the AND gates in the set of AND gates, and further comprising generating the local clock signal by the OR gates.

15. The method according to claim 13, further comprising: The supply of an output signal from the last delay cell in the chain is selectively gated by a logic gate to the logical sum received by the first delay cell in the chain.

16. The method of claim 13, wherein the digital oscillator has a clock divider coupled thereto, and the method further comprising: dividing the frequency of the local clock signal by the clock divider; as well as The counter is clocked by the local clock signal divided at the clock divider.

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