Display panel and display device

Abstract

A display panel and a display device, the display panel comprising: a display area and a binding area located on the first side of the display area; the display area comprises: a plurality of sub-pixels arranged in an array and a plurality of data lines electrically connected with the plurality of sub-pixels; the binding area comprises: a plurality of data line leads connected with the plurality of data lines and a plurality of pins connected with the plurality of data line leads, the plurality of pins are located on the side of the plurality of data line leads away from the display area; wherein the binding area further comprises: a first wiring area, a bending area and a second wiring area arranged in sequence along the first direction, the second wiring area comprises: a first through hole, the first through hole is located between the plurality of data line leads, and the first through hole is configured to correspond to a first photosensitive element.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, the field of display technology, and in particular to a display panel and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, and extremely fast response speed. With the continuous development of display technology, flexible display devices that use OLEDs as light-emitting devices and thin-film transistors (TFTs) for signal control have become the mainstream products in the display field. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0004] On one hand, this disclosure provides a display panel, including: a display area and a bonding area located on one side of the display area in a first direction; the display area includes: a plurality of sub-pixels arranged in an array and a plurality of data lines electrically connected to the plurality of sub-pixels; the bonding area includes: a plurality of data line leads connected to the plurality of data lines and a plurality of pins connected to the plurality of data line leads, the plurality of pins being located on the side of the plurality of data line leads away from the display area; wherein, the bonding area further includes: a first wiring area, a bending area and a second wiring area arranged sequentially along the first direction, the second wiring area including: a first through hole, the first through hole being located between the plurality of data line leads, the first through hole being configured to correspond to a first photosensitive element.

[0005] On the other hand, this disclosure also provides a display device, including: the display panel described in the above embodiments and a first photosensitive element, wherein the position of the first photosensitive element corresponds to the position of the first through hole.

[0006] Other features and advantages of this disclosure will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the disclosure. Other advantages of this disclosure may be realized and obtained by means of the methods described in the description and the accompanying drawings.

[0007] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0008] The accompanying drawings are provided to illustrate the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure, but do not constitute a limitation on the technical solutions of this disclosure. The shape and size of each component in the drawings do not reflect actual proportions and are only intended to illustrate the content of this disclosure.

[0009] Figure 1A This is a schematic diagram of the structure of an OLED display device;

[0010] Figure 1B This is a schematic diagram of an equivalent circuit for a pixel driving circuit.

[0011] Figure 1C This is a timing diagram of a pixel driving circuit.

[0012] Figure 2 This is a schematic diagram of the structure of the display panel in an exemplary embodiment of this disclosure;

[0013] Figure 3A This is a schematic diagram of a display area in a display panel according to an exemplary embodiment of the present disclosure;

[0014] Figure 3B This is another structural schematic diagram of the display area in the display panel of the exemplary embodiments of this disclosure;

[0015] Figure 4 This is a schematic diagram of the structure of the binding area in the display panel in an exemplary embodiment of the present disclosure;

[0016] Figure 5 for Figure 4 The side view of the display panel shown;

[0017] Figure 6A for Figure 4 A schematic diagram of the wiring layout in the bonding area of ​​the display panel shown;

[0018] Figure 6B This is an enlarged schematic diagram of a first through hole in a display panel according to an exemplary embodiment of the present disclosure;

[0019] Figure 6C This is another enlarged schematic diagram of the first through hole in the display panel in an exemplary embodiment of the present disclosure;

[0020] Figure 6D This is an enlarged schematic diagram of a second through hole in a display panel according to an exemplary embodiment of the present disclosure;

[0021] Figure 6E This is another enlarged schematic diagram of the second through-hole in the display panel of an exemplary embodiment of the present disclosure;

[0022] Figure 7 for Figure 6A An enlarged schematic diagram of the traces in region A of the binding area shown;

[0023] Figure 8 for Figure 6A An enlarged schematic diagram of the wiring in region B of the binding area shown;

[0024] Figure 9 This is a schematic diagram of the structure of the display device in an exemplary embodiment of the present disclosure. Detailed Implementation

[0025] This document describes several embodiments, but these descriptions are exemplary and not limiting. Many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the accompanying drawings and discussed in exemplary embodiments, many other combinations of the disclosed features are possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with, or substitute for, any feature or element of any other embodiment.

[0026] In describing representative embodiments, the specification may have presented a method or process as a specific sequence of steps. However, the method or process should not be limited to a specific order of steps to the extent that it is independent of this specific order. Other orders of steps are possible, as will be understood by those skilled in the art. Therefore, the specific order of steps set forth in the specification should not be construed as a limitation of the claims. Furthermore, the claims relating to the method or process should not be limited to the steps performed in the order written, and those skilled in the art will readily understand that these orders may be varied and still remain within the spirit and scope of the embodiments disclosed herein.

[0027] In the accompanying drawings, the size of each component, the thickness of a layer, or the area are sometimes exaggerated for clarity. Therefore, this disclosure is not necessarily limited to these dimensions, and the shape and size of each part in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0028] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0029] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or element referred to has a specific orientation, or is constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the direction in which each constituent element is described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0030] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection or an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the meaning of these terms in this disclosure as appropriate.

[0031] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on the "elements that have a certain electrical function," as long as they enable the transmission and reception of electrical signals between the connected components. Examples of "elements that have a certain electrical function" include electrodes or wiring, switching elements such as transistors, or other functional elements such as resistors, inductors, or capacitors.

[0032] In this specification, a transistor is a device that includes at least three terminals: a gate electrode (or control electrode), a drain electrode (drain terminal, drain region, or drain electrode), and a source electrode (source terminal, source region, or source electrode). A transistor has a channel region between the drain and source electrodes, and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the area through which current primarily flows.

[0033] In this specification, to distinguish the two terminals of a transistor other than the gate electrode (gate or control electrode), one terminal is directly described as the first terminal and the other as the second terminal. The first terminal can be the drain electrode and the second terminal can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged.

[0034] The transistors used in the embodiments of this disclosure can all be thin-film transistors (TFTs), field-effect transistors (FETs), or other devices with similar characteristics. For example, the thin-film transistors used in the embodiments of this disclosure may include, but are not limited to, oxide TFTs or low-temperature poly-silicon TFTs (LTPS TFTs). Here, the embodiments of this disclosure do not limit the scope of the application.

[0035] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0036] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.

[0037] With the continuous development of display technology, the form factor of display devices (such as mobile phones) is rapidly changing, and many flexible display devices (such as foldable display devices) have emerged in the market, gaining popularity among consumers. Current flexible display devices typically have photosensitive elements (such as fingerprint recognition sensors, camera components, or infrared sensors), which, in order to match the overall device installation, are not conducive to achieving a full-screen display.

[0038] Figure 1A This is a schematic diagram of the structure of an OLED display device. Figure 1AAs shown, an OLED display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is connected to the data driver, the scan driver, and the light-emitting driver. The data driver is connected to multiple data signal lines (D1 to Dn), the scan driver is connected to multiple scan signal lines (S1 to Sm), and the light-emitting driver is connected to multiple light-emitting signal lines (E1 to Eo). The pixel array may include multiple sub-pixels Pxij, where i and j can be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting device connected to the circuit unit. The circuit unit may include at least one scan signal line (also called a gate line), at least one data signal line (also called a data line), at least one light-emitting signal line, and a pixel driving circuit. In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals of specifications suitable for the data driver to the data driver, provide clock signals, scan start signals, etc. of specifications suitable for the scan driver to the scan driver, and provide clock signals, light-emitting stop signals, etc. of specifications suitable for the light-emitting driver to the light-emitting driver. The data driver can use grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to data signal lines D1, D2, D3, ..., Dn. For example, the data driver can sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to data signal lines D1 to Dn on a pixel-by-pixel basis, where n can be a natural number. The scan driver can receive clock signals, scan start signals, etc., from the timing controller to generate scan signals to be provided to scan signal lines S1, S2, S3, ..., Sm. For example, the scan driver can sequentially provide scan signals with on-level pulses to scan signal lines S1 to Sm. For example, the scan driver can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals, provided in the form of on-level pulses, to the next stage circuit under the control of a clock signal, where m can be a natural number. The light-emitting driver can receive clock signals, light-emitting stop signals, etc., from the timing controller to generate light-emitting signals to be provided to light-emitting signal lines E1, E2, E3, ..., Eo. For example, an LED driver can sequentially provide transmit signals with cutoff level pulses to LED signal lines E1 to Eo. For example, the LED driver can be configured as a shift register and can generate transmit signals by sequentially transmitting transmit stop signals in the form of cutoff level pulses to the next stage circuit under the control of a clock signal, where o can be a natural number.

[0039] In one exemplary embodiment, the pixel driving circuit may include, but is not limited to, a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, or 7T1C structure. This disclosure does not limit the specific implementation of the embodiment.

[0040] Figure 1B This is a schematic diagram of an equivalent circuit for a pixel driving circuit. (Example) Figure 1B As shown, the pixel driving circuit may include 7 transistors (first transistor T1 to seventh transistor T7), 1 storage capacitor C, and 7 signal lines (data signal line D, first scan signal line S1, second scan signal line S2, light emission signal line E, initial signal line INIT, first power supply line VDD, and second power supply line VSS).

[0041] In one exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, and a third node N3. The first node N1 is connected to the first terminal of the third transistor T3, the second terminal of the fourth transistor T4, and the second terminal of the fifth transistor T5, respectively. The second node N2 is connected to the second terminal of the first transistor, the first terminal of the second transistor T2, the control terminal of the third transistor T3, and the second terminal of the storage capacitor C, respectively. The third node N3 is connected to the second terminal of the second transistor T2, the second terminal of the third transistor T3, and the first terminal of the sixth transistor T6, respectively.

[0042] In one exemplary embodiment, the first end of the storage capacitor C is connected to the first power line VDD, and the second end of the storage capacitor C is connected to the second node N2, that is, the second end of the storage capacitor C is connected to the control electrode of the third transistor T3.

[0043] The control electrode of the first transistor T1 is connected to the second scan signal line S2, the first electrode of the first transistor T1 is connected to the initial signal line INIT, and the second electrode of the first transistor is connected to the second node N2. When the on-level scan signal is applied to the second scan signal line S2, the first transistor T1 transmits the initialization voltage to the control electrode of the third transistor T3 to initialize the charge of the control electrode of the third transistor T3.

[0044] The control electrode of the second transistor T2 is connected to the first scan signal line S1, the first electrode of the second transistor T2 is connected to the second node N2, and the second electrode of the second transistor T2 is connected to the third node N3. When a conduction-level scan signal is applied to the first scan signal line S1, the second transistor T2 connects the control electrode of the third transistor T3 to its second electrode.

[0045] The control electrode of the third transistor T3 is connected to the second node N2, meaning the control electrode of the third transistor T3 is connected to the second terminal of the storage capacitor C. The first electrode of the third transistor T3 is connected to the first node N1, and the second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 can be called the driving transistor. The amount of driving current flowing between the first power line VDD and the second power line VSS is determined by the potential difference between its control electrode and its first electrode.

[0046] The control electrode of the fourth transistor T4 is connected to the first scan signal line S1, the first electrode of the fourth transistor T4 is connected to the data signal line D, and the second electrode of the fourth transistor T4 is connected to the first node N1. The fourth transistor T4 can be called a switching transistor, scanning transistor, etc. When a conduction-level scan signal is applied to the first scan signal line S1, the fourth transistor T4 causes the data voltage of the data signal line D to be input to the pixel driving circuit.

[0047] The control electrode of the fifth transistor T5 is connected to the light-emitting signal line E, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the first node N1. The control electrode of the sixth transistor T6 is connected to the light-emitting signal line E, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light-emitting device. The fifth transistor T5 and the sixth transistor T6 can be referred to as light-emitting transistors. When a conduction-level light-emitting signal is applied to the light-emitting signal line E, the fifth transistor T5 and the sixth transistor T6 cause the light-emitting device to emit light by forming a driving current path between the first power supply line VDD and the second power supply line VSS.

[0048] The control electrode of the seventh transistor T7 is connected to the first scan signal line S1, the first electrode of the seventh transistor T7 is connected to the initial signal line INIT, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light-emitting device. When a conduction level scan signal is applied to the first scan signal line S1, the seventh transistor T7 transmits an initialization voltage to the first electrode of the light-emitting device to initialize or release the accumulated charge in the first electrode of the light-emitting device.

[0049] In one exemplary embodiment, the second electrode of the light-emitting device is connected to the second power line VSS, where the signal of the second power line VSS is a low-level signal, and the signal of the first power line VDD is a continuously high-level signal. The first scan signal line S1 is the scan signal line in the pixel driving circuit of this display row, and the second scan signal line S2 is the scan signal line in the pixel driving circuit of the previous display row. That is, for the nth display row, the first scan signal line S1 is S(n), and the second scan signal line S2 is S(n-1). The second scan signal line S2 of this display row and the first scan signal line S1 in the pixel driving circuit of the previous display row are the same signal line, which can reduce the signal lines of the display panel and realize a narrow bezel of the display panel.

[0050] In one exemplary embodiment, the first transistor T1 to the seventh transistor T7 can be either P-type transistors or N-type transistors. Using the same type of transistor in the pixel driving circuit simplifies the manufacturing process, reduces the manufacturing difficulty of the display panel, and improves product yield. In some possible implementations, the first transistor T1 to the seventh transistor T7 may include both P-type and N-type transistors.

[0051] In one exemplary embodiment, the first scan signal line S1, the second scan signal line S2, the light emission signal line E, and the initial signal line INIT can extend in a horizontal direction, while the second power supply line VSS, the first power supply line VDD, and the data signal line D can extend in a vertical direction.

[0052] In one exemplary embodiment, the light-emitting device may be an organic light-emitting diode (OLED), including a first electrode (e.g., as an anode), an organic light-emitting layer, and a second electrode (e.g., as a cathode) stacked together.

[0053] Figure 1C This is a timing diagram of a pixel driving circuit. The following is a breakdown of the circuit's operation. Figure 1B The operation of the example pixel driving circuit illustrates an exemplary embodiment of this disclosure. Figure 1B The pixel driving circuit includes 7 transistors (first transistor T1 to sixth transistor T7), 1 storage capacitor C, and 7 signal lines (data signal line D, first scan signal line S1, second scan signal line S2, light emission signal line E, initial signal line INIT, first power supply line VDD and second power supply line VSS). All 7 transistors are P-type transistors.

[0054] In one exemplary embodiment, the operation of the pixel driving circuit may include:

[0055] In the first stage A1, also known as the reset stage, the signal on the second scan signal line S2 is low, while the signals on the first scan signal line S1 and the light-emitting signal line E are high. The low signal on the second scan signal line S2 turns on the first transistor T1, and the initial signal line INIT is supplied to the second node N2 to initialize the storage capacitor C, clearing the original data voltage in the capacitor. The high signals on the first scan signal line S1 and the light-emitting signal line E turn off the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7; during this stage, the OLED does not emit light.

[0056] The second stage, A2, is called the data writing stage or threshold compensation stage. During this stage, the signal on the first scan signal line S1 is low, while the signals on the second scan signal line S2 and the light-emitting signal line E are high. The data signal line D outputs a data voltage. Because the second terminal of the storage capacitor C is low, the third transistor T3 is turned on. The low signal on the first scan signal line S1 turns on the second transistor T2, the fourth transistor T4, and the seventh transistor T7. The turn-on of the second transistor T2 and the fourth transistor T4 allows the data voltage output from the data signal line D to be supplied to the second node N2 via the first node N1, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2. The difference between the data voltage output from the data signal line D and the threshold voltage of the third transistor T3 is charged into the storage capacitor C. The voltage at the second terminal of the storage capacitor C (second node N2) is Vd - |Vth|, where Vd is the data voltage output from the data signal line D, and Vth is the threshold voltage of the third transistor T3. The seventh transistor T7 is turned on, providing the initial voltage of the initial signal line INIT to the first electrode of the OLED, initializing (resetting) the first electrode of the OLED, clearing its internal pre-stored voltage, completing the initialization, and ensuring that the OLED does not emit light. The signal of the second scan signal line S2 is a high-level signal, causing the first transistor T1 to turn off. The signal of the light emission signal line E is a high-level signal, causing the fifth transistor T5 and the sixth transistor T6 to turn off.

[0057] The third stage, A3, is called the light-emitting stage. During this stage, the light-emitting signal line E is at a low level, while the first scan signal line S1 and the second scan signal line S2 are at a high level. The low level of the light-emitting signal line E turns on the fifth transistor T5 and the sixth transistor T6. The power supply voltage output from the first power line VDD then provides a driving voltage to the first electrode of the OLED through the turned-on fifth transistor T5, third transistor T3, and sixth transistor T6, driving the OLED to emit light.

[0058] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and its first electrode. Since the voltage at the second node N2 is Vdata - |Vth|, the driving current of the third transistor T3 is:

[0059] I = K * (Vgs - Vth) 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*[(Vdd-Vd)] 2

[0060] Where I is the driving current flowing through the third transistor T3, which is the driving current driving the OLED, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vd is the data voltage output by the data signal line D, and Vdd is the power supply voltage output by the first power supply line VDD.

[0061] In this embodiment, the first direction DR1 can refer to the vertical direction, the second direction DR2 can refer to the horizontal direction, and the third direction DR3 can refer to the thickness direction of the display panel or a direction perpendicular to the plane of the display panel, etc. The first direction DR1 intersects with the second direction DR2, and the first direction DR1 intersects with the third direction DR3. For example, the first direction DR1 and the second direction DR2 can be perpendicular to each other, and the first direction DR1 and the third direction DR3 can be perpendicular to each other.

[0062] This disclosure provides a display panel, which may include: a display area and a bonding area located on one side of the display area in a first direction; the display area may include: a plurality of sub-pixels arranged in an array and a plurality of data lines electrically connected to the plurality of sub-pixels; the bonding area includes: a plurality of data line leads connected to the plurality of data lines and a plurality of pins connected to the plurality of data line leads, the plurality of pins being located on the side of the plurality of data line leads away from the display area; wherein, the bonding area may further include: a first wiring area, a bending area and a second wiring area arranged sequentially along the first direction, the second wiring area may include: a first through hole, the first through hole being located between the plurality of data line leads, the first through hole being configured to correspond to a first photosensitive element. Thus, by drilling a hole in the bonding area of ​​the display panel to avoid the first photosensitive element (e.g., a camera assembly), it is easier to match the installation of the entire device, which is beneficial for achieving a full-screen display.

[0063] In one exemplary embodiment, the second routing area may include: a first sub-area, with the first through-hole located in the first sub-area; the second routing area has a center line extending along a first direction, and the first through-hole is symmetrically arranged about the center line. This ensures the uniformity of the routing load around the first through-hole in the second routing area, thereby ensuring consistent routing impedance on the display panel and avoiding the wiring pressure caused by routing concentrated on one side. This improves the display effect.

[0064] In one exemplary embodiment, the second wiring area may further include a second through hole located on one side of the first through hole along a second direction, the second through hole being configured to correspond to a second photosensitive element, the second direction intersecting the first direction.

[0065] In one exemplary embodiment, the second wiring area may further include a dummy hole located on the side of the second through hole away from the first through hole along the second direction. The first sub-area may include a first hole area, a second hole area, and a third hole area arranged sequentially along the second direction, with the first through hole located in the second hole area, the second through hole located in the first hole area, and the dummy hole located in the third hole area.

[0066] In one exemplary embodiment, the shape of the virtual hole is the same as the shape of the second through hole, and the size of the second through hole is the same as the size of the virtual hole.

[0067] In one exemplary embodiment, the dummy hole and the second through hole can be symmetrically arranged relative to the center line, with the second direction intersecting the first direction. Thus, by creating through holes in the bonding area of ​​the display panel, symmetrically arranging the second through hole and the dummy hole relative to the center line, and symmetrically arranging the first through hole about the center line, the uniformity of the wiring load in the second routing area can be ensured. This guarantees consistent wiring impedance on the display panel and avoids the wiring pressure caused by wiring concentrated on one side. Consequently, the display effect can be improved.

[0068] In one exemplary embodiment, the first via region may further include: a plurality of first traces extending along a first direction and a plurality of second traces extending along the first direction, wherein the plurality of first traces and the plurality of second traces are respectively located on both sides of the second via along a second direction, the length of the first traces is greater than the length of the second traces, and the width of the first traces is greater than the width of the second traces. Thus, by setting the width of the relatively longer traces (e.g., the first traces) on both sides of the second via to be relatively wider, and setting the width of the relatively shorter traces (e.g., the second traces) to be relatively thinner, the overall resistance of the relatively longer traces (e.g., the first traces) can be reduced, thereby reducing the load on the relatively longer traces (e.g., the first traces), ensuring that the resistance of the traces on both sides of the first via changes uniformly and the load is relatively balanced.

[0069] In an exemplary embodiment, the third via region may further include: a plurality of third traces extending along a first direction and a plurality of fourth traces extending along the first direction, the plurality of third traces and the plurality of fourth traces being located on both sides of the virtual via, the length of the third traces being greater than the length of the fourth traces, the width of the third traces being greater than the width of the fourth traces, the third traces being symmetrically arranged with respect to the first traces and the fourth traces being symmetrically arranged with respect to the second traces and the center line. Thus, by setting the width of the relatively longer traces (e.g., the third traces) on both sides of the virtual via to be relatively wider and the width of the relatively shorter traces (e.g., the fourth traces) to be relatively thinner, the overall resistance of the relatively longer traces (e.g., the third traces) can be reduced, thereby reducing the load on the relatively longer traces (e.g., the third traces), ensuring a uniform change in resistance and a relatively balanced load on both sides of the virtual via. Furthermore, since the third traces are symmetrically arranged with respect to the first traces and the fourth traces are symmetrically arranged with respect to the second traces and the center line, a uniform change in resistance of the traces in the second trace region can be ensured.

[0070] In one exemplary embodiment, the display panel may further include a second sub-region and a third sub-region located on either side of the first sub-region along a second direction, wherein the second and third sub-regions are symmetrically arranged with respect to the center line. Thus, by setting the second and third sub-regions, the uniformity of the wiring load in the second wiring area can be ensured. This ensures consistent wiring impedance on the display panel and avoids the wiring stress caused by wiring concentrated on one side. Consequently, the display effect can be improved.

[0071] In one exemplary embodiment, the display panel may further include: dummy traces, which include at least one of a first dummy trace surrounding a first via and a second dummy trace surrounding a second via. Thus, by providing dummy traces around the vias, the risk of crack defects around the vias can be reduced during the drilling process in the fabrication of the display panel, avoiding adverse effects on the normal traces around the vias and improving product yield.

[0072] Figure 2 This is a schematic diagram of the structure of a display panel in an exemplary embodiment of this disclosure. Figure 2 As shown, the display panel may include a display area 100 and a non-display area surrounding the display area 100. The non-display area may include a binding area 200 on one side of the display area 100 and a border area 300 on other sides of the display area 100. For example, the binding area 200 may be located on one side of the display area 100 in the first direction DR1.

[0073] In one exemplary embodiment, such as Figure 2As shown, the display area 100 may include: a plurality of sub-pixels Pxij arranged in an array and a plurality of data lines (not shown) electrically connected to the plurality of sub-pixels Pxij, where i and j can be natural numbers. For example, the display area 100 may also include: a plurality of gate lines electrically connected to the plurality of sub-pixels Pxij. Here, sub-pixel Pxij may refer to a sub-pixel in which a transistor is connected to the i-th gate line and connected to the j-th data line.

[0074] The display area will be explained below with reference to the attached diagram.

[0075] Figure 3A This is a schematic diagram illustrating a structure of a display area in a display panel according to an exemplary embodiment of this disclosure. Figure 3A As shown, in one exemplary embodiment, the display area 100 may include a plurality of pixel units P arranged in a matrix. At least one of the plurality of pixel units P may include a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light. For example, the first sub-pixel P1 may be a red (R) sub-pixel, the second sub-pixel P2 may be a green (G) sub-pixel, and the third sub-pixel P3 may be a blue (B) sub-pixel. Alternatively, at least one of the plurality of pixel units P may include a first sub-pixel P1, a second sub-pixel P2, a third sub-pixel P3, and a fourth sub-pixel P4 emitting different colors of light. For example, pixel unit P may include four sub-pixels, such as a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel. Here, the embodiments disclosed herein do not limit this.

[0076] In one exemplary embodiment, each sub-pixel may include a pixel driving circuit and a light-emitting device. The pixel driving circuit in the sub-pixel is connected to a scan signal line, a data signal line, and a light-emitting signal line, respectively. The light-emitting device in the sub-pixel is connected to the pixel driving circuit of its respective sub-pixel. The pixel driving circuit is configured to receive data voltage transmitted by the data signal line and output a corresponding current to the light-emitting device under the control of the scan signal line and the light-emitting signal line. The light-emitting device is configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit of its respective sub-pixel.

[0077] In one exemplary embodiment, the multiple sub-pixels in a pixel unit can be arranged in a horizontal, vertical, X-shaped, cross-shaped, or triangular pattern. For example, if a pixel unit includes three sub-pixels, the three sub-pixels can be arranged in a horizontal, vertical, or triangular pattern. For example, if a pixel unit includes four sub-pixels, the four sub-pixels can be arranged in a horizontal, vertical, or square pattern. This disclosure does not limit the scope of the embodiments.

[0078] In one exemplary embodiment, the shape of the sub-pixel can be any one or more of a triangle, square, rectangle, rhombus, trapezoid, parallelogram, pentagon, hexagon, and other polygons. This disclosure does not limit the shape in this regard.

[0079] Figure 3B This is another structural schematic diagram of the display area in a display panel according to an exemplary embodiment of the present disclosure, illustrating the structure of three sub-pixels of an OLED display panel. For example... Figure 3B As shown, in one exemplary embodiment, on a plane perpendicular to the display panel, the display panel may include: a driving circuit layer 12 disposed on the substrate 10, a light-emitting structure layer 13 disposed on the side of the driving circuit layer 12 away from the substrate 10, and an encapsulation layer 14 disposed on the side of the light-emitting structure layer 13 away from the substrate 10. In some possible implementations, the display panel may include other film layers, such as spacers, etc., which are not limited herein.

[0080] In one exemplary embodiment, the substrate 10 may be a flexible substrate or a rigid substrate. The driving circuit layer 12 for each sub-pixel may include a plurality of transistors and storage capacitors constituting a pixel driving circuit. Figure 3B The example uses only one transistor 11A and one storage capacitor 11B. The light-emitting structure layer 13 may include an anode 31, a pixel definition layer 32, an organic light-emitting layer 33, and a cathode 34. The anode 31 can be connected to the drain electrode of the transistor 11A via a via. The pixel definition layer 32 covers the anode 31 and has a pixel opening exposing the anode 31. The organic light-emitting layer 33 is connected to the anode 31 through this pixel opening, and the cathode 34 is connected to the organic light-emitting layer 33. The organic light-emitting layer 33 emits light of the corresponding color under the drive of the anode 31 and the cathode 34. The encapsulation layer 14 may include a first encapsulation layer 41, a second encapsulation layer 42, and a third encapsulation layer 43 stacked together. For example, the first encapsulation layer 41 and the third encapsulation layer 43 may be made of inorganic materials, while the second encapsulation layer 42 may be made of organic materials. The second encapsulation layer 42 is disposed between the first encapsulation layer 41 and the third encapsulation layer 43 to ensure that external moisture cannot enter the light-emitting structure layer 13.

[0081] In one exemplary embodiment, the driving circuit layer of each sub-pixel may include: a first insulating layer disposed on a flexible substrate, an active layer disposed on the first insulating layer, a second insulating layer covering the active layer, a gate electrode and a first capacitor electrode disposed on the second insulating layer, a third insulating layer covering the gate electrode and the first capacitor electrode, a second capacitor electrode disposed on the third insulating layer, a fourth insulating layer covering the second capacitor electrode, a via formed in the fourth insulating layer exposing the active layer, a source electrode and a drain electrode disposed on the fourth insulating layer, the source electrode and the drain electrode being connected to the active layer through the via, and a planarization layer covering the aforementioned structure. The active layer, the gate electrode, the source electrode, and the drain electrode constitute a transistor, and the first capacitor electrode and the second capacitor electrode constitute a storage capacitor. In one exemplary embodiment, the active layer may be made of amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), hexathiophene, or polythiophene, etc., that is, this disclosure is applicable to transistors manufactured based on oxide technology, silicon technology, or organic technology.

[0082] In one exemplary embodiment, the organic light-emitting layer may include an emitting layer (EML) and any one or more of the following: a hole injection layer (HIL), a hole transport layer (HTL), an electron block layer (EBL), a hole block layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). For example, the hole injection layers of all sub-pixels may be a common layer connected together, the electron injection layers of all sub-pixels may be a common layer connected together, the hole transport layers of all sub-pixels may be a common layer connected together, the electron transport layers of all sub-pixels may be a common layer connected together, and the hole block layers of all sub-pixels may be a common layer connected together. The emitting layers of adjacent sub-pixels may have a small overlap or may be isolated, and the electron block layers of adjacent sub-pixels may have a small overlap or may be isolated.

[0083] In one exemplary embodiment, each sub-pixel in the display panel may include a light-emitting area and a non-light-emitting area. Since the organic light-emitting layer emits light from the pixel opening area defined by the pixel definition layer, the pixel opening area is the light-emitting area FA of the sub-pixel, and the area outside the pixel opening is the non-light-emitting area BF of the sub-pixel. The non-light-emitting area BF is located between the light-emitting areas FA of adjacent sub-pixels.

[0084] The binding area is explained below with reference to the attached diagram.

[0085] Figure 4 This is a schematic diagram of the structure of the binding area in the display panel of an exemplary embodiment of the present disclosure. Figure 5 for Figure 4 The side view of the display panel shown. Figure 6A for Figure 4 The diagram shows the wiring layout of the bonding area in the display panel. Figure 6B This is an enlarged schematic diagram of a first through-hole in a display panel according to an exemplary embodiment of the present disclosure. Figure 6C This is another enlarged schematic diagram of the first through-hole in the display panel of an exemplary embodiment of the present disclosure. Figure 6D This is an enlarged schematic diagram of a second through-hole in a display panel according to an exemplary embodiment of the present disclosure. Figure 6E This is another enlarged schematic diagram of the second through-hole in the display panel of an exemplary embodiment of the present disclosure. Figure 7 for Figure 6A The diagram shown is an enlarged view of the traces in region A of the binding area. Figure 8 for Figure 6A The diagram shows an enlarged view of the traces in region B of the bound area. Figures 6A to 8 The routing shown is merely an illustrative example; the number of routing traces does not represent the actual number. Here, Figures 4 to 8 The illustration uses a circular first through hole and a rounded rectangle as an example. The shape of the through hole does not represent the actual shape.

[0086] In one exemplary embodiment, such as Figure 4 and Figure 5 As shown, the bonding area 200 may include: multiple data line leads (not shown) connected to multiple data lines (not shown in the figure) and multiple pins (not shown in the figure) connected to the multiple data line leads (not shown in the figure), with the multiple pins (not shown in the figure) located on the side of the multiple data line leads (not shown in the figure) away from the display area 100. In a plane parallel to the display panel, the bonding area 200 may further include: a first trace area 201, a bending area 202, a second trace area 203, and a composite circuit area 204 sequentially arranged along a first direction DR1 (i.e., the direction away from the display area 100). Specifically, the first trace area 201 is connected to the display area 100, the bending area 202 is connected to the first trace area 201, the second trace area 203 is connected to the bending area 202, and the composite circuit area 203 is connected to the second trace area 203.

[0087] In one exemplary embodiment, the first routing area may include multiple leads, such as multiple data leads, multiple touch leads, a first power connection line, or a second power connection line. For example, the multiple data leads are configured to connect the data signal lines (also referred to as data lines) of the display area in a fan-out routing manner. For example, the multiple scan connection lines are configured to connect the scan signal lines of the display area in a fan-out routing manner. For example, the multiple touch leads are configured to connect the touch signal lines (e.g., touch drive signal TX line and touch sensing signal RX line) in the bezel area in a fan-out routing manner, and the touch signal lines are configured to connect the touch electrodes of the display area. For example, the first power connection line is configured to connect a first power line (VDD) in the display area that provides a high voltage, and the second power connection line is configured to connect a second power line (VSS) in the bezel area that provides a low voltage. Here, this disclosure embodiment does not limit the scope of the invention.

[0088] In one exemplary embodiment, such as Figure 5 As shown, the bending area 202 may include a composite insulating layer with grooves, configured to allow a portion of the bonding area 200 to be bent to the back of the display area 100. For example, as Figure 5 As shown, the bending area can be bent with a curvature in the third direction D3, which can reverse the surfaces of the second wiring area 203 and the composite circuit area 204. That is, the upward-facing surfaces of the second wiring area 203 and the upward-facing surfaces of the composite circuit area 204 can be transformed into downward-facing surfaces by bending the bending area 202, and the third direction DR3 intersects with the first direction DR1. For example, when the bending area 202 is bent, the second wiring area 203 and the composite circuit area 204 can overlap with the display area 100 in the third direction DR3 (i.e., the thickness direction of the display panel).

[0089] In one exemplary embodiment, the composite circuit region may include: an anti-static region, an integrated circuit (IC) region, and a bonding electrode region sequentially disposed along a first direction DR1 (i.e., a direction away from the display area 100). For example, the anti-static region may include an anti-static circuit configured to prevent electrostatic damage to the display substrate by eliminating static electricity. For example, the integrated circuit region may house a touch and display driver integrated circuit (TDDI) configured to be connected to multiple data line leads. For example, the bonding electrode region may include multiple bonding pads configured to be bonded to an external flexible printed circuit (FPC). This disclosure does not limit the scope of the embodiments described herein.

[0090] In one exemplary embodiment, the second wiring area may include multiple data lines or multiple touch lines extended in a fan-out wiring manner. This disclosure does not limit the scope of the embodiment.

[0091] In one exemplary embodiment, such as Figure 4 and Figure 6A As shown, the second routing area 203 may include: a first sub-area 400, and a second sub-area 404 and a third sub-area 405 located on either side of the first sub-area 400 in the second direction DR2. The second routing area 203 may have a center line CL extending along the first direction DR1. For example, the second sub-area 404 and the third sub-area 405 may be symmetrically arranged with respect to the center line CL. Here, the center line CL may be a straight line extending along the first direction DR1 and evenly dividing the second routing area 203 (or the binding area 100). The second direction DR2 intersects the first direction DR1. Wherein, in Figure 4 The example shown is illustrated by arranging the second sub-region 404, the first sub-region 400, and the third sub-region 405 sequentially along the second direction DR2. This embodiment of the present disclosure does not limit the scope of the example.

[0092] In one exemplary embodiment, such as Figure 4 and Figure 6A As shown, the first sub-region 400 may include: a second hole region 402, and a first hole region 401 and a third hole region 403 located on both sides of the second hole region 402 in the second direction DR2. The second routing region 203 may have a center line CL extending along the first direction DR1. The first hole region 401 is provided with a second through hole 501, the second hole region 402 is provided with a first through hole 503, and the third hole region 403 is provided with a virtual hole 505. The first through hole 503 may be symmetrically arranged about the center line 503. Here, the center line CL may be a straight line extending along the first direction DR1 and evenly dividing the second routing region 203 (or the binding region 100). The second direction DR2 intersects the first direction DR1. Wherein, in Figure 4 In this example, the first hole area 401, the second hole area 402, and the third hole area 403 are arranged sequentially along the second direction DR2. This embodiment does not limit the scope of the invention.

[0093] In one exemplary embodiment, the first through-hole 503 can be a hole that penetrates the membrane layer.

[0094] In one exemplary embodiment, the second through-hole 501 can be a hole that penetrates the membrane layer.

[0095] In one exemplary embodiment, the dummy hole 505 may not penetrate any membrane layer, or the dummy hole may be a hole that penetrates the membrane layer. Here, the embodiments of this disclosure do not limit this.

[0096] In one exemplary embodiment, the shape of the virtual hole may be the same as the shape of the second through hole, and the size of the second through hole may be the same as the size of the virtual hole. For example, the second through hole 501 and the virtual hole 505 may be symmetrically arranged with respect to the center line CL. Here, the size may include one or more of the characteristic dimensions of the second through hole in the first direction DR1 and the characteristic dimensions in the second direction DR2.

[0097] In one exemplary embodiment, the first aperture region may have the function of avoiding the second photosensitive element.

[0098] In one exemplary embodiment, the position of the second through-hole may correspond to the position of the second photosensitive element. Thus, by creating the second through-hole in the first hole area of ​​the bonding region, the second photosensitive element can be avoided. For example, the second photosensitive element may be a fingerprint recognition component, a camera component (e.g., a multi-level diffractive lens (MDL), or an infrared sensor, etc.). This disclosure does not limit the scope of the embodiments.

[0099] In one exemplary embodiment, the shape of the second through-hole and the shape of the virtual hole can be selected from any one of rectangle, rounded rectangle, ellipse, polygon, and circle in a plane parallel to the display panel. For example, as Figure 4 and Figure 6A As shown, the shapes of the second through hole 501 and the virtual hole 505 can be rounded rectangles. However, this embodiment does not limit the shape of these shapes.

[0100] For example, if both the second through hole and the virtual hole are rounded rectangles, the dimensions of the rounded rectangle can include: the length of the rounded rectangle (e.g., the feature dimension of the rounded rectangle in the first direction DR1) and the width (e.g., the feature dimension of the rounded rectangle in the second direction DR2). For example, if both the second through hole and the virtual hole are circles, the dimensions of the circle can include: the diameter of the circle (e.g., the feature dimension of the circle in the first direction DR1 or the second direction DR2). For example, if both the second through hole and the virtual hole are ellipses, the dimensions of the ellipse can include: the major axis of the ellipse (e.g., the feature dimension of the ellipse in the first direction DR1) and the minor axis (e.g., the feature dimension of the ellipse in the second direction DR2).

[0101] In one exemplary embodiment, such as Figure 4 and Figure 6AAs shown, taking the shape of the second through hole 501 and the virtual hole 505 as rounded rectangles as examples, the length of the rounded rectangle in the first direction DR1 can be approximately 2 mm to 15 mm, and the width of the rounded rectangle in the second direction DR2 can be approximately 2 mm to 5 mm. For example, the length of the rounded rectangle in the first direction can be approximately 7.3 mm or 10 mm, etc. For example, the width of the rounded rectangle in the second direction can be approximately 3 mm or 4.2 mm, etc. Here, the length can refer to the feature dimension in the first direction DR1, and the width can refer to the feature dimension in the second direction DR2. Here, this embodiment of the disclosure does not limit this.

[0102] In one exemplary embodiment, taking the shape of the second through hole 501 and the shape of the virtual hole 505 as circular as an example, the diameter of the circle can be approximately 2 mm to 5 mm. For example, the diameter of the circle can be approximately 3 mm or 3.6 mm, etc. Here, the embodiments of this disclosure do not limit it in this way.

[0103] In one exemplary embodiment, the second aperture region may have the function of avoiding the first photosensitive element.

[0104] In one exemplary embodiment, the position of the first through-hole may correspond to the position of the first photosensitive element. Thus, by creating the first through-hole in the bonding area, the first photosensitive element can be avoided. For example, the first photosensitive element may be a fingerprint recognition component, a camera component, or an infrared sensor, etc. This disclosure does not limit the scope of the embodiments.

[0105] In one exemplary embodiment, the shape of the first through hole and the shape of the second through hole in a plane parallel to the display panel can be selected from any one or more of the following: circle, rectangle, rounded rectangle, ellipse and polygon.

[0106] In one exemplary embodiment, the shape of the first through-hole in a plane parallel to the display panel can be selected from any one of a circle, rectangle, rounded rectangle, ellipse, and polygon. For example, as shown... Figure 4 and Figure 6A As shown, the first through hole 503 can be circular in shape.

[0107] In one exemplary embodiment, taking the shape of the first through hole as circular as an example, the diameter of the circle can be approximately 2 mm to 5 mm. For example, the diameter of the circle can be approximately 3 mm or 3.6 mm, etc. Here, the embodiments of this disclosure do not limit this.

[0108] In one exemplary embodiment, the first hole area may also have the function of configuring wiring, and the wiring is connected to the lead wire in the first wiring area.

[0109] In one exemplary embodiment, such as Figures 6A to 8As shown, the first via region 401 may further include: multiple first traces L1 extending along the first direction DR1 on both sides of the second via 501 in the second direction DR2, and multiple second traces L2 extending along the first direction DR1. The length of the first traces L1 is greater than the length of the second traces L2, and the width w1 of the first traces L1 is greater than the width w2 of the second traces L2. The width of the traces can refer to a feature dimension in the second direction DR2, and the length of the traces can refer to a feature dimension in the first direction DR1. Thus, by setting the width of the relatively longer traces (e.g., the first trace L1) on both sides of the second via to be relatively wider, and setting the width of the relatively shorter traces (e.g., the second trace L2) to be relatively thinner, the overall resistance of the relatively longer traces (e.g., the first trace L1) can be reduced, thereby reducing the load on the relatively longer traces (e.g., the first trace L1), ensuring that the resistance of the traces on both sides of the second via changes uniformly and the load is relatively balanced.

[0110] In one exemplary embodiment, such as Figures 6A to 8 As shown, the width w1 of the first trace L1 can be approximately 4.5 micrometers to 6.5 micrometers, and the width w2 of the second trace L2 can be approximately 2.5 micrometers to 4.4 micrometers. For example, the width w1 of the first trace L1 can be approximately 5.4 micrometers, and the width w2 of the second trace L2 can be approximately 3.4 micrometers. Here, the width of the trace can refer to the feature dimension in the second direction. This embodiment of the present disclosure does not limit this aspect.

[0111] In one exemplary embodiment, such as Figures 6A to 8 As shown, in the second direction DR2, the pitch 1 between adjacent first traces L1 and the pitch 2 between adjacent second traces L2 can be the same. The pitch between adjacent traces (also known as center distance) can refer to the distance between the center points of two adjacent traces in the second direction DR2, or it can refer to the distance between the same side of two adjacent traces in the second direction DR2.

[0112] In one exemplary embodiment, such as Figures 6A to 8 As shown, in the second direction DR2, at least one of the pitch 1 between adjacent first traces L1 and the pitch 2 between adjacent second traces L2 can be approximately 16 micrometers to 20 micrometers. For example, the pitch 1 between adjacent first traces L1 and the pitch 2 between adjacent second traces L2 can both be 18 micrometers. Here, this disclosure does not limit this aspect.

[0113] In one exemplary embodiment, the first trace L1 and the second trace L2 can be multiple data lines or multiple touch lines extended in a fan-out manner. This disclosure does not limit the scope of the embodiments.

[0114] In one exemplary embodiment, the third hole area may also have the function of configuring wiring, and the wiring is connected to the lead wire in the first wiring area.

[0115] In one exemplary embodiment, such as Figure 6A As shown, the third hole area 403 may further include: multiple third traces L3 extending along the first direction DR1 on both sides of the virtual hole 505 in the second direction DR2, and multiple fourth traces L4 extending along the first direction DR1. The length of the third traces L3 is greater than the length of the fourth traces L4, and the width of the third traces L3 is greater than the width of the fourth traces L4. The third traces L3 and the first traces L1 may be symmetrically arranged with respect to the center line CL, and the fourth traces L4 and the second traces L2 may be symmetrically arranged with respect to the center line CL. The width of the traces may refer to the feature dimension in the second direction DR2, and the length of the traces may refer to the feature dimension in the first direction DR1. Thus, by setting the width of the relatively longer traces (e.g., the third trace L3) on both sides of the virtual via to be relatively wide, and the width of the relatively shorter traces (e.g., the fourth trace L4) to be relatively narrow, the overall resistance of the relatively longer traces (e.g., the third trace L3) can be reduced. This reduces the load on the relatively longer traces (e.g., the third trace L3), ensuring a uniform resistance variation and relatively balanced load on both sides of the virtual via. Furthermore, since the third trace L3 and the first trace L1 are symmetrically positioned relative to the center line CL, and the fourth trace L4 and the second trace L2 are symmetrically positioned relative to the center line CL, a uniform resistance variation in the traces within the second trace area can be ensured.

[0116] In one exemplary embodiment, the width of the third trace L3 may be the same as the width of the first trace L1. For example, the width of the third trace L3 may be approximately 4.5 micrometers to 6.5 micrometers. For example, the width of the third trace L3 may be approximately 5.4 micrometers. Here, the width of the trace may refer to the feature dimension in the second direction. This disclosure does not limit this aspect.

[0117] In one exemplary embodiment, the width of the fourth trace L4 can be the same as the width of the second trace L2. For example, the width of the fourth trace L4 can be approximately 2.5 micrometers to 4.4 micrometers. For example, the width of the fourth trace L4 can be approximately 3.4 micrometers. The width of the trace can refer to the feature dimension in the second direction. This disclosure does not limit this aspect.

[0118] In one exemplary embodiment, the spacing between adjacent third traces L3 can be the same as the spacing between adjacent first traces L1. The spacing between adjacent fourth traces L4 can be the same as the spacing between adjacent second traces L2. The spacing between adjacent traces (also known as center distance) can refer to the distance between the center points of two adjacent traces in the second direction DR2, or it can refer to the distance between the same side of two adjacent traces in the second direction DR2.

[0119] In one exemplary embodiment, in the second direction DR2, at least one of the spacing between adjacent third traces L3 and the spacing between adjacent fourth traces L4 can be approximately 16 micrometers to 20 micrometers. For example, the spacing between adjacent third traces L3 and the spacing between adjacent fourth traces L4 can both be 18 micrometers. Here, this disclosure does not limit the scope of the embodiments.

[0120] In one exemplary embodiment, the third trace L3 and the fourth trace L4 can be multiple data lines or multiple touch lines extended in a fan-out manner. This embodiment does not limit the scope of the invention.

[0121] In one exemplary embodiment, such as Figure 6A As shown, the second sub-region 404 may include a fifth trace L5 extending along the first direction DR1, and the third sub-region 405 may include a sixth trace L6 extending along the first direction DR1. The fifth trace L5 and the sixth trace L6 may be symmetrically arranged with respect to the center line CL.

[0122] In one exemplary embodiment, the width of the sixth trace L6 can be the same as the width of the fifth trace L5. For example, the width of the sixth trace L6 and the width of the fifth trace L5 can be approximately 2 micrometers to 7 micrometers. For example, the width of the sixth trace L6 and the width of the fifth trace L5 can be approximately 5.4 micrometers. Here, this disclosure does not limit the scope of the embodiments.

[0123] In one exemplary embodiment, the spacing between adjacent sixth traces L6 can be the same as the spacing between adjacent fifth traces L5. For example, in the second direction DR2, at least one of the spacings between adjacent sixth traces L6 and adjacent fifth traces L5 can be approximately 16 micrometers to 20 micrometers. For example, the spacing between adjacent sixth traces L6 and adjacent fifth traces L5 can both be 18 micrometers. The spacing between adjacent traces (also referred to as center distance) can refer to the distance between the center points of two adjacent traces in the second direction DR2, or it can refer to the distance between the same side edges of two adjacent traces in the second direction DR2. This disclosure does not limit this aspect.

[0124] In one exemplary embodiment, such as Figure 4 As shown, the display panel may further include virtual traces, which may include at least one of a second virtual trace 502 located in the first hole area 401 surrounding the second through hole 501 and a first virtual trace 504 located in the second hole area 402 surrounding the first through hole 503. Thus, by setting virtual traces around the through holes, the risk of crack defects around the through holes can be reduced during the drilling process in the manufacturing of the display panel, avoiding adverse effects on the normal traces around the through holes, and improving product yield. This disclosure does not limit the scope of the embodiments described herein.

[0125] For example, when the dummy via does not penetrate any film layer, a third dummy trace can be provided around the dummy via. Alternatively, when the dummy via can penetrate the film layer, a third dummy trace may not be provided around the dummy via. Or, when the dummy via can penetrate the film layer, a third dummy trace can be provided around the dummy via. In this way, during the drilling process, the risk of crack defects around the dummy via can be reduced, avoiding adverse effects on the normal traces around the via, and improving product yield. Here, the embodiments of this disclosure do not limit this.

[0126] In one exemplary embodiment, such as Figure 4 As shown, the shape of the first virtual trace 504 can be the same as the shape of the first via 503. However, this embodiment of the present disclosure does not limit this.

[0127] In one exemplary embodiment, such as Figure 4 As shown, the shape of the second virtual trace 502 can be the same as the shape of the second via 501. However, this embodiment of the present disclosure does not limit this.

[0128] In one exemplary embodiment, a virtual trace may include one or more of continuous closed traces and discontinuous open traces. For example, taking the virtual trace as an example where the virtual trace includes discontinuous open traces, the virtual trace may include: multiple virtual trace segments and discontinuities located between two adjacent virtual trace segments. Here, the embodiments of this disclosure do not limit this.

[0129] In one exemplary embodiment, such as Figure 4 As shown, the first virtual trace 504 can be a continuous trace. Or, as... Figure 6B and Figure 6CAs shown, the first virtual trace 504 can be a discontinuous trace. The first virtual trace 504 may include: multiple first virtual trace segments 504-1 and a first discontinuity 504-2 located between two adjacent first virtual trace segments 504-1. Wherein, in Figure 6B and Figure 6C The eight first virtual trace segments 504-1 and four first discontinuities 504-2 in the first virtual trace 504 are used as examples for illustration, and do not represent the actual number of first virtual trace segments and first discontinuities. Furthermore, in Figure 6B and Figure 6C The first virtual trace 504 is illustrated by an example of a combination of continuous closed virtual traces and discontinuous virtual traces. However, this embodiment does not limit the scope of the invention.

[0130] In one exemplary embodiment, such as Figure 6C As shown, the first discontinuity 504-2 may include a first sub-mark structure 61. For example, the first sub-mark structure 61 may be, but is not limited to, any one or more of an inverted "T" shape, a rectangular structure, or a cross shape. Here, this disclosure embodiment does not limit it in this way.

[0131] In one exemplary embodiment, such as Figure 6C As shown, the first through-hole 503 may include a second sub-mark structure 62. For example, the second sub-mark structure 62 may be, but is not limited to, any one or more of an inverted "T" shape, a rectangular structure, or a cross shape. Here, this disclosure embodiment does not limit it in this way.

[0132] In one exemplary embodiment, such as Figure 6B and Figure 6C As shown, a first cutting line 71 can be provided on the outside of the second sub-mark structure. The shape of the first cutting line 71 is the same as the outline of the first through hole 503. After the film layer process of the display motherboard is completed, the cutting equipment cuts the display motherboard along the first cutting line 71 to form the first through hole 503 in multiple display panels.

[0133] In one exemplary embodiment, such as Figure 4 As shown, the second virtual trace 502 can be a continuous trace. Or, as... Figure 6D and Figure 6E As shown, the second virtual trace 502 can be a discontinuous trace. The second virtual trace 502 may include: multiple second virtual trace segments 502-1 and a second discontinuity 502-2 located between two adjacent second virtual trace segments 502-1. Wherein, in Figure 6D and Figure 6EThe example shown is of eight second virtual trace segments 502-1 and four second discontinuities 502-2 within the second virtual trace 502. This does not represent the actual number of second virtual trace segments and second discontinuities. Furthermore, in... Figure 6D and Figure 6E The second virtual trace 502 is illustrated by an example of a combination of continuous closed virtual traces and discontinuous virtual traces. However, this embodiment does not limit the scope of the invention.

[0134] In one exemplary embodiment, such as Figure 6E As shown, the second discontinuity 502-2 may include a third sub-mark structure 63. For example, the third sub-mark structure 63 may be, but is not limited to, any one or more of an inverted "T" shape, a rectangular structure, or a cross shape. Here, this disclosure embodiment does not limit it in this way.

[0135] In one exemplary embodiment, such as Figure 6E As shown, the second through-hole 501 may include a fourth sub-mark structure 64. For example, the fourth sub-mark structure 64 may be, but is not limited to, any one or more of an inverted "T" shape, a rectangular structure, or a cross-shaped structure. Here, this disclosure embodiment does not limit it in this way.

[0136] In one exemplary embodiment, such as Figure 6D and Figure 6E As shown, a second cutting line 72 can be provided on the outside of the fourth sub-mark structure 64. The shape of the second cutting line 72 is the same as the outline of the second through hole 501. After the film layer process of the display motherboard is completed, the cutting equipment cuts the display motherboard along the second cutting line 72 to form multiple second through holes 501 in the display panel.

[0137] In one exemplary embodiment, the width of the second virtual trace 502 may be the same as the width of the first virtual trace 504. The width of the trace may refer to the feature dimension in the second direction DR2.

[0138] In one exemplary embodiment, the width of the second virtual trace 502 and the width of the first virtual trace 504 can be approximately 3 micrometers to 8 micrometers. For example, the width of the second virtual trace 502 and the width of the first virtual trace 504 can be approximately 5.4 micrometers. Here, this disclosure does not limit the scope of the embodiments.

[0139] In one exemplary embodiment, the binding region can be an irregularly shaped binding region. Here, an irregularly shaped binding region can refer to a binding region that is different from a binding region with a regular shape (e.g., a rectangular binding region).

[0140] In one exemplary embodiment, such as Figure 6A As shown, in a plane parallel to the display panel, the outline shape of the binding area 200 may include: a first edge 200-1 (e.g., as the upper edge), a second edge 200-2 (e.g., as the lower edge opposite to the upper edge), a third edge 200-3 (e.g., as the left edge) and a fourth edge 200-4 (e.g., as the right edge opposite to the left edge).

[0141] In one exemplary embodiment, such as Figure 6A As shown, the first edge 200-1 can extend along the second direction DR2 and is located on the side closer to the display area 100; the second edge 200-2 can extend along the second direction DR2 and is located on the side of the first edge 200-1 away from the display area 100; the third edge 200-3 can extend along the first direction DR1, and the third edge 200-3 may include: a first part that bends and extends in sequence along the first direction DR1 and a second part that extends vertically, the first end of the first part bends in the opposite direction to the second direction DR2 and connects to the first end of the first edge 200-1, and the second end of the first part bends in the opposite direction to the second direction DR2. The second edge 200-2 bends in the opposite direction to DR2 and connects to the first end of the second part. The second end of the second part connects to the first end of the second edge 200-2. The fourth edge 200-4 can extend along the first direction DR1 and may include: a curved third part and a vertically extending fourth part arranged sequentially along the first direction DR1. The first end of the third part bends towards the second direction DR2 and connects to the second end of the first edge 200-1. The second end of the third part bends towards the second direction DR2 and connects to the first end of the fourth part. The second end of the fourth part connects to the second end of the second edge 200-2. The first direction DR1 and the second direction DR2 intersect. Here, in Figure 6A In the example shown, the lower edge of the display area 100 (i.e., the edge located near the binding area 200) can coincide with the upper edge of the binding area 200 (i.e., the first edge 200-1 located near the display area 100) for illustration.

[0142] This disclosure also provides a display device. The display device may include: a display panel as described in one or more of the exemplary embodiments above, and a first photosensitive element, wherein the position of the first photosensitive element corresponds to the position of the first through hole.

[0143] In one exemplary embodiment, the display device may further include a second photosensitive element, and the second wiring area may further include a second through hole located on one side of the first through hole in a second direction, wherein the position of the second photosensitive element corresponds to the position of the second through hole.

[0144] Figure 9This is a schematic diagram of the structure of the display device in an exemplary embodiment of this disclosure, such as... Figure 9 As shown, in an exemplary embodiment, the display device may include: a display panel, a first photosensitive element 600, and a second photosensitive element (not shown). The display panel may include: a display area 100 and a bonding area 200 located on one side of the display area 100 along a first direction DR1. The bonding area 200 may include: a first trace area 201, a bending area 202, a second trace area 203, and a composite circuit area 204 sequentially arranged along the first direction DR1 (i.e., the direction away from the display area 100). The second trace area 203 may include: a first sub-area, and a second sub-area (not shown) and a third sub-area (not shown) located on both sides of the first sub-area along a second direction DR2. The first sub-area may include: a second hole area, and a first hole area (not shown) and a third hole area (not shown) located on both sides of the second hole area along a second direction DR2. The first hole area is provided with a second through hole (not shown), the second hole area is provided with a first through hole 503, and the third hole area is provided with a virtual hole (not shown). The first photosensitive element 600 can be positioned to correspond with the first through-hole 503, and the second photosensitive element can be positioned to correspond with the second through-hole. Thus, by symmetrically arranging the first through-holes about the center line in the bonding area of ​​the display panel, the uniformity of the wiring load in the second wiring area can be ensured. This guarantees consistent wiring impedance on the display panel and avoids the wiring pressure caused by wiring concentrated on one side. Consequently, the display effect can be improved. Furthermore, by positioning the photosensitive elements to correspond with the through-holes in the bonding area, there is no need to create holes in the display area, which is beneficial for achieving a full-screen display.

[0145] In one exemplary embodiment, the first photosensitive element may be a fingerprint recognition component, a camera component, or an infrared sensor, etc. For example, the first photosensitive element may include a camera component, such as an MDL device. This disclosure does not limit the scope of the embodiments.

[0146] In one exemplary embodiment, the second photosensitive element may be a fingerprint recognition component, a camera component, or an infrared sensor, etc. For example, the second photosensitive element may include a fingerprint recognition component. For example, the fingerprint recognition component may be an optical fingerprint recognition component or an ultrasonic fingerprint recognition component, etc., and this disclosure does not limit the specific embodiment.

[0147] In one exemplary embodiment, the display device may include, but is not limited to, an OLED display device or an AMOLED (Active-matrix organic light-emitting diode) display device. This disclosure does not limit the scope of the application.

[0148] In one exemplary embodiment, the display device may include, but is not limited to, any product or component with display functionality such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. This disclosure does not limit the scope of the embodiment.

[0149] The description of the above display device embodiments is similar to that of the above display panel embodiments, and has similar beneficial effects. For technical details not disclosed in the display device embodiments of this disclosure, those skilled in the art should refer to the description in the display panel embodiments of this disclosure for understanding, and will not repeat them here.

[0150] While the embodiments disclosed herein are as described above, the above content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit this disclosure. Any person skilled in the art to which this disclosure pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed herein, but the scope of patent protection of this disclosure shall still be determined by the scope defined in the appended claims.

Claims

1. A display panel, comprising: The display area and the binding area located on one side of the display area in a first direction; The display area includes: a plurality of sub-pixels arranged in an array and a plurality of data lines electrically connected to the plurality of sub-pixels; the bonding area includes: a plurality of data line leads connected to the plurality of data lines and a plurality of pins connected to the plurality of data line leads, wherein the plurality of pins are located on the side of the plurality of data line leads away from the display area; wherein, The binding area further includes: a first routing area, a bending area, and a second routing area arranged sequentially along a first direction. The second routing area includes: a first sub-area, a first through-hole, a second through-hole, and a virtual hole. The second routing area has a center line extending along the first direction. The first through-hole is located between the multiple data line leads and is configured to correspond to a first photosensitive element. The second through-hole is configured to correspond to a second photosensitive element. The first sub-area includes: a first hole area, a second hole area, and a third hole area arranged sequentially along a second direction. The first through-hole is located in the second hole area, the second through-hole is located in the first hole area, and the virtual hole is located in the third hole area. The virtual hole and the second through-hole are symmetrically arranged with respect to the center line, and the shape of the virtual hole is the same as the shape of the second through-hole. The size of the second through-hole is the same as the size of the virtual hole to ensure the uniformity of the routing load in the second routing area. The first hole area further includes: multiple first traces extending along the first direction and multiple second traces extending along the first direction, wherein the multiple first traces and the multiple second traces are respectively located on both sides of the second through hole along the second direction, the length of the first trace is greater than the length of the second trace, and the width of the first trace is greater than the width of the second trace; the third hole area further includes: multiple third traces extending along the first direction and multiple fourth traces extending along the first direction, wherein the multiple third traces and the multiple fourth traces are respectively located on both sides of the virtual hole, the length of the third trace is greater than the length of the fourth trace, and the width of the third trace is greater than the width of the fourth trace, the third traces and the first traces are symmetrically arranged with respect to the center line, and the fourth traces and the second traces are symmetrically arranged with respect to the center line; to ensure that the resistance of the traces on both sides of the virtual hole changes uniformly and the load is relatively balanced, and that the resistance of the traces in the second trace area changes uniformly.

2. The display panel according to claim 1, wherein, The first through hole is symmetrically arranged about the center line.

3. The display panel according to claim 1, wherein, The second direction intersects with the first direction.

4. The display panel according to claim 1, wherein, In a plane parallel to the display panel, the shape of the second through hole and the shape of the virtual hole are selected from any one of rectangle, rounded rectangle, ellipse, polygon and circle.

5. The display panel according to claim 4, wherein, In a plane parallel to the display panel, the second through hole is a rounded rectangle with a length of 2 mm to 15 mm in the first direction and a width of 2 mm to 5 mm in the second direction.

6. The display panel according to claim 1, wherein, In the second direction, the spacing between adjacent first traces is the same as the spacing between adjacent second traces.

7. The display panel according to claim 1, wherein the second wiring area further comprises: The virtual trace includes at least one of a first virtual trace surrounding the first via and a second virtual trace surrounding the second via.

8. The display panel according to claim 7, wherein, The shape of the first virtual trace is the same as the shape of the first via, and the shape of the second virtual trace is the same as the shape of the second via.

9. The display panel according to claim 7, wherein, The width of the first virtual trace is the same as the width of the second virtual trace.

10. The display panel according to claim 7, wherein, The virtual routing includes: multiple virtual routing segments and discontinuities located between two adjacent virtual routing segments.

11. The display panel according to claim 1, wherein, The second routing area further includes a second sub-area and a third sub-area located on both sides of the first sub-area along the second direction. The second sub-area and the third sub-area are symmetrically arranged with respect to the center line, and the second direction intersects the first direction.

12. The display panel according to claim 11, wherein, The second sub-region includes a fifth trace extending along the first direction, and the third sub-region includes a sixth trace extending along the first direction, wherein the fifth trace and the sixth trace are symmetrically arranged with respect to the center line.

13. The display panel according to claim 12, wherein, The width of the sixth trace is the same as the width of the fifth trace.

14. The display panel according to claim 1, wherein, In a plane parallel to the display panel, the shapes of the first through hole and the second through hole are selected from any one or more of the following: circle, rectangle, rounded rectangle, ellipse and polygon.

15. A display device, comprising: The display panel and the first photosensitive element as described in any one of claims 1 to 14, wherein the position of the first photosensitive element corresponds to the position of the first through hole.

16. The display device according to claim 15, further comprising: The second photosensitive element, the second wiring area further includes a second through hole, located on one side of the first through hole in the second direction, and the setting position of the second photosensitive element corresponds to the setting position of the second through hole.

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