A current detection circuit

Abstract

This application discloses a current detection circuit, comprising: a test output terminal connected to a first signal input terminal of the circuit under test (DUT); a test input terminal connected to the first signal output terminal of the DUT; a detection module connected to the test input terminal; and a current limiting module connected to both the detection module and the test output terminal. The current limiting module provided in this application can limit the current in the detection circuit when the DUT exits the test, preventing oscillation at the output terminal of the DUT from damaging the DUT. This protects the chip in the DUT and reduces the probability of chip damage.

Description

Technical Field

[0001] The embodiments of this application relate to the field of chip testing technology, and in particular to a current detection circuit. Background Technology

[0002] Power device driver ICs (integrated circuits) have corresponding maximum source current and maximum sink current capabilities. A driver IC typically includes at least two transistors and ESD protection circuitry. Before shipping or using the driver IC, its maximum source current and maximum sink current must be tested. The test circuit includes parasitic inductors, sampling resistors, and loads. After testing, during the process of exiting the maximum source current or maximum sink current test, because the current in the parasitic inductor in the test circuit is still relatively large, with one transistor inside the driver IC off and the other on, severe oscillations will occur at the driver IC's output. This may trigger the chip's internal ESD protection circuitry, potentially causing damage or failure of the driver IC. Summary of the Invention

[0003] Embodiments of this application provide a current detection circuit to solve the technical problem in the prior art that the driver IC may be damaged when exiting the test.

[0004] To address the aforementioned technical problems, embodiments of this application disclose the following technical solutions:

[0005] This application provides a current detection circuit, including:

[0006] The test output terminal is connected to the first signal input terminal of the circuit under test.

[0007] A test input terminal is connected to the first signal output terminal of the circuit under test.

[0008] A detection module is connected to the test input terminal;

[0009] A current limiting module is provided, which is connected to both the detection module and the test output terminal.

[0010] Furthermore, the current limiting module includes a first transistor and a third capacitor. The drain of the first transistor is connected to the detection module, the source of the first transistor is connected to one end of the third capacitor, the other end of the third capacitor is connected to the detection module, and the gate of the first transistor receives a first control signal.

[0011] Furthermore, the detection module includes a first inductor, a first diode, a first resistor, and a first capacitor;

[0012] One end of the first inductor is connected to the test input terminal, the other end of the first inductor is connected to the anode of the first diode, the cathode of the first diode is connected to one end of the first resistor, the other end of the first resistor is connected to one end of the first capacitor, and the other end of the first capacitor is connected to the drain of the first transistor.

[0013] The other end of the third capacitor is connected between the first resistor and the first capacitor.

[0014] Furthermore, the detection module includes a first detection line and a second detection line; the first detection line includes a first switch, a first inductor, a first diode, a first resistor, and a first capacitor;

[0015] One end of the first switch is connected to the test input terminal, the other end of the first switch is connected to one end of the first inductor, the other end of the first inductor is connected to the anode of the first diode, the cathode of the first diode is connected to one end of the first resistor, the other end of the first resistor is connected to one end of the first capacitor, and the other end of the first capacitor is connected to the drain of the first transistor.

[0016] The other end of the third capacitor is connected between the first resistor and the first capacitor.

[0017] Furthermore, the second detection circuit includes a second switch, a second inductor, a second diode, a second resistor, a third switch, a fourth transistor, a fourth capacitor, and a fifth capacitor;

[0018] One end of the second switch is connected to the test input terminal, the other end of the second switch is connected to one end of the second inductor, the other end of the second inductor is connected to the cathode of the second diode, the anode of the second diode is connected to one end of the second resistor, the other end of the second resistor is connected to one end of the third switch, and the other end of the third switch is connected to the operating voltage; the gate of the fourth transistor receives the second control signal, the drain of the fourth transistor is connected to one end of the fourth capacitor, the source of the fourth transistor is connected between the second resistor and the third switch, the other end of the fourth capacitor is grounded, and the fifth capacitor is connected in parallel with the fourth transistor and the fourth capacitor.

[0019] Furthermore, the detection module includes a first switch, a first inductor, a first diode, a first resistor, a first capacitor, a second switch, a second inductor, a second diode, a third switch, and a fourth transistor;

[0020] One end of the first switch is connected to the test input terminal, and the other end of the first switch is connected to one end of the first inductor. The other end of the first inductor is connected to the anode of the first diode. The cathode of the first diode is connected to one end of the first resistor. The other end of the first resistor is connected to one end of the first capacitor. The other end of the first capacitor is connected to the drain of the first transistor. The other end of the first capacitor is also connected to one end of the third switch, and the other end of the third switch is connected to the operating voltage. One end of the second switch is connected to the test input terminal, and the other end of the second switch is connected to one end of the second inductor. The other end of the second inductor is connected to the cathode of the second diode. The anode of the second diode is connected to the cathode of the first diode. The source of the fourth transistor is connected to the source of the first transistor. The gate of the fourth transistor receives the first control signal, and the drain of the fourth transistor is grounded.

[0021] Furthermore, the current detection circuit also includes a signal generator, the positive terminal of which is connected to the test output terminal, and the negative terminal of which is grounded.

[0022] Furthermore, the current detection circuit also includes a ground terminal, which is connected to the second signal output terminal of the circuit under test.

[0023] Furthermore, the current detection circuit also includes a power supply terminal, which is connected to the second signal input terminal of the circuit under test and is connected to the power supply voltage.

[0024] Furthermore, the current detection circuit also includes a second capacitor, one end of which is connected to the power supply terminal, and the other end of which is grounded.

[0025] One of the above technical solutions has the following advantages or beneficial effects:

[0026] Compared with existing technologies, this application provides a current detection circuit, comprising: a test output terminal connected to a first signal input terminal of the circuit under test (DUT); a test input terminal connected to the first signal output terminal of the DUT; a detection module connected to the test input terminal; and a current limiting module connected to both the detection module and the test output terminal. The current limiting module provided in this application can limit the current in the detection circuit when the DUT exits the test, preventing oscillation at the output terminal of the DUT from damaging the DUT. This protects the chip in the DUT and reduces the probability of chip damage. Attached Figure Description

[0027] The technical solution and other beneficial effects of this application will become apparent from the following detailed description of specific embodiments in conjunction with the accompanying drawings.

[0028] Figure 1 This is a schematic diagram of the circuit structure provided in Embodiment 1 of this application;

[0029] Figure 2 This is a schematic diagram of the source current control timing provided in an embodiment of this application;

[0030] Figure 3 This is a schematic diagram of the circuit structure provided in Embodiment 2 of this application;

[0031] Figure 4 This is a schematic diagram of the circuit structure provided in Embodiment 3 of this application;

[0032] Figure 5 This is a schematic diagram of the sink current control timing provided in an embodiment of this application.

[0033] The attached figures are labeled as follows:

[0034] 1-Signal generator, 2-Logic controller, 3-First protection circuit, 4-Second protection circuit, 5-Driver IC module. Detailed Implementation

[0035] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. In the description of this application, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the accompanying drawings and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0036] The specific implementation methods of this application are illustrated below through examples:

[0037] Example 1

[0038] like Figure 1As shown in the figure, this application discloses a current detection circuit, including a test output terminal A, a test input terminal B, a detection module, and a current limiting module. The test output terminal A is connected to the first signal input terminal of the circuit under test 5; the test input terminal B is connected to the first signal output terminal of the circuit under test 5; the detection module is connected to the test input terminal B; and the current limiting module is connected to both the detection module and the test output terminal A. The circuit under test 5 is a driver IC circuit, including a logic controller 2, a second transistor Q2, a third transistor Q3, a first protection circuit 3, and a second protection circuit 4. The input terminal of the logic controller 2 is the first signal input terminal of the circuit under test 5. The first output terminal of the logic controller 2 is connected to the gate of the second transistor Q2, and the second output terminal of the logic controller 2 is connected to the gate of the third transistor Q3. The drain of the second transistor Q2 is connected to the drain of the third transistor Q3, and the source of the third transistor Q3 is connected to the supply voltage VCC. The source of the second transistor Q2 is grounded. The two ends of the first protection circuit 3 are connected to the drain and source of the third transistor Q3, respectively, and the two ends of the second protection circuit 4 are connected to the source and drain of the second transistor Q2, respectively.

[0039] like Figure 1 As shown in the embodiment of this application, the current limiting module includes a first transistor Q1 and a third capacitor C3. The drain of the first transistor Q1 is connected to the detection module, the source of the first transistor Q1 is connected to one end of the third capacitor C3, the other end of the third capacitor C3 is connected to the detection module, and the gate of the first transistor Q1 receives a first control signal G3.

[0040] like Figure 1 As shown in this embodiment, the detection module includes a first inductor L1, a first diode D1, a first resistor R1, and a first capacitor C1. One end of the first inductor L1 is connected to the test input terminal B, and the other end of the first inductor L1 is connected to the anode of the first diode D1. The cathode of the first diode D1 is connected to one end of the first resistor R1, and the other end of the first resistor R1 is connected to one end of the first capacitor C1. The other end of the first capacitor C1 is connected to the drain of the first transistor Q1. The other end of the third capacitor C3 is connected between the first resistor R1 and the first capacitor C1. It can be understood that the first diode D1 is used to prevent reverse current from flowing into the circuit under test 5 when the test is exited. The first capacitor C1 and the third capacitor C3 are used to simulate a load, and the capacitance of the first capacitor C1 is greater than the capacitance of the third capacitor C3. The first transistor Q1 is a power transistor.

[0041] like Figure 2The diagram shown is a timing diagram in an embodiment of this application, where t0, t1, t2, t3, and t4 are different time nodes. Before time t0, the current detection circuit is in the preparation stage, the output voltage of the first signal output terminal of the circuit under test is 0V, and the first transistor Q1 is turned off. At time t0, the first control signal G3 is input at a high level, the first transistor Q1 is turned on, and the simulated load, the first capacitor C1 and the third capacitor C3, are connected in parallel to the current detection circuit. During the t0 to t1 stage, the first signal input terminal of the circuit under test 5 receives a signal, which turns on the third transistor Q3 inside the circuit under test 5 at time t1, and the first signal output terminal starts to rise from 0V, while the output current I at the first output terminal increases. pk The current rises rapidly to its maximum value. Due to the relatively large capacitance of the first capacitor C1 and the presence of the first inductor L1, the output current I at the first signal output terminal increases rapidly. PK After reaching its maximum value, it remains constant; during the t1 to t2 period, the maximum source current I of the first resistor R1 at the first signal output terminal is... PK Sampling and recording are performed. During the t2-t3 phase, after the output current at the first signal output terminal is reported and recorded, at time t2, the first control signal G3 is input at a low level, turning off the first transistor Q1, disconnecting the simulated load first capacitor C1, and the current of the first inductor L1 charges the third capacitor C3 and quickly drops to zero. The voltage at the first signal output terminal quickly rises to be equal to the supply voltage VCC. During the t3-t4 phase, the voltage at the first signal output terminal reaches equal to the supply voltage VCC, and the output current at the first signal output terminal is zero. The input signal at the first signal input terminal of the circuit under test 5 is changed. At time t4, the internal third transistor Q3 of the circuit under test 5 is turned off, the second transistor Q2 is turned on, and the first signal output terminal drops from VCC to 0V. At this time, the test ends.

[0042] In this embodiment, a large-capacity first capacitor C1 and a small-capacity third capacitor C3 are used as analog loads. The first capacitor C1 is switched by the first transistor Q1, so that the current on the first inductor L1 drops to 0 in advance, ensuring that the state of the first output terminal does not oscillate when it changes from high to low, or that the circuit under test 5 does not oscillate when it is powered off after the test is completed.

[0043] In this embodiment, the current detection circuit further includes a signal generator 1, a ground terminal, a power supply terminal, and a second capacitor C2. The positive terminal of the signal generator 1 is connected to the test output terminal A, and the negative terminal of the signal generator 1 is grounded. The ground terminal is connected to the second signal output terminal of the circuit under test 5. The power supply terminal is connected to the second signal input terminal of the circuit under test 5 and is connected to the power supply voltage VCC. One end of the second capacitor C2 is connected to the power supply terminal, and the other end of the second capacitor C2 is grounded.

[0044] Example 2

[0045] like Figure 3 As shown in the figure, this application discloses a current detection circuit, including a test output terminal A, a test input terminal B, a detection module, and a current limiting module. The test output terminal A is connected to the first signal input terminal of the circuit under test 5; the test input terminal B is connected to the first signal output terminal of the circuit under test 5; the detection module is connected to the test input terminal B; and the current limiting module is connected to both the detection module and the test output terminal A. The circuit under test 5 is a driver IC circuit, including a logic controller 2, a second transistor Q2, a third transistor Q3, a first protection circuit 3, and a second protection circuit 4. The input terminal of the logic controller 2 is the first signal input terminal of the circuit under test 5. The first output terminal of the logic controller 2 is connected to the gate of the second transistor Q2, and the second output terminal of the logic controller 2 is connected to the gate of the third transistor Q3. The drain of the second transistor Q2 is connected to the drain of the third transistor Q3, and the source of the third transistor Q3 is connected to the supply voltage VCC. The source of the second transistor Q2 is grounded. The two ends of the first protection circuit 3 are connected to the drain and source of the third transistor Q3, respectively, and the two ends of the second protection circuit 4 are connected to the source and drain of the second transistor Q2, respectively.

[0046] like Figure 3 As shown in the embodiment of this application, the current limiting module includes a first transistor Q1 and a third capacitor C3. The drain of the first transistor Q1 is connected to the detection module, the source of the first transistor Q1 is connected to one end of the third capacitor C3, the other end of the third capacitor C3 is connected to the detection module, and the gate of the first transistor Q1 receives a first control signal G3.

[0047] like Figure 3 As shown in the embodiment of this application, the detection module includes a first detection line and a second detection line; wherein the first detection line is an output source current test circuit, and the second detection line is an output sink current test circuit. The first detection line includes a first switch S1, a first inductor L1, a first diode D1, a first resistor R1, and a first capacitor C1; one end of the first switch S1 is connected to the test input terminal B, the other end of the first switch S1 is connected to one end of the first inductor L1, the other end of the first inductor L1 is connected to the anode of the first diode D1, the cathode of the first diode D1 is connected to one end of the first resistor R1, the other end of the first resistor R1 is connected to one end of the first capacitor C1, and the other end of the first capacitor C1 is connected to the drain of the first transistor Q1; wherein, the other end of the third capacitor is connected between the first resistor R1 and the first capacitor C1.

[0048] In this embodiment, the second detection circuit includes a second switch S2, a second inductor L2, a second diode D2, a second resistor R2, a third switch S3, a fourth transistor Q4, a fourth capacitor C4, and a fifth capacitor C5. One end of the second switch S2 is connected to the test input terminal B, and the other end of the second switch S2 is connected to one end of the second inductor L2. The other end of the second inductor L2 is connected to the cathode of the second diode D2, the anode of the second diode D2 is connected to one end of the second resistor R2, the other end of the second resistor R2 is connected to one end of the third switch S3, and the other end of the third switch S3 is connected to the operating voltage. The gate of the fourth transistor Q4 receives a second control signal, the drain of the fourth transistor Q4 is connected to one end of the fourth capacitor C4, the source of the fourth transistor Q4 is connected between the second resistor R2 and the third switch S3, the other end of the fourth capacitor C4 is grounded, and the fifth capacitor C5 is connected in parallel with the fourth transistor Q4 and the fourth capacitor C4. Understandably, when testing the maximum output source current, the first switch S1 is closed and the second switch S2 is open, while when testing the maximum output sink current, the first switch S1 is open and the second switch S2 is closed. The maximum output sink current and the maximum output source current are tested separately by controlling the two switches.

[0049] like Figure 5 The diagram shown is a timing diagram of an embodiment of this application, where t5, t6, t7, t8, and t9 are different time nodes. Before time t5, the current detection circuit is in the test preparation stage, the first signal output terminal of the circuit under test 5 outputs a high level, the first switch S1 is open, the second switch S2 is closed, and the fourth transistor Q4 is turned off. At time t5, the second control signal G4 is input at a low level, the fourth transistor Q4 is turned on, and the fourth capacitor C4 and the fifth capacitor C5 are connected in parallel to the circuit. During the t5-t6 stage, after the fourth transistor Q4 is turned on, the third switch S3 is turned on, charging the fourth capacitor C4 and the fifth capacitor C5 to be equal to the working voltage VDD, and then the third switch S3 is turned off. The first signal input terminal of the circuit under test 5 receives a signal, which at time t6 turns on the second transistor Q2 inside the circuit under test 5, and the voltage at the first signal output terminal begins to change from high to low. At this time, the output current I at the first signal output terminal... PK2 The current rapidly increases to its negative maximum value due to the presence of the second inductor L2 and the relatively large capacitance of the fourth capacitor C4, resulting in the output current I at the first signal output terminal. PK2 After reaching its negative maximum, it remains essentially unchanged; during the t6 to t7 stage, the second resistor R2 samples the maximum sink current I at the output terminal of the first signal. PK2And report the record; during the t7 to t8 phase, after the output current at the first signal output terminal is reported and recorded, at time t7, the second control signal G4 is input at a high level, turning off the fourth transistor Q4, disconnecting the fourth capacitor C4, and allowing the fifth capacitor C5 to continue discharging. The current of the second inductor L2 drops rapidly to zero, and the voltage at the first signal output terminal drops rapidly to 0V; during the t8 to t9 phase, the voltage at the first signal output terminal reaches 0V, and the current of the second inductor L2 is also zero. At time t9, the second switch S2 is opened, and the electrical test of the circuit under test 5 ends.

[0050] In this embodiment, a large-capacity first capacitor C1 and a small-capacity third capacitor C3 are used as analog loads. The first capacitor C1 is switched by the first transistor Q1, so that the current on the first inductor L1 drops to 0 in advance, ensuring that the state of the first output terminal does not oscillate when it changes from high to low, or that the circuit under test 5 does not oscillate when it is powered off after the test is completed.

[0051] In this embodiment, the current detection circuit further includes a signal generator, a ground terminal, a power supply terminal, and a second capacitor C2. The positive terminal of the signal generator is connected to the test output terminal A, and the negative terminal of the signal generator is grounded. The ground terminal is connected to the second signal output terminal of the circuit under test 5. The power supply terminal is connected to the second signal input terminal of the circuit under test 5 and is connected to the power supply voltage VCC. One end of the second capacitor C2 is connected to the power supply terminal, and the other end of the second capacitor C2 is grounded.

[0052] Example 3

[0053] like Figure 4 As shown in the figure, this application discloses a current detection circuit, including a test output terminal A, a test input terminal B, a detection module, and a current limiting module. The test output terminal A is connected to the first signal input terminal of the circuit under test 5; the test input terminal B is connected to the first signal output terminal of the circuit under test 5; the detection module is connected to the test input terminal B; and the current limiting module is connected to both the detection module and the test output terminal A. The circuit under test 5 is a driver IC circuit, including a logic controller 2, a second transistor Q2, a third transistor Q3, a first protection circuit 3, and a second protection circuit 4. The input terminal of the logic controller 2 is the first signal input terminal of the circuit under test 5. The first output terminal of the logic controller 2 is connected to the gate of the second transistor Q2, and the second output terminal of the logic controller 2 is connected to the gate of the third transistor Q3. The drain of the second transistor Q2 is connected to the drain of the third transistor Q3, and the source of the third transistor Q3 is connected to the supply voltage VCC. The source of the second transistor Q2 is grounded. The two ends of the first protection circuit 3 are connected to the drain and source of the third transistor Q3, respectively, and the two ends of the second protection circuit 4 are connected to the source and drain of the second transistor Q2, respectively.

[0054] like Figure 4As shown in the embodiment of this application, the current limiting module includes a first transistor Q1, a fourth transistor Q4, and a third capacitor C3. The drain of the first transistor Q1 is connected to the detection module, the source of the first transistor Q1 is connected to the source of the fourth transistor Q4, the drain of the fourth transistor Q4 is connected to one end of the third capacitor C3, the other end of the third capacitor C3 is connected to the detection module, and the gate of the first transistor Q1 receives a first control signal G3.

[0055] like Figure 4 As shown in this embodiment, the detection module includes a first switch S1, a first inductor L1, a first diode D1, a first resistor R1, a first capacitor C1, a second switch S2, a second inductor L2, a second diode D2, a third switch S3, and a fourth transistor Q4. One end of the first switch S1 is connected to the test input terminal B, and the other end of the first switch S1 is connected to one end of the first inductor L1. The other end of the first inductor L1 is connected to the anode of the first diode D1, the cathode of the first diode D1 is connected to one end of the first resistor R1, and the other end of the first resistor R1 is connected to one end of the first capacitor C1. The other end of capacitor C1 is connected to the drain of the first transistor Q1; the other end of the first capacitor C1 is also connected to one end of the third switch S3, and the other end of the third switch S3 is connected to the working voltage; one end of the second switch S2 is connected to the test input terminal B, the other end of the second switch S2 is connected to one end of the second inductor L2, the other end of the second inductor L2 is connected to the cathode of the second diode D2, the anode of the second diode D2 is connected to the cathode of the first diode D1, the source of the fourth transistor Q4 is connected to the source of the first transistor Q1, the gate of the fourth transistor Q4 receives the first control signal, and the drain of the fourth transistor Q4 is grounded.

[0056] In this embodiment, a large-capacity first capacitor C1 and a small-capacity third capacitor C3 are used as analog loads. The first capacitor C1 is switched by the first transistor Q1, so that the current on the first inductor L1 drops to 0 in advance, ensuring that the state of the first output terminal does not oscillate when it changes from high to low, or that the circuit under test 5 does not oscillate when it is powered off after the test is completed.

[0057] In this embodiment, the current detection circuit further includes a signal generator, a ground terminal, a power supply terminal, and a second capacitor C2. The positive terminal of the signal generator is connected to the test output terminal A, and the negative terminal of the signal generator is grounded. The ground terminal is connected to the second signal output terminal of the circuit under test 5. The power supply terminal is connected to the second signal input terminal of the circuit under test 5 and is connected to the power supply voltage VCC. One end of the second capacitor C2 is connected to the power supply terminal, and the other end of the second capacitor C2 is grounded.

[0058] The foregoing has provided a detailed description of a current detection circuit provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A current detection circuit, characterized in that, include: The test output terminal is connected to the first signal input terminal of the circuit under test. A test input terminal is connected to the first signal output terminal of the circuit under test. A detection module is connected to the test input terminal; A current limiting module is connected to both the detection module and the test output terminal. The current limiting module includes a first transistor and a third capacitor. The drain of the first transistor is connected to the detection module, the source of the first transistor is connected to one end of the third capacitor, the other end of the third capacitor is connected to the detection module, and the gate of the first transistor receives a first control signal. The detection module includes a first inductor, a first diode, a first resistor, and a first capacitor; one end of the first inductor is connected to the test input terminal, the other end of the first inductor is connected to the anode of the first diode, the cathode of the first diode is connected to one end of the first resistor, the other end of the first resistor is connected to one end of the first capacitor, and the other end of the first capacitor is connected to the drain of the first transistor; wherein, the other end of the third capacitor is connected between the first resistor and the first capacitor. The first capacitor and the third capacitor are used to simulate a load. The first capacitor is switched by the first transistor so that the current on the first inductor drops to zero in advance.

2. The current detection circuit as described in claim 1, characterized in that, The detection module also includes a first switch; One end of the first switch is connected to the test input terminal, and the other end of the first switch is connected to one end of the first inductor. The other end of the third capacitor is connected between the first resistor and the first capacitor.

3. The current detection circuit as described in claim 2, characterized in that, The detection module further includes a second detection circuit, which includes a second switch, a second inductor, a second diode, a second resistor, a third switch, a fourth transistor, a fourth capacitor, and a fifth capacitor. One end of the second switch is connected to the test input terminal, the other end of the second switch is connected to one end of the second inductor, the other end of the second inductor is connected to the cathode of the second diode, the anode of the second diode is connected to one end of the second resistor, the other end of the second resistor is connected to one end of the third switch, and the other end of the third switch is connected to the operating voltage; the gate of the fourth transistor receives the second control signal, the drain of the fourth transistor is connected to one end of the fourth capacitor, the source of the fourth transistor is connected between the second resistor and the third switch, the other end of the fourth capacitor is grounded, and the fifth capacitor is connected in parallel with the fourth transistor and the fourth capacitor.

4. The current detection circuit as described in claim 1, characterized in that, The detection module further includes a first switch, a first diode, a first resistor, a second switch, a second inductor, a second diode, a third switch, and a fourth transistor; One end of the first switch is connected to the test input terminal, and the other end of the first switch is connected to one end of the first inductor. The other end of the first inductor is connected to the anode of the first diode. The cathode of the first diode is connected to one end of the first resistor. The other end of the first resistor is connected to one end of the first capacitor. The other end of the first capacitor is connected to the drain of the first transistor. The other end of the first capacitor is also connected to one end of the third switch, and the other end of the third switch is connected to the operating voltage. One end of the second switch is connected to the test input terminal, and the other end of the second switch is connected to one end of the second inductor. The other end of the second inductor is connected to the cathode of the second diode. The anode of the second diode is connected to the cathode of the first diode. The source of the fourth transistor is connected to the source of the first transistor. The gate of the fourth transistor receives the first control signal, and the drain of the fourth transistor is grounded.

5. The current detection circuit as described in claim 1, characterized in that, The current detection circuit also includes a signal generator, the positive terminal of which is connected to the test output terminal, and the negative terminal of which is grounded.

6. The current detection circuit as described in claim 1, characterized in that, The current detection circuit also includes a ground terminal, which is connected to the second signal output terminal of the circuit under test.

7. The current detection circuit as described in claim 1, characterized in that, The current detection circuit also includes a power supply terminal, which is connected to the second signal input terminal of the circuit under test and is connected to the power supply voltage.

8. The current detection circuit as described in claim 7, characterized in that, The current detection circuit also includes a second capacitor, one end of which is connected to the power supply terminal, and the other end of which is grounded.

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