Bus conversion device, method and system

Abstract

The embodiments of the present disclosure provide a bus conversion device, method, and system for use in the field of computer hardware technology. The device includes a write address channel slave handshake module for capturing the write address channel number of a first AXI device; a number cache FIFO module for caching the write address channel number; a write channel packet completion judgment module for capturing a packet completion flag and, after the capture is complete, triggering the number cache FIFO module to update the cached write address channel number; a write channel number output module for outputting the write address channel number as the write data channel number of a second AXI device when the number cache FIFO module is empty; and also for outputting the cached write address channel number as the write data channel number of the second AXI device when the number cache FIFO module is not empty. In this way, in a system architecture that simultaneously uses different versions of AXI devices, system integration can be compatible with devices of multiple protocol versions.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, in particular to the field of computer hardware technology, and specifically to a bus conversion device, method, and system. Background Art

[0002] A bus protocol for interconnecting master / slave devices (Advanced eXtensible Interface, AXI) can operate at a higher clock frequency and can meet the interconnection needs of a large number of devices without the need for complex bridging. In the current system architecture, either all AXI4 devices are used, or all AXI3 devices are used. In a system that uses AXI4 devices, if AXI3 devices are needed, that is, in a system architecture that uses both AXI3 and AXI4 devices, the existing AXI3 devices need to be redesigned and modified. This will bring additional risks to mature and stable devices, and some encapsulated and unmodifiable devices will have to be abandoned. Based on this, in a system architecture that uses both AXI3 and AXI4 devices, there is an issue of incompatibility between devices with multiple protocol versions during system integration. Summary of the Invention

[0003] The present disclosure provides a bus conversion device, method and system.

[0004] According to a first aspect of the present disclosure, a bus conversion device is provided. The device includes:

[0005] The write address channel slave handshake module is used to capture the write address channel number of the first AXI device;

[0006] A number cache FIFO module, used for caching the write address channel number;

[0007] A write channel packet completion judgment module is used to capture a packet completion flag and trigger the number cache FIFO module to update the cached write address channel number after the capture is completed;

[0008] A write channel number output module is used to output the write address channel number as the write data channel number of the second AXI device when the number cache FIFO module is empty; and is also used to output the cached write address channel number as the write data channel number of the second AXI device when the number cache FIFO module is not empty.

[0009] According to the aspects described above and any possible implementation method, an implementation method is further provided, wherein the write channel packet completion judgment module is also used to send an update instruction to the number cache FIFO module when outputting the write data channel number of the second AXI device, and the update instruction is used to trigger the number cache FIFO module to update the cached write address channel number according to the packet completion flag.

[0010] According to the aspects described above and any possible implementation method, an implementation method is further provided, wherein the apparatus further includes a write address channel master handshake module, which is used to transmit the write address signal of the write address channel slave handshake module, and to stop transmission to the second AXI device by setting the VALID signal to 0 when the cache of the number cache FIFO module is full.

[0011] According to the aspects and any possible implementations described above, an implementation is further provided, wherein the write address channel slave handshake module is further configured to, when the cache of the number cache FIFO module is full, backpressure the first AXI device to stop transmission by setting the READY signal to 0.

[0012] According to a second aspect of the present disclosure, a method XX is provided. The method comprises:

[0013] Get the write address channel number of the first AXI device;

[0014] Capture package completion flag;

[0015] Cache the write address channel number;

[0016] When the FIFO is empty, outputting the write address channel number as the write data channel number of the second AXI device;

[0017] When the FIFO is not empty, the buffered write address channel number is output as the write data channel number of the second AXI device.

[0018] According to the above aspects and any possible implementation manner, an implementation manner is further provided, wherein the method further includes:

[0019] In the case of outputting the write data channel number of the second AXI device, the cached write address channel number is updated according to the packet completion flag.

[0020] According to the above aspects and any possible implementation manner, an implementation manner is further provided, wherein the method further includes:

[0021] When a write address signal is received and the FIFO buffer is full, the transmission to the second AXI device is stopped by setting the VALID signal to 0.

[0022] According to the above aspects and any possible implementation manner, an implementation manner is further provided, wherein the method further includes:

[0023] When the FIFO buffer is full, the READY signal is set to 0 to backpressure the first AXI device to stop transmission.

[0024] According to a third aspect of the present disclosure, an XX system is provided. The system includes a bus conversion device, a first AXI device, and a second AXI device;

[0025] Among them, the first AXI device is connected to the bus conversion device through the AWVALID signal, the AWREADY signal and the AWID signal, and is used to capture the write address channel number of the AXI transmission; the first AXI device is connected to the bus conversion device through the WLAST signal, and is used to complete the transmission of the write data channel of the AXI transmission and update the output write data channel number; the bus conversion device is connected to the second AXI device through the WID signal, and is used to output the write data channel number.

[0026] According to the above aspects and any possible implementation, an implementation is further provided, wherein the first AXI device is connected to the bus conversion device via an AWVALID signal, an AWREADY signal, and an AWID signal, and is further configured to, when a FIFO buffer is full, set the AWREADY signal to 0 to backpressure the first AXI device to stop transmission; the bus conversion device is connected to the second AXI device via the AWVALID signal and the AWREADY signal, and is configured to, when the FIFO buffer is full, set the AWVALID signal to 0 to stop transmission to the second AXI device.

[0027] According to a fourth aspect of the present disclosure, an electronic device is provided, comprising: a memory and a processor, wherein a computer program is stored in the memory, and the processor implements the above method when executing the program.

[0028] According to a fifth aspect of the present disclosure, a computer-readable storage medium is provided, on which a computer program is stored. When the program is executed by a processor, the method described above is implemented.

[0029] The embodiments of the present application provide a bus conversion device, method, and system, which can capture and cache the write address channel number of a first AXI device through the bus conversion device, and then capture the packet completion flag. When the FIFO is empty, the write address channel number is output as the write data channel number of the second AXI device; when the FIFO is not empty, the cached write address channel number is output as the write data channel number of the second AXI device, and the write address channel number of the first AXI device is converted into the write data channel number of the second AXI device, so that in a system architecture that simultaneously uses different versions of AXI devices, the system can be compatible with multi-protocol version devices during system integration.

[0030] It should be understood that the contents described in the Summary of the Invention section are not intended to limit the key or important features of the embodiments of the present disclosure, nor are they intended to limit the scope of the present disclosure. Other features of the present disclosure will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The above and other features, advantages and aspects of the embodiments of the present disclosure will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. The accompanying drawings are provided for a better understanding of the present disclosure and do not constitute a limitation of the present disclosure. In the accompanying drawings, the same or similar reference numerals represent the same or similar elements, among which:

[0032] Figure 1 A block diagram of a bus conversion system according to an embodiment of the present disclosure is shown;

[0033] Figure 2 A block diagram of a bus conversion device according to an embodiment of the present disclosure is shown;

[0034] Figure 3 A flowchart of a bus conversion method according to an embodiment of the present disclosure is shown;

[0035] Figure 4 A block diagram of an exemplary electronic device capable of implementing embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0036] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present disclosure.

[0037] In this document, the term "and / or" simply describes a relationship between related objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A exists alone, A and B exist simultaneously, or B exists alone. Furthermore, the character " / " in this document generally indicates that the related objects are in an "or" relationship.

[0038] In the present disclosure, the write address channel number of the first AXI device can be converted into the write data channel number of the second AXI device, so that in a system architecture that simultaneously uses different versions of AXI devices, the system can be compatible with multiple protocol version devices during system integration.

[0039] Figure 1 FIG. 1 shows a block diagram of a bus conversion system according to an embodiment of the present disclosure. Figure 1 As shown, the system 100 includes a first AXI device 101 , a bus conversion apparatus 102 , and a second AXI device 103 .

[0040] Among them, the first AXI device 101 is connected to the bus conversion device through the AWVALID signal, the AWREADY signal and the AWID signal, which is used to capture the write address channel number of the AXI transmission; the first AXI device 101 is connected to the bus conversion device through the WLAST signal, which is used to complete the write data channel transmission of the AXI transmission and update the output write data channel number; the bus conversion device 102 is connected to the second AXI device 103 through the WID signal, which is used to output the write data channel number.

[0041] In some embodiments, the first AXI device 101 and the second AXI device 103 may be devices using different protocol versions. For example, the first AXI device 101 may be an AXI4 device, and the second AXI device 103 may be an AXI3 device.

[0042] In some embodiments, in a system architecture that simultaneously uses devices of different protocol versions, such as a system architecture that simultaneously uses AXI3 and AXI4 bus protocols, the bus conversion device 102 can be used to output the write data channel number to solve the problem that the AXI4 protocol does not support the write data channel number of the AXI3 protocol, so that the system can be compatible with master devices and slave devices of both AXI4 and AXI3 bus protocols.

[0043] Through the above system, the bus conversion device captures and caches the write address channel number of the first AXI device, and then updates the output write data channel number to the second AXI device, so that in a system architecture that simultaneously uses different versions of AXI devices, the system can be compatible with multiple protocol version devices during system integration.

[0044] In some embodiments, the first AXI device 101 is connected to the bus conversion device 102 through the AWVALID signal, the AWREADY signal and the AWID signal, and is also used to stop transmission to the first AXI device 101 by setting the AWREADY signal to 0 when the data buffer (First In First Out, FIFO) is full; the bus conversion device 102 is connected to the second AXI device 103 through the AWVALID signal and the AWREADY signal, and is used to stop transmission to the second AXI device 103 by setting the AWVALID signal to 0 when the FIFO buffer is full.

[0045] In some embodiments, when the bus conversion device 102 determines that the FIFO buffer is full, it selects to apply back pressure to the first AXI device 101 through a corresponding signal, i.e., front-stage back pressure; or selects to stop the transmission to the second AXI device 103, i.e., back-stage stop transmission.

[0046] Through the above system, when the FIFO buffer of the bus conversion device is full, back pressure can be applied to the front stage or transmission can be stopped to the back stage to avoid FIFO storage overflow.

[0047] The above is an introduction to the system embodiment. The following is a further explanation of the solution described in this disclosure through an apparatus embodiment.

[0048] Figure 2 FIG. 1 shows a block diagram of a bus conversion device according to an embodiment of the present disclosure. Figure 2 As shown, the device 102 includes a write address channel slave handshake module 1021 , a number buffer FIFO module 1022 , a write channel packet completion judgment module 1023 and a write channel number output module 1024 .

[0049] The write address channel retrieves the write address channel number of the first AXI device from the handshake module 1021. The number buffer FIFO module 1022 caches the write address channel number retrieved from the handshake module 1021. The write channel packet completion determination module 1023 retrieves the packet completion flag. When the number buffer FIFO module 1022 is empty, the write channel number output module 1024 outputs the write address channel number as the write data channel number of the second AXI device. When the number buffer FIFO module 1022 is not empty, the write channel number output module 1024 outputs the cached write address channel number as the write data channel number of the second AXI device.

[0050] When the write channel number output module 1024 outputs the write data channel number and performs the next round of conversion, the write channel packet completion judgment module 1023 triggers the number cache FIFO module 1022 to update the cached write address channel number after the capture is completed. The number cache FIFO module 1022 updates the output, indicating that a write transfer is completed.

[0051] It should be noted that the number cache FIFO module 1022 is empty, indicating that due to cache delay, the number cache FIFO module 1022 has not completed the cache of the write address channel number captured by the write address channel from the handshake module 1021, and the number cache FIFO module 1022 does not cache any write address channel number captured by the write address channel from the handshake module 1021. At this time, the captured write address channel number is synchronized with the data of the write data channel, and the write channel number output module 1024 can output the write address channel number captured by the write address channel from the handshake module 1021 as the write data channel number of the second AXI device.

[0052] The number cache FIFO module 1022 is not empty, indicating that the number cache FIFO module 1022 has completed the caching of the write address channel number captured by the write address channel from the handshake module 1021, or the number cache FIFO module 1022 has already cached the write address channel number captured by the write address channel from the handshake module 1021. At this time, based on the fact that the transmission of the write address channel is greater than the transmission of the write data channel, that is, the transmission of the write address channel takes precedence over the transmission of the write data channel, the captured write address channel number is not synchronized with the data of the write data channel. According to the FIFO first-in-first-out principle, that is, the number cache FIFO module 1022 stores the address number of the write address channel asynchronous advance packet in a first-in-first-out manner, the write channel number output module 1024 can output the cached write address channel number as the write data channel number of the second AXI device, thereby achieving transmission synchronization between the write address channel and the write data channel.

[0053] According to the embodiments of the present disclosure, the following technical effects are achieved:

[0054] The write address channel number of the first AXI device is captured from the handshake module through the write address channel in the bus conversion device, the number cache FIFO module caches the captured write address channel number, and the write channel packet completion judgment module then captures the packet completion flag. When the number cache FIFO module is empty, the write channel number output module outputs the write address channel number as the write data channel number of the second AXI device; when the number cache FIFO module is not empty, the write channel number output module outputs the cached write address channel number as the write data channel number of the second AXI device, so as to realize the conversion of the write address channel number of the first AXI device into the write data channel number of the second AXI device, so that in the system architecture that uses different versions of AXI devices at the same time, the system can be compatible with multi-protocol version devices during system integration.

[0055] In some embodiments, the above-mentioned write channel packet completion judgment module 1023 sends an update instruction to the number cache FIFO module 1022 when outputting the write data channel number of the second AXI device. The update instruction is used to trigger the number cache FIFO module 1022 to update the cached write address channel number according to the packet completion flag.

[0056] Whenever the write address channel receives the write address channel handshake of the first AXI device from the handshake module 1021 , ie, the AWVALID signal and the AWREADY signal are set to 1 at the same time, the write address number AWID is stored in the number buffer FIFO module 1022 .

[0057] Whenever the write channel packet completion judgment module 1023 receives the write data channel handshake of the second AXI device with a packet completion flag, that is, the WVALID signal and the WREADY signal are set to 1 at the same time and the WLAST signal is set to 1, it automatically sends an update instruction to trigger the number cache FIFO module 1022 to output an update.

[0058] By means of the above device, the number conversion between the write address channel number and the write data channel number can be performed when each write transmission is completed, so as to ensure the transmission synchronization between the write address channel and the write data channel.

[0059] In some embodiments, the apparatus further includes a write address channel master handshake module 1025. The write address channel master handshake module 1025 transmits the write address signal of the write address channel slave handshake module 1021, and stops transmission to the second AXI device by setting the VALID signal to 0 when the number buffer FIFO module 1022 is full.

[0060] When the write address channel number buffer in the number buffer FIFO module 1022 is full, in order to avoid storage overflow, which causes the write address channel and the write data channel to be out of synchronization, the transmission to the second AXI device can be stopped by setting the VALID signal to 0.

[0061] Through the above device, the write address channel master handshake module transmits the write address signal of the write address channel slave handshake module 1021, so that the write address channel master handshake module transmits a VALID signal set to 0 to the second AXI device to stop transmission to the second AXI device and avoid storage overflow of the number cache FIFO module.

[0062] In some embodiments, the write address channel slave handshake module 1021 is further configured to backpressure the first AXI device to stop transmission by setting the READY signal to 0 when the buffer of the number buffer FIFO module 1022 is full.

[0063] When the write address channel number buffer in the number buffer FIFO module 1022 is full, in order to avoid storage overflow, which causes the transmission of the write address channel and the write data channel to be out of synchronization, the READY signal can be set to 0 to backpressure the first AXI device to stop transmission.

[0064] Through the above device, the write address channel transmits a READY signal set to 0 from the handshake module to the first AXI device, so as to achieve back pressure suspension of the first AXI device transmission and avoid storage overflow of the number buffer FIFO module.

[0065] The above is an introduction to the device embodiment. The following is a method embodiment to further illustrate the solution described in this disclosure.

[0066] Figure 3 FIG. 3 is a flow chart of a bus conversion method 300 according to an embodiment of the present disclosure. The method 300 may be performed by Figure 1 The bus conversion device 102 in is executed.

[0067] At block 310 , the write address channel number of the first AXI device is retrieved.

[0068] At block 320, a packet completion flag is captured.

[0069] At block 330 , the write address channel number is cached.

[0070] At block 340 , when the FIFO is empty, the write address channel number is output as the write data channel number of the second AXI device.

[0071] In block 350 , when the FIFO is not empty, the buffered write address channel number is output as the write data channel number of the second AXI device.

[0072] According to the embodiments of the present disclosure, the following technical effects are achieved:

[0073] By capturing and caching the write address channel number of the first AXI device, and then capturing the packet completion flag, when the FIFO is empty, the write address channel number is output as the write data channel number of the second AXI device; when the FIFO is not empty, the cached write address channel number is output as the write data channel number of the second AXI device, and the write address channel number of the first AXI device is converted into the write data channel number of the second AXI device. In this way, in a system architecture that uses different versions of AXI devices at the same time, the system can be compatible with multi-protocol version devices during system integration.

[0074] In some embodiments, the above method further comprises:

[0075] In the case of outputting the write data channel number of the second AXI device, the cached write address channel number is updated according to the packet completion flag.

[0076] In some embodiments, the above method further comprises:

[0077] When a write address signal is received and the FIFO buffer is full, the transmission to the second AXI device is stopped by setting the VALID signal to 0.

[0078] In some embodiments, the above method further comprises:

[0079] When the FIFO buffer is full, the READY signal is set to 0 to backpressure the first AXI device to stop transmission.

[0080] It should be noted that for the aforementioned method embodiments, for simplicity of description, they are all expressed as a series of action combinations, but those skilled in the art should be aware that the present disclosure is not limited by the order of the actions described, because according to the present disclosure, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all optional embodiments, and the actions and modules involved are not necessarily required by the present disclosure.

[0081] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the described method can refer to the corresponding process in the aforementioned device embodiment, and will not be repeated here.

[0082] In the technical solutions disclosed herein, the acquisition, storage, and application of user personal information involved comply with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0083] According to an embodiment of the present disclosure, the present disclosure also provides an electronic device, a readable storage medium, and a computer program product.

[0084] Figure 4A schematic block diagram of an electronic device 400 that can be used to implement an embodiment of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital assistants, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0085] The electronic device 400 includes a computing unit 401, which can perform various appropriate actions and processes according to a computer program stored in a ROM 402 or a computer program loaded from a storage unit 408 into a RAM 403. The RAM 403 may also store various programs and data required for the operation of the electronic device 400. The computing unit 401, the ROM 402, and the RAM 403 are connected to each other via a bus 404. An I / O interface 405 is also connected to the bus 404.

[0086] Multiple components in the electronic device 400 are connected to the I / O interface 405, including an input unit 406, such as a keyboard, a mouse, etc.; an output unit 407, such as various types of displays, speakers, etc.; a storage unit 408, such as a magnetic disk, an optical disk, etc.; and a communication unit 409, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 409 allows the electronic device 400 to exchange information / data with other devices via a computer network such as the Internet and / or various telecommunication networks.

[0087] The computing unit 401 can be a variety of general-purpose and / or specialized processing components with processing and computing capabilities. Some examples of the computing unit 401 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units that run machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The computing unit 401 performs the various methods and processes described above, such as method 300. For example, in some embodiments, the method 300 can be implemented as a computer software program that is tangibly contained in a machine-readable medium, such as a storage unit 408. In some embodiments, part or all of the computer program can be loaded and / or installed on the electronic device 400 via the ROM 402 and / or the communication unit 409. When the computer program is loaded into the RAM 403 and executed by the computing unit 401, one or more steps of the method 300 described above can be performed. Alternatively, in other embodiments, the computing unit 401 can be configured to perform the method 300 in any other appropriate manner (e.g., by means of firmware).

[0088] Various embodiments of the systems and techniques described herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), system-on-chip systems (SOCs), programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments can include being implemented in one or more computer programs that are executable and / or interpreted on a programmable system comprising at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0089] The program code for implementing the method of the present disclosure can be written in any combination of one or more programming languages. These program codes can be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device so that when the program code is executed by the processor or controller, the functions / operations specified in the flow chart and / or block diagram are implemented. The program code can be executed entirely on the machine, partially on the machine, as a stand-alone software package, partially on the machine and partially on a remote machine, or entirely on a remote machine or server.

[0090] In the context of the present disclosure, a machine-readable medium can be a tangible medium that can contain or store a program for use by or in conjunction with an instruction execution system, device or equipment. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or equipment, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium can include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0091] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the computer. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0092] The systems and techniques described herein can be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include a local area network (LAN), a wide area network (WAN), and the Internet.

[0093] A computer system may include a client and a server. The client and server are generally remote from each other and typically interact through a communication network. The client-server relationship arises through computer programs running on the respective computers and having a client-server relationship with each other. The server may be a cloud server, a server in a distributed system, or a server integrated with a blockchain.

[0094] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in this disclosure can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved. This is not limited herein.

[0095] The above specific embodiments do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure shall be included within the scope of protection of this disclosure.

Claims

1. A bus conversion device, characterized in that: include: The write address channel slave handshake module is used to capture the write address channel number of the first AXI device; A number cache FIFO module, used for caching the write address channel number; A write channel packet completion judgment module is used to capture a packet completion flag and trigger the number cache FIFO module to update the cached write address channel number after the capture is completed; A write channel number output module is used to output the write address channel number as the write data channel number of the second AXI device when the number cache FIFO module is empty; and is also used to output the cached write address channel number as the write data channel number of the second AXI device when the number cache FIFO module is not empty.

2. The device according to claim 1, characterized in that The write channel packet completion judgment module is also used to send an update instruction to the number cache FIFO module when outputting the write data channel number of the second AXI device. The update instruction is used to trigger the number cache FIFO module to update the cached write address channel number according to the packet completion flag.

3. The device according to claim 1, characterized in that The apparatus further comprises a write address channel master handshake module for transmitting the write address signal of the write address channel slave handshake module, and stopping transmission to the second AXI device by setting a VALID signal to 0 when the number buffer FIFO module is full.

4. The device according to claim 1, characterized in that The write address channel slave handshake module is further configured to, when the buffer of the number buffer FIFO module is full, backpressure the first AXI device to stop transmission by setting the READY signal to 0.

5. A bus conversion method, applied to the bus conversion device according to any one of claims 1 to 4, characterized in that: include: Get the write address channel number of the first AXI device; Capture package completion flag; Cache the write address channel number; When the FIFO is empty, outputting the write address channel number as the write data channel number of the second AXI device; When the FIFO is not empty, the buffered write address channel number is output as the write data channel number of the second AXI device.

6. The method according to claim 5, characterized in that The method further comprises: In the case of outputting the write data channel number of the second AXI device, the cached write address channel number is updated according to the packet completion flag.

7. The method according to claim 5, characterized in that The method further comprises: When a write address signal is received and the FIFO buffer is full, the transmission to the second AXI device is stopped by setting the VALID signal to 0.

8. The method according to claim 5, characterized in that The method further comprises: When the FIFO buffer is full, the READY signal is set to 0 to backpressure the first AXI device to stop transmission.

9. A bus conversion system, characterized in that: include: The bus conversion device, the first AXI device, and the second AXI device according to any one of claims 1 to 4; Among them, the first AXI device is connected to the bus conversion device through the AWVALID signal, the AWREADY signal and the AWID signal, and is used to capture the write address channel number of the AXI transmission; the first AXI device is connected to the bus conversion device through the WLAST signal, and is used to complete the transmission of the write data channel of the AXI transmission and update the output write data channel number; the bus conversion device is connected to the second AXI device through the WID signal, and is used to output the write data channel number.

10. The system according to claim 9, characterized in that The first AXI device is connected to the bus conversion device through the AWVALID signal, the AWREADY signal and the AWID signal, and is also used to stop transmission to the first AXI device by setting the AWREADY signal to 0 when the FIFO buffer is full; the bus conversion device is connected to the second AXI device through the AWVALID signal and the AWREADY signal, and is used to stop transmission to the second AXI device by setting the AWVALID signal to 0 when the FIFO buffer is full.

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