Method for detecting a memory

Abstract

The application provides a memory detection method, and relates to the technical field of semiconductors.The memory detection method comprises the following steps: writing first storage data into a storage unit connected with a first word line, writing second storage data into a storage unit connected with a second word line, the first storage data being different from the second storage data; starting the first word line, keeping the first word line open for a first preset time period, and then closing the first word line, the first preset time period being greater than a first time threshold value.The application increases the opening time of the first word line, so as to increase the time of the leakage current of the first word line to the second word line and the amount of leaked charges, then, by comparing the actual storage data of the connected storage unit connected with the first word line with the first storage data, whether the first word line and the second word line exist leakage is accurately judged, the detection accuracy of the leakage between adjacent word lines is ensured, and the yield of the memory is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a method for detecting a memory. Background Art

[0002] Dynamic random access memory (DRAM) is a semiconductor memory that can write and read data randomly at high speed and is widely used in data storage devices or apparatuses.

[0003] Dynamic random access memory (DRAM) consists of multiple repetitive memory cells. Each memory cell typically includes a capacitor structure and a transistor. The transistor's gate is connected to a word line, its drain is connected to a bit line, and its source is connected to the capacitor structure. A voltage signal on the word line controls the transistor's on and off state, allowing it to read data stored in the capacitor structure through the bit line or write data to the capacitor structure for storage.

[0004] As dynamic random access memory (DRAM) develops toward miniaturization and integration, the distance between adjacent storage cells decreases, which in turn causes leakage between adjacent word lines. However, there is currently no detection method to accurately detect whether there is leakage between adjacent word lines, resulting in a low yield of dynamic random access memory. Summary of the Invention

[0005] In view of the above problems, an embodiment of the present application provides a memory detection method for testing whether adjacent word lines have leakage, thereby improving the yield of the memory.

[0006] In order to achieve the above objectives, the embodiments of the present application provide the following technical solutions:

[0007] An embodiment of the present application provides a memory detection method. Among any two adjacent word lines, one of the word lines is a first word line and the other word line is a second word line. The detection method includes:

[0008] Writing first storage data into a memory cell connected to the first word line, and writing second storage data into a memory cell connected to the second word line, wherein the first storage data is different from the second storage data;

[0009] activating the first word line to turn on a transistor of a memory cell connected to the first word line, and keeping the transistor on for a first preset time period before turning it off, where the first preset time period is greater than a first time threshold;

[0010] After turning off the first word line, turning on the second word line, and keeping the second word line for the first time threshold before turning it off;

[0011] The actual storage data of the memory cell connected to the first word line is obtained through the bit line, and it is determined whether the actual storage data is the same as the second storage data, wherein the bit line is connected to the memory cell connected to the first word line.

[0012] In some embodiments, the step of starting the first word line includes: applying a first voltage to the first word line to start the first word line, wherein the first voltage is greater than a turn-on voltage of the first word line.

[0013] In some embodiments, the step of starting the first word line further includes applying a second voltage to the first word line to turn off the first word line, wherein the second voltage is greater than a turn-off voltage of the first word line.

[0014] In some embodiments, the first word line is turned off, and after waiting for a second preset time period, the second word line is turned on.

[0015] In some embodiments, the second preset time period is between 5-20 ns.

[0016] In some embodiments, the memory further includes a plurality of reference bit lines, the plurality of reference bit lines being arranged in a one-to-one correspondence with the plurality of bit lines. After the step of turning off the first word line, turning on the second word line, and keeping it turned off after the first time threshold, and before the step of acquiring actual storage data of a memory cell connected to the first word line through the bit line, the detection method further includes:

[0017] The bit line shared with the first word line and the second word line and the reference bit line are precharged so that a potential of the precharged bit line is not equal to a potential of the reference bit line.

[0018] In some embodiments, the memory includes an equalization circuit, the equalization circuit of the memory is activated, and the bit line shared with the first word line and the second word line and the reference bit line are in a precharge state within a third preset time period, and the third preset time period is less than a second time threshold.

[0019] In some embodiments, the equalization circuit includes a first transistor, a second transistor, and a third transistor disposed between the bit line and the reference bit line;

[0020] The gates of the first transistor, the second transistor, and the third transistor are connected to a first signal line, and the first signal line is used to provide a voltage to the balancing circuit to turn on or off the balancing circuit;

[0021] The source of the first transistor is connected with the bit line, and the drain of the first transistor is connected with the reference bit line.

[0022] The source of the second transistor is connected with the bit line, and the drain of the second transistor is connected with the source of the third transistor.

[0023] The drain of the third transistor is connected with the reference bit line.

[0024] The drain of the second transistor and the source of the third transistor are also connected with a second signal line, and the second signal line is used to provide a reset voltage for the bit line and the reference bit line.

[0025] In some embodiments, the first storage data is "1", and the second storage data is "0".

[0026] If the actual storage data of the storage unit connected with the first word line is "0", it is proved that the leakage occurs between the first word line and the second word line.

[0027] In some embodiments, in the step of obtaining the actual storage data of the storage unit connected with the first word line through the bit line, the step comprises:

[0028] The memory comprises a reading circuit and a peripheral circuit, the reading circuit is connected with the bit line, and the reading circuit is started to transmit the storage data connected with the first word line into the peripheral circuit.

[0029] In some embodiments, the reading circuit comprises a reading transistor, the gate of the reading transistor is connected with a third signal line, and the third signal line is used to control the opening or closing of the reading transistor.

[0030] The source of the reading transistor is connected with the bit line, and the drain of the reading transistor is connected with the peripheral circuit.

[0031] In some embodiments, a fourth signal line is arranged between the drain of the reading transistor and the peripheral circuit.

[0032] In some embodiments, the memory further comprises a sensitive amplifier, the sensitive amplifier is arranged between the bit line and the reference bit line corresponding to the bit line, and is used to amplify the voltage difference between the bit line and the reference bit line corresponding to the bit line.

[0033] In some embodiments, the sensitive amplifier comprises a fourth transistor, a fifth transistor, a sixth transistor and a seventh transistor.

[0034] The gate of the fourth transistor is connected with the reference bit line, and the source of the fourth transistor is connected with the bit line.

[0035] The gate of the fifth transistor is connected with the bit line, the source of the fifth transistor is connected with the reference bit line, the drain of the fifth transistor is connected with the drain of the fourth transistor and a first power supply line for providing a low potential voltage;

[0036] The gate of the sixth transistor is connected with the reference bit line, and the source of the sixth transistor is connected with the bit line.

[0037] The gate of the seventh transistor is connected with the bit line, the source of the seventh transistor is connected with the reference bit line, the drain of the seventh transistor is connected with the drain of the sixth transistor and a second power supply line for providing a high potential voltage.

[0038] In some embodiments, the fourth transistor and the fifth transistor are both N-type transistors, and the sixth transistor and the seventh transistor are both P-type transistors.

[0039] In the memory detection method provided by the embodiments of the present application, the opening time of the first word line is increased to increase the time of the leakage current of the first word line to the second word line, thereby increasing the amount of charge leaked from the first word line to the second word line, and the amount of charge is sufficient to change the actual storage data of the storage unit connected with the first word line. Then, by comparing the actual storage data with the second storage data, it is accurately judged whether there is leakage between the first word line and the second word line, the detection accuracy of the leakage between adjacent word lines is ensured, and the yield of the memory is improved.

[0040] In addition to the technical problems solved by the embodiments of the present application described above, the technical features constituting the technical solutions and the beneficial effects brought by these technical features, other technical problems solved by the memory detection method provided by the embodiments of the present application, other technical features included in the technical solutions and the beneficial effects brought by these technical features will be further described in detail in the specific embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0041] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the drawings needed in the embodiments or the prior art description will be briefly introduced as follows. Obviously, the drawings in the following description are some embodiments of the present application, and those skilled in the art can also obtain other drawings according to these drawings without creating any creative labor.

[0042] Figure 1 The layout schematic diagram of the memory provided by the embodiments of the present application is shown in the following figure.

[0043] Figure 2 A schematic diagram of a storage unit of a memory provided in an embodiment of the present application;

[0044] Figure 3 A process flow chart of a memory detection method provided in an embodiment of the present application;

[0045] Figure 4 A schematic diagram of writing first stored data and second stored data in a memory detection method provided in an embodiment of the present application;

[0046] Figure 5 This is a timing diagram of the operation of the first word line and the second word line in the memory provided in an embodiment of the present application;

[0047] Figure 6 A circuit diagram of a memory provided in an embodiment of the present application;

[0048] Figure 7 This is a working timing diagram of the first word line of the memory provided in an embodiment of the present application. DETAILED DESCRIPTION

[0049] As described in the background art, there is a problem of leakage current between adjacent word lines of a dynamic random access memory, but the detection method in the related art cannot accurately detect whether there is leakage between adjacent word lines. The inventors have found that the reason for this problem is that, among two adjacent word lines, if the current leaked from one word line to the other word line is not sufficient to change the storage data of the memory cell connected to the other word line, then when the data of the memory cell connected to the other word line is subsequently read, the data will be the same as the theoretical storage data, making it difficult to determine whether there is leakage between adjacent word lines.

[0050] In response to the above-mentioned technical problems, in an embodiment of the present application, the turn-on time of the first word line is increased to increase the time for the current to leak from the first word line to the second word line, thereby increasing the amount of charge leaked from the first word line to the second word line, and making the charge amount sufficient to change the actual storage data of the storage unit connected to the first word line. Afterwards, by comparing the actual storage data with the second storage data, it is accurately determined whether there is leakage between the first word line and the second word line, thereby ensuring the accuracy of leakage detection between adjacent word lines, thereby improving the yield of the memory.

[0051] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present application more obvious and easy to understand, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0052] Figure 1 A schematic diagram of the memory layout provided in an embodiment of the present application; Figure 2 A schematic diagram of a storage unit of a memory provided in an embodiment of the present application; Figure 3 A process flow chart of a memory detection method provided in an embodiment of the present application; Figure 4 A schematic diagram of writing first stored data and second stored data in a memory detection method provided in an embodiment of the present application; Figure 5 This is a timing diagram of the operation of the first word line and the second word line in the memory provided in an embodiment of the present application; Figure 6 A circuit diagram of a memory provided in an embodiment of the present application; Figure 7 The working timing diagram of the first word line of the memory provided in the embodiment of the present application is as follows: Figure 1-Figure 7 The preparation method of semiconductor structure is introduced in detail.

[0053] The memory detection method provided in an embodiment of the present application is used to detect whether there is leakage between adjacent word lines of the memory, wherein the memory includes multiple relatively independent bit lines (BL), multiple relatively independent word lines (WL), and multiple memory cells 10, wherein each memory cell 10 is connected to a corresponding word line WL and a bit line BL.

[0054] like Figure 1 As shown, the plurality of bit lines BL are distributed in rows, and the plurality of bit lines are divided into 128 bit line groups, each of which has 8 bit lines BL. For the convenience of the following description, the bit lines in each bit line group may be denoted as BL0, BL1, BL2...BL7.

[0055] The multiple word lines WL are distributed in columns and divided into 128 word line groups. Each word line group has 8 word lines WL. For the convenience of the following description, the bit lines in each bit line group may be recorded as WL0, WL1, WL2...WL7.

[0056] Multiple memory cells 10 are distributed in a matrix, wherein the memory cells 10 in the first column are all connected to the word line WL0, the memory cells 10 in the second column are all connected to the word line WL1, and so on, the memory cells 10 in the eighth column are all connected to the word line WL7; the memory cells in the first row are all connected to the bit line BL0, the memory cells in the second row are all connected to the bit line BL1, and so on, the memory cells in the eighth row are all connected to the bit line BL7, so that each memory cell 10 is connected to a word line WL and a bit line BL.

[0057] Among them, such as Figure 2 As shown, each memory cell 10 includes a transistor 12 and a capacitor 11, the gate of the transistor 12 is connected to the word line WL, the source of the transistor 12 is connected to the bit line BL, and the drain of the transistor 12 is connected to the capacitor 11. It should be noted that the source of the transistor 12 can also be connected to the capacitor 11, and accordingly, the drain of the transistor 12 is connected to the bit line BL.

[0058] In order to facilitate the description of the memory detection method, it is recommended to define one of the two adjacent word lines as the first word line and the other word line as the second word line. For example, Figure 1 As shown, from left to right, the first word line WL0 can be defined as a first word line, and the second word line WL1 can be defined as a second word line.

[0059] like Figure 3 As shown, the memory detection method includes the following steps:

[0060] Step S100 : writing first storage data into a memory cell connected to a first word line, and writing second storage data into a memory cell connected to a second word line, wherein the first storage data is different from the second storage data.

[0061] For example, Figure 4 As shown, the memory cell 10 is first initialized to activate the memory cell 10, and then a write operation is performed, so that each memory cell 10 connected to the first word line WL0 is written with the first storage data, and each memory cell 10 connected to the second word line WL1 is written with the second storage data. The first storage data is different from the second storage data. For example, when the first storage data is "1", the second storage data is "0"; for another example, when the first storage data is "0", the second storage data is "1".

[0062] In order to facilitate the description of the technical solution of the present application, the following description is given as an example in which the first stored data is "1", the second stored data is "0", and the first bit line BL0 is used to read the data of the storage unit 10 connected thereto.

[0063] Step S200: Start the first word line to turn on the transistor of the memory cell connected to the first word line, and keep it on for a first preset time period and then turn it off. The first preset time period is greater than a first time threshold. The first time threshold is the timing parameter tRAS (Row Address Strobe Time, tRAS for short). The timing parameter tRAS refers to the row activity time, which is actually the entire time from the activation of addressing (ACT for short) to the completion of reading after a row address precharge command (Precharge, PRE for short).

[0064] Exemplarily, in this step, a high level is first written to the first word line WL0, so that the first word line WL0 is in an on state and is kept turned off after a first preset time period. When the first word line WL0 is in an on state, the first word line WL0 applies a high level to the gate of the transistor 12 of the memory cell 10 connected thereto, so that the source and drain of the transistor 12 are connected, thereby enabling the data in the capacitor 11 in the memory cell 10 to be transferred to the bit line BL0.

[0065] It should be noted that when the first word line WL0 is turned on, no read operation is performed on the memory cell 10 connected to the first word line WL0 , and the first word line WL0 is simply turned on for the first preset time period.

[0066] Step S300: After turning off the first word line, turning on the second word line, and keeping it on for a first time threshold before turning it off.

[0067] In this embodiment, during the process of turning on the second word line WL1 within the first time threshold, the storage data of the memory cell 10 connected to the second word line WL1 is not read. The second word line is simply turned on for the first preset time period. This configuration increases the leakage current duration between the first word line WL0 and the second word line WL1, thereby increasing the amount of leakage current between the first word line WL0 and the second word line WL1, and facilitates the detection of the leakage current between the first word line WL0 and WL1.

[0068] Step S400: obtaining actual storage data of a memory cell connected to a first word line through a bit line. If the actual storage data is the same as the second storage data, it indicates that leakage occurs between the first word line and the second word line, wherein the bit line is connected to the memory cell connected to the first word line.

[0069] For example, the first bit line BL0 can be used to read the memory cell 10 connected to the first word line WL0 to obtain the actual storage data of the memory cell 10. If the actual storage data is "0", which is different from the first storage data "1", it proves that leakage occurs between the first word line WL0 and the second word line WL1.

[0070] When the first word line WL0 leaks, the charge on the memory cell 10 connected to the first word line WL0 will be transmitted to the bit line corresponding to the memory cell, for example, the charge on the memory cell 10 connected to the first word line WL0 will be transmitted to the bit line BL0, which will reduce the amount of charge in the memory cell connected to the first word line WL0, and in the process, the timing parameter tRAS will be increased. By setting this way, the amount of current leaked by the first word line WL0 can be increased, and then the second word line WL1 is turned on. Since the second word line WL1 shares a set of word lines with the first word line WL0, the charge on the memory cell 10 connected to the second word line WL1 will also be transmitted to the bit line BL0, so that the potential of the bit line BL0 is low. Compared with the reference bit line / BL, the potential of the bit line BL0 is reduced by△V. By setting this way, when the first word line WL0 is turned on again and the storage data of the memory cell 10 connected to the first word line WL0 is read by using the bit line BL0, the actual storage data is "0", which is the same as the second storage data "0". In this way, it can be proved that the first word line WL0 and the second word line WL1 leak.

[0071] The embodiment is to increase the opening time of the first word line to increase the time of the first word line leaking current to the second word line, thereby increasing the amount of charge leaked from the first word line to the second word line, and making the charge amount change the actual storage data of the memory cell connected to the first word line. Then, by comparing the actual storage data with the first storage data, it can be accurately judged whether the first word line and the second word line leak. The detection accuracy of the leakage between adjacent word lines is ensured, and the yield of the memory is improved.

[0072] In the present application, the time of the first word line WL0 leaking current to the second word line WL1 can be increased by the following two implementation modes.

[0073] In an optional embodiment, the step of starting the first word line includes: applying a first voltage to the first word line WL0 to start the transistor 12 connected to the first word line WL0, wherein the first voltage is greater than the opening voltage of the first word line WL0.

[0074] The transistor 12 usually has a threshold voltage, for example, the threshold voltage of the NMOS transistor is 0.7V. When the voltage applied to the gate of the NMOS transistor is greater than the threshold voltage of the NMOS transistor, the NMOS transistor will be in the on state.

[0075] The word line WL also has a peak voltage Vpp and Vkk, when the voltage applied to the word line WL is greater than Vpp, the word line WL will be selected and open, so the voltage Vpp can be called the opening voltage of the word line WL, wherein the value of Vpp is about 3v; when the voltage applied to the word line is less than Vkk, the word line WL will be closed, so the voltage Vkk can be called the closing voltage of the word line WL.

[0076] As shown in Figure 5 When the first voltage applied to the first word line WL0 is greater than the opening voltage of the first word line WL0, the voltage applied to the gate of the transistor 12 by the first word line WL0 is greater than the threshold voltage of the transistor 12, thereby increasing the opening degree of the transistor 12 to increase the charge amount of the capacitor 11 to the bit line BL connected to the storage unit 10, and reduce the charge amount of the storage unit 10 connected to the first word line WL0.

[0077] Then, the second word line WL1 is opened again, since the second word line WL1 shares a set of bit lines and reference bit lines with the first word line W1, the second storage data of the storage unit connected to the second word line WL1 reduces the potential of the bit line BL, so that the potential of the bit line BL is less than the potential of the reference bit line / BL.

[0078] Finally, in view of the fact that the potential of the first word line WL0 has been reduced, the first word line WL0 is opened again, and the potential of the bit line BL is still less than the potential of the reference bit line / BL, so that after the potential difference between the bit line BL and the reference bit line / BL is amplified by the sensitive amplifier, the actual storage data of the storage unit 10 connected to the first word line WL1 read is "0", which is opposite to the first storage data "1" of the storage unit 10, which proves that leakage occurs between the first word line WL0 and the second word line WL1.

[0079] In another alternative embodiment, the step of activating the first word line WL0 further includes applying a second voltage to the first word line WL0 to close the transistor 12 connected to the first word line WL0, wherein the second voltage is greater than the closing voltage of the first word line WL0.

[0080] When the second voltage applied to the first word line WL0 is greater than the closing voltage, the closing degree of the transistor 12 is weakened, which will cause the capacitor 11 to leak current to the bit line BL connected to the storage unit 10, thereby causing the charge of the storage unit connected to the first word line WL0 to still transmit to the bit line BL, so as to increase the amount of leakage current of the storage unit 10 connected to the first word line WL0.

[0081] When the second word line WL1 is opened, the second storage data of the storage unit connected with the second word line WL1 will reduce the potential of the bit line BL, so that the potential of the bit line BL is less than the potential on the reference bit line / BL.

[0082] Finally, the first word line WL0 is opened again. Since the opening time of the first word line WL0 is increased, most of the potential of the storage unit 10 connected with the first word line WL0 has been leaked, and at this time, the remaining potential of the storage unit 10 connected with the first word line WL0 is not enough to change the potential difference between the bit line BL and the reference bit line / BL, so that the potential of the bit line BL is still less than the potential on the reference bit line / BL. After the potential difference between the bit line BL and the reference bit line / BL is amplified by the sense amplifier, the actual storage data of the storage unit 10 connected with the first word line WL1 read is "0", which is opposite to the first storage data "1" of the storage unit 10, which proves that the leakage occurs between the first word line WL0 and the second word line WL1.

[0083] It should be noted that after the structure of the memory is prepared, the memory needs to be tested (Design for Test, referred to as DFT), therefore, the peripheral circuit area of the memory needs to be provided with a test circuit. In the actual test process, the test circuit can be started, and the first voltage and the second voltage are applied to the first word line WL0 and the second word line WL1 respectively by using the test circuit.

[0084] In some embodiments, the second word line is started after the first word line is closed and a second preset time period is waited, wherein the second preset time period can be understood as a timing parameter tRP. In this stage, the bit line BL and the reference bit line / BL need to be pre-charged and reset, so that the bit line BL and the reference bit line / BL return to the intermediate potential V BLE .

[0085] The second preset time period is 5-20 ns, so that the bit line BL and the reference bit line / BL can return to the intermediate potential V BLE .

[0086] In some embodiments, the memory further includes a plurality of reference bit lines, which are arranged one by one with the bit lines, that is, one bit line corresponds to one reference bit line. For example, continuing to refer to Figure 1 , the memory has a plurality of bit line groups, each of which has 8 bit lines BL. When reading the storage data on one of the bit lines BL, the bit line BL adjacent to the bit line BL can be used as the reference bit line / BL, and the voltage difference between the bit line BL and the reference bit line / BL is used to obtain the storage data on one of the bit lines BL.

[0087] For example, when the data in the first row of memory cells 10 is to be read, the data in the memory cells 10 connected to the first bit line BL0 can be read using the first bit line BL0, and at this time, the second bit line BL1 can be used as the reference bit line / BL.

[0088] For another example, when the data in the second row of memory cells 10 is to be read, the data in the memory cells 10 connected to the second bit line BL1 can be read using the second bit line BL1, and at this time, the first bit line BL0 or the third bit line BL2 can be used as the reference bit line.

[0089] In a normal read operation, after the storage data of the memory cells 10 connected to the first word line WL0 is read, the potential on the bit line BL and the reference bit line / BL corresponding to the first word line WL0 needs to be pre-charged, so that the potential on the bit line BL and the reference bit line / BL is restored to the same value, so that when the second word line WL1 is opened, the storage data of the memory cells 10 connected to the second word line WL1 can be read using the bit line BL and the reference bit line / BL.

[0090] Based on the above theory, in this embodiment, before the step of obtaining the actual storage data of the memory cells 10 connected to the first word line WL0 through the bit line after the second word line WL1 is closed, the detection method of the memory further comprises:

[0091] Pre-charging the bit line BL and the reference bit line / BL shared by the first word line WL0 and the second word line WL1, so that the potential of the pre-charged bit line BL is not equal to the potential of the reference bit line / BL.

[0092] For example, as shown in Figure 1 and Figure 4 The bit line BL corresponding to the second word line WL1 has 8 bit lines, which are BL0-BL7 in sequence. It can be understood that one of the 8 bit lines, for example, the first bit line BL0, corresponds to the reference bit line BL1.

[0093] After the second word line WL1 is opened, since the first storage data on the memory cells 10 connected to the second word line WL1 is "0", at this time, the first storage data "0" is transmitted to the bit line BL, so that the data on the memory cells 10 and the bit line BL are in the charge sharing stage, so that the potential on the bit line BL is lower than the potential on the reference bit line / BL.

[0094] For another example, as shown in Figure 5In this embodiment, after the second word line WL1 is turned off, the potential of the precharged bit line BL is made unequal to the potential of the reference bit line / BL, so that the potential on the bit line BL is lower than the potential on the reference bit line / BL. With this configuration, when the first word line WL0 is turned on, the memory cells connected to the first word line WL0 have already leaked most of the current. When the first word line WL0 is turned on again, the memory cells connected to the first word line WL0 have already leaked most of the charge, which is insufficient to change the potential on the bit line BL. As a result, the potential on the bit line BL remains lower than the potential on the reference bit line / BL, causing the potential on the bit line BL to decrease by ΔV. In this way, after the sense amplifier subsequently amplifies ΔV, the read data is "0", ensuring that the current leakage problem between the first word line WL0 and the second word line WL1 can be accurately detected.

[0095] In some embodiments, as Figure 6 As shown, the memory includes an equalization circuit BLEQ. When the bit line BL and the reference bit line / BL need to be reset, the equalization circuit BLEQ of the memory can be started, and the bit line BL and the reference bit line / BL corresponding to the bit line BL are in a precharge state within a third preset time period, and the third preset time period is less than a second time threshold; the second time threshold is the time taken for the potential of the bit line and the potential of the reference bit line to reach equal potential after precharging, that is, the second time threshold is a timing parameter tRP. tRP is the time between the precharge command (PRE) of the previous word line and the activate command (ACT) of the next word line in the DRAM, and is used to characterize the speed at which the DRAM array recovers to the precharge state, especially the time required for the bit lines in the array to charge from a high level or a low level to an intermediate potential.

[0096] If the tRP time is shortened, the potential on the bit line BL will not be restored to the intermediate potential V when the first bit line WL0 starts the activation command. BLE , making the potential on the bit line BL less than or greater than the reference bit line / BL, resulting in the sense amplifier SA giving an erroneous data result when reading data of the memory cell 10 connected to the first bit line WL0.

[0097] For example, Figure 6 As shown, the equalizer circuit BLEQ includes a first transistor P1, a second transistor P2, and a third transistor P3 disposed between the bit line BL and the reference bit line / BL.

[0098] The gates of the first transistor P1, the second transistor P2, and the third transistor P3 are connected and connected to the first signal line 20. The first signal line 20 is used to provide a voltage to the balancing circuit to turn on or off the balancing circuit. In other words, the first signal line 20 is used to provide a high level or a low level to the gates of the first transistor P1, the second transistor P2, and the third transistor P3 to turn on or off the above-mentioned transistors.

[0099] A source of the first transistor P1 is connected to the bit line BL, and a drain of the first transistor P1 is connected to the reference bit line / BL.

[0100] A source of the second transistor P2 is connected to the bit line BL, and a drain of the second transistor P2 is connected to a source of the third transistor P3.

[0101] The drain of the third transistor P3 is connected to the reference bit line / BL. The drain of the second transistor P2 and the source of the third transistor P3 are also connected to the second signal line 30. The second signal line 30 is used to provide a reset voltage to the bit line BL and the reference bit line / BL. The second signal line 30 is connected to the peripheral circuit and is used to provide an intermediate voltage V to the bit line BL and the reference bit line / BL. BLE .

[0102] In some embodiments, the step of obtaining actual storage data of the memory cell connected to the second word line further includes:

[0103] like Figure 6 As shown, the memory includes a read circuit and a peripheral circuit (not shown in the figure), the read circuit is connected to the bit line, the read circuit is started to transfer the storage data of the memory cell connected to the first word line to the peripheral circuit, and the storage data of the memory cell is obtained using the peripheral circuit.

[0104] Exemplarily, the reading circuit includes: a reading transistor YSW, the gate of the reading transistor YSW is connected to the third signal line 40, and the third signal line 40 is used to control the opening or closing of the reading transistor YSW; the source of the reading transistor YSW is connected to the bit line BL, and the drain of the reading transistor YSW is connected to the peripheral circuit, wherein a fourth signal line 50 is arranged between the drain of the reading transistor YSW and the peripheral circuit.

[0105] When the potential of the third signal line 40 is at a high level, the read transistor YSW is turned on, and the source and drain of the read transistor YSW are connected, so that the potential on the bit line BL is transmitted to the peripheral circuit through the fourth signal line 50, and then the potential on the bit line BL is read using the peripheral circuit.

[0106] In some embodiments, in order to improve the accuracy of reading data of the memory, a sense amplifier SA is usually arranged in the memory, wherein the sense amplifier SA is arranged between a bit line BL and a reference bit line / BL corresponding to the bit line BL, one end of the sense amplifier SA is connected with the bit line BL, and the other end is connected with the reference bit line / BL, for amplifying the voltage difference between the bit line BL and the reference bit line / BL corresponding to the bit line BL.

[0107] Exemplarily, the sense amplifier SA includes a fourth transistor P4, a fifth transistor P5, a sixth transistor P6 and a seventh transistor P7.

[0108] The gate of the fourth transistor P4 is connected with the reference bit line / BL, and the source of the fourth transistor P4 is connected with the bit line BL.

[0109] The gate of the fifth transistor P5 is connected with the bit line BL, the source of the fifth transistor P5 is connected with the reference bit line / BL, the drain of the fifth transistor P5 is connected with the drain of the fourth transistor P4, and is connected with a first power line NCS for providing a low potential voltage.

[0110] The gate of the sixth transistor P6 is connected with the reference bit line / BL, and the source of the sixth transistor P6 is connected with the bit line BL.

[0111] The gate of the seventh transistor P7 is connected with the bit line BL, the source of the seventh transistor P7 is connected with the reference bit line / BL, the drain of the seventh transistor P7 is connected with the drain of the sixth transistor P6, and is connected with a second power line PCS for providing a high potential voltage.

[0112] In the embodiment, the fourth transistor P4 and the fifth transistor P5 are both N-type transistors, and the sixth transistor P6 and the seventh transistor P7 are both P-type transistors.

[0113] In the embodiment, when reading data “0” by using the bit line BL, the sense amplifier SA can pull down the potential on the bit line BL to the lowest potential Vss, and pull up the potential on the reference bit line / BL to the highest potential Vary, so as to amplify the voltage difference between the bit line BL and the reference bit line / BL corresponding to the bit line BL, and facilitate the reading of the reading circuit.

[0114] When reading the stored data of the storage unit connected with the second word line, the following processes are mainly included: Figure 7As shown, after the second word line WL1 is closed and the reset is completed, the equalization circuit BLEQ is closed, and the first word line WL0 is opened to open the storage unit 10 connected with the first word line WL0, so that the data in the storage unit 10 is shared with the potential on the bit line BL. Since the potential on the bit line BL and the reference bit line / BL is not reset to the intermediate potential V BLE After the first word line WL0 is opened, since the opening time of the first word line WL0 is increased, most of the potential of the storage unit 10 connected with the first word line WL0 has been leaked. At this time, the remaining potential of the storage unit 10 connected with the first word line WL0 is not enough to change the potential difference between the bit line BL and the reference bit line / BL. In this way, the sensitive amplifier SA is opened, the potential on the reference bit line / BL is quickly pulled up to the highest potential Vary by the sensitive amplifier SA, and the potential on the bit line BL is quickly pulled down to the lowest potential Vss, so as to amplify the potential difference between the bit line BL and the reference bit line / BL. Then, the reading circuit is opened, and the data in the storage unit 10 is transmitted to the peripheral circuit by the fourth signal line 50, so as to obtain the data of the storage unit 10 connected with the first word line WL0. After that, the reference bit line / BL and the bit line BL are pre-charged, and the first word line WL0 and the sensitive amplifier are closed, so that the potential of the bit line BL and the reference bit line / BL returns to the intermediate potential V BLE , so as to facilitate reading the data in the storage unit connected with the remaining word lines.

[0115] In this embodiment, on the one hand, the opening time of the first word line WL0 is increased to be greater than the timing parameter tRAS, so as to increase the time of the first word line leakage current. On the other hand, the timing parameter tRP between the closing of the second word line WL1 and the restarting of the first word line WL0 is shortened, so as to reduce the pre-charging time of the bit line and the reference bit line, and make it difficult for the potential of the bit line and the reference bit line to return to the intermediate value V BLE , so as to affect the type of reading the storage data of the storage unit connected with the first word line. Based on this, the two aspects of improvement can timely detect whether the adjacent word line leaks, which provides a guarantee for improving the yield of the memory.

[0116] The embodiments or implementations in the specification are described in a progressive manner, and each embodiment focuses on the difference from other embodiments. The same or similar parts between the embodiments can be referred to each other.

[0117] In the description of the specification, the description of the terms "one embodiment", "some embodiments", "exemplary embodiment", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are contained in at least one embodiment or example of the present application.

[0118] In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiment", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are contained in at least one embodiment or example of the present application.

[0119] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A memory detection method, characterized in that: Among any two adjacent word lines, one of the word lines is a first word line and the other word line is a second word line, the detection method includes: Writing first storage data into a memory cell connected to the first word line, and writing second storage data into a memory cell connected to the second word line, wherein the first storage data is different from the second storage data; activating the first word line to turn on a transistor of a memory cell connected to the first word line, and keeping the transistor on for a first preset time period before turning it off, where the first preset time period is greater than a first time threshold; After turning off the first word line, turning on the second word line, and keeping the second word line for the first time threshold before turning it off; acquiring actual storage data of a memory cell connected to the first word line through a bit line, and determining whether the actual storage data is the same as the second storage data, wherein the bit line is connected to the memory cell connected to the first word line; If actual storage data of a memory cell on one of the bit lines connected to the first word line is the same as the second storage data, leakage occurs between the first word line and the second word line.

2. The memory detection method according to claim 1, wherein: The step of starting the first word line includes: applying a first voltage to the first word line to start the first word line, wherein the first voltage is greater than a turn-on voltage of the first word line.

3. The memory detection method according to claim 2, wherein: The step of starting the first word line further includes applying a second voltage to the first word line to turn off the first word line, wherein the second voltage is greater than a turn-off voltage of the first word line.

4. The memory detection method according to any one of claims 1 to 3, characterized in that: The first word line is turned off, and after waiting for a second preset time period, the second word line is turned on.

5. The memory detection method according to claim 4, characterized in that: The second preset time period is between 5-20 ns.

6. The memory detection method according to any one of claims 1 to 3, characterized in that: The memory further includes a plurality of reference bit lines, the plurality of reference bit lines being arranged in a one-to-one correspondence with the plurality of bit lines. After the step of turning off the first word line, turning on the second word line, and keeping the second word line turned off after the first time threshold, and before the step of acquiring actual storage data of a memory cell connected to the first word line through the bit line, the detection method further includes: The bit line shared with the first word line and the second word line and the reference bit line are precharged so that a potential of the precharged bit line is not equal to a potential of the reference bit line.

7. The memory detection method according to claim 6, characterized in that: The memory includes an equalization circuit. The equalization circuit of the memory is activated to place the bit line shared with the first word line and the second word line and the reference bit line in a precharge state within a third preset time period, where the third preset time period is less than a second time threshold.

8. The memory detection method according to claim 7, characterized in that: The equalization circuit includes a first transistor, a second transistor, and a third transistor disposed between the bit line and the reference bit line; The gates of the first transistor, the second transistor, and the third transistor are connected to a first signal line, and the first signal line is used to provide a voltage to the balancing circuit to turn on or off the balancing circuit; The source of the first transistor is connected to the bit line, and the drain of the first transistor is connected to the reference bit line; The source of the second transistor is connected to the bit line, and the drain of the second transistor is connected to the source of the third transistor; The drain of the third transistor is connected to the reference bit line; The drain of the second transistor and the source of the third transistor are further connected to a second signal line, and the second signal line is used to provide a reset voltage to the bit line and the reference bit line.

9. The memory detection method according to any one of claims 1 to 3, characterized in that: The step of acquiring actual storage data of a memory cell connected to the first word line through the bit line includes: The memory includes a read circuit and a peripheral circuit. The read circuit is connected to the bit line. The read circuit is activated to transfer storage data connected to the first word line to the peripheral circuit.

10. The memory detection method according to claim 9, characterized in that: The read circuit includes: a read transistor, wherein a gate of the read transistor is connected to a third signal line, and the third signal line is used to control the opening or closing of the read transistor; A source of the read transistor is connected to the bit line, and a drain of the read transistor is connected to the peripheral circuit.

11. The memory detection method according to claim 10, wherein: A fourth signal line is provided between the drain of the read transistor and the peripheral circuit.

12. The memory detection method according to claim 6, characterized in that: The memory further includes a sensitive amplifier, which is arranged between the bit line and the reference bit line corresponding to the bit line, and is used to amplify the voltage difference between the bit line and the reference bit line corresponding to the bit line.

13. The memory detection method according to claim 12, wherein: The sense amplifier includes a fourth transistor, a fifth transistor, a sixth transistor and a seventh transistor; A gate of the fourth transistor is connected to the reference bit line, and a source of the fourth transistor is connected to the bit line; The gate of the fifth transistor is connected to the bit line, the source of the fifth transistor is connected to the reference bit line, the drain of the fifth transistor is connected to the drain of the fourth transistor, and is connected to a first power line, wherein the first power line is used to provide a low potential voltage; The gate of the sixth transistor is connected to the reference bit line, and the source of the sixth transistor is connected to the bit line; The gate of the seventh transistor is connected to the bit line, the source of the seventh transistor is connected to the reference bit line, the drain of the seventh transistor is connected to the drain of the sixth transistor and to a second power line, and the second power line is used to provide a high potential voltage.

14. The memory detection method according to claim 13, wherein: The fourth transistor and the fifth transistor are both N-type transistors, and the sixth transistor and the seventh transistor are both P-type transistors.

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