Chip packaging structure and preparation method therefor, and electronic device

Abstract

The embodiments of the present application relate to the technical field of semiconductors. Disclosed are a chip packaging structure and a preparation method therefor, and an electronic device. The chip packaging structure comprises a first substrate, a first chip, a second substrate, a first heat dissipation component, a first connecting portion and a second chip, wherein the first chip is electrically connected to one side of the first substrate; the second substrate is located on the side of the first chip away from the first substrate and is electrically connected to the first substrate; the second substrate is internally provided with an opening extending therethrough, and the orthographic projection of the opening on the first substrate at least partially overlaps the orthographic projection of the first chip on the first substrate; the first heat dissipation component is located in the opening; the first connecting portion is connected between the first chip and the first heat dissipation component; and the second chip is electrically connected to the side of the second substrate away from the first substrate. By means of the provision of the opening in the second substrate and the arrangement of the first heat dissipation component in the opening, an upward heat dissipation path can be provided for the first chip, and the overall heat capacity of the chip packaging structure can also be improved, thereby effectively improving the heat dissipation effect of POP packaging.

Description

Chip packaging structure and its fabrication method, electronic devices

[0001] This application claims priority to Chinese patent application filed on May 28, 2024, with application number 202410679241.7 and entitled "Chip Packaging Structure and Preparation Method Thereof, Electronic Device", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of semiconductor technology, and in particular to a chip packaging structure and its fabrication method, and electronic devices. Background Technology

[0003] With the continuous development of science and technology, consumers have increasingly higher demands for the functions of electronic devices, leading to the integration of more and more chips into these devices. At least some chips are packaged using POP (package-on-package) technology to reduce the package area.

[0004] However, as the performance of electronic devices improves, the power density of chips gradually increases, and correspondingly, the heat generated by the chips also increases significantly. Therefore, how to enhance the heat dissipation effect of POP packaging has become an urgent problem to be solved. Summary of the Invention

[0005] This application provides a chip packaging structure and its fabrication method, as well as an electronic device, for improving the heat dissipation effect of the chip packaging structure and the electronic device.

[0006] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0007] In a first aspect, a chip packaging structure is provided, comprising: a first substrate, a first chip, a second substrate, a first heat dissipation component, a first connecting portion, and a second chip. The first chip is located on one side of the first substrate and is electrically connected to the first substrate. The second substrate is located on the side of the first chip away from the first substrate and is electrically connected to the first substrate. Furthermore, an opening is formed in the second substrate, penetrating the second substrate, and the orthographic projection of the opening onto the first substrate at least partially overlaps with the orthographic projection of the first chip onto the first substrate. The first heat dissipation component is located within the opening. The first connecting portion is located between the first chip and the first heat dissipation component; the first connecting portion connects the first chip and the first heat dissipation component. The second chip is located on the side of the second substrate away from the first substrate and is electrically connected to the second substrate. The second chip covers the opening.

[0008] The chip packaging structure provided in some embodiments of this application achieves POP packaging by stacking a first substrate, a first chip, a second substrate, and a second chip, thereby reducing the area of ​​the chip packaging structure. Furthermore, by creating a through-hole in the second substrate and positioning it above the first chip, the heat dissipation restriction of the second substrate on the first chip is removed, providing an upward (i.e., the direction from the first substrate to the second substrate) heat dissipation path for the first chip. This allows the heat generated by the first chip to diffuse out through the opening in the second substrate. Of the heat diffused through this opening, some can continue to diffuse upward through the second chip, while another portion can be dissipated laterally through the space between the second substrate and the second chip. Further, by providing a first heat dissipation component within the opening in the second substrate and connecting the first chip and the first heat dissipation component via a first connecting portion, the overall thermal capacity of the chip packaging structure can be effectively increased, accelerating the upward heat dissipation rate of the first chip. This allows the heat generated by the first chip to diffuse out more quickly through the opening in the second substrate and to dissipate more quickly through the second chip or through the space between the second chip and the second substrate. This effectively improves the heat dissipation effect of the POP package formed by the chip packaging structure and enhances the heat dissipation effect of the electronic devices in which this chip packaging structure is applied.

[0009] In one possible design aspect, the first heat dissipation component has a lower surface, an upper surface, and multiple side surfaces. The lower surface faces the first chip, and the upper surface faces away from the first chip. The multiple side surfaces are connected end-to-end and connect the lower surface and the upper surface. The roughness of at least one of the lower surface and the multiple side surfaces is greater than the roughness of the upper surface. This increases the contact area between the first heat dissipation component and the first connecting portion, increases the bonding force between the first heat dissipation component and the first connecting portion, and thus helps improve the structural stability of the chip packaging structure.

[0010] In one possible design approach, the first connection portion includes a first connection layer and a second connection layer, with the first connection layer located between the first chip and the second connection layer. The second connection layer has a higher thermal conductivity than the first connection layer. This, on the one hand, accelerates the diffusion of heat generated by the chip to the first heat dissipation component, improving heat dissipation; on the other hand, it strengthens the bond between the first heat dissipation component and the chip, improving the structural stability of the chip packaging structure.

[0011] In one possible design aspect, the chip package structure further includes a packaging layer. At least a portion of this packaging layer is located between the first substrate and the second substrate, and surrounds the first chip, the first connection portion, and the first heat dissipation component. The surface of the packaging layer away from the first substrate is flush with the surface of the first heat dissipation component away from the first substrate. In this case, the surface of the first heat dissipation component away from the first substrate is not covered by the packaging layer. This prevents the packaging layer from affecting the heat dissipation of the first heat dissipation component and thus avoids affecting the heat dissipation effect of the chip package structure.

[0012] In one possible design approach, the first heat dissipation component is made of either a metallic or ceramic material. The surface of the first heat dissipation component away from the first substrate is flush with the surface of the second substrate away from the first substrate. This ensures the integrity of the first heat dissipation component's structure while avoiding increasing the thickness of the chip package structure.

[0013] In one possible design approach, the chip package structure further includes a first connection component. This first connection component is located between the second substrate and the second chip, and connects the pads of the second substrate and the second chip. The first connection component is used to achieve an electrical connection between the second chip and the second substrate. This arrangement avoids increasing the thickness of the chip package structure, thus avoiding increasing the fabrication difficulty and structural complexity of the chip package structure.

[0014] In one possible design aspect, the material of the first heat dissipation component includes silicon. The surface of the first heat dissipation component, away from the first substrate, is higher than the surface of the second substrate, also away from the first substrate. A portion of the encapsulation layer is also located on the side of the second substrate away from the first substrate, covering the second substrate. This avoids damage to the first heat dissipation component during the fabrication of the chip package structure. Furthermore, the encapsulation layer can also protect the second substrate.

[0015] In one possible design aspect, the chip package structure further includes a solder pad and a first connection component. The solder pad is located between the second substrate and the second chip; and it penetrates the portion of the package layer on the side of the second substrate furthest from the first substrate, and is electrically connected to the pads of the second substrate. The first connection component is located between the solder pad and the second chip, and connects the solder pad and the second chip. This allows signal transmission between the second chip and the second substrate to be achieved using the solder pad and the first connection component, while protecting the first heat dissipation component with the portion of the package layer covering the second substrate.

[0016] In one possible design aspect, the chip package structure further includes a second heat dissipation component and a second connection portion. The second heat dissipation component is located on the side of the first heat dissipation component away from the first substrate, and is spaced apart from the second chip. The second connection portion is located between the first and second heat dissipation components, and connects the first and second heat dissipation components. This further improves the overall thermal capacity of the chip package structure and enhances its heat dissipation effect.

[0017] In one possible design approach, the second heat sink is made of the same material as the first heat sink. Alternatively, both the second and first heat sinks can be made of metal, ceramic, or silicon.

[0018] In one possible design approach, the structure of the second heat sink is identical to that of the first heat sink. For example, the roughness of at least one of the lower surface and multiple sides of the second heat sink is greater than the roughness of the upper surface of the second heat sink. This increases the contact area between the second heat sink and the second connector, increases the bonding force between the second heat sink and the second connector, and improves the structural stability of the chip package structure.

[0019] In one possible design approach, the material of the second heat dissipation component is the same as that of the first heat dissipation component, and the structure of the second heat dissipation component is the same as that of the first heat dissipation component.

[0020] In one possible design approach, the material of the second connector is the same as that of the first connector. Alternatively, both the second connector and the first connector may be made of adhesive or solder paste.

[0021] In one possible design approach, the structure of the second connecting part is the same as that of the first connecting part. For example, if the first connecting part is a single-layer structure, the second connecting part is also a single-layer structure. Similarly, if the first connecting part is a structure of multiple film layers stacked together, the second connecting part is also a structure of multiple film layers stacked together.

[0022] In one possible design approach, the material of the first connector includes adhesive or solder paste. The first connector is used to connect (e.g., to bond) the first chip and the first heat dissipation component. The first connector can be a single-layer thin-film structure or a structure composed of multiple layers of thin films.

[0023] In one possible design approach, the chip package structure further includes a second connection component located between the first substrate and the second substrate. This second connection component is electrically connected to both the first substrate and the second substrate. The orthographic projection of the second connection component onto the first substrate does not overlap with the orthographic projection of the first chip onto the first substrate. For example, the second connection component may include multiple solder balls or multiple conductive pillars. This allows for both electrical connection between the first and second substrates and avoids interference between the second connection component and the first chip.

[0024] In one possible design approach, the chip package structure further includes a thermally conductive adhesive layer located between the second substrate and the second chip, which connects the second substrate, the first heat dissipation component, and the second chip. This enhances the connection stability between the second substrate 3 and the second chip 4, strengthens lateral heat dissipation, and further improves the heat dissipation effect of the chip package structure.

[0025] In a second aspect, a method for fabricating a chip packaging structure is provided, the method comprising: connecting a first chip to one side of a first substrate; disposing a second substrate on the side of the first chip away from the first substrate, and connecting the second substrate to the first substrate; having an opening in the second substrate, the opening penetrating the second substrate; the orthographic projection of the opening on the first substrate and the orthographic projection of the first chip on the first substrate at least partially overlapping; sequentially forming a first connecting portion and a first heat dissipation component on the side of the first chip away from the first substrate, the first heat dissipation component being located within the opening; and connecting a second chip to the side of the second substrate away from the first substrate.

[0026] In a possible design in the second aspect, the first connecting portion and the first heat dissipation component are disposed before the second substrate is disposed on the side of the first chip away from the first substrate.

[0027] In a second possible design, the first connecting portion and the first heat dissipation component are disposed after the second substrate is disposed on the side of the first chip away from the first substrate.

[0028] In a possible design in the second aspect, the first heat dissipation component has a lower surface, an upper surface, and multiple side surfaces. The lower surface faces the first chip, the upper surface faces away from the first chip, and the multiple side surfaces are connected end-to-end and connect the lower surface and the upper surface. The above-mentioned fabrication method further includes: before sequentially setting the first connecting portion and the first heat dissipation component on the side of the first chip away from the first substrate, processing at least one of the lower surface and the multiple side surfaces to increase the roughness.

[0029] In a possible design approach in the second aspect, providing the first connection portion includes: forming a first connection layer on the side of the first chip away from the first substrate; forming a second connection layer on the side of the first connection layer away from the first substrate; the thermal conductivity of the second connection layer is greater than that of the first connection layer.

[0030] In a possible design approach in the second aspect, before connecting the second chip to the side of the second substrate away from the first substrate, the fabrication method further includes: forming an encapsulation layer at least between the first substrate and the second substrate. The encapsulation layer surrounds the first chip, the first connection portion, and the first heat dissipation component, with the surface of the encapsulation layer away from the first substrate flush with the surface of the first heat dissipation component away from the first substrate.

[0031] In a possible design in the second aspect, the material of the first heat dissipation component includes silicon; the surface of the first heat dissipation component away from the first substrate is higher than the surface of the second substrate away from the first substrate relative to the first substrate. Before forming an encapsulation layer at least between the first and second substrates, the fabrication method further includes: forming solder pads on pads on the side of the second substrate away from the first substrate. Forming an encapsulation layer at least between the first and second substrates includes: forming an encapsulation film between the first and second substrates and on the side of the second substrate away from the first substrate, the encapsulation film covering the solder pads and the first heat dissipation component; and polishing the encapsulation film to expose the solder pads and the first heat dissipation component.

[0032] Thirdly, an electronic device is provided, comprising: a chip package structure and a circuit board, the circuit board being electrically connected to the chip package structure. The chip package structure is as described in any embodiment of the first aspect.

[0033] The technical effects of any of the design methods in the second or third aspect can be found in the technical effects of different design methods in the first aspect, and will not be repeated here. Attached Figure Description

[0034] Figure 1 is a structural diagram of an electronic device provided in an embodiment of this application;

[0035] Figure 2 is an exploded structural diagram of the electronic device shown in Figure 1;

[0036] Figure 3 is a partial structural diagram of the electronic device shown in Figure 1;

[0037] Figure 4 is a top view of a chip packaging structure provided in an embodiment of this application;

[0038] Figure 5 is a cross-sectional view of the chip packaging structure shown in Figure 4 along the A-A' direction;

[0039] Figure 6 is a top view of another chip packaging structure provided in an embodiment of this application;

[0040] Figure 7 is a cross-sectional view of the chip packaging structure shown in Figure 6 along the B-B' direction;

[0041] Figure 8 is a partial cross-sectional view of the chip packaging structure shown in Figure 6;

[0042] Figure 9 is another partial cross-sectional view of the chip packaging structure shown in Figure 6;

[0043] Figure 10 is another partial cross-sectional view of the chip packaging structure shown in Figure 6;

[0044] Figure 11 is another cross-sectional view of the chip packaging structure shown in Figure 6 along the B-B' direction;

[0045] Figure 12 is another cross-sectional view of the chip packaging structure shown in Figure 6 along the B-B' direction;

[0046] Figure 13 is another cross-sectional view of the chip packaging structure shown in Figure 6 along the B-B' direction;

[0047] Figure 14 is a flowchart of a chip packaging structure fabrication method provided in an embodiment of this application;

[0048] Figure 15 is a flowchart of another method for fabricating a chip packaging structure provided in an embodiment of this application;

[0049] Figures 16-22 are structural diagrams corresponding to each step in a chip packaging structure fabrication method provided in the embodiments of this application. Detailed Implementation

[0050] The technical solutions of the embodiments of this application will be described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0051] In the description of this application, unless otherwise stated, "multiple" means two or more. "At least one" or similar expressions refer to any combination of these items, including any combination of single or multiple items. For example, at least one of a, b, or c can mean: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.

[0052] "AND / OR" describes the relationship between related objects, indicating that there can be three relationships. For example, A AND / OR B can mean: A alone, A and B simultaneously, or B alone. A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "OR" relationship.

[0053] Furthermore, to facilitate a clear description of the technical solutions in the embodiments of this application, the terms "first" and "second" are used in the embodiments of this application to distinguish identical or similar items with substantially the same function and effect. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order, and that "first" and "second" are not necessarily different. Meanwhile, in the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is being used as an example, illustration, or description. Any embodiment or design scheme described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design schemes. Specifically, the use of terms such as "exemplary" or "for example" is intended to present related concepts in a concrete manner for ease of understanding.

[0054] In the embodiments of this application, unless otherwise expressly specified and limited, the term "connection" can refer to a direct mechanical connection or an electrical connection, or an indirect mechanical connection or electrical connection via an intermediate medium. The mechanical connection here is not limited to whether it is used for transmitting electrical signals, while the electrical connection is used for transmitting electrical signals.

[0055] This application describes exemplary embodiments with reference to cross-sectional views and / or plan views as idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown in this application, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0056] Furthermore, the architecture and scenarios described in the embodiments of this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the evolution of architecture and the emergence of new scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0057] This application provides an electronic device. This electronic device can be a mobile phone, tablet, smart screen, speaker, monitor, television, desktop computer, laptop computer, handheld computer, laptop, ultra-mobile personal computer (UMPC), netbook, as well as cellular phone, personal digital assistant (PDA), augmented reality (AR) device, virtual reality (VR) device, artificial intelligence (AI) device, smart wearable device (e.g., smartwatch, smart bracelet), in-vehicle device, smart home device, and / or smart city device, etc. This application does not impose any special limitations on the specific type of this electronic device.

[0058] For ease of explanation, the following example uses a mobile phone as an example, which should not be considered a specific limitation on the structural form of the electronic device. Figure 1 is a structural diagram of an electronic device in some embodiments, Figure 2 is an exploded structural diagram of the electronic device shown in Figure 1, and Figure 3 is a partial structural diagram of the electronic device shown in Figure 1.

[0059] As shown in Figure 1, the electronic device 1000 includes a housing 100. Exemplarily, as shown in Figure 2, the housing 100 may include a front frame 101, a middle frame 102, and a rear housing 103. The middle frame 102 includes a side frame 1021 and a middle plate 1022. The middle plate 1022 is, for example, a flat plate-like structure, and the side frame 1021 is, for example, an annular structure, surrounding the middle plate 1022. The side frame 1021 can be connected to the middle plate 1022 by welding, bonding, or other methods. Alternatively, the side frame 1021 and the middle plate 1022 can be integrally formed to improve the reliability of the connection between them.

[0060] The front frame 101 is connected to one edge of the side frame 1021, and the rear shell 103 is connected to the side edge of the side frame 1021 away from the front frame 101. The front frame 101, side frame 1021, and rear shell 103 can enclose an accommodating space. The middle plate 1022 is located within this accommodating space, for example. The middle plate 1022 can serve as the skeleton of the electronic device 1000, providing support. The front frame 101 and rear shell 103 can be connected to the side frame 1021 by means of snap-fit ​​or adhesive bonding, for example. The connection methods between the front frame 101 and the side frame 1021 and between the rear shell 103 and the side frame 1021 can be the same or different.

[0061] In some examples, continuing to refer to Figure 2, the above-mentioned electronic device 1000 may also include a display screen 200.

[0062] The aforementioned display screen 200 is used to display image information. The image information displayed on the display screen 200 can be a static image (such as a picture or photograph) or a dynamic image (such as a video or game screen). The display screen 200 can be of various types. Optionally, it can be a liquid crystal display (LCD), an organic light-emitting diode (OLED) display, a quantum dot light-emitting diode (QLED) display, a mini light-emitting diode (Mini LED) display, or a micro light-emitting diode (Micro LED) display, etc. Of course, the display screen 200 can also be other types of display screens.

[0063] The aforementioned front frame 101 is open (not shown in the figure), and the open end extends through the front frame 101 along its thickness direction. The display screen 200 is located in the receiving space between the middle plate 1022 and the front frame 101, and is embedded in the open end and connected to the front frame 101 to prevent the front frame 101 from obstructing the image information displayed on the display screen 200.

[0064] In some examples, continuing to refer to Figure 2, the aforementioned electronic device 1000 may further include a camera assembly 300. This camera assembly 300 has image acquisition capabilities. The camera assembly 300 is located within a receiving space between the middle plate 1022 and the rear housing 103. As shown in Figure 2, a first through-hole is formed on the rear housing 103, extending through the rear housing 103 along its thickness direction. The camera assembly 300 is embedded within the first through-hole and connected to the rear housing 103, preventing the rear housing 103 from obstructing the camera assembly 300.

[0065] The number of camera components 300 can be one or more. When there are multiple camera components 300, the number of first through holes can be one, in which case the multiple camera components 300 are embedded in the one first through hole; or, the number of first through holes can also be multiple, in which case at least one camera component 300 is embedded in one first through hole.

[0066] In some examples, in conjunction with Figures 2 and 3, the electronic device 1000 also includes structures such as a circuit board 400, a battery 500, and a chip packaging structure 600.

[0067] The aforementioned circuit board 400, battery 500, chip packaging structure 600, and other structures are located within the accommodating space enclosed by the housing 100. This allows the housing 100 to protect the circuit board 400, battery 500, chip packaging structure 600, and other structures, reducing the risk of damage to these structures.

[0068] Optionally, the circuit board 400 and the chip package structure 600 may be located within the receiving space between the middle plate 1022 and the rear shell 103, or the circuit board 400 and the chip package structure 600 may also be located within the receiving space between the middle plate 1022 and the front frame 101. The battery 500 is located, for example, within the receiving space between the middle plate 1022 and the rear shell 103. This application embodiment does not further limit the positions of structures such as the circuit board 400, battery 500, and chip package structure 600 within the housing 100.

[0069] For example, the circuit board 400 is electrically connected to the display screen 200 to control the image information displayed on the display screen 200.

[0070] The aforementioned circuit board 400 can be a printed circuit board (PCB). Of course, the circuit board 400 can also be a flexible circuit board, a rigid-flex circuit board, etc. Optionally, the circuit board 400 can be fixed between the middle plate 1022 and the rear shell 103 by means of threaded connection, snap-fit, adhesive, etc.

[0071] Furthermore, a universal serial bus (USB) device can be integrated on the aforementioned circuit board 400. This USB device can be a USB Type-C interface device, a USB Type-A interface device, a USB Type-B Micro-B interface device, or a USB Type-B interface device. A port is provided on the frame 1021 corresponding to the location of the USB device. Accessories such as chargers, headphones, and data cables can be electrically connected to the USB device via this port to achieve the transmission of power, signals, and data.

[0072] For example, as shown in Figure 3, the chip package structure 600 described above can be integrated onto the circuit board 400. The chip package structure 600 includes a chip that is electrically connected to the circuit board 400. The number of chips included in the chip package structure 600 can be, for example, one, two, three, or even more.

[0073] Optionally, the aforementioned chips include, but are not limited to, system on chip (SOC), charging management chip, power management unit (PMU), radio frequency (RF) chip, display chip, application processor (AP), double data rate synchronous dynamic random access memory (DDR SDRAM), universal flash storage (UFS), etc.

[0074] Understandably, with the continuous development of science and technology, consumers have increasingly higher functional demands for electronic devices 1000, leading to the integration of more and more chips within these devices. Due to the limited size of the electronic devices 1000, chip packaging structures 600 mostly adopt POP (Package on Package) to encapsulate multiple chips, thereby reducing the packaging area. POP packaging mainly includes two forms: FOPOP (fan-out package on package) and HBPOP (high-band package on package).

[0075] Taking HBPOP as an example, HBPOP mainly includes: a lower substrate, an upper substrate, a first chip, a second chip, and a packaging layer. The upper substrate and the lower substrate are positioned opposite each other and are typically electrically connected by solder balls. The first chip is located between the lower substrate and the upper substrate and is also electrically connected to the lower substrate. The packaging layer fills the space between the lower substrate and the upper substrate, forming a plastic encapsulation of the chip and contacting both the lower substrate and the upper substrate. The second chip is located on the side of the upper substrate furthest from the lower substrate and is also electrically connected to the lower substrate.

[0076] During the operation of the electronic device 1000, the aforementioned first chip generates heat. Due to the presence of the upper substrate, the upward heat dissipation path of the first chip (i.e., the direction from the lower substrate to the upper substrate) is greatly limited.

[0077] In some possible implementations, the overall heat capacity can be increased by increasing the thickness of the first chip, thereby improving the heat dissipation effect of the HBPOP.

[0078] However, due to the limited diameter of the solder balls, there is an upper limit to the spacing between the lower and upper substrates, which in turn limits the increase in the thickness of the first chip. This makes it difficult to further improve the heat dissipation effect of HBPOP.

[0079] Based on this, some embodiments of this application provide a chip packaging structure. This chip packaging structure can be applied to the aforementioned electronic device 1000. Optionally, this chip packaging structure can be the chip packaging structure 600 shown in FIG. 3. The embodiments of this application do not limit the application scenarios of the aforementioned chip packaging structure. FIG. 4 and FIG. 6 respectively illustrate top views of a chip packaging structure provided in the embodiments of the application; FIG. 5 illustrates a cross-sectional view of the chip packaging structure shown in FIG. 4 along the A-A' direction; FIG. 7, FIG. 11, FIG. 12 and FIG. 13 respectively illustrate cross-sectional views of the chip packaging structure shown in FIG. 6 along the B-B' direction; FIG. 8-FIG. 10 respectively illustrate partial cross-sectional views of the chip packaging structure shown in FIG. 6, with the cross-sectional direction being, for example, the B-B' direction.

[0080] In some examples, referring to Figures 4-7, the chip package structure 600 includes a first substrate 1, a first chip 2, a second substrate 3, a second chip 4, a first heat dissipation component 5, and a first connection portion 6.

[0081] The types of the first substrate 1 and the second substrate 3 mentioned above include various types. Optionally, the first substrate 1 includes, but is not limited to, a packaging substrate, a redistribution layer (RDL), etc., and the second substrate 3 includes, but is not limited to, a packaging substrate, a redistribution layer, etc. The types of the first substrate 1 and the second substrate 3 can be the same or different. For example, both the first substrate 1 and the second substrate 3 are packaging substrates. The packaging substrate includes, but is not limited to, organic substrates, ceramic substrates, silicon substrates, etc.

[0082] The number of first chips 2 can be one or more; the number of second chips 4 can also be one or more. Figures 6 and 7 illustrate this with an example where both the number of first chips 2 and second chips 4 is one. Optionally, the first chip 2 can be a bare die obtained by dicing a wafer with functional layers formed on it; a bare die can also be called a chip or particle. The second chip 4 can be a chip obtained by packaging the bare die. In some cases, the types of first chips 2 and second chips 4 are not limited to these. For example, the first chip 2 can be a System-on-a-Chip (SoC), and the second chip 4 can be a DDR (DDR memory).

[0083] As shown in Figures 5 and 7, the first chip 2 is located on one side of the first substrate 1 and is electrically connected to the first substrate 1. The chip package structure 600, for example, further includes a first connector 7 disposed between the first chip 2 and the first substrate 1, through which the first chip 2 can be connected (or soldered) to the first substrate 1. This first connector 7 is, for example, a controlled collapse chip connection bump (C4 bump). Referring to Figures 3, 5, and 7, the chip package structure 600 also includes, for example, a second connector 8 disposed between the circuit board 400 and the first substrate 1, through which the circuit board 400 can be connected (or soldered) to the first substrate 1. The second connector 8 is, for example, a solder ball (also known as a solder ball).

[0084] In this way, the first chip 2 and the circuit board 400 are respectively connected to the opposite sides of the first substrate 1, and the first chip 2 can be electrically connected and transmit signals to the circuit board 400 through the first connector 7, the first substrate 1, and the second connector 8 in sequence.

[0085] As shown in Figures 5 and 7, the second substrate 3 is located on the side of the first chip 2 away from the first substrate 1. Along the thickness direction of the first substrate 1 (that is, the stacking direction of the first substrate 1, the first chip 2, and the second substrate 3), the second substrate 3 and the first chip 2 are spaced apart, and the second substrate 3 and the first chip 2 are not in direct contact.

[0086] The second substrate 3 is electrically connected to the first substrate 1. For example, as shown in Figures 5 and 7, the chip package structure 600 further includes a second connection component 9, which is located between the first substrate 1 and the second substrate 3, and is electrically connected to both substrates 1 and 3. The second substrate 3 can be connected (or soldered) to the first substrate 1 via the second connection component 9. For example, the second connection component 9 may include multiple solder balls; or it may include multiple conductive pillars extending along the thickness direction of the first substrate 1, the material of which includes, but is not limited to, metallic materials. Of course, the structure of the second connection component 9 is not limited to these.

[0087] Furthermore, the orthographic projection of the second connecting component 9 on the first substrate 1 does not overlap with the orthographic projection of the first chip 2 on the first substrate 1. The second connecting component 9 may be arranged, for example, around the first chip 2, or it may be located on opposite sides of the first chip 2. This avoids interference between the second connecting component 9 and the first chip 2.

[0088] As shown in Figure 7, the second chip 4 is located on the side of the second substrate 3 away from the first substrate 1 and is electrically connected to the second substrate 3.

[0089] In this way, the second chip 4 can be electrically connected and transmit signals to the circuit board 400 in sequence through the second substrate 3, the second connecting component 9, the first substrate 1, and the second connector 8; or, the second chip 4 can be electrically connected and transmit signals to the first chip 2 in sequence through the second substrate 3, the second connecting component 9, the first substrate 1, and the first connector 7.

[0090] Here, as shown in Figures 4 and 5, when the second chip 4 is not connected to the second substrate 3, the first substrate 1, the first chip 2 electrically connected to the first substrate 1, and the second substrate 3 electrically connected to the first substrate 1 can also be considered as a single structure. In this case, the second substrate 3 can be used for electrical connection testing equipment to ensure that there are no abnormalities in the electrical connections between the second substrate 3, the first substrate 1, the first chip 2, and other structures, thereby ensuring that the chip packaging structure 600 can function normally after the second chip 4 is electrically connected to the second substrate 3.

[0091] Referring again to Figure 7, an opening K is formed in the second substrate 3, which penetrates the second substrate 3. The second chip 4 covers the opening K. That is, as shown in Figure 6, the orthographic projection of the opening K on the first substrate 1 is located within the orthographic projection range of the second chip 4 on the first substrate 1.

[0092] Furthermore, as shown in Figures 5-7, the orthographic projection of the opening K on the first substrate 1 and the orthographic projection of the first chip 2 on the first substrate 1 at least partially overlap. This means that the opening K is located above the first chip 2 (i.e., on the side of the first chip 2 away from the first substrate 1), and the second substrate 3 does not completely cover the first chip 2.

[0093] Optionally, the opening K is staggered with the first chip 2 along the thickness direction of the first substrate 1. The second substrate 3 covers a portion of the first chip 2 and exposes another portion of the first chip 2.

[0094] Optionally, along the thickness direction of the first substrate 1, the opening K is located directly above the first chip 2. As shown in Figures 5 and 7, the second substrate 3 covers a portion of the first chip 2 and exposes another portion of the first chip 2. Alternatively, the second substrate 3 does not cover the first chip 2.

[0095] The number, shape, and size of the openings K in the second substrate 3 can be determined according to the actual wiring inside the second substrate 3. This application embodiment does not limit this, as long as the second substrate 3 does not completely cover the first chip 2. Figure 6 illustrates an example with one opening K and a rectangular shape.

[0096] As shown in Figures 5 and 7, the first heat dissipation component 5 is located inside the opening K, and the first connecting portion 6 is located between the first chip 2 and the first heat dissipation component 5. For example, a portion of the first connecting portion 6 may be located inside the opening K, or the entire first connecting portion 6 may be located outside the opening K.

[0097] Optionally, the number of first heat dissipation components 5 located within the same opening K can be one or more. For example, the first connecting portion 6 and the first heat dissipation component 5 are arranged in a one-to-one correspondence; of course, one first connecting portion 6 can also correspond to multiple first heat dissipation components 5. The first connecting portion 6 connects the first chip 2 and its corresponding first heat dissipation component 5 to fix the first heat dissipation component 5 to the side of the first chip 2 away from the first substrate 1.

[0098] Furthermore, as shown in Figures 4 and 6, the projected area of ​​the first heat dissipation component 5 on the first substrate 1 is smaller than the projected area of ​​the opening K on the first substrate 1. Along a direction perpendicular to the thickness direction of the first substrate 1, there is a certain distance between the first heat dissipation component 5 and the inner wall of the opening K; they are not in direct contact.

[0099] The projected area of ​​the first connecting part 6 on the first substrate 1 can be smaller than, equal to or larger than the projected area of ​​the opening K on the first substrate 1; and there is a certain distance between the first connecting part 6 and the inner wall of the opening K, and the two are not in direct contact.

[0100] This facilitates the filling of the encapsulation layer material, thereby increasing the structural strength and reliability of the chip package structure 600. Furthermore, it prevents positional interference between the first heat sink 5 and the second substrate 3 during the connection process, thus improving the yield of the chip package structure 600. The connection process of the encapsulation layer and the first heat sink 5 and the second substrate 3 is described in detail below and will not be repeated here.

[0101] Here, the first heat dissipation component 5 has a high thermal conductivity, and the material of the first heat dissipation component 5 includes materials with high thermal conductivity. Optionally, the material of the first heat dissipation component 5 includes, but is not limited to, silicon (Si), metallic materials, ceramic materials, etc.

[0102] The material and size of the first heat dissipation component 5 and the size of the first connecting part 6 can be selected and set according to actual needs to optimize the overall operability and reliability of the chip packaging structure 600.

[0103] Understandably, based on the aforementioned opening K, the heat generated by the first chip 2, during its upward diffusion (i.e., the direction from the first substrate 1 to the second substrate 3), will preferentially diffuse out through opening K compared to the second substrate 3 itself. Of the heat diffused through opening K, some can diffuse through the second chip 4, while the remaining heat can be dissipated laterally through the space between the second substrate 3 and the second chip 4. In other words, the opening K breaks the restriction imposed by the second substrate 3 on the upward heat dissipation path of the first chip 2. This enhances upward heat dissipation, improving the poor heat dissipation effect caused by the difficulty in quickly dissipating heat through the second substrate 3, thereby enhancing the heat dissipation effect and improving heat dissipation performance.

[0104] Furthermore, by providing the first heat dissipation component 5 within the aforementioned opening K, the overall heat capacity of the chip package structure 600 can be effectively increased, accelerating the upward heat dissipation rate of the first chip 2. This significantly improves the heat dissipation effect of the chip package structure 600 (or the POP package constituted by the chip package structure 600) and the electronic device 1000 used therein.

[0105] The aforementioned first heat dissipation component 5 has multiple surfaces, referring to the outer surfaces of the first heat dissipation component 5. As shown in Figures 8 and 9, the first heat dissipation component 5 has a lower surface A1, an upper surface A2, and multiple side surfaces A3. The lower surface A1 faces the first chip 2, and the upper surface A2 faces away from the first chip 2. The multiple side surfaces A3 are connected end-to-end and connect the lower surface A1 and the upper surface A2. The number of side surfaces A3 is related to the shape of the first heat dissipation component 5. Figure 6 shows an example where the first heat dissipation component 5 is a cuboid; in this case, there are four side surfaces A3.

[0106] Referring again to Figures 8 and 9, after the first heat dissipation component 5 is connected to the first connecting portion 6, the lower surface A1 of the first heat dissipation component 5 is in direct contact with the first connecting portion 6. Furthermore, multiple sides A3 of the first heat dissipation component 5 are also in direct contact with the first connecting portion 6. Of course, the multiple sides A3 of the first heat dissipation component 5 can also be in direct contact with the encapsulation layer. Regarding the encapsulation layer, please refer to the relevant description below; it will not be repeated here.

[0107] Optionally, the roughness of at least one of the lower surface A1 and the plurality of side surfaces A3 is greater than the roughness of the upper surface A2. Here, "at least one of the lower surface A1 and the plurality of side surfaces A3" can mean, for example: only the lower surface A1 (as shown in Figure 9), only one side surface A3, only two side surfaces A3, only the lower surface A1 and one side surface A3, or the lower surface A1 and all the side surfaces A3 (as shown in Figure 8), etc. "Roughness" can mean, for example, the microscopic geometric characteristics of a surface composed of small spacing and minute peaks and valleys.

[0108] In other words, at the microscopic level, the upper surface A2 of the first heat dissipation component 5 is relatively flat (or has high flatness), while the lower surface A1 and at least one of the multiple side surfaces A3 are relatively rough (or have low flatness). In this embodiment, for example, the lower surface A1 and at least one of the multiple side surfaces A3 of the first heat dissipation component 5 can be treated by roughening (surface morphology as shown in Figure 8) or drilling (surface morphology as shown in Figure 9) to reduce flatness and increase roughness.

[0109] This increases the surface area of ​​the lower surface A1 and at least one of the multiple side surfaces A3 of the first heat dissipation component 5, thereby increasing the contact area between the first heat dissipation component 5 and the first connecting portion 6, and increasing the bonding force between them. When the first heat dissipation component 5 is in contact with the encapsulation layer, the contact area between them can also be increased, further enhancing the bonding force. This is beneficial for improving the structural stability of the chip package structure 600.

[0110] The structure of the first connection part 6 mentioned above includes various types, which can be selected and set according to actual needs to optimize the overall operability and reliability of the chip packaging structure 600.

[0111] In some embodiments, as shown in Figures 8 and 9, the first connecting portion 6 is a single-layer thin film structure.

[0112] In this case, the material of the first connecting part 6 includes, but is not limited to, adhesive, solder paste, etc. Where the material of the first connecting part 6 includes adhesive, the material of the first connecting part 6 includes, but is not limited to, DAF (die attach film) adhesive, silver paste with high thermal conductivity, etc.

[0113] For example, the first connecting part 6 can be a film formed of DAF glue or silver paste. Alternatively, the first connecting part 6 can be a thin film formed of solder paste.

[0114] In other embodiments, the first connection portion 6 is a structure composed of multiple thin film layers. As shown in FIG10, the first connection portion 6 includes a first connection layer 61 and a second connection layer 62, with the first connection layer 61 located between the first chip 2 and the second connection layer 62. That is, the first connection layer 61 connects the first chip 2 and the second connection layer 62, and the second connection layer 62 connects the first connection layer 61 and the first heat dissipation component 5. The thermal conductivity of the second connection layer 62 is greater than that of the first connection layer 61.

[0115] In this way, on the one hand, the second connection layer 62 can be used to accelerate the heat diffusion speed, so that the heat generated by the first chip 2 can be diffused upward through the first connection part 6 and the first heat dissipation component 5 more quickly, thereby improving the heat dissipation effect of the chip packaging structure 600; on the other hand, the second connection layer 62 can be used to enhance the bonding force between the first connection part 6 and the first heat dissipation component 5, thereby enhancing the bonding force between the first heat dissipation component 5 and the first chip 2, and improving the structural stability of the chip packaging structure 600.

[0116] Optionally, the material of the first connecting layer 61 includes, but is not limited to, DAF adhesive, silver paste with high thermal conductivity, solder paste, etc.; the material of the second connecting layer 62 includes, but is not limited to, metallic materials such as titanium (Ti) and copper (Cu).

[0117] For example, the first connecting layer 61 can be a film formed by DAF glue or silver glue, and the second connecting layer 62 can be a thermally conductive metal film formed by copper.

[0118] The chip packaging structure 600 provided in this application embodiment may also include other structures, which will be illustrated below with reference to the accompanying drawings.

[0119] In some embodiments, as shown in Figures 7 and 11, the chip package structure 600 further includes a package layer 10. At least a portion of the package layer 10 is located between the first substrate 1 and the second substrate 3. For example, as shown in Figure 7, the entire package layer 10 is located between the first substrate 1 and the second substrate 3. As another example, as shown in Figure 11, a portion of the package layer 10 is located between the first substrate 1 and the second substrate 3, and another portion is located on the side of the second substrate 3 away from the first substrate 1.

[0120] In the case where the chip packaging structure 600 also includes a second connection component 9, the second connection component 9 penetrates the packaging layer 10.

[0121] Referring again to Figures 7 and 11, the encapsulation layer 10 is in contact with the first substrate 1 and the second substrate 3. The encapsulation layer 10 also surrounds the first chip 2, the first connection portion 6, and the first heat dissipation component 5. The portion of the encapsulation layer 10 located within the opening K separates the first heat dissipation component 5 from the inner wall of the opening K. Furthermore, the surface of the encapsulation layer 10 away from the first substrate 1 is flush with the surface of the first heat dissipation component 5 away from the first substrate 1. That is, the encapsulation layer 10 does not cover the first heat dissipation component 5 and exposes the upper surface A2 of the first heat dissipation component 5. The term "flush" as used herein is not strictly flush; due to unavoidable process errors, any deviation within an acceptable range can be considered flush.

[0122] Optionally, the material of the encapsulation layer 10 includes, but is not limited to, encapsulation materials such as polyimide, silicone, and epoxy resin.

[0123] By providing the encapsulation layer 10, the connection stability between the first substrate 1 and the second substrate 3 can be enhanced, as can the connection stability between the first substrate 1, the first chip 2, the first connecting portion 6, and the first heat dissipation component 5. Furthermore, it can prevent interference with the heat dissipation of the first heat dissipation component 5 and thus the heat dissipation effect of the chip packaging structure 600.

[0124] Here, among the aforementioned possible methods, a molding compound with high thermal conductivity can be used to form the encapsulation layer to improve the heat dissipation of the HBPOP. However, due to the characteristics of the molding compound, its thermal conductivity is difficult to increase, thus hindering further improvement in the heat dissipation performance of the HBPOP.

[0125] In some embodiments of this application, by opening an opening K through the second substrate 3 and placing a first heat dissipation component 5 inside the opening K, the heat dissipation effect of the chip packaging structure 600 can be effectively improved without being limited by the characteristics of the molding compound.

[0126] In some examples, as shown in Figures 7 and 11, the chip package structure 600 further includes an underfill portion 11. This underfill portion 11 fills the space between the first substrate 1 and the first chip 2, and is in direct contact with both the first substrate 1 and the first chip 2. Furthermore, the underfill portion 11 surrounds each of the first connectors 7, spacing out adjacent first connectors 7.

[0127] Optionally, the material of the filler portion 11 may include, but is not limited to, epoxy resin.

[0128] The filling part 11 can enhance the connection stability between the first substrate 1 and the first chip 2, and also provide insulation protection for the first connector 7, so as to avoid short circuits between two adjacent first connectors 7.

[0129] It is understood that there are various ways to set the encapsulation layer 10, and correspondingly, there are various positional relationships between the first heat dissipation component 5 and the second substrate 3. This application embodiment does not limit these relationships, and the specific arrangement can be selected according to actual needs. The arrangement of the encapsulation layer 10 is related to the material of the first heat dissipation component 5.

[0130] In some embodiments, the material of the first heat dissipation component 5 includes a metallic material or a ceramic material. In this case, as shown in FIG7, the surface of the first heat dissipation component 5 away from the first substrate 1 is flush with the surface of the second substrate 3 away from the first substrate 1. Since the surface of the first heat dissipation component 5 away from the first substrate 1 is flush with the surface of the encapsulation layer 10 away from the first substrate 1, the surface of the second substrate 3 away from the first substrate 1 is also flush with the surface of the encapsulation layer 10 away from the first substrate 1.

[0131] Understandably, during the fabrication of the encapsulation layer 10, the molding compound may cover the first heat dissipation component 5. When the molding compound covers the first heat dissipation component 5, it is necessary to grind the molding compound to remove the portion covering it, exposing the upper surface A2 of the first heat dissipation component 5. The first heat dissipation component 5, made of materials such as metals or ceramics, has low brittleness. Therefore, during the grinding process to remove part of the molding compound, the first heat dissipation component 5 is less likely to crack.

[0132] In this configuration, the surfaces of the first heat dissipation component 5, the encapsulation layer 10, and the second substrate 3 that are away from the first substrate 1 can be flush. This ensures the integrity of the structure of the first heat dissipation component 5 while avoiding increasing the thickness of the chip package structure 600.

[0133] Of course, during the fabrication of the encapsulation layer 10, the molding material may not cover the first heat dissipation component 5. In this way, the encapsulation layer 10 formed is located on the side of the first substrate 1 away from the encapsulation layer 1, for example, slightly below the side of the first heat dissipation component 5 away from the first substrate 1.

[0134] Understandably, the second substrate 3 includes multiple metal trace layers and multiple dielectric layers, which are alternately stacked. A dielectric layer is disposed on each of the opposite sides of each metal trace layer. For example, a second via is formed in the dielectric layer between two adjacent metal trace layers, allowing the two adjacent metal trace layers to be electrically connected through the second via. When the second substrate 3 is a packaging substrate, it may further include a solder mask layer covering the aforementioned multiple metal trace layers and multiple dielectric layers. A third via is formed on the side of the solder mask layer closest to the second chip 4. A portion of the metal trace layer closest to the second chip 4 is exposed by the third via and forms the pads of the second substrate 3.

[0135] In some examples, continuing to refer to Figure 7, the chip package structure 600 further includes a first connection component 12. This first connection component 12 is located between the second substrate 3 and the second chip 4, and connects the pads of the second substrate 3 and the second chip 4. The second chip 4 can be connected (or soldered) to the second substrate 3 via the first connection component 12. For example, the first connection component 12 includes multiple solder balls. Of course, the structure of the first connection component 12 is not limited to this.

[0136] The first connecting component 12 and the pads of the second substrate 3 are in direct contact to form an electrical connection, without the need for other structures. This avoids increasing the thickness of the chip package structure 600, and avoids increasing the difficulty of fabrication and the complexity of the chip package structure 600.

[0137] In some embodiments, the material of the first heat dissipation component 5 includes silicon. In this case, as shown in FIG11, the surface of the first heat dissipation component 5 away from the first substrate 1 (i.e., the upper surface A2) is higher than the surface of the second substrate 3 away from the first substrate 1 relative to the first substrate 1. Since the surface of the first heat dissipation component 5 away from the first substrate 1 is flush with the surface of the encapsulation layer 10 away from the first substrate 1, the surface of the encapsulation layer 10 away from the first substrate 1 is also higher than the surface of the second substrate 3 away from the first substrate 1 relative to the first substrate 1. As shown in FIG11, a portion of the encapsulation layer 10 is also located on the side of the second substrate 3 away from the first substrate 1, covering the second substrate 3. The portion of the encapsulation layer 10 covering the second substrate 3 also surrounds the first heat dissipation component 5.

[0138] Understandably, the first heat dissipation component 5, including the silicon component, is highly brittle. Therefore, during the grinding process to remove part of the molding compound to form the encapsulation layer 10, the first heat dissipation component 5 is easily cracked.

[0139] In this case, a portion of the encapsulation material covering the second substrate 3 can be retained to protect the first heat dissipation component 5 and prevent damage to the first heat dissipation component 5 during the grinding process to form the encapsulation layer 10.

[0140] In some examples, where a portion of the encapsulation layer 10 covering the second substrate 3 is retained, this portion of the encapsulation layer 10 may cover the pads of the second substrate 3. Therefore, continuing to refer to FIG11, the chip package structure 600 further includes: solder pads 13 and a first connection assembly 12. For example, the material of the solder pads 13 includes tin; in this case, the solder pads 13 may also be referred to as solder bumps. Similarly, the first connection assembly 12 includes a plurality of solder balls. Of course, the structure of the first connection assembly 12 is not limited to this.

[0141] As shown in Figure 11, there are multiple solder pads 13. Each solder pad 13 is located between the second substrate 3 and the second chip 4, and also penetrates the portion of the encapsulation layer 10 on the side of the second substrate 3 away from the first substrate 1, and is electrically connected to the pads of the second substrate 3. Each solder pad 13 is provided in a one-to-one correspondence with the pads of the second substrate 3, and each solder pad 13 is in direct contact with the corresponding pad in the second substrate 3. For example, the surface of each solder pad 13 away from the first substrate 1 is flush with the surface of the encapsulation layer 10 away from the first substrate 1. The encapsulation layer 10 does not cover the solder pads 13.

[0142] As shown in Figure 11, the first connecting component 12 is located between the solder pad 13 and the second chip 4, and connects the solder pad 13 and the second chip 4. Taking the first connecting component 12 as an example, which includes multiple solder balls, the multiple solder balls and the multiple solder pads 13 are arranged in a one-to-one correspondence. At this time, the second chip 4 can be connected (or soldered) to the second substrate 3 in sequence through the first connecting component 12 and the solder pads 13.

[0143] This allows for signal transmission between the second chip 4 and the second substrate 3 while protecting the first heat dissipation component 5.

[0144] The chip packaging structure 600 provided in this application embodiment may also include other structures, which will be illustrated below with reference to the accompanying drawings.

[0145] In some embodiments, as shown in FIG12, the chip package structure 600 further includes a second heat dissipation component 14 and a second connection portion 15. The second heat dissipation component 14 is located on the side of the first heat dissipation component 5 away from the first substrate 1. The second connection portion 15 is located between the first heat dissipation component 5 and the second heat dissipation component 14, and connects the first heat dissipation component 5 and the second heat dissipation component 14.

[0146] The orthographic projection of the second heat dissipation component 14 on the first substrate 1 at least partially overlaps with the orthographic projection of the first heat dissipation component 5 on the first substrate 1. Furthermore, the second heat dissipation component 14 is spaced apart from the second chip 4, and the second heat dissipation component 14 and the second chip 4 do not directly contact each other. The orthographic projection of the second heat dissipation component 14 on the first substrate 1 is located within the orthographic projection range of the second chip 4 on the first substrate 1; or, the orthographic projection of the second heat dissipation component 14 on the first substrate 1 partially overlaps with the orthographic projection of the second chip 4 on the first substrate 1; the specific arrangement can be selected according to the arrangement of the first connecting component 12. The number of second heat dissipation components 14 can be one or more, and this embodiment does not limit this. The relative positional relationship between the second heat dissipation component 14 and the opening K in the second substrate 3 can be selected according to actual needs.

[0147] Here, the second heat dissipation component 14 has a high thermal conductivity, and the material of the second heat dissipation component 14 includes materials with high thermal conductivity. Optionally, the material of the second heat dissipation component 14 includes, but is not limited to, silicon, metal materials, ceramic materials, etc.

[0148] By connecting the second heat dissipation component 14 to the first heat dissipation component 5, the overall heat capacity of the chip packaging structure 600 can be further improved, and the heat dissipation effect of the chip packaging structure 600 can be further improved.

[0149] In some examples, the material of the second heat dissipation component 14 is the same as that of the first heat dissipation component 5. And / or, the structure of the second heat dissipation component 14 is the same as that of the first heat dissipation component 5.

[0150] Optionally, if the material of the second heat sink 14 is the same as that of the first heat sink 5, the materials of the second heat sink 14 and the first heat sink 5 may both include metal, ceramic, or silicon. This allows the second heat sink 14 and the first heat sink 5 to be fabricated simultaneously, which simplifies the fabrication process of the chip package structure 600.

[0151] Optionally, when the structure of the second heat sink 14 is the same as that of the first heat sink 5, the outer surfaces of the first heat sink 5 and the second heat sink 14 in the same orientation (e.g., the lower surface A1 of the first heat sink 5 and the lower surface of the second heat sink 14) are both roughened or hollowed out, and their roughness is the same or approximately the same. This allows for simultaneous roughening or hollowing out of the outer surfaces of the second heat sink 14 and the first heat sink 5 in the same orientation, which can simultaneously enhance the bonding force between the second heat sink 14 and the first heat sink 5, and between the first heat sink 5 and the first chip 2, and also simplify the fabrication process of the chip packaging structure 600.

[0152] In some examples, the material of the second connecting portion 15 is the same as the material of the first connecting portion 6. And / or, the structure of the second connecting portion 15 is the same as the structure of the first connecting portion 6.

[0153] Optionally, if the material of the second connecting part 15 is the same as the material of the first connecting part 6, the materials of the second connecting part 15 and the first connecting part 6 may both be DAF glue, silver paste, or solder paste.

[0154] Optionally, if the structure of the second connecting portion 15 is the same as that of the first connecting portion 6, both the second connecting portion 15 and the first connecting portion 6 may be single-layer structures or multi-layer thin film stacked structures. This allows the second connecting portion 15 and the first connecting portion 6 to be fabricated simultaneously, which simplifies the fabrication process of the chip packaging structure 600.

[0155] In some embodiments, as shown in FIG13, the chip package structure 600 further includes a thermally conductive adhesive layer 16. The thermally conductive adhesive layer 16 is located between the second substrate 3 and the second chip 4, and connects the second substrate 3, the first heat dissipation component 5, and the second chip 4.

[0156] The aforementioned thermally conductive adhesive layer 16 can also be referred to as a filler adhesive layer. The thermally conductive adhesive layer 16 can directly contact the second substrate 3 and the second chip 4 to enhance the connection stability between the second substrate 3 and the second chip 4. Optionally, the orthographic projection of the thermally conductive adhesive layer 16 on the first substrate 1 and the orthographic projection of the second chip 4 on the first substrate 1 at least partially overlap.

[0157] When the chip package structure 600 does not have a second heat dissipation component 14 and a second connecting portion 15, as shown in FIG13, the thermally conductive adhesive layer 16 can be directly connected (or in direct contact) to the surface of the first heat dissipation component 5 away from the first substrate 1. When the chip package structure 600 includes a second heat dissipation component 14 and a second connecting portion 15, depending on the different positional relationships between the second heat dissipation component 14 and the first heat dissipation component 5, the thermally conductive adhesive layer 16 can be directly connected to the surface of the first heat dissipation component 5 away from the first substrate 1, or the thermally conductive adhesive layer 16 can be directly connected to the surface of the second heat dissipation component 14 away from the first substrate 1, thereby indirectly connecting to the first heat dissipation component 5 through the second heat dissipation component 14.

[0158] The aforementioned thermally conductive adhesive layer 16 exhibits good thermal conductivity. Optionally, the material of the thermally conductive adhesive layer 16 may include an adhesive with high thermal conductivity, which can be selected and configured according to actual needs. The thermally conductive adhesive layer 16 can be formed between the second substrate 3 and the second chip 4 through processes such as filling and curing.

[0159] In this way, as the heat generated by the first chip 2 diffuses upward through the opening K in the second substrate 3, some of the heat that diffuses through the space between the second substrate 3 and the second chip 4 can be conducted relatively quickly through the thermally conductive adhesive layer 16, which is beneficial to enhance lateral heat dissipation and further improve the heat dissipation effect of the chip packaging structure 600.

[0160] Some embodiments of this application also provide a method for fabricating a chip package structure, which is used, for example, to fabricate the chip package structure 600 in some of the above embodiments. Figures 14 and 15 illustrate flowcharts of a method for fabricating a chip package structure; Figures 16-22 illustrate structural diagrams corresponding to each step in the method for fabricating a chip package structure; and Figures 18a(a) and (b) and 18b(a) and (b) respectively illustrate structures corresponding to different sequences of steps in the method for fabricating a chip package structure. It should be understood that the steps shown in Figures 14 and 15 are not exclusive, and other steps may be performed before, after, or between any of the steps shown in Figures 14 and 15. Furthermore, some steps may be performed simultaneously or in a sequence different from that shown in Figures 14 and 15.

[0161] The fabrication method of the chip packaging structure is illustrated below with reference to the accompanying drawings. As shown in Figures 14 and 15, the fabrication method includes steps S100-S300.

[0162] S100, as shown in Figure 16, connects the first chip 2 to one side of the first substrate 1.

[0163] For example, the first chip 2 is a chip that has been ground and patterned. Before connecting the first substrate 1 and the first chip 2, a first connector 7 can be provided on the first substrate 1; then the first chip 2 is mounted on the first substrate 1; and then a reflow soldering process can be used to connect the first substrate 1 and the first chip 2.

[0164] For example, referring to Figures 16 and 17, after connecting the first chip 2, a material such as glue can be filled between the first substrate 1 and the first chip 2 to form a filling portion 11, so as to fix the first chip 2 on the first substrate 1 using the filling portion 11. The filling portion 11 can also form an insulating protection for the first connector 7, preventing short circuits between two adjacent first connectors 7.

[0165] S200, as shown in Figure 18a(b) and Figure 18b(a), a second substrate 3 is disposed on the side of the first chip 2 away from the first substrate 1, and the second substrate 3 is connected to the first substrate 1. An opening K is formed in the second substrate 3, penetrating the second substrate 3. The orthographic projection of the opening K onto the first substrate 1 at least partially overlaps with the orthographic projection of the first chip 2 onto the first substrate 1.

[0166] For example, before the second substrate 3 is disposed on the side of the first chip 2 away from the first substrate 1, balls can be placed on the wafer where the second substrate 3 is located to form the second connection component 9; then the wafer where the second substrate 3 is located is cut to obtain a single second substrate 3; then the second substrate 3 with the second connection component 9 connected can be soldered to the first substrate 1.

[0167] Here, after the second substrate 3 is soldered onto the first substrate 1, the second substrate 3 and the first chip 2 are spaced apart, and the opening K in the second substrate 3 is located directly above the first chip 2, exposing at least a portion of the first chip 2. The area of ​​the first chip 2 exposed by the opening K can be selected according to the actual heat dissipation requirements and the wiring of the second substrate 3, and this embodiment does not limit this.

[0168] S300, as shown in Figure 22, connects the second chip 4 to the side of the second substrate 3 away from the first substrate 1.

[0169] For example, the second chip 4 is a chip that has been ground and polished. Before connecting the second chip 4 to the second substrate 3, a first connection component 12 can be provided on the second substrate 3 or the second chip 4; then the second chip 4 is attached to the side of the second substrate 3 away from the first substrate 1 to realize the electrical connection between the second chip 4 and the second substrate 3.

[0170] Optionally, referring to Figures 22 and 13, after connecting the second chip 4, a high thermal conductivity adhesive material can be filled between the second substrate 3 and the second chip 4, and then the adhesive material can be cured to form a thermally conductive adhesive layer 16. For details regarding the thermally conductive adhesive layer 16, please refer to the relevant description above; it will not be repeated here.

[0171] In some examples, as shown in Figures 14 and 15, the above preparation method also includes: S400.

[0172] As shown in Figure 18a(a) and Figure 18b(b), in S400, a first connecting part 6 and a first heat dissipation component 5 are sequentially arranged on the side of the first chip 2 away from the first substrate 1, and the first heat dissipation component 5 is located inside the opening K.

[0173] It is understood that the first connecting part 6 and the first heat dissipation component 5 can be disposed before S200; or, the first connecting part 6 and the first heat dissipation component 5 can be disposed after S200. The following is a schematic description with reference to the accompanying drawings.

[0174] Optionally, as shown in FIG14, the first connecting part 6 and the first heat dissipation component 5 are disposed before S200.

[0175] Specifically, referring to (a) and (b) of Figure 18a, before connecting the second substrate 3, a first connecting portion 6 and a first heat dissipation component 5 are sequentially arranged on the side of the first chip 2 away from the first substrate 1. After connecting the second substrate 3, the first heat dissipation component 5 is located inside the opening K.

[0176] For example, in the embodiments of this application, relevant equipment can be used to first coat the surface of the first chip 2 away from the first substrate 1 with a connecting material (including but not limited to DAF glue, silver paste, solder paste, etc.); then, relevant equipment can be used to attach the first heat dissipation component 5 to the connecting material; then, the connecting material can be cured to form the first connecting part 6, thereby fixing the first heat dissipation component 5 and thus realizing the connection between the first heat dissipation component 5 and the first chip 2.

[0177] The position of the first heat dissipation component 5 on the first chip 2 corresponds to the position of the opening K in the second substrate 3 that is subsequently connected. This ensures that the first heat dissipation component 5 is located within the opening K in the second substrate 3 that is subsequently connected.

[0178] Optionally, as shown in FIG15, the first connecting part 6 and the first heat dissipation component 5 are disposed after S200.

[0179] Specifically, referring to (a) and (b) in Figure 18b, a first connection portion 6 and a first heat dissipation component 5 are sequentially formed on the side of the first chip 2 away from the first substrate 1 through the opening K, and the first heat dissipation component 5 is located inside the opening K.

[0180] For example, the method of forming the first connecting part 6 and the first heat dissipation component 5 can be referred to the relevant description in the above embodiments, and will not be repeated here.

[0181] The materials used for the first heat dissipation component 5 include various types, such as silicon (Si), metallic materials, and ceramic materials. When the material of the first heat dissipation component 5 is silicon, it can be referred to as a silicon wafer. When the material of the first heat dissipation component 5 is copper, it can be referred to as a copper wafer.

[0182] The chip packaging structure fabrication method provided in some embodiments of this application, by opening an opening K in the second substrate 3 and positioning the opening K above the first chip 2, can break the limitation of the second substrate 3 on the upward heat dissipation path of the first chip 2. This can enhance upward heat dissipation, improve the problem of poor heat dissipation caused by the difficulty of heat dissipation through the second substrate 3 quickly, thereby enhancing the heat dissipation effect and improving heat dissipation performance.

[0183] Furthermore, the above-described fabrication method, by connecting the first heat dissipation component 5 to the side of the first chip 2 away from the first substrate 1 and positioning the first heat dissipation component 5 within the opening K, can effectively increase the overall heat capacity of the fabricated chip package structure 600 and accelerate the upward heat dissipation rate of the first chip 2. This can significantly improve the heat dissipation effect of the fabricated chip package structure 600 and the electronic device 1000 to which it is applied.

[0184] In some embodiments, the first heat dissipation component 5 has a lower surface A1, an upper surface A2, and a plurality of side surfaces A3. The arrangement and connection relationship of the lower surface A1, upper surface A2, and side surfaces A3, as well as the roughness mentioned below, can be found in the relevant descriptions above, and will not be repeated here.

[0185] For example, prior to S400, the preparation method further includes: processing at least one of the lower surface A1 and the plurality of side surfaces A3 of the first heat dissipation component 5 to increase its roughness. In this case, the roughness of the processed surface (e.g., the lower surface A1) is greater than the roughness of the unprocessed surface (e.g., the upper surface A2).

[0186] The phrase "at least one of the lower surface A1 and multiple sides A3" can mean, for example, only the lower surface A1 (as shown in Figure 9), only one side A3, only two sides A3, only the lower surface A1 and one side A3, or the lower surface A1 and all the sides A3 (as shown in Figure 8), etc.

[0187] Optionally, in this embodiment of the application, at least one of the lower surface A1 and multiple side surfaces A3 of the first heat dissipation component 5 can be processed by roughening (surface morphology as shown in Figure 8) and drilling (surface morphology as shown in Figure 9) to reduce flatness and increase roughness.

[0188] After the first heat dissipation component 5 is attached to the first connecting part 6, a portion of the first connecting part 6 will fill the recesses of the treated surfaces in the lower surface A1 and multiple side surfaces A3, increasing the contact area between the first connecting part 6 and the first heat dissipation component 5, and increasing the bonding force between the first heat dissipation component 5 and the first connecting part 6.

[0189] Furthermore, if the side surface A3 of the first heat dissipation component 5 is processed and the side surface A3 is in contact with the subsequently formed encapsulation layer 10, the contact area between the first heat dissipation component 5 and the encapsulation layer 10 can be increased, thereby increasing the bonding force between the first heat dissipation component 5 and the encapsulation layer 10.

[0190] It is understandable that the first connecting part 6 can be a single-layer thin film structure or a structure composed of multiple layers of thin films.

[0191] When the first connection portion 6 is a structure composed of multiple thin film layers, as shown in FIG18a(a), in the above S400, the provision of the first connection portion 6 includes: forming a first connection layer 61 on the side of the first chip 2 away from the first substrate 1; and forming a second connection layer 62 on the side of the first connection layer 61 away from the first substrate 1. The thermal conductivity of the second connection layer 62 is greater than that of the first connection layer 61.

[0192] Regarding the materials and structures of the first connecting layer 61 and the second connecting layer 62, please refer to the relevant descriptions above, which will not be repeated here.

[0193] By setting the first connection layer 61 and the second connection layer 62, the second connection layer 62 can be used to accelerate the heat diffusion rate and improve the heat dissipation effect of the chip package structure 600; the second connection layer 62 can also be used to enhance the bonding force between the first connection part 6 and the first heat dissipation component 5.

[0194] In some embodiments, before S300, that is, before the second chip 4 is connected to the side of the second substrate 3 away from the first substrate 1, the above preparation method further includes: S290.

[0195] S290, as shown in Figures 19 and 20b, an encapsulation layer 10 is formed at least between the first substrate 1 and the second substrate 3. The encapsulation layer 10 surrounds the first chip 2, the first connection portion 6, and the first heat dissipation component 5. Furthermore, the surface of the encapsulation layer 10 away from the first substrate 1 is flush with the surface of the first heat dissipation component 5 away from the first substrate 1.

[0196] For example, the encapsulation layer 10 can be formed by injection molding, grinding, or other processes in the embodiments of this application. After the encapsulation layer 10 is formed, for example, related printing can be performed. Then, as shown in FIG21, balls are placed on the surface of the first substrate 1 away from the first chip 2 to form the second connector 8. Afterwards, the first substrate 1 can be cut.

[0197] By forming the encapsulation layer 10, the connection stability between the first substrate 1 and the second substrate 3 can be enhanced, as can the connection stability between the first substrate 1, the first chip 2, the first connection portion 6, and the first heat dissipation component 5. Furthermore, it can prevent interference with the heat dissipation of the first heat dissipation component 5 and thus the heat dissipation effect of the chip package structure 600.

[0198] Understandably, based on the material of the first heat dissipation component 5, the encapsulation layer 10 can be arranged differently on the side surface away from the first substrate 1 and on the side surface of the second substrate 3 away from the first substrate 1.

[0199] Optionally, as shown in FIG19, when the material of the first heat dissipation component 5 includes a metal material or a ceramic material, the surface of the first heat dissipation component 5 away from the first substrate 1 is flush with the surface of the second substrate 3 away from the substrate 1. Correspondingly, after grinding the molding compound to form the encapsulation layer 10, the surface of the encapsulation layer 10 away from the first substrate 1 is flush with the surface of the second substrate 3 away from the first substrate 1. The encapsulation layer 10 does not cover the second substrate 3.

[0200] Optionally, as shown in FIG20b, when the material of the first heat dissipation component 5 includes silicon, the surface of the first heat dissipation component 5 away from the first substrate 1 is higher than the surface of the second substrate 3 away from the first substrate 1 relative to the first substrate 1. Correspondingly, after the molding compound is polished to form the encapsulation layer 10, the surface of the encapsulation layer 10 away from the first substrate 1 is higher than the surface of the second substrate 3 away from the first substrate 1. As shown in FIG20b, a portion of the encapsulation layer 10 is also located on the side of the second substrate 3 away from the first substrate 1, covering the second substrate 3.

[0201] In this case, the encapsulation layer 10 will cover the pads of the second substrate 3. Based on this, as shown in Figures 20a and 20b, before S290 above, the above preparation method further includes forming a solder pad 13 on the pads of the second substrate 3 on the side away from the first substrate 1.

[0202] For example, solder pads 13 can be formed on each pad of the second substrate 3 by stencil printing.

[0203] Furthermore, the above S290 includes: S291-S292.

[0204] S291, as shown in FIG20a, an encapsulation film 10a is formed between the first substrate 1 and the second substrate 3 and on the side of the second substrate 3 away from the first substrate 1. The encapsulation film 10a covers the solder pad 13 and the first heat dissipation component 5.

[0205] For example, in embodiments of this application, an encapsulation film 10a can be formed by filling with encapsulation material.

[0206] S292, referring to Figures 20a and 20b, the encapsulation film 10a is ground to expose the solder pad 13 and the first heat dissipation component 5.

[0207] That is, while grinding the molding compound and exposing the surface of the first heat dissipation component 5 away from the first substrate 1, the solder pad 13 is also exposed. The solder pad 13 is used to connect with the first connection component 12, thereby realizing the connection between the second substrate 3 and the second chip 4.

[0208] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed herein should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A chip packaging structure, characterized in that, The chip packaging structure includes: First substrate; The first chip is located on one side of the first substrate and is electrically connected to the first substrate; The second substrate is located on the side of the first chip away from the first substrate and is electrically connected to the first substrate; the second substrate has an opening that penetrates the second substrate; the orthographic projection of the opening on the first substrate and the orthographic projection of the first chip on the first substrate at least partially overlap. The first heat dissipation component is located inside the opening; A first connecting portion is located between the first chip and the first heat dissipation component; the first connecting portion connects the first chip and the first heat dissipation component. The second chip is located on the side of the second substrate away from the first substrate and is electrically connected to the second substrate; the second chip covers the opening.

2. The chip packaging structure according to claim 1, characterized in that, The first heat dissipation component has a lower surface, an upper surface, and multiple side surfaces. The lower surface is opposite to the first chip, the upper surface is opposite to the first chip, and the multiple side surfaces are connected end to end and connect the lower surface and the upper surface. The roughness of at least one of the lower surface and the plurality of side surfaces is greater than the roughness of the upper surface.

3. The chip packaging structure according to claim 1 or 2, characterized in that, The first connection portion includes a first connection layer and a second connection layer, wherein the first connection layer is located between the first chip and the second connection layer; The thermal conductivity of the second connecting layer is greater than that of the first connecting layer.

4. The chip packaging structure according to any one of claims 1-3, characterized in that, The chip packaging structure also includes a packaging layer; At least a portion of the encapsulation layer is located between the first substrate and the second substrate, and surrounds the first chip, the first connection portion and the first heat dissipation component; The surface of the encapsulation layer away from the first substrate is flush with the surface of the first heat dissipation component away from the first substrate.

5. The chip packaging structure according to claim 4, characterized in that, The material of the first heat dissipation component includes metal or ceramic materials; The surface of the first heat dissipation component away from the first substrate is flush with the surface of the second substrate away from the first substrate.

6. The chip packaging structure according to claim 5, characterized in that, The chip packaging structure also includes a first connection component; The first connection component is located between the second substrate and the second chip, and connects the pads of the second substrate and the second chip.

7. The chip packaging structure according to claim 4, characterized in that, The material of the first heat dissipation component includes silicon; Relative to the first substrate, the surface of the first heat dissipation component away from the first substrate is higher than the surface of the second substrate away from the first substrate; A portion of the encapsulation layer is also located on the side of the second substrate away from the first substrate, covering the second substrate.

8. The chip packaging structure according to claim 7, characterized in that, The chip packaging structure also includes: A solder pad is located between the second substrate and the second chip; the solder pad penetrates the portion of the encapsulation layer on the side of the second substrate away from the first substrate and is electrically connected to the pads of the second substrate; A first connection component is located between the solder pad and the second chip, and connects the solder pad and the second chip.

9. The chip packaging structure according to any one of claims 1-8, characterized in that, The chip packaging structure also includes: The second heat dissipation component is located on the side of the first heat dissipation component away from the first substrate; the second heat dissipation component is spaced apart from the second chip; The second connecting part is located between the first heat dissipation component and the second heat dissipation component; the second connecting part connects the first heat dissipation component and the second heat dissipation component.

10. The chip packaging structure according to claim 9, characterized in that, The material of the second heat dissipation component is the same as that of the first heat dissipation component; and / or, the structure of the second heat dissipation component is the same as that of the first heat dissipation component.

11. The chip packaging structure according to claim 10, characterized in that, The material of the second connecting part is the same as that of the first connecting part; and / or, the structure of the second connecting part is the same as that of the first connecting part.

12. The chip packaging structure according to any one of claims 1-11, characterized in that, The material of the first connection part includes adhesive and solder paste.

13. The chip packaging structure according to any one of claims 1-12, characterized in that, The chip packaging structure further includes a second connection component located between the first substrate and the second substrate, the second connection component being electrically connected to the first substrate and the second substrate respectively; The orthographic projection of the second connection component on the first substrate and the orthographic projection of the first chip on the first substrate do not overlap.

14. The chip packaging structure according to any one of claims 1-13, characterized in that, The chip packaging structure further includes a thermally conductive adhesive layer located between the second substrate and the second chip, the thermally conductive adhesive layer connecting the second substrate, the first heat dissipation component and the second chip.

15. A method for fabricating a chip packaging structure, characterized in that, The preparation method includes: The first chip is connected to one side of the first substrate; A second substrate is disposed on the side of the first chip away from the first substrate, and the second substrate is connected to the first substrate; an opening is formed in the second substrate, and the opening penetrates the second substrate; the orthographic projection of the opening on the first substrate and the orthographic projection of the first chip on the first substrate at least partially overlap. A first connecting portion and a first heat dissipation component are sequentially disposed on the side of the first chip away from the first substrate, and the first heat dissipation component is located inside the opening; A second chip is connected to the side of the second substrate away from the first substrate.

16. The preparation method according to claim 15, characterized in that, The first connecting portion and the first heat dissipation component are disposed before the second substrate is disposed on the side of the first chip away from the first substrate.

17. The preparation method according to claim 15, characterized in that, The first connecting portion and the first heat dissipation component are disposed after the second substrate is disposed on the side of the first chip away from the first substrate.

18. The preparation method according to any one of claims 15-17, characterized in that, The first heat dissipation component has a lower surface, an upper surface, and multiple side surfaces. The lower surface is opposite to the first chip, the upper surface is opposite to the first chip, and the multiple side surfaces are connected end to end and connect the lower surface and the upper surface. The preparation method further includes: Before sequentially arranging the first connecting portion and the first heat dissipation component on the side of the first chip away from the first substrate, the lower surface and at least one of the plurality of side surfaces are processed to increase the roughness.

19. The preparation method according to any one of claims 15-18, characterized in that, The first connecting part includes: A first interconnect layer is formed on the side of the first chip away from the first substrate; A second connection layer is formed on the side of the first connection layer away from the first substrate; the thermal conductivity of the second connection layer is greater than that of the first connection layer.

20. The preparation method according to any one of claims 15-19, characterized in that, Before connecting the second chip to the side of the second substrate away from the first substrate, the fabrication method further includes: An encapsulation layer is formed at least between the first substrate and the second substrate; the encapsulation layer surrounds the first chip, the first connection portion and the first heat dissipation component, and the surface of the encapsulation layer away from the first substrate is flush with the surface of the first heat dissipation component away from the first substrate.

21. The preparation method according to claim 20, characterized in that, The material of the first heat dissipation component includes silicon; relative to the first substrate, the side surface of the first heat dissipation component away from the first substrate is higher than the side surface of the second substrate away from the first substrate. Before forming the encapsulation layer at least between the first substrate and the second substrate, the fabrication method further includes: A solder pad is formed on the pad on the side of the second substrate away from the first substrate; The formation of an encapsulation layer at least between the first substrate and the second substrate includes: An encapsulation film is formed between the first substrate and the second substrate, and on the side of the second substrate away from the first substrate, the encapsulation film covering the solder pad and the first heat dissipation component; The encapsulation film is ground to expose the solder pad and the first heat dissipation component.

22. An electronic device, characterized in that, The electronic device includes: The chip packaging structure as described in any one of claims 1-14, The circuit board is electrically connected to the chip package structure.

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