A variable resistance circuit based on dual memristors

Abstract

The present invention discloses a variable resistor circuit based on a dual memristor, belonging to the technical field of variable resistors. It includes a control signal input circuit, a resistance adjustment circuit and a resistance output circuit; the control signal input circuit is connected to the resistance adjustment circuit, and is used to input the control signal into the resistance adjustment circuit to adjust the resistance of the resistance adjustment circuit, and the output of the resistance adjustment circuit is connected to the resistance output circuit to output the resistance. The device prepared by the present invention has an extremely small size and is suitable for large-scale integration; it is compatible with CMOS technology, and the circuit design is simple and easy, which greatly improves the utilization rate, reproducibility and innovation. Through the variable load controlled by the computer, it is more flexible, controllable, stable and efficient, and realizes multi-scenario control of the circuit.

Description

Technical Field

[0001] The present invention belongs to the technical field of variable resistors, and in particular relates to a variable resistor circuit based on a dual memristor. Background Art

[0002] Variable resistors are widely used in electronic circuits and play an important role in circuit regulation measures such as current limiting, current shunting and voltage division. With the continuous development of microelectronic systems, the miniaturization and integration of electronic components have become an urgent need. Common variable resistor devices on the market now, such as mechanical variable resistors and magnetron fluid resistors, have the defects of large size, high power consumption, high production cost, and inconvenient integration and automatic control. At the same time, during the use process, the resistance change action is easy to affect the external circuit, resulting in reduced stability of the entire circuit. Summary of the invention

[0003] In order to overcome the shortcomings of the above-mentioned prior art, the purpose of the present invention is to provide a variable resistance circuit based on dual memristors to solve the technical defects of the existing variable memory that is large in size, not convenient for large-scale integration and not convenient for automatic control, and to avoid the technical problem of the impact on external circuits during resistance change action.

[0004] In order to achieve the above object, the present invention adopts the following technical solutions:

[0005] The invention discloses a dual-memristor-based variable resistor circuit, comprising a control signal input circuit, a resistance adjustment circuit, and a resistance output circuit. The control signal input circuit is connected to the resistance adjustment circuit, and is used to input a control signal into the resistance adjustment circuit to adjust the resistance of the memristor element; the resistance adjustment circuit is composed of two parallel control units, and one control unit includes a memristor element and its unit adjustment circuit; the resistance adjustment circuit is connected to the resistance output circuit.

[0006] Furthermore, the control signal input circuit includes a first input terminal, a second input terminal, a ground terminal and a Control control terminal. The first input terminal and the second input terminal are control signal pulse access ports, the Control control terminal is a control high and low level signal access port, and the ground terminal is a ground access port. The first input terminal, the second input terminal, the Control control terminal and the ground terminal are respectively connected to the resistance adjustment circuit through MOS tubes.

[0007] Furthermore, the first input terminal, the second input terminal, the ground terminal and the Control terminal are respectively connected to the control computer.

[0008] Furthermore, the gates of the first N-type MOS tube, the second N-type MOS tube, the first P-type MOS tube, and the second P-type MOS tube are commonly connected to the Control terminal, and their drains are respectively connected to the anodes of the first, second, third, and fourth diodes in the resistance adjustment circuit.

[0009] Further, the sources of the first N-type MOS transistor and the first P-type MOS transistor are commonly connected to the first input terminal, and the sources of the second N-type MOS transistor and the second P-type MOS transistor are commonly connected to the second input terminal.

[0010] Specifically, the resistance adjustment circuit mainly includes two control units composed of two memristor elements connected in parallel, and each control unit is connected to the first input terminal, the second input terminal, the Control terminal and the ground terminal through a MOS tube and a diode.

[0011] Furthermore, each control unit includes two branches, each branch is composed of a diode and a MOS tube, and is connected in series with a memristor device; the first and second input terminals are respectively divided into two paths, and one path of each terminal is connected to the same control unit.

[0012] Furthermore, in the left control unit circuit, the first input terminal is divided into two paths, one of which is connected to the source of the first N-type MOS tube, and the drain of the first N-type MOS tube is connected to the positive electrode of the first diode; the cathode of the first diode is connected to the gate of the fifth N-type MOS tube, one end of the first memristor element and the drain of the sixth N-type MOS tube; the second input terminal is divided into two paths, one of which is connected to the source of the second N-type MOS tube, and the drain of the second N-type MOS tube is connected to the positive electrode of the second diode; the cathode of the second diode is connected to the gate of the sixth N-type MOS tube, the other end of the first memristor element and the drain of the fifth N-type MOS tube; the above together constitute the first control unit.

[0013] Furthermore, in the right-side control unit circuit, one of the two paths divided by the first input terminal is different from the one connected to the first control unit, connected to the source of the first P-type MOS tube, and the drain of the first P-type MOS tube is connected to the anode of the third diode; the cathode of the third diode is connected to the gate of the third N-type MOS tube, one end of the second memristor element, and the drain of the fourth N-type MOS tube; one of the two paths divided by the second input terminal is different from the one connected to the first control unit, connected to the source of the second P-type MOS tube, and the drain of the second P-type MOS tube is connected to the anode of the fourth diode; the cathode of the fourth diode is connected to the gate of the fourth N-type MOS tube, the other end of the second memristor element, and the drain of the third N-type MOS tube; the above together constitute the second control unit.

[0014] Furthermore, sources of the third N-type MOS transistor, the fourth N-type MOS transistor, the fifth N-type MOS transistor and the sixth N-type MOS transistor are connected to a common ground.

[0015] Furthermore, the resistance output circuit is used for outputting resistance, one end of each memristor element is connected to the first output terminal through a MOS tube, and the other end is connected to the second output terminal through a MOS tube, and the two memristor elements form a parallel relationship; the resistance output circuit as a whole is coupled to the external circuit in series;

[0016] Furthermore, one end of the first memristor element is connected to the source of the third P-type MOS tube, and the drain of the third P-type MOS tube is connected to the first output terminal, and the other end is connected to the source of the fourth P-type MOS tube, and the drain of the fourth P-type MOS tube is connected to the second output terminal; one end of the second memristor element is connected to the source of the seventh N-type MOS tube, and the drain of the seventh N-type MOS tube is connected to the first output terminal, and the other end is connected to the source of the eighth N-type MOS tube, and the drain of the eighth N-type MOS is connected to the second output terminal.

[0017] Furthermore, the gates of the third P-type MOS transistor, the fourth P-type MOS transistor, the seventh N-type MOS transistor and the eighth N-type MOS transistor are respectively connected to the Control terminal.

[0018] Compared with the prior art, the present invention has the following beneficial effects:

[0019] The present invention discloses a variable resistor circuit based on dual memristors, which is connected to a resistance adjustment circuit through a control signal input circuit, and is used to input a control signal into the resistance adjustment circuit to adjust the resistance of a memristor element; the resistance adjustment circuit is composed of two parallel memristor control units; the resistance adjustment circuit is connected to a resistance output circuit to achieve resistance output; the circuit is supplemented by a MOS tube and a diode, and has the advantages of small size, convenience for large-scale integration, simple circuit design, compatibility with CMOS technology, more flexible controllability, stability and efficiency. Compared with traditional variable resistors, the present invention realizes small size, more portability, compatibility with CMOS technology, and is convenient for automation and integration. Compared with the variable resistor circuit of a single memristor, it effectively overcomes the influence of an external circuit, is safer, more intuitive, accurate, and stable, and has broad market application prospects.

[0020] Furthermore, the control signal input terminal can be connected to an external device, such as a control computer. By connecting the control signal sent by the control device to the resistance adjustment circuit, the circuit resistance can be adjusted and controlled. The control signal sent by the control computer is connected to the resistance adjustment circuit via the control signal input circuit, which can realize automatic control of the resistance. Furthermore, the resistance adjustment circuit is based on the resistance change mechanism of the memristor, and its switching action time reaches the nanosecond level, with low latency, and can adjust the circuit resistance in a very short time, ensuring the stability of the external circuit.

[0021] Further, the sources of the third N-type MOS tube, the fourth N-type MOS tube, the fifth N-type MOS tube and the sixth N-type MOS tube are respectively connected to the ground terminal signal line of the control signal input circuit, and the drains of the third N-type MOS tube and the fourth N-type MOS tube are respectively connected to one end of the second memristor element different from that to which their gates are connected; the fifth N-type MOS tube and the sixth N-type MOS tube are respectively connected to one end of the first memristor element different from that to which their gates are connected. The purpose is that, taking the left control unit as an example, when the control signal pulse passes through the first memristor element in the forward direction, the drain and source of the sixth N-type MOS tube are turned on at the same time, and the source of the sixth N-type MOS tube is directly connected to the ground terminal, so that the pulse signal passing through the memristor element directly flows into the ground terminal instead of flowing into the external circuit, so that the control signal will not be superimposed on the external circuit while changing the resistance value, thereby ensuring the stability and safety of the circuit.

[0022] Furthermore, in the resistance adjustment circuit, the cathode of the first diode is connected to the gate of the fifth N-type MOS tube, one end of the first memristor element and the drain of the sixth N-type MOS tube; the cathode of the second diode is connected to the gate of the sixth N-type MOS tube, the other end of the first memristor element and the drain of the fifth N-type MOS tube; the cathode of the third diode is connected to the gate of the third N-type MOS tube, one end of the second memristor element and the drain of the fourth N-type MOS tube; the cathode of the fourth diode is connected to the gate of the fourth N-type MOS tube, the other end of the second memristor element and the drain of the third N-type MOS tube; based on the unidirectional conductivity of the diode, when a control signal with an amplitude greater than the diode turn-on voltage is input, the diode is turned on, so that the control signal flows smoothly into the resistance adjustment circuit, on the contrary, the external circuit current cannot flow into the control device through the control signal input end, thereby ensuring the stability and safety of the circuit.

[0023] Furthermore, the third N-type MOS tube and the fourth N-type MOS tube, the fifth N-type MOS tube and the sixth N-type MOS tube in the resistance adjustment circuit are symmetrically arranged in pairs, and together form two control units. By alternately applying control signals to the symmetrically arranged diodes and MOS tubes, the two control units can both adjust the resistance of the memristor element.

[0024] Furthermore, the two output terminals of the resistance output circuit are coupled to the external circuit in series, and the resistance of the memristor element in the resistance adjustment circuit is connected in series to the external circuit. By adjusting the resistance of the memristor element, the resistance of the external circuit can be adjusted accordingly. The two memristor elements are in a parallel relationship and can arbitrarily select one of the channels to be connected to the external circuit by adjusting the signal input terminal.

[0025] Furthermore, the two memristor elements in the resistance output circuit form a parallel relationship through the MOS tube, and the MOS tubes are all connected to the Control control terminal. By controlling the Control control terminal, the resistance of the memristor element in one of the control units can be adjusted while ensuring that the external circuit current does not flow into its control unit but flows through the other control unit, effectively reducing the impact of the external circuit current on the control circuit, ensuring safer, more reliable, more stable and more accurate.

[0026] Furthermore, the first output terminal and the second output terminal in the resistance output circuit are respectively connected to the two ends of the memristor element through the MOS tube, and the resistance of the memristor element can be output to the external circuit through the first output terminal and the second output terminal. When connecting the external circuit, there is no need to distinguish the access polarity of the first output terminal and the second output terminal. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 is a circuit schematic diagram of the present invention;

[0028] Figure 2 is a schematic diagram of a control signal input circuit of the present invention;

[0029] Figure 3 It is a schematic diagram of a resistance adjustment circuit of the present invention;

[0030] Figure 4 It is a schematic diagram of a resistance output circuit of the present invention;

[0031] Among them: 1-control signal input circuit; 2-resistance adjustment circuit; 3-resistance output circuit; 4-Control control terminal; 5-ground terminal; 6-first input terminal; 7-second input terminal; 8-first N-type MOS tube; 9-second N-type MOS tube; 10-first P-type MOS tube; 11-second P-type MOS tube; 12-first diode; 13-second diode; 14-third diode; 15-fourth diode; 16-third N-type MOS tube; 17-fourth N-type MOS tube; 18-fifth N-type MOS tube; 19-sixth N-type MOS tube; 20-first memristor element; 21-second memristor element; 22-third P-type MOS tube; 23-seventh N-type MOS tube; 24-fourth P-type MOS tube; 25-eighth N-type MOS tube; 26-first output terminal; 27-second output terminal. DETAILED DESCRIPTION

[0032] In order to enable those skilled in the art to understand the characteristics and effects of the present invention, the following is a general description and definition of the terms and expressions mentioned in the specification and claims. Unless otherwise specified, all technical and scientific terms used in the text are the common meanings understood by those skilled in the art for the present invention. In the event of a conflict, the definition in this specification shall prevail.

[0033] The theories or mechanisms described and disclosed herein, whether correct or incorrect, should not limit the scope of the present invention in any way, that is, the present invention can be implemented without being limited by any specific theory or mechanism.

[0034] Herein, all features such as values, quantities, contents and concentrations defined in the form of numerical ranges or percentage ranges are for simplicity and convenience only. Accordingly, the description of numerical ranges or percentage ranges should be considered to have included and specifically disclosed all possible secondary ranges and individual values ​​within the range (including integers and fractions).

[0035] In this document, unless otherwise specified, “includes,” “including,” “contains,” “has,” or similar terms cover the meanings of “consisting of” and “mainly consisting of,” for example, “A includes a” covers the meanings of “A includes a and other” and “A only includes a.”

[0036] In this document, in order to make the description concise, not all possible combinations of various technical features in various embodiments or examples are described. Therefore, as long as there is no contradiction in the combination of these technical features, the various technical features in various embodiments or examples can be combined arbitrarily, and all possible combinations should be considered to be within the scope of this specification.

[0037] A memristor is a passive component that has the function of memorizing the changes in the charge flowing through it. Its resistance value depends on the direction and amount of the charge flowing through it. In other words, its resistance value also depends on the direction and magnitude of the current flowing through it. A memristor can memorize the charge or current flowing through it, and its resistance value is only a function of the current or resistance and has nothing to do with time or other parameters. When a positive electric field is applied to both ends of a memristor device, the resistance of the memristor gradually decreases as the electric field increases, and when a reverse electric field is applied to both ends of the device, the resistance gradually increases. Researchers have discovered the memristive effect in a variety of materials, and some materials have better performance in terms of switching ratio and switching action time, such as metal oxides such as TiO2 and ZnO.

[0038] At present, the industry's advanced memristor switching ratio can reach 10 4 The switching time is as low as 1ns, making it an ideal material for use in memristor-based variable resistor circuits.

[0039] like Figure 1 As shown, the present invention discloses a variable resistor circuit based on a dual memristor, including a control signal input circuit 1, a resistance adjustment circuit 2 and a resistance output circuit 3. The control signal input circuit 1 is connected to the resistance adjustment circuit 2 to input the control signal of the input circuit 1 into the resistance adjustment circuit 2 to adjust the resistance of the resistance adjustment circuit 2. The output of the resistance adjustment circuit 2 is connected to the resistance output circuit 3 to output the resistance.

[0040] As shown in 2, the control signal input circuit 1 includes a Control control terminal 4, a ground terminal 5, a first input terminal 6, a second input terminal 7, a first N-type MOS transistor 8, a second N-type MOS transistor 9, a first P-type MOS transistor 10 and a second P-type MOS transistor 11; the Control control terminal 4 is a control high and low level signal access port, the first input terminal 6 and the second input terminal 7 are control signal pulse access ports, and the ground terminal 5 is a ground access port; by applying high and low level pulses to the first input terminal 6 and the second input terminal 7 and applying high and low level signals to the Control control terminal 4, the resistance of the first memristor element 20 and the second memristor element 21 in the resistance adjustment circuit 2 is adjusted.

[0041] Preferably, the first input terminal 6 is divided into two paths, respectively connected to the first N-type MOS transistor 8 and the first P-type MOS transistor 10, and the second input terminal 7 is divided into two paths, respectively connected to the second N-type MOS transistor 9 and the second P-type MOS transistor 11; the Control terminal 4 is connected to the first N-type MOS transistor 8, the second N-type MOS transistor 9, the first P-type MOS transistor 10 and the second P-type MOS transistor 11. By applying high and low level pulses to the first input terminal 6 and the second input terminal 7 and applying high and low level signals to the Control terminal 4, the on-off control of the first N-type MOS transistor 8, the second N-type MOS transistor 9, the first P-type MOS transistor 10 and the second P-type MOS transistor 11 is realized.

[0042] like Figure 3 As shown, the resistance adjustment circuit 2 includes two adjustment units, the left adjustment unit includes a first diode 12, a second diode 13, a fifth N-type MOS transistor 18, a sixth N-type MOS transistor 19 and a first memristor element 20, and the resistance of the first memristor element 20 is adjusted accordingly according to the input signal of the control signal input circuit 1; the right adjustment unit includes a third diode 14, a fourth diode 15, a third N-type MOS transistor 16, a fourth N-type MOS transistor 17, and a second memristor element 21, and the resistance of the second memristor element 21 can be adjusted accordingly according to the input signal of the control signal input circuit 1, and the sources of the third N-type MOS transistor 16, the fourth N-type MOS transistor 17, the fifth N-type MOS transistor 18 and the sixth N-type MOS transistor 19 are connected to the ground.

[0043] Preferably, in the left control unit, the first input terminal 6 is divided into two paths, one of which is connected to the source of the first N-type MOS tube 8, and the drain of the first N-type MOS tube 8 is connected to the positive electrode of the first diode 12; the cathode of the first diode 12 is connected to the gate of the fifth N-type MOS tube 18, one end of the first memristor element 20 and the drain of the sixth N-type MOS tube 19; the second input terminal 7 is divided into two paths, one of which is connected to the source of the second N-type MOS tube 9, and the drain of the second N-type MOS tube 9 is connected to the positive electrode of the second diode 13; the cathode of the second diode 13 is connected to the gate of the sixth N-type MOS tube 19, the other end of the first memristor element 20 and the drain of the fifth N-type MOS tube 18.

[0044] Preferably, in the right-side control unit, one of the two paths divided by the first input terminal 6 is different from the one connected to the first control unit, and the source of the first P-type MOS tube 10 is connected, and the drain of the first P-type MOS tube 10 is connected to the positive electrode of the third diode 14; the cathode of the third diode 14 is connected to the gate of the third N-type MOS tube 16, one end of the second memristor element 21, and the drain of the fourth N-type MOS tube 17; one of the two paths divided by the second input terminal 7 is different from the one connected to the first control unit, and the source of the second P-type MOS tube 11 is connected, and the drain of the second P-type MOS tube 11 is connected to the positive electrode of the fourth diode 15; the cathode of the fourth diode 15 is connected to the gate of the fourth N-type MOS tube 17, the other end of the second memristor element 21, and the drain of the third N-type MOS tube 16.

[0045] like Figure 4 As shown, the resistance output circuit 3 includes a first output terminal 26 and a second output terminal 27. The input signal from the control signal input circuit 1 can realize corresponding adjustment of the resistance of the first and second memristor elements 20 and 21, and the output of the resistance of the first memristor element 20 is realized through the third P-type MOS tube 22 and the fourth P-type MOS tube 24, and the output of the resistance of the second memristor element 21 is realized through the seventh N-type MOS tube 23 and the eighth N-type MOS tube 25.

[0046] Preferably, the first memristor element 20 is connected in series to the source of the third P-type MOS tube 22 connected to the first output terminal 26, and the source of the fourth P-type MOS tube 24 connected to the second output terminal 27; the second memristor element 21 is connected in series to the source of the seventh N-type MOS tube 23 connected to the first output terminal 26, and the source of the eighth N-type MOS tube 25 connected to the second output terminal 27; the Control control terminal 4 is connected to the gates of the third P-type MOS tube 22, the fourth P-type MOS tube 24, the seventh N-type MOS tube 23 and the eighth N-type MOS tube 25; the first memristor element 20 and the second memristor element 21 form a parallel relationship, and each memristor element can realize the output resistance by connecting in series with the external circuit through the MOS tube.

[0047] It should be noted that when the resistance of the first memristor element 20 is adjusted through the first input terminal 6 and the second input terminal 7, a control circuit based on a variable resistor of a memristor is formed, that is, the left-side control unit is connected to the resistance adjustment circuit, and the external circuit current can only flow through the second memristor element 21 on the right, that is, the right-side control unit circuit. Similarly, when the resistance of the second memristor element 21 is adjusted through the first input terminal 6 and the second input terminal 7, the external circuit current can only flow through the first memristor element 20, thereby effectively avoiding the influence of the state of the external circuit itself on its control in the circuit.

[0048] Applying high and low level signals to the Control terminal 4, and applying a high level pulse signal to either the first input terminal 6 or the second input terminal 7, triggers the change in the resistance value of the first memristor element 20 or the second memristor element 21, that is, only triggers the change in the resistance value of one control unit, and the other control unit is connected to the external circuit. Here, the application of a high level to the Control terminal 4 and a high level pulse signal to the first input terminal 6 is discussed as an example, and it is assumed that the resistance value of the first memristor element 20 is infinite at the initial moment. Since the Control terminal 4 is a high-level signal, the second N-type MOS transistor 9 is in the on state. When a high-level pulse signal with an amplitude at least greater than the diode conduction voltage and the MOS transistor turn-on voltage is connected to the first input terminal 6, the current will pass through the second diode 13 and then be divided into two branches, flowing to the gate of the sixth N-type MOS transistor 19 and the left end of the first memristor element 20 respectively, causing the drain and source of the sixth N-type MOS transistor 19 to be turned on and forming a positive electric field from left to right at both ends of the first memristor element 20. The current passes through the first memristor element 20 and flows to the ground terminal 5 through the source of the sixth N-type MOS transistor 19 in the on state, forming a closed loop.

[0049] According to the conductive mechanism of the memristor, the resistance value of the memristor is related to the historical current flow. Even if the high-level pulse signal disappears, the resistance value of the memristor will not change due to the unchanged magnetic flux. Therefore, the memristor has a definite resistance value at this time, and this resistance value is only related to the amplitude of the applied pulse signal.

[0050] In summary, the resistance of the first memristor element 20 can be adjusted by adjusting the amplitude of the applied pulse signal. Similarly, applying a high-level pulse signal to the second input terminal 7 will trigger the change of the resistance of the first memristor element 20 in the opposite direction. However, applying a pulse signal to only one terminal, that is, applying a unidirectional electric field to the first memristor element 20, cannot achieve arbitrary adjustment of the resistance of the first memristor element 20. If the first input terminal 6 and the second input terminal 7 are used in combination and a certain regular pulse signal is applied to them alternately, the resistance of the first memristor element 20 can be adjusted at will.

[0051] like Figure 3As shown, in the resistance adjustment circuit 2, a pulse signal input to any terminal of the control signal input circuit 1 will not be superimposed on the external circuit connected to the resistance output circuit; the reason is that, taking the application of a high-level signal to the Control terminal 4 and the application of a high-level pulse signal to the first input terminal 6 as an example, when the current passes through the first memristor element 20 in the forward direction, the drain and source of the sixth N-type MOS tube 19 are turned on at the same time, and the source of the sixth N-type MOS tube 19 is directly connected to the ground terminal 5, so that the pulse signal passing through the first memristor element 20 directly flows into the ground terminal 5 instead of flowing into the external circuit.

[0052] Taking the application of a high-level signal to the Control terminal 4 and a high-level pulse signal to the first input terminal 6 as an example, when the resistance of the first memristor element 20 is adjusted, a high-level signal is applied to the Control terminal 4, the drain and source of the eighth N-type MOS tube 25 are turned on, and the external circuit current flows into the right-side regulating unit circuit through the eighth N-type MOS tube 25, thereby avoiding the influence of the external circuit on a group of circuits actually used to adjust the resistance, namely, the left-side regulating unit circuit.

[0053] In the resistance adjustment circuit 3, the external circuit current does not flow into the control signal input circuit 1 to cause damage to the control device; the reason is that the Control terminal 4 of the control signal input circuit 1 controls the on and off of the third P-type MOS transistor 22, the fourth P-type MOS transistor 24, the seventh N-type MOS transistor 23 and the eighth N-type MOS transistor 25 respectively, so that the control signal smoothly flows into a control unit that is actually used to adjust the resistance, and then flows into the resistance output circuit, while the external circuit current cannot flow in and can only flow into another control unit.

[0054] The following is a clear and complete description of the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings of the embodiments of the present invention. It should be noted that when a component is considered to be "connected" to another component, it can be directly connected to another component, or there may be several components at the same time. Unless otherwise defined, all technical and scientific terms used in this article have the same meaning as those generally understood by technicians in the technical field of the present invention. It should also be noted that, unless otherwise clearly specified and limited, the terms "access", "connectivity" and "connection" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or a connection between two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances. The terms used in the specification of the present invention herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0055] The specific implementation scenario of this embodiment is introduced below:

[0056] The first input terminal 6, the second input terminal 7, the Control terminal 4 and the ground terminal 5 of the present invention are connected to the control computer respectively, and the first output terminal 26 and the second output terminal 27 are connected to the external circuit, that is, the resistance output circuit 3 is coupled to the external circuit in series, and there is no need to distinguish between positive and negative polarities; by applying signals to the first input terminal 6, the second input terminal 7 and the Control terminal 4 in the control signal input circuit 1 by the control computer, the resistance value of the first memristor element 20 or the resistance value of the second memristor element 21 can be adjusted accordingly, and the possible influence caused by the connection of the control unit circuit and the external circuit is avoided. For the external circuit, it not only plays the role of a variable resistor, but also effectively avoids the influence of the external circuit state on the resistance control to a certain extent.

[0057] In summary, the present invention is a variable resistor circuit based on dual memristors, which is designed to form the entire control circuit using two memristor elements in parallel, and several simple MOS tubes and diodes. The control signal input circuit 1 is used to receive an external control signal, and the signal of the Control control terminal 4 is controlled to realize the selection of two control units, that is, the selection of two memristor elements. The resistance adjustment circuit 2 applies the control signal to both ends of the memristor element, so that the memristor element adjusts the resistance according to the control signal pulse, and the external circuit current flows into the other control unit, so as to realize the adjustment and control of the resistance of one of the memristor elements, and at the same time avoid the influence of the external circuit state on the resistance regulation.

[0058] The above contents are only for explaining the technical idea of ​​the present invention and cannot be used to limit the protection scope of the present invention. Any changes made on the basis of the technical solution in accordance with the technical idea proposed by the present invention shall fall within the protection scope of the claims of the present invention.

Claims

1. A variable resistance circuit based on dual memristors, characterized in that: The invention comprises a control signal input circuit (1), a resistance adjustment circuit (2), and a resistance output circuit (3); the control signal input circuit (1) is connected to the resistance adjustment circuit (2) and is used to input a control signal into the resistance adjustment circuit (2) to adjust the resistance of a memristor element; the resistance adjustment circuit (2) is composed of two parallel-connected memristor control units; the resistance adjustment circuit (2) is connected to the resistance output circuit (3) to achieve resistance output; In the resistance adjustment circuit (2), each memristor control unit comprises a MOS tube and a diode, which realizes connection with the first input terminal (6), the second input terminal (7), the Control terminal (4) and the ground terminal (5); The two parallel memristor control units in the resistance adjustment circuit (2) include two branches connected in parallel on the left and right sides; The branch on the left side comprises a first diode (12), a second diode (13), a fifth N-type MOS transistor (18), a sixth N-type MOS transistor (19) and a first memristor element (20); the branch on the right side comprises a third diode (14), a fourth diode (15), a third N-type MOS transistor (16), a fourth N-type MOS transistor (17) and a second memristor element (21); The first input terminal (6) is divided into two paths, one of which is connected to the source of the first N-type MOS tube (8), and the drain of the first N-type MOS tube (8) is connected to the positive electrode of the first diode (12); the negative electrode of the first diode (12) is connected to the gate of the fifth N-type MOS tube (18), one end of the first memristor element (20), and the drain of the sixth N-type MOS tube (19); the second input terminal (7) is divided into two paths, one of which is connected to the source of the second N-type MOS tube (9), and the drain of the second N-type MOS tube (9) is connected to the positive electrode of the second diode (13); the negative electrode of the second diode (13) is connected to the gate of the sixth N-type MOS tube (19), the other end of the first memristor element (20), and the drain of the fifth N-type MOS tube (18); One of the two paths divided by the first input terminal (6) and different from the one connected to the first control unit is connected to the source of the first P-type MOS tube (10), and the drain of the first P-type MOS tube (10) is connected to the positive electrode of the third diode (14); the negative electrode of the third diode (14) is connected to the gate of the third N-type MOS tube (16), one end of the second memristor element (21) and the drain of the fourth N-type MOS tube (17); one of the two paths divided by the second input terminal (7) and different from the one connected to the first control unit is connected to the source of the second P-type MOS tube (11), and the drain of the second P-type MOS tube (11) is connected to the positive electrode of the fourth diode (15); the negative electrode of the fourth diode (15) is connected to the gate of the fourth N-type MOS tube (17), the other end of the second memristor element (21) and the drain of the third N-type MOS tube (16).

2. The dual memristor-based variable resistor circuit according to claim 1, characterized in that: The control signal input circuit (1) comprises a first input terminal (6), a second input terminal (7), a ground terminal (5) and a Control terminal (4); the first input terminal (6) and the second input terminal (7) are control signal pulse access ports, the Control terminal (4) is a control high and low level signal access port, and the ground terminal (5) is a ground access port; the first input terminal (6), the second input terminal (7), the Control terminal (4) and the ground terminal (5) are respectively connected to the resistance adjustment circuit (2) via MOS tubes.

3. The dual memristor-based variable resistor circuit according to claim 2, characterized in that: The first input terminal (6), the second input terminal (7), the ground terminal (5) and the Control terminal (4) are respectively connected to a control computer.

4. The dual memristor-based variable resistor circuit according to claim 3, characterized in that: The MOS tubes in the control signal input circuit (1) include a first N-type MOS tube (8), a second N-type MOS tube (9), a first P-type MOS tube (10) and a second P-type MOS tube (11); the Control terminal (4) is respectively connected to the gates of the first N-type MOS tube (8), the second N-type MOS tube (9), the first P-type MOS tube (10) and the second P-type MOS tube (11); and the drains of the first N-type MOS tube (8), the second N-type MOS tube (9), the first P-type MOS tube (10) and the second P-type MOS tube (11) are respectively connected to the resistance adjustment circuit (2).

5. The dual memristor-based variable resistor circuit according to claim 4, characterized in that: The source electrodes of the first N-type MOS transistor (8) and the first P-type MOS transistor (10) included in the control signal input circuit (1) are connected to the first input terminal (6); and the source electrodes of the second N-type MOS transistor (9) and the second P-type MOS transistor (11) are connected to the second input terminal (7).

6. The dual memristor-based variable resistor circuit according to claim 1, characterized in that: The sources of the third N-type MOS transistor (16), the fourth N-type MOS transistor (17), the fifth N-type MOS transistor (18) and the sixth N-type MOS transistor (19) are connected to a common ground; The drain electrodes of the first N-type MOS transistor (8), the second N-type MOS transistor (9), the first P-type MOS transistor (10) and the second P-type MOS transistor (11) are respectively connected to the positive electrodes of the first diode (12), the second diode (13), the third diode (14) and the fourth diode (15) in the resistance adjustment circuit (2).

7. The dual-memristor-based variable resistance circuit according to claim 6, characterized in that: The resistance output circuit (3) comprises a third P-type MOS transistor (22), a seventh N-type MOS transistor (23), a fourth P-type MOS transistor (24), an eighth N-type MOS transistor (25), a first output terminal (26) and a second output terminal (27); one end of the first memristor element (20) is connected to the source of the third P-type MOS transistor (22), and the drain of the third P-type MOS transistor (22) is connected to the first output terminal (6); the other end is connected to the source of the fourth P-type MOS transistor (24); the drain of the fourth P-type MOS transistor (24) is connected to the second output terminal (7); one end of the second memristor element (21) is connected to the source of the seventh N-type MOS transistor (23), the drain of the seventh N-type MOS transistor (23) is connected to the first output terminal (6), and the other end is connected to the source of the eighth N-type MOS transistor (25); the drain of the eighth N-type MOS transistor (25) is connected to the second output terminal (7).

8. The dual-memristor-based variable resistor circuit according to claim 7, characterized in that: The gate electrodes of the third P-type MOS transistor (22), the fourth P-type MOS transistor (24), the seventh N-type MOS transistor (23) and the eighth N-type MOS transistor (25) are respectively connected to the Control terminal (4).

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