Method for manufacturing a semiconductor structure and semiconductor structure, memory

Abstract

The embodiment of the present disclosure relates to the field of semiconductor, in particular to a preparation method of semiconductor structure, semiconductor structure, memory, and the preparation method of semiconductor structure comprises: forming a first semiconductor layer on a substrate, the first semiconductor layer has a first channel region and a to-be-doped region located on the opposite sides of the first channel region; forming a word line, the word line surrounds the side surface of the first semiconductor layer of the first channel region, and the projection of at least part of the first semiconductor layer of the to-be-doped region coincides with the projection of the word line on the surface of the substrate; forming a doping main body part, the doping main body part has a first doping ion, and the doping main body part is in contact with the end surface of the to-be-doped region away from the first channel region; performing annealing treatment, so that the first doping ion diffuses to the to-be-doped region, the to-be-doped region is converted into a doped region, and along the direction of the doped region pointing to the first channel region, the concentration of the doping ion in the doped region decreases. The embodiment of the present disclosure is beneficial to improve the control ability of the gate in the semiconductor structure.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to the semiconductor field, and in particular, to a semiconductor structure manufacturing method, a semiconductor structure and a memory. BACKGROUND

[0002] Memory is a common semiconductor structure. As the size of the semiconductor structure continues to shrink, more memory can be incorporated on a chip, which helps to increase the product capacity. There are many small conductive structure units in the semiconductor structure, such as gates, bit lines, and source-drain electrodes, etc. The gate is used to form a conductive channel between the source and the drain to control the conduction of the source and the drain. As the size of the semiconductor structure shrinks, it becomes increasingly important to optimize the performance of the conductive structure units in the semiconductor structure.

[0003] However, there is a problem of poor control ability of the gate. SUMMARY

[0004] Embodiments of the present disclosure provide a semiconductor structure manufacturing method, a semiconductor structure and a memory, which at least help to improve the problem of poor control ability of the gate in the semiconductor structure.

[0005] According to some embodiments of the present disclosure, in one aspect, a semiconductor structure manufacturing method is provided, which includes: providing a substrate; forming a first semiconductor layer on the substrate, the first semiconductor layer having a first channel region and a to-be-doped region located on opposite sides of the first channel region, the arrangement direction of the first channel region and the to-be-doped region being parallel to the surface of the substrate; forming a word line, the word line surrounding the side surface of the first semiconductor layer of the first channel region, and the projection of at least part of the first semiconductor layer of the to-be-doped region on the substrate surface coinciding with the projection of the word line on the substrate surface; forming a doping main body part, the doping main body part having first doping ions therein, and the doping main body part being in contact with the end surface of the to-be-doped region away from the first channel region; and performing an annealing process to diffuse the first doping ions to the to-be-doped region, convert the to-be-doped region into a doped region, and the concentration of the doping ions in the doped region decreases in the direction of the doped region pointing to the first channel region.

[0006] In some embodiments, the step of forming the doping main body part includes: forming a first via hole, the first via hole penetrating through the first semiconductor layer, and the first via hole exposing part of the end surface of the first semiconductor layer of the to-be-doped region; and forming the doping main body part in the first via hole, the doping main body part having a first doping concentration.

[0007] In some embodiments, the first semiconductor layer has second doping ions, the second doping ions are different from the first doping ions in type, and the second doping ions have a second doping concentration, the first doping concentration being greater than the second doping concentration.

[0008] In some embodiments, the annealing process is performed at a temperature of 500-1000 °C.

[0009] In some embodiments, the method further comprises: etching the doped body portion to form a second via; and forming a conductive pillar in the second via, the conductive pillar contacting the doped region away from the first channel region.

[0010] In some embodiments, the method of forming the word line comprises: forming a first sacrificial layer on a surface of the first semiconductor layer facing the substrate and a second sacrificial layer on a surface of the first semiconductor layer facing away from the substrate; removing portions of the first and second sacrificial layers that contact the surface of the first semiconductor layer in the first channel region using an etching process to form first and second air gaps; and depositing a gate material in the first and second air gaps using a deposition process to form the word line, the word line filling the first and second air gaps.

[0011] In some embodiments, the method further comprises forming a gate oxide layer on the surface of the first semiconductor layer in the first channel region.

[0012] In some embodiments, the etching process is a wet etching process.

[0013] In some embodiments, the method further comprises: sequentially forming a second semiconductor layer and a third semiconductor layer on the substrate, the second and third semiconductor layers being located above the first semiconductor layer away from the substrate, and the word line surrounding portions of side surfaces of the second and third semiconductor layers, the first, second, and third semiconductor layers having the same type of dopant ions.

[0014] In some embodiments, the method further comprises: forming a first oxide isolation layer between the first and second semiconductor layers, and forming a second oxide isolation layer between the second and third semiconductor layers.

[0015] In some embodiments, the dopant ions of the first, second, and third semiconductor layers have the same doping concentration.

[0016] In some embodiments, the dopant ions of the first, second, and third semiconductor layers have a doping concentration that varies in a stepwise manner.

[0017] Correspondingly, the embodiments of the present disclosure further provide a semiconductor structure, comprising: a substrate; a first semiconductor layer, the first semiconductor layer being located on the substrate, the first semiconductor layer having a first channel region and a doped region located on opposite sides of the first channel region, an arrangement direction of the first channel region and the doped region being parallel to a surface of the substrate; in a direction from the doped region to the first channel region, a concentration of doped ions in the doped region decreases; a word line, the word line surrounding a side surface of the first semiconductor layer of the first channel region, and a projection of at least part of the first semiconductor layer of the doped region on the surface of the substrate coincides with a projection of the word line on the surface of the substrate.

[0018] In some embodiments, further comprising: a second semiconductor layer and a third semiconductor layer located above the first semiconductor layer away from the substrate and arranged in sequence, and the word line surrounds part of side surfaces of the second semiconductor layer and the third semiconductor layer.

[0019] In some embodiments, further comprising: a conductive column, the conductive column being electrically connected with a side wall of the doped region away from the first channel region of the first semiconductor layer, and in a direction perpendicular to the surface of the substrate, a distance from the conductive column to the substrate is greater than a distance from a surface of the word line away from the substrate to the substrate.

[0020] In some embodiments, the conductive column comprises a first conductive column and a second conductive column, and further comprising: a capacitor structure, the capacitor structure being located on a surface of the first conductive column away from the substrate; a bit line structure, the bit line structure being located on a surface of the second conductive column away from the substrate.

[0021] In some embodiments, the number of the first semiconductor layers is multiple, and the multiple first semiconductor layers are arranged at intervals, and the multiple first semiconductor layers are connected by the word line.

[0022] Correspondingly, the embodiments of the present disclosure further provide a memory comprising the semiconductor structure provided by any one of the above embodiments.

[0023] The preparation method of the semiconductor structure provided by the embodiments of the present disclosure includes: forming a first semiconductor layer on a substrate, the first semiconductor layer having a first channel region and a to-be-doped region located on opposite sides of the first channel region; forming a word line, the word line surrounding the side surface of the first semiconductor layer of the first channel region, so that the contact area between the word line and the surface of the first semiconductor layer of the first channel region is large, thereby making the channel length of the semiconductor structure long, which is conducive to reducing the threshold voltage of the gate, thereby making the control ability of the gate strong; the projection of at least part of the first semiconductor layer of the to-be-doped region on the surface of the substrate coincides with the projection of the word line on the surface of the substrate; forming a doping main body, the doping main body having first doping ions therein, the doping main body being in contact with the end surface of the to-be-doped region away from the first channel region; performing an annealing process to diffuse the first doping ions to the to-be-doped region, thereby converting the to-be-doped region into a doped region, and in the direction of the doped region pointing to the first channel region, the concentration of the doping ions in the doped region decreases, that is, the doping main body dopes the to-be-doped regions on both sides of the first semiconductor layer in the horizontal direction. Since the end surfaces of the first semiconductor layer on both sides are exposed to the outside, compared with doping the substrate in the vertical direction to form a doped region, doping the first semiconductor layer in the horizontal direction can provide more operation space for the doping process, thereby making the doping concentration easy to control, and further increasing the control ability of the gate. In addition, in the direction of the doped region pointing to the first channel region, the concentration of the doping ions in the doped region decreases, that is, the concentration of the doping ions in the doped region away from the word line is higher. Since the word line is far away from the part of the doped region with a higher concentration of doping ions, the influence of the enhanced electric field generated by the gate when it is turned on on most of the doping ions in the doped region is small, which is conducive to avoiding the risk of leakage current of the doped region under the influence of the strong electric field, thereby improving the control ability of the gate. BRIEF DESCRIPTION OF DRAWINGS

[0024] One or more embodiments are illustrated by way of example in the figures that are part of this disclosure and which are illustrative, but not restrictive, of the present embodiments, unless otherwise specified, the figures in the drawings do not constitute a proportional limit.

[0025] Figures 1 to 4 The preparation method of the semiconductor structure provided by an embodiment of the present disclosure includes forming a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer corresponding structure schematic diagram;

[0026] Figures 5 to 6 The preparation method of the semiconductor structure provided by an embodiment of the present disclosure includes forming an isolation structure corresponding structure schematic diagram;

[0027] Figures 7 to 12 The preparation method of the semiconductor structure provided by an embodiment of the present disclosure includes forming a word line corresponding structure schematic diagram;

[0028] Figures 13 to 18This is a schematic diagram of the structure corresponding to the formation of the doped region in a method for fabricating a semiconductor structure according to an embodiment of the present disclosure.

[0029] Figures 19 to 22 This is a schematic diagram of the structure corresponding to the formation of conductive pillars in a method for fabricating a semiconductor structure according to an embodiment of the present disclosure.

[0030] Figure 23 This is a cross-sectional structural diagram of a semiconductor structure provided in an embodiment of the present disclosure;

[0031] Figure 24 This is a top view schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure;

[0032] Figure 25 This is a cross-sectional schematic diagram of another semiconductor structure provided in an embodiment of the present disclosure. Detailed Implementation

[0033] As can be seen from the background technology, the existing technology has the problem of poor gate control capability.

[0034] Analysis revealed that the poor gate control capability stems from the fact that current methods for forming doped regions in semiconductor structures typically involve vertical doping of the substrate. Vertical doping only requires performing the doping process on the surface of the substrate to be doped, creating a doped region corresponding to that surface. However, with the miniaturization of semiconductors, substrate sizes and the area of ​​the surface to be doped also decrease, resulting in less operating space. This increases the difficulty of the doping process, making it harder to control the doping concentration in the vertical direction, thus affecting the gate control capability.

[0035] The embodiment of the present disclosure provides a preparation method of a semiconductor structure, which comprises the following steps: a first semiconductor layer with a first channel region and a to-be-doped region located on opposite sides of the first channel region on a substrate; forming a word line, the word line surrounds the side surface of the first semiconductor layer of the first channel region, so that the contact area of the word line and the surface of the first semiconductor layer of the first channel region is large, thereby the channel length in the semiconductor structure is long, which is beneficial to reduce the threshold voltage of the gate, thereby the control ability of the gate is strong; forming a doping main body part, the doping main body part has first doping ions, and the doping main body part is in contact with the end surface of the to-be-doped region away from the first channel region; performing annealing treatment, so that the first doping ions diffuse to the to-be-doped region, the to-be-doped region is converted into a doped region, and along the direction in which the doped region points to the first channel region, the doping ion concentration in the doped region decreases, that is, the doping main body part dopes the to-be-doped regions on the two sides of the first semiconductor layer in the horizontal direction, since the end surfaces on the two sides of the first semiconductor layer are exposed to the outside, compared with doping the substrate in the vertical direction to form the doped region, doping the first semiconductor layer in the horizontal direction can provide more operation space for the doping process, thereby the doping concentration is easy to control, and then the control ability of the gate is increased. In addition, along the direction in which the doped region points to the first channel region, the doping ion concentration in the doped region decreases, therefore, the influence of the enhanced electric field generated when the gate is turned on on most of the doping ions in the doped region is small, which is beneficial to avoid the risk of leakage current of the doped region under the influence of the strong electric field, thereby the control ability of the gate is improved.

[0036] The embodiments of the present disclosure will be described in detail below with reference to the drawings. However, those skilled in the art can understand that, in the embodiments of the present disclosure, many technical details are proposed in order to enable the readers to better understand the present disclosure. However, the technical solutions claimed by the present disclosure can be implemented even without these technical details and various changes and modifications based on the following embodiments.

[0037] Figure 1 A cross-sectional structure main view corresponding to the formation of the first semiconductor layer, the second semiconductor layer and the third semiconductor layer in the preparation method of the semiconductor structure provided by an embodiment of the present disclosure is provided, Figure 2 A top view corresponding to the formation of the first semiconductor layer, the second semiconductor layer and the third semiconductor layer in the preparation method of the semiconductor structure provided by an embodiment of the present disclosure is provided.

[0038] Reference Figure 1 and Figure 2The substrate 100 is provided; the first semiconductor layer 110 is formed on the substrate 100, the first semiconductor layer 110 has a first channel region 111 and a to-be-doped region 112 located on opposite sides of the first channel region 111, and the arrangement direction of the first channel region 111 and the to-be-doped region 112 is parallel to the surface of the substrate 100. The to-be-doped region 112 is located on both sides of the first channel region 111, so that the two ends of the to-be-doped region 112 away from the first channel region 111 can be exposed. When the to-be-doped region 112 is doped in the horizontal direction later, the entire exposed end surface of the to-be-doped region 112 can be doped, so that the doping area is larger, that is, the doping process has a larger doping space, which is beneficial to control the doping concentration of the to-be-doped region 112.

[0039] The material of the substrate 100 is a semiconductor material. In some embodiments, the material of the substrate 100 is silicon. In other embodiments, the substrate 100 can also be a germanium substrate, a germanium-silicon substrate, a silicon carbide substrate, or a silicon-on-insulator substrate.

[0040] In some embodiments, at least two first semiconductor layers 110 spaced from each other can be formed on the substrate 100, for subsequent formation of a plurality of mutually spaced word lines.

[0041] In some embodiments, the method for forming the first semiconductor layer 110 includes:

[0042] The initial first semiconductor layer 110 is formed by a deposition process. Specifically, the material of the first semiconductor layer 110 can be the same as that of the substrate 100. In some embodiments, the material of the initial first semiconductor layer 110 can be silicon, and in other embodiments, the material of the initial first semiconductor layer can also be a germanium substrate, a germanium-silicon substrate, a silicon carbide substrate, or a silicon-on-insulator substrate.

[0043] The initial first semiconductor layer 110 is doped to form the first semiconductor layer 110. In some embodiments, the first semiconductor layer 110 can be doped by any one of an ion implantation process or a thermal diffusion process. Specifically, in some embodiments, the initial first semiconductor layer 110 can be doped with P-type ions. In other embodiments, the initial first semiconductor layer 110 can also be doped with N-type ions. The N-type ions are at least one of arsenic ions, phosphorus ions, or antimony ions; and the P-type ions are at least one of boron ions, indium ions, or gallium ions.

[0044] In some embodiments, further comprising: forming a first sacrificial layer 151 on the surface of the first semiconductor layer 110 facing the substrate 100, and a second sacrificial layer 152 on the surface of the first semiconductor layer 110 away from the substrate 100. In this way, a basis is provided for the subsequent formation of the word line around the first semiconductor layer 110, i.e. part of the first sacrificial layer 151 and part of the second sacrificial layer 152 can be removed later to provide space for the formation of the word line. Specifically, in some embodiments, a deposition process can be used to form the first sacrificial layer 151 and the second sacrificial layer 152 on the surface of the substrate 100 and the surface of the first semiconductor layer 110 away from the substrate 100. In some embodiments, the material of the first sacrificial layer 151 and the second sacrificial layer 152 can be any one of a carbon material or an SOC material. In other embodiments, the material of the sacrificial layer can be at least one of a low dielectric constant material such as borosilicate glass, borophosphosilicate glass, tetraethyl orthosilicate or silicon oxide.

[0045] In some embodiments, further comprising: sequentially forming a second semiconductor layer 120 and a third semiconductor layer 130 on the substrate 100, the second semiconductor layer 120 and the third semiconductor layer 130 being located above the first semiconductor layer 110 away from the substrate 100, and the word line surrounding part of the side surface of the second semiconductor layer 120 and the third semiconductor layer 130, the first semiconductor layer 110, the second semiconductor layer 120 and the third semiconductor layer 130 having the same type of doped ions. The second semiconductor layer 120 includes a second channel region and doped regions located on both sides of the second channel region, and the third semiconductor layer 130 includes a third channel region and doped regions located on both sides of the third channel region, i.e. three channels are formed in the semiconductor structure, and each channel has the effect of forming a conductive channel when a voltage is applied to the gate, so that the control ability of the gate can be enhanced. Specifically, the same process method can be used to form the second semiconductor layer 120 and the third semiconductor layer 130.

[0046] It can be understood that, in some embodiments, the doping concentration of the doped ions of the first semiconductor layer 110, the second semiconductor layer 120 and the third semiconductor layer 130 can be equal. That is, the same threshold voltage needs to be applied when each channel is turned on to form a conductive channel and turn on the source and drain. In this way, if a channel does not work, the source and drain can be turned on by other channels, so that the semiconductor structure can still work normally, thereby improving the control ability of the gate.

[0047] In some embodiments, the doping concentration of the doping ions in the first semiconductor layer 110, the second semiconductor layer 120 and the third semiconductor layer 130 can vary in a step shape. That is, different threshold voltages can be applied to turn on the channels in the first semiconductor layer 110, the second semiconductor layer 120 and the third semiconductor layer 130, respectively. For example, a first threshold voltage can be applied to turn on the channel in the first semiconductor layer 110; a second threshold voltage can be applied to turn on the channel in the second semiconductor layer 120; and a third threshold voltage can be applied to turn on the channel in the third semiconductor layer 130. In this way, three different voltages can be applied to the gate to turn on the source and the drain, thereby greatly improving the control ability of the gate.

[0048] In some embodiments, the method further comprises: forming a first oxide isolation layer 141 between the first semiconductor layer 110 and the second semiconductor layer 120, and forming a second oxide isolation layer 142 between the second semiconductor layer 120 and the third semiconductor layer 130. The first oxide isolation layer 141 is used to isolate the first semiconductor layer 110 and the second semiconductor layer 120, and the second oxide isolation layer 142 is used to isolate the second semiconductor layer 120 and the third semiconductor layer 130. Specifically, in some embodiments, the first oxide isolation layer 141 and the second oxide isolation layer 142 can be formed by a deposition process, such as any one of a thermal oxidation process or an atomic layer deposition process. In some embodiments, the material of the first oxide isolation layer 141 and the second oxide isolation layer 142 can be at least one of silicon oxide, silicon nitride, silicon carbon nitride or silicon carbon nitrogen oxide.

[0049] It can be understood that, in some embodiments, the method further comprises:

[0050] A third sacrificial layer 153 is formed on the surface of the second semiconductor layer 120, and a fourth sacrificial layer 154 is formed on the surface of the third semiconductor layer 130. In this way, the second semiconductor layer 120 and the third semiconductor layer 130 provide a basis for the subsequent formation of the word line.

[0051] In some embodiments, the method further comprises forming a gate cap layer 160 on the surface of the fourth sacrificial layer 154. The gate cap layer 160 is used to isolate the word line from other conductive structures in the semiconductor structure, and also serves to protect the word line.

[0052] In some embodiments, before forming the first sacrificial layer 151, the method further comprises forming a dielectric layer 170 on the surface of the substrate 100. The dielectric layer 170 is located between the first sacrificial layer 151 and the substrate 100, and is used to isolate the subsequently formed word line from the substrate 100. Specifically, in some embodiments, the material of the dielectric layer 170 can be at least one of silicon oxide, silicon nitride, silicon carbon nitride or silicon carbon nitrogen oxide.

[0053] Figure 3A schematic view of a cross-sectional structure corresponding to forming the at least two spaced first semiconductor layers is provided in an embodiment of the present disclosure, Figure 4 A schematic view of a top view corresponding to forming the at least two spaced first semiconductor layers is provided in an embodiment of the present disclosure.

[0054] Reference is made to Figure 3 and Figure 4 Specifically, the method of forming the at least two spaced first semiconductor layers 110 includes: performing a patterning process on the first semiconductor layer 110 to form the at least two spaced first semiconductor layers 110. In some embodiments, a self-aligned quadruple patterning (SAQP) or a self-aligned double patterning (SADP) technique can be used to perform the patterning process on the base first semiconductor layer 110.

[0055] Figure 3 A schematic view of a cross-sectional structure corresponding to forming the isolation structure is provided in an embodiment of the present disclosure, Figure 4 A schematic view of a top view corresponding to forming the isolation structure is provided in an embodiment of the present disclosure.

[0056] Reference is made to Figure 3 and Figure 4 In some embodiments, the method further includes: forming an isolation structure 180 between the adjacent first semiconductor layers 110, the isolation structure 180 being configured to isolate the two adjacent first semiconductor layers 110. In some embodiments, the isolation structure 180 can be formed by a deposition process. Specifically, the material of the isolation structure 180 can be at least one of silicon oxide, silicon nitride, silicon carbon nitride, or silicon carbon nitride oxide.

[0057] Figures 7 to 12 A schematic view of a structure corresponding to forming the word line is provided in an embodiment of the present disclosure.

[0058] Reference is made to Figures 7 to 12 The word line 190 is formed to surround the side of the first semiconductor layer 110 of the first channel region 111, and the projection of the first semiconductor layer 110 of the at least partially to-be-doped region 112 coincides with the projection of the word line 190 on the surface of the substrate 100. The word line 190 is arranged to surround the side of the first semiconductor layer 110 of the first channel region 111, forming a Gate-All-Around (GAA) transistor, which can form a 3D stacked memory device, and is conducive to improving the integration density of the semiconductor structure.

[0059] In some embodiments, the projection of the to-be-doped region 112 towards the end surface of the first channel region 111 on the surface of the substrate 100 can coincide with the projection of the word line 190 towards the end surface of the to-be-doped region 112 on the surface of the substrate 100, so that the first channel region 111 can form a communication between the doped regions 112 located on both sides of the first channel region 111.

[0060] In some other embodiments, the projection of the part of the surface of the first semiconductor layer 110 of the to-be-doped region 112 on the surface of the substrate 100 can coincide with the projection of the part of the word line 190 on the surface of the substrate 100, that is, the word line 190 can also surround the side of the part of the first semiconductor layer 110 of the to-be-doped region 112, so as to ensure the conduction of the doped regions 112 located on both sides of the first channel region 111. The word line 190 surrounds the side of the first semiconductor layer 110 of the first channel region 111, so that the contact area of the word line 190 with the surface of the first semiconductor layer 110 of the first channel region 111 is large, so that the channel length in the semiconductor structure is long, and thus, the threshold voltage of the gate is reduced, so that the control ability of the gate is strong. In some embodiments, the surface of the substrate 100 is provided with at least two first semiconductor layers 110 spaced from each other, and the two adjacent first semiconductor layers 110 can be connected by the word line 190.

[0061] In some embodiments, the method for forming the word line 190 comprises:

[0062] Figure 7 A main view schematic diagram of a cross-sectional structure corresponding to the formation of the first air layer and the second air layer in the method for preparing the semiconductor structure provided by an embodiment of the present disclosure, Figure 8 A top view schematic diagram of a cross-sectional structure corresponding to the formation of the first air layer and the second air layer in the method for preparing the semiconductor structure provided by an embodiment of the present disclosure, referring to Figures 7 to 8 The etching process is used to remove part of the first sacrificial layer 151 and the second sacrificial layer 152 in contact with the surface of the first semiconductor layer 110 of the first channel region 111, so as to form the first air layer 10 and the second air layer 20.

[0063] In some embodiments, the etching process can be a wet etching process. Since at least two first semiconductor layers 110 spaced from each other are provided on the substrate 100 in some embodiments, the wet etching process can be used to remove part of the first sacrificial layer 151 and the second sacrificial layer 152 in the at least two first semiconductor layers 110 spaced from each other in the same etching step, so as to improve the etching efficiency. In some embodiments, the etching solvent used in the wet etching process can be any one of nitric acid or hydrofluoric acid.

[0064] Specifically, in some embodiments, the specific method of removing part of the first sacrificial layer 151 and the second sacrificial layer 152 can include: patterning the gate cap layer 160; etching the isolation structure 180 and the gate cap layer 160 to expose the side surfaces of the first sacrificial layer 151 and the second sacrificial layer 152 corresponding to the first channel region 111; and etching the exposed first sacrificial layer 151 and the second sacrificial layer 152 to expose the surface of the first semiconductor layer 110 of the first channel region 111. It can be understood that, in some embodiments, at least two first semiconductor layers 110 are arranged on the substrate 100 and spaced apart from each other, the isolation structure 180 can be patterned and etched to expose the surface of the dielectric layer 170 between the adjacent two first semiconductor layers 110, so that the word line 190 can be connected to the adjacent two first semiconductor layers 110 in the subsequent process of forming the word line 190. It can be understood that, in some embodiments, when the second semiconductor layer 120 and the third semiconductor layer 130 are sequentially formed on the substrate 100, the third sacrificial layer 153 and the fourth sacrificial layer 154 are also etched, so that the word line 190 also surrounds the side surface of the second semiconductor layer 120 of the second channel region and the side surface of the third semiconductor layer 130 corresponding to the third channel region.

[0065] Figure 9 A cross-sectional structure main view of forming a gate oxide layer in a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure, Figure 10 A top view of forming a gate oxide layer in a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure, referring to Figure 9 And Figure 10 In some embodiments, before forming the word line 190, the method further includes forming a gate oxide layer 191 on the surface of the first semiconductor layer 110 of the first channel region 111. That is, the gate oxide layer 191 surrounds the side surface of the first semiconductor layer 110 of the first channel region 111. The gate oxide layer 191 is used to isolate the word line 190 from the first semiconductor layer 110 of the first channel region 111. In some embodiments, the gate oxide layer 191 also surrounds part of the side surface of the first semiconductor layer 110 of the doped region, so that the gate oxide layer 191 can protect the side surface of the first semiconductor layer 110 of the doped region and avoid process damage to the surface of the doped region during the manufacturing process, thereby improving the electrical performance of the semiconductor structure.

[0066] Specifically, in some embodiments, the gate oxide layer 191 can be formed by a deposition process, and the material of the gate oxide layer 191 can include at least one of silicon oxide, silicon nitride, or silicon oxynitride.

[0067] Figure 11A schematic diagram of a cross-sectional structure corresponding to formation of a word line is provided in a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure, Figure 12 A schematic diagram of a top view corresponding to formation of a word line is provided in a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure, with reference to Figures 11 to 12 The word line 190 is formed by depositing a gate material in the first air layer 10 and the second air layer 20 using a deposition process. The word line 190 fills the first air layer 10 and the second air layer 20. It can be understood that, in some embodiments, the word line 190 can be flush with the top surface of the gate cap layer 160 in order to make the deposition process easier to control.

[0068] Specifically, the method for forming the word line 190 includes chemical vapor deposition, physical vapor deposition, atomic layer deposition, or metal organic chemical vapor deposition. The material of the word line 190 can include at least one of cobalt, nickel, molybdenum, titanium, tungsten, tantalum, or platinum.

[0069] In some embodiments, after the word line 190 is formed, the method further includes: performing a back etching on part of the word line 190 so that the top surface of the word line 190 is flush with the bottom surface of the gate cap layer 160 close to the substrate 100; and depositing a material of the gate cap layer 160 on the top surface of the word line 190 to form the gate cap layer 160 covering the top surface of the word line 190. In this way, the gate cap layer 160 can play a role of isolating and protecting the gate.

[0070] Figures 13 to 18 A schematic diagram of a structure corresponding to formation of a doped region is provided in a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure.

[0071] With reference to Figures 13 to 16 In some embodiments, the step of forming the doped body part 40 includes: forming a first through hole 30, the first through hole 30 penetrating through the first semiconductor layer 110, and the first through hole 30 exposing part of an end surface of the first semiconductor layer 110 of the to-be-doped region 112; and forming the doped body part 40 in the first through hole 30, the doped body part 40 having a first doping concentration. That is, the doped body part 40 is in contact with the end surface of the first semiconductor layer 110 to perform horizontal direction doping on the first semiconductor layer 110. In this way, compared with vertical direction doping on the substrate 100, the surface area for performing the doping process is larger, that is, the doping process has a larger doping space, which is beneficial to control the doping concentration of the to-be-doped region 112.

[0072] It can be understood that, in some embodiments, the semiconductor structure further includes a second semiconductor layer 120 and a third semiconductor layer 130, and the first through hole 30 further exposes part of an end surface of the second semiconductor layer 120 and the third semiconductor layer 130 of the to-be-doped region 112.

[0073] It can be understood that, in some embodiments, the semiconductor structure further includes a second semiconductor layer 120 and a third semiconductor layer 130, and the first through hole 30 further exposes part of an end surface of the second semiconductor layer 120 and the third semiconductor layer 130 of the to-be-doped region 112.Figure 13 FIG. 1 is a schematic diagram of a cross-sectional structure corresponding to the formation of a first via in a method of manufacturing a semiconductor structure according to an embodiment of the present disclosure, Figure 14 FIG. 2 is a schematic diagram of a top view corresponding to the formation of a first via in a method of manufacturing a semiconductor structure according to an embodiment of the present disclosure, Figure 13 and Figure 14 Specifically, in some embodiments, the process of forming the first via 30 includes: performing a patterning process on the partial gate cap layer 160; etching the gate cap layer 160, the fourth sacrificial layer 154, the third semiconductor layer 130, the second oxide isolation layer 142, the third sacrificial layer 153, the second semiconductor layer 120, the first oxide isolation layer 141, the second sacrificial layer 152, the first semiconductor layer 110, and the first sacrificial layer 151 to expose a portion of the surface of the dielectric layer 170. In some embodiments, a dry etching process can be used for etching.

[0074] Figure 15 FIG. 4 is a schematic diagram of a cross-sectional structure corresponding to the formation of a doped body in a method of manufacturing a semiconductor structure according to an embodiment of the present disclosure, Figure 16 FIG. 5 is a schematic diagram of a top view corresponding to the formation of a doped body in a method of manufacturing a semiconductor structure according to an embodiment of the present disclosure, Figure 15 and Figure 16 In some embodiments, any one of vapor deposition, physical vapor deposition, or atomic layer deposition can be used to form the doped body 40 in the first via 30.

[0075] Figure 17 FIG. 6 is a schematic diagram of a cross-sectional structure corresponding to the formation of a doped region in a method of manufacturing a semiconductor structure according to an embodiment of the present disclosure, Figure 18 In some embodiments, the first semiconductor layer 110 has a second doping ion, the second doping ion is different from the first doping ion in type, and the second doping ion has a second doping concentration, the first doping concentration being greater than the second doping concentration. When the doping ions diffuse, they usually diffuse from a location with a high concentration to a location with a low concentration. Therefore, the first doping concentration being greater than the second doping concentration can form a concentration difference between the first doping ion and the second doping ion, so that the first doping ion in the doped body 40 can diffuse to both ends of the first semiconductor layer 110. Specifically, the first doping ion is different from the second doping ion in type. In some embodiments, the first doping ion can be a P-type ion, and the second doping ion can be an N-type ion; in other embodiments, the first doping ion can also be an N-type ion, and the second doping ion can be a P-type ion.

[0076] It can be understood that in other embodiments, the first doping ion type can also be the same as the second doping ion type.

[0077] In some embodiments, the temperature of the annealing process is 500-1000℃. Within this temperature range, the first doping ions in the doping body part 40 are allowed to undergo thermal diffusion phenomenon, diffusing from the doping body part 40 to both ends of the first semiconductor layer 110, the second semiconductor layer 120 and the third semiconductor layer 130, thereby forming a doping region in the first semiconductor layer 110, the second semiconductor layer 120 and the third semiconductor layer 130, respectively as the source or drain of the semiconductor structure.

[0078] Since the first doping ions are diffused from the doping body part 40 to both ends of the first semiconductor layer 110, a structure can be formed in which the doping ion concentration in the doping region decreases in the direction pointing from the doping region to the first channel region 111. That is, the doping ion concentration of the doping region away from the word line 190 is higher, and since the word line 190 is farther away from the part of the doping region with higher doping ion concentration, the enhanced electric field generated when the gate is turned on has less effect on most of the doping ions in the doping region, which is beneficial to avoid the risk of current leakage of the doping region under the influence of a strong electric field, thereby improving the control ability of the gate.

[0079] Figures 19 to 22 A structure diagram corresponding to the formation of the conductive pillar in the method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure is shown.

[0080] Reference Figures 19 to 22 In some embodiments, further comprising: etching the doping body part 40 to form a second through hole 50 by using an etching process; and forming a conductive pillar 60 in the second through hole 50, the conductive pillar 60 being in contact with the part of the doping region away from the first channel region 111.

[0081] In some embodiments, the doping body part 40 can be etched by using any one of a dry etching process or a wet etching process. It can be understood that the process of forming the second through hole 50 can be the same as the process step of forming the first through hole 30.

[0082] Figure 21 A main view schematic diagram of the cross-sectional structure corresponding to the formation of the conductive pillar in the method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure is shown. Figure 22A top view of forming the conductive pillar in the method for manufacturing the semiconductor structure provided by an embodiment of the present disclosure is shown in FIG. 6. The conductive pillar 60 is used to lead out the electrical signal of the doped region. In some embodiments, a deposition process can be used to form the conductive part, such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any one of metal organic chemical vapor deposition. Specifically, in some embodiments, the material of the conductive part can include at least one of cobalt, nickel, molybdenum, titanium, tungsten, tantalum, or platinum.

[0083] The method for manufacturing the semiconductor structure provided by the above embodiments includes the following steps. The first semiconductor layer 110 has the first channel region 111 and the to-be-doped region 112 located on the opposite sides of the first channel region 111 on the substrate 100. The word line 190 is formed to surround the side surface of the first semiconductor layer 110 of the first channel region 111. In this way, the contact area between the word line 190 and the surface of the first semiconductor layer 110 of the first channel region 111 is large, so that the channel length in the semiconductor structure is long, which is beneficial to reduce the threshold voltage of the gate, so that the control ability of the gate is strong. The doped body part 40 is formed, and the doped body part 40 has the first doped ions. The doped body part 40 is in contact with the end surface of the to-be-doped region 112 away from the first channel region 111. The annealing process is performed to diffuse the first doped ions to the to-be-doped region 112, so as to convert the to-be-doped region 112 into the doped region. In the direction of the doped region pointing to the first channel region 111, the concentration of the doped ions in the doped region decreases. That is, the doped body part 40 dopes the to-be-doped regions 112 on the two sides of the first semiconductor layer 110 in the horizontal direction. Since the end surfaces on the two sides of the first semiconductor layer 110 are exposed to the outside, compared with doping the substrate 100 in the vertical direction to form the doped region, doping the first semiconductor layer 110 in the horizontal direction can provide more operation space for the doping process, so that the doping concentration is easy to control, and thus the control ability of the gate is increased. In addition, in the direction of the doped region pointing to the first channel region 111, the concentration of the doped ions in the doped region decreases. Therefore, the influence of the enhanced electric field generated when the gate is turned on on most of the doped ions in the doped region is small, which is beneficial to avoid the risk of leakage current of the doped region under the influence of the strong electric field, so as to improve the control ability of the gate.

[0084] Correspondingly, the present disclosure also provides a semiconductor structure, which can be manufactured by the method for manufacturing the semiconductor structure provided by the above embodiments. The semiconductor structure provided by an embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0085] Figure 23 A cross-sectional structure of a semiconductor structure provided by an embodiment of the present disclosure is shown in FIG. 7, Figure 24 A top view of a semiconductor structure provided by an embodiment of the present disclosure is shown in FIG. 8,Figure 23 and Figure 24 , a semiconductor structure, comprising: a substrate 100; a first semiconductor layer 110, the first semiconductor layer 110 is located on the substrate 100, the first semiconductor layer 110 has a first channel region 111 and a doped region located on opposite sides of the first channel region 111, the arrangement direction of the first channel region 111 and the doped region is parallel to the surface of the substrate 100; the concentration of the doped ions in the doped region decreases in the direction from the doped region to the first channel region 111; a word line 190, the word line 190 surrounds the side surface of the first semiconductor layer 110 of the first channel region 111, and the projection of the first semiconductor layer 110 of at least part of the doped region on the surface of the substrate 100 coincides with the projection of the word line 190 on the surface of the substrate 100.

[0086] The concentration of the doped ions in the doped region decreases in the direction from the doped region to the first channel region 111, that is, the concentration of the doped ions in the doped region far away from the word line 190 is higher. Since the word line 190 is far away from the part of the doped region with higher concentration of the doped ions, the influence of the enhanced electric field generated when the gate is turned on on most of the doped ions in the doped region is smaller, which is beneficial to avoid the risk of current leakage of the doped region under the influence of strong electric field, thereby improving the control ability of the gate. The word line 190 surrounds the side surface of the first semiconductor layer 110 of the first channel region 111, so that the contact area of the word line 190 and the surface of the first semiconductor layer 110 of the first channel region 111 is larger, thereby making the channel length in the semiconductor structure longer, which is beneficial to reduce the threshold voltage of the gate, thereby making the control ability of the gate stronger.

[0087] In some embodiments, the projection of the end surface of the to-be-doped region 112 towards the first channel region 111 on the surface of the substrate 100 can coincide with the projection of the end surface of the word line 190 towards the to-be-doped region 112 on the surface of the substrate 100, thereby realizing that the first channel region 111 can form a communication between the doped regions 112 located on both sides of the first channel region 111.

[0088] Reference Figure 25 , Figure 25 Another cross-sectional structure schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure, in other embodiments, the projection of part of the surface of the first semiconductor layer 110 of the to-be-doped region 112 on the surface of the substrate 100 can coincide with the projection of part of the word line 190 on the surface of the substrate 100, that is, the word line 190 can also surround part of the side surface of the first semiconductor layer 110 of the to-be-doped region 112, thereby ensuring the conduction of the doped regions 112 located on both sides of the first channel region 111.

[0089] The material of the substrate 100 is a semiconductor material. In some embodiments, the material of the substrate 100 is silicon. In other embodiments, the substrate 100 can also be a germanium substrate, a germanium-silicon substrate, a silicon carbide substrate or a silicon-on-insulator substrate.

[0090] The material of the first semiconductor layer 110 can be the same as that of the substrate 100. In some embodiments, the material of the first semiconductor layer 110 can be silicon, and in other embodiments, the material of the first semiconductor layer 110 can also be a germanium substrate, a silicon-germanium substrate, a silicon carbide substrate, or a silicon-on-insulator substrate.

[0091] The doped regions on both sides of the first channel region 111 constitute the source and the drain of the semiconductor structure. In some embodiments, the doped ions in the doped regions can be different from the type of doped ions in the first channel region 111. Specifically, in some embodiments, the doped ions in the doped regions can be P-type ions, such as at least one of boron ions, indium ions, or gallium ions, and the doped ions in the first channel region 111 can be N-type ions, such as at least one of arsenic ions, phosphorus ions, or antimony ions. In other embodiments, the doped ions in the doped regions can be N-type ions, and the doped ions in the first channel region 111 can be P-type ions.

[0092] It can be understood that in other embodiments, the doped ions in the doped regions can also be the same type as the doped ions in the first channel region 111.

[0093] In some embodiments, the semiconductor structure further comprises a second semiconductor layer 120 and a third semiconductor layer 130 disposed in sequence above the first semiconductor layer 110 away from the substrate 100, and the word line 190 surrounds part of the side surfaces of the second semiconductor layer 120 and the third semiconductor layer 130. Specifically, in some embodiments, the second semiconductor layer 120 has a second channel region and doped regions on opposite sides of the second channel region, and the third semiconductor layer 130 has a third channel region and doped regions on opposite sides of the third channel region. That is, the semiconductor structure has three channels, so that when a voltage is applied to the gate, different channels have the effect of forming a conductive channel, thereby enhancing the control ability of the gate.

[0094] It can be understood that in some embodiments, the doping concentration of the doped ions in the first semiconductor layer 110, the second semiconductor layer 120, and the third semiconductor layer 130 can be equal. When each channel is turned on, the same threshold voltage needs to be applied to form a conductive channel and turn on the source and the drain. Thus, if a channel does not work, other channels can be turned on, so that the semiconductor structure can still work normally, thereby enhancing the control ability of the gate.

[0095] In some embodiments, the doping concentration of the doping ions in the first semiconductor layer 110, the second semiconductor layer 120 and the third semiconductor layer 130 can vary in a stepwise manner. That is, different threshold voltages can be applied to turn on the channels in the first semiconductor layer 110, the second semiconductor layer 120 and the third semiconductor layer 130. For example, a first threshold voltage can be applied to turn on the channel in the first semiconductor layer 110; a second threshold voltage can be applied to turn on the channel in the second semiconductor layer 120; and a third threshold voltage can be applied to turn on the channel in the third semiconductor layer 130. In this way, three different voltages can be applied to the gate to turn on the source and the drain, thereby greatly improving the control ability of the gate.

[0096] In some embodiments, a gate oxide layer 191 can also be included, which surrounds the side surfaces of the first semiconductor layer 110 of the first channel region 111, the second semiconductor layer 120 of the second channel region and the third semiconductor layer 130 of the third channel region. The gate oxide layer 191 is used to isolate the word line 190 from the first semiconductor layer 110 of the first channel region 111, the second semiconductor layer 120 of the second channel region and the third semiconductor layer 130 of the third channel region.

[0097] In some embodiments, a first oxide isolation layer 141 and a second oxide isolation layer 142 can also be included. The first oxide isolation layer 141 is located between the first semiconductor layer 110 and the second semiconductor layer 120, and is used to isolate the first semiconductor layer 110 and the second semiconductor layer 120. The second oxide isolation layer 142 is located between the second semiconductor layer 120 and the third semiconductor layer 130, and is used to isolate the second semiconductor layer 120 and the third semiconductor layer 130.

[0098] In some embodiments, a gate cap layer 160 is also included, which covers the top surface of the word line 190 away from the substrate 100. On the one hand, the gate cap layer 160 isolates the word line 190 from other conductive structures in the semiconductor structure, and on the other hand, the gate cap layer 160 protects the word line 190.

[0099] In some embodiments, a conductive pillar 60 is also included, which is electrically connected to the doped region away from the sidewall of the first semiconductor layer 110 of the first channel region 111, and in a direction perpendicular to the surface of the substrate 100, the distance from the conductive pillar 60 to the substrate 100 is greater than the distance from the word line 190 away from the surface of the substrate 100 to the substrate 100.

[0100] The conductive column 60 is used to lead out the electrical signal of the doped region. It can be understood that, in some embodiments, the semiconductor structure further comprises a second semiconductor layer 120 and a third semiconductor layer 130, and the conductive column 60 is further electrically connected to the sidewall of the second semiconductor layer 120 away from the doped region of the first channel region and the sidewall of the third semiconductor layer 130 away from the doped region of the second channel region. In this way, the conductive column 60 can lead out the electrical signal of the doped region in the first semiconductor layer 110, the second semiconductor layer 120 and the third semiconductor layer 130 at the same time, so that the first channel region 111 in the first semiconductor layer 110, the second channel region in the second semiconductor layer 120 and the third channel region in the third semiconductor layer 130 can jointly control the same conductive device connected to the conductive column 60, thereby enhancing the control ability of the gate.

[0101] In some embodiments, the conductive column 60 can include a first conductive column 61 and a second conductive column 62, and can further include a capacitor structure 70 located on the surface of the first conductive column 61 away from the substrate 100, and a bit line structure 80 located on the surface of the second conductive column 62 away from the substrate 100. The first conductive column 61 is connected to the capacitor structure 70, so that when the semiconductor structure has the first semiconductor layer 110, the second semiconductor layer 120 and the third semiconductor layer 130, the first channel region 111 in the first semiconductor layer 110, the second channel region in the second semiconductor layer 120 and the third channel region in the third semiconductor layer 130 can jointly control the capacitor structure 70, thereby improving the performance of the semiconductor structure.

[0102] Specifically, in some embodiments, the capacitor structure 70 can include a lower electrode layer (not shown), a capacitor dielectric layer (not shown) and an upper electrode layer (not shown) stacked in sequence away from the first conductive column 61. The material of the lower electrode layer and the material of the upper electrode layer can be the same, and the material of the lower electrode layer and the material of the upper electrode layer can be at least one of nickelized platinum, titanium, tantalum, cobalt, polysilicon, copper, tungsten, tantalum nitride, titanium nitride or ruthenium. In other embodiments, the material of the lower electrode layer and the material of the upper electrode layer can also be different. The material of the capacitor dielectric layer includes silicon oxide, tantalum oxide, hafnium oxide, zirconium oxide, niobium oxide, titanium oxide, barium oxide, strontium oxide, yttrium oxide, lanthanum oxide, praseodymium oxide or barium strontium titanate and other high dielectric constant materials.

[0103] In some embodiments, the bit line structure 80 can include a blocking layer 81, a conductive layer 82 and an insulating layer 83 stacked in sequence in a direction away from the second conductive pillar 62. In some embodiments, the conductive layer 82 can be a metal material, for example, can be any one of tungsten, copper or aluminum, in other embodiments, the conductive layer 82 can also be a semiconductor material, for example, can be polysilicon. The blocking layer 81 prevents interdiffusion between the conductive layer 82 and the second conductive pillar 62, the material of the blocking layer 81 can be titanium nitride, and the insulating layer 83 is used to isolate the conductive layer 82 from other conductive devices in the semiconductor structure, the material of the insulating layer 83 can be any one of silicon oxide or silicon nitride.

[0104] In some embodiments, the number of the first semiconductor layers 110 is multiple, and the multiple first semiconductor layers 110 are arranged at intervals, and the multiple first semiconductor layers 110 are connected by the word line 190. In this way, through one word line 190, multiple semiconductor structures can be controlled, which not only saves the space for forming the word line 190, but also is conducive to the miniaturization of the semiconductor structure, and simplifies the process steps for forming the word line 190.

[0105] The semiconductor structure provided by the above embodiments has the first semiconductor layer 110 with the first channel region 111 and the doped region located on the opposite sides of the first channel region 111, the arrangement direction of the first channel region 111 and the doped region is parallel to the surface of the substrate 100; the concentration of the doped ions in the doped region decreases in the direction from the doped region to the first channel region 111; the word line 190 surrounds the side of the first semiconductor layer 110 of the first channel region 111, and the projection of at least part of the doped region of the first semiconductor layer 110 on the surface of the substrate 100 coincides with the projection of the word line 190 on the surface of the substrate 100. The concentration of the doped ions in the doped region decreases in the direction from the doped region to the first channel region 111, that is, the concentration of the doped ions in the doped region far away from the word line 190 is higher. Since the word line 190 is far away from the part of the doped region with higher concentration of doped ions, the influence of the enhanced electric field generated when the gate is turned on on most of the doped ions in the doped region is small, which is conducive to avoiding the risk of leakage current of the doped region under the influence of the strong electric field, thereby improving the control ability of the gate.

[0106] Correspondingly, the embodiments of the present disclosure also provide a memory including the semiconductor structure provided by any one of the above embodiments. In some embodiments, the memory can be any one of DRAM (Dynamic Random Access Memory), SRAM (Static Random-Access Memory) or SDRAM (Synchronous Dynamic Random-Access Memory). For details, refer to Figure 23In the semiconductor structure provided by the above embodiments, the to-be-doped regions 112 on both sides of the first semiconductor layer 110 are doped in the horizontal direction, so that the concentration of the doping ions in the to-be-doped regions decreases in the direction along which the to-be-doped regions point to the first channel region 111, that is, the concentration of the doping ions in the to-be-doped regions far from the word line 190 is higher. Since the word line 190 is far from the to-be-doped regions with higher concentration of the doping ions, the enhanced electric field generated when the gate is turned on has less effect on most of the doping ions in the to-be-doped regions, which is beneficial to avoiding the risk of current leakage of the to-be-doped regions under the influence of the strong electric field, thereby improving the control ability of the gate, and further improving the performance of the memory.

[0107] Those skilled in the art can understand that the above embodiments are specific embodiments for implementing the present disclosure, and in actual applications, various changes can be made in form and details without departing from the spirit and scope of the present disclosure. Any person skilled in the art can make respective changes and modifications without departing from the spirit and scope of the present disclosure, and therefore the protection scope of the present disclosure should be subject to the scope defined by the claims.

Claims

1. A method of fabricating a semiconductor structure, characterized by, The method comprises: providing a substrate; forming a first semiconductor layer on the substrate, the first semiconductor layer having a first channel region and a to-be-doped region located on opposite sides of the first channel region, the arrangement direction of the first channel region and the to-be-doped region being parallel to the surface of the substrate; forming a word line, the word line surrounding the first semiconductor layer side surface of the first channel region, at least part of the projection of the first semiconductor layer of the to-be-doped region coinciding with the projection of the word line on the surface of the substrate; forming a doping bulk, the doping bulk having a first doping ion, the doping bulk being in contact with the end surface of the to-be-doped region away from the first channel region; performing an annealing treatment to diffuse the first doping ion to the to-be-doped region, convert the to-be-doped region into a doped region, and the concentration of the doping ion in the doped region decreases in the direction of the doped region pointing to the first channel region.

2. The method of claim 1, wherein the semiconductor structure is prepared by a method comprising: The step of forming the doping bulk comprises: forming a first via hole, the first via hole penetrating through the first semiconductor layer, and the first via hole exposing part of the end surface of the first semiconductor layer of the to-be-doped region; forming the doping bulk in the first via hole, the doping bulk having a first doping concentration.

3. The method of claim 1, wherein the semiconductor structure is prepared by a method comprising: The first semiconductor layer has a second doping ion, the second doping ion being different from the first doping ion, and the concentration of the second doping ion being a second doping concentration, the concentration of the first doping ion being greater than the second doping concentration.

4. The method of claim 1, wherein the semiconductor structure is prepared by a method comprising: The temperature of the annealing treatment is 500-1000°C.

5. The method of claim 1, wherein the semiconductor structure is prepared by a method comprising: Further comprising: etching the doping bulk by using an etching process to form a second via hole; forming a conductive column in the second via hole, the conductive column being in contact with part of the end surface of the doped region away from the first channel region.

6. The method of claim 1, wherein the semiconductor structure is prepared by a method comprising: The method for forming the word line comprises: forming a first sacrificial layer and a second sacrificial layer, the first sacrificial layer being located on the surface of the first semiconductor layer towards the substrate, and the second sacrificial layer being located on the surface of the first semiconductor layer away from the substrate; removing part of the first sacrificial layer and the second sacrificial layer in contact with the surface of the first semiconductor layer of the first channel region by using an etching process to form a first air layer and a second air layer; depositing a gate material in the first air layer and the second air layer by using a deposition process to form the word line, the word line filling the first air layer and the second air layer.

7. The method of claim 6, wherein the semiconductor structure is prepared by a method comprising: Further comprising forming a gate oxide layer on the surface of the first semiconductor layer of the first channel region.

8. The method of claim 5, wherein the semiconductor structure is prepared by a method comprising: The etching process is a wet etching process.

9. The method of claim 1, wherein Further comprising: forming a second semiconductor layer and a third semiconductor layer on the substrate in sequence, the second semiconductor layer and the third semiconductor layer being located above the first semiconductor layer away from the substrate, and the word line surrounding part of the side surface of the second semiconductor layer and the third semiconductor layer, the first semiconductor layer, the second semiconductor layer and the third semiconductor layer having the same type of doping ion.

10. The method of claim 9, wherein the semiconductor structure is prepared by a method comprising: Further comprising: A first oxide isolation layer is formed between the first semiconductor layer and the second semiconductor layer, and a second oxide isolation layer is formed between the second semiconductor layer and the third semiconductor layer.

11. The method of claim 9, wherein the semiconductor structure is prepared by a method comprising: The doping concentration of the doping ions in the first semiconductor layer, the second semiconductor layer and the third semiconductor layer is equal.

12. The method of claim 9, wherein the semiconductor structure is prepared by a method comprising: The doping concentration of the doping ions in the first semiconductor layer, the second semiconductor layer and the third semiconductor layer is in a step shape.

13. A semiconductor structure, characterized by Comprising: a substrate; a first semiconductor layer on the substrate, the first semiconductor layer having a first channel region and a doped region on opposite sides of the first channel region, the arrangement direction of the first channel region and the doped region being parallel to the substrate surface; the concentration of the doping ions in the doped region decreases in the direction from the doped region to the first channel region; a word line around the side of the first semiconductor layer of the first channel region, and the projection of at least part of the first semiconductor layer of the doped region on the substrate surface coincides with the projection of the word line on the substrate surface.

14. The semiconductor structure of claim 13, wherein, Further comprising: a second semiconductor layer and a third semiconductor layer on the first semiconductor layer away from the substrate and arranged in sequence, and the word line surrounds part of the side of the second semiconductor layer and the third semiconductor layer.

15. The semiconductor structure of claim 14, wherein, Further comprising: a conductive column electrically connected to the side wall of the doped region away from the first channel region of the first semiconductor layer, and in the direction perpendicular to the substrate surface, the distance from the conductive column to the substrate is greater than the distance from the surface of the word line away from the substrate to the substrate.

16. The semiconductor structure of claim 15, wherein, The conductive column comprises a first conductive column and a second conductive column, further comprising: a capacitor structure on the surface of the first conductive column away from the substrate; a bit line structure on the surface of the second conductive column away from the substrate.

17. The semiconductor structure of claim 13, wherein, The number of the first semiconductor layers is multiple, and the multiple first semiconductor layers are arranged at intervals, and the multiple first semiconductor layers are connected by the word line.

18. A memory, comprising: Comprising the semiconductor structure of any one of claims 13 to 17.

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