Electronic device and method of manufacturing the same

Abstract

The present disclosure provides an electronic device and a method of manufacturing the same. The electronic device includes a first insulating layer, a first metal bump disposed on the first insulating layer, and a second insulating layer disposed on the first metal bump, wherein the second insulating layer has a first opening, and the first opening exposes part of the first metal bump, and wherein a thickness of the first insulating layer is greater than a thickness of the second insulating layer.

Description

Technical Field

[0001] This disclosure relates to an electronic device and a method for manufacturing the same, and more particularly to an electronic device and a method for manufacturing the same that improves the effect of roughness. Background Technology

[0002] With technological advancements and in response to consumer demands, most electronic products today are trending towards high integration, meaning a single electronic device can possess multiple functions. More functions in an electronic product necessitate a greater number of chips, which puts a strain on circuit I / O design. This can typically be addressed by re-distributing layers to modify the original circuit I / O design, or by increasing the spacing or number of I / O pins to meet these requirements.

[0003] However, with the increase of process steps, the surface roughness of the metal layers in the circuit also increases, which in turn affects the electrical performance of the electronic device. Therefore, there is an urgent need to provide an electronic device and its fabrication method to improve upon previous shortcomings. Summary of the Invention

[0004] This disclosure provides an electronic device comprising: a first insulating layer; a first metal bump disposed on the first insulating layer; and a second insulating layer disposed on the first metal bump, wherein the second insulating layer has a first opening and the first opening exposes a portion of the first metal bump; wherein the thickness of the first insulating layer is greater than the thickness of the second insulating layer.

[0005] This disclosure also provides a method for manufacturing an electronic device, comprising the following steps: providing a substrate; forming a first insulating layer on the substrate; forming a first metal bump on the first insulating layer; and forming a second insulating layer on the first metal bump, wherein the second insulating layer has a first opening and the first opening exposes a portion of the first metal bump; wherein the thickness of the first insulating layer is greater than the thickness of the second insulating layer. Attached Figure Description

[0006] Figure 1A This is a cross-sectional view of an electronic device according to an embodiment of the present disclosure.

[0007] Figure 1B for Figure 1A A magnified view of a portion of the image.

[0008] Figure 1C for Figure 1A A partially enlarged view of another implementation.

[0009] Figure 2 This is a cross-sectional view of an electronic device according to an embodiment of the present disclosure.

[0010] Figure 3This is a cross-sectional view of an electronic device according to an embodiment of the present disclosure.

[0011] Figure 4A This is a cross-sectional view of an electronic device according to an embodiment of the present disclosure.

[0012] Figure 4B for Figure 4A A magnified view of a portion of the image.

[0013] Figure 5A This is a cross-sectional view of an electronic device according to an embodiment of the present disclosure.

[0014] Figure 5B for Figure 5A A magnified view of a portion of the image.

[0015] Figure 5C for Figure 5A A partially enlarged view of another implementation.

[0016] Figure 6A to Figure 6G This is a cross-sectional view of a method for manufacturing an electronic device according to an embodiment of the present disclosure.

[0017] [Explanation of Labels in the Attached Image]

[0018] 11: First insulating layer

[0019] 111: Lower surface

[0020] 112: Upper surface

[0021] 12: Second insulating layer

[0022] 121: Surface

[0023] 13: First metal layer

[0024] 131: Sidewall

[0025] 14: Third metal layer

[0026] 141: Edge

[0027] 15: Third insulation layer

[0028] 16: Insulation layer

[0029] 17: Second metal layer

[0030] 18, 21: Substrate

[0031] 19: Fourth Insulation Layer

[0032] 191: Lower surface

[0033] 192: Upper surface

[0034] 22, 27, 29: Metallic layer

[0035] 23, 24, 25, 26, 28: Insulation layer

[0036] M1: First metal bump

[0037] M11, M411, M431: Surface

[0038] M12, M21, M412, M432: Sidewall

[0039] M2: Second metal bump

[0040] M3: Third metal bump

[0041] M31, M421: Extension

[0042] M41, M42, M43: Metal bumps

[0043] E: Electronic components

[0044] H1: First opening

[0045] H2: Second opening

[0046] H31, H32: Openings

[0047] R1: First Region

[0048] R2: Second Region

[0049] T1, T2, T3: Thickness

[0050] D1: Distance

[0051] X: First direction

[0052] Z: Normal direction Detailed Implementation

[0053] The following describes the implementation of this disclosure through specific embodiments. Those skilled in the art can easily understand other advantages and effects of this disclosure from the content disclosed in this specification. This disclosure can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified and changed for different viewpoints and applications without departing from the spirit of this disclosure.

[0054] It should be noted that, unless otherwise specified herein, the use of the word "a" in the specification and claims does not imply a single element, but may refer to one or more of the elements. Furthermore, the use of ordinal numbers such as "first" and "second" in the specification and claims to modify elements of a claim does not itself imply or represent any prior ordinal number for that claimed element, nor does it represent the order of one claimed element with another, or the order of manufacture. The use of these ordinal numbers is solely for the purpose of clearly distinguishing a claimed element with a given name from another claimed element with the same name.

[0055] Throughout this disclosure and in the appended claims, certain terms are used to refer to specific elements. Those skilled in the art will understand that electronic device manufacturers may use different names to refer to the same element. This document is not intended to distinguish between elements that have the same function but different names. In the following description and claims, words such as “comprising,” “containing,” and “having” are open-ended terms and should therefore be interpreted as “containing but not limited to…”. Therefore, when the terms “comprising,” “containing,” and / or “having” are used in the description of this disclosure, they specify the presence of the corresponding feature, area, step, operation, and / or component, but do not exclude the presence of one or more of the corresponding feature, area, step, operation, and / or component.

[0056] In this text, the terms "about," "approximately," "substantially," and "roughly" typically indicate within 10%, 5%, 3%, 2%, 1%, or 0.5% of a given value or range. The given quantity is an approximate quantity; that is, even without specific mention of "about," "approximately," "substantially," or "roughly," the meaning of these terms is implied. Furthermore, the phrases "range from the first value to the second value" or "range between the first value and the second value" indicate that the range includes the first value, the second value, and other values ​​in between.

[0057] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by those skilled in the art to which this disclosure is made. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the relevant art and the background or context of this disclosure, and should not be interpreted in an idealized or overly formal manner, unless specifically defined herein.

[0058] Furthermore, relative terms such as "below" or "bottom" and "above" or "top" may be used in the embodiments to describe the relative relationship of one element to another in the figures. It is understood that if the apparatus in the figures is flipped upside down, the element described as being on the "below" side will become the element on the "above" side. When a corresponding component (e.g., a membrane or region) is referred to as "on another component," it can be directly on the other component, or there may be other components between them. On the other hand, when a component is referred to as "directly on another component," there are no components between them. Additionally, when a component is referred to as "on another component," there is a vertical relationship between them in the top view, and this component can be above or below the other component, depending on the orientation of the apparatus.

[0059] In this disclosure, the thickness, length, and width can be measured using an optical microscope, and the thickness can be measured from a cross-sectional image in an electron microscope, but is not limited thereto. Furthermore, any two values ​​or directions used for comparison may have a certain degree of error. If the first value equals the second value, it implies an error of approximately 10% between the first and second values; if the first direction is perpendicular to the second direction, the angle between the first and second directions may be between 80 and 100 degrees; if the first direction is parallel to the second direction, the angle between the first and second directions may be between 0 and 10 degrees.

[0060] It should be noted that the technical solutions provided in the different embodiments below can be substituted for, combined or mixed with each other to constitute another embodiment without violating the spirit of this disclosure.

[0061] Figure 1A This is a cross-sectional view of an electronic device according to an embodiment of the present disclosure. Figure 1B for Figure 1A A magnified view of a portion of the image.

[0062] like Figure 1A and Figure 1B As shown, the electronic device disclosed herein includes: a first insulating layer 11; a first metal bump M1 disposed on the first insulating layer 11; and a second insulating layer 12 disposed on the first metal bump M1, wherein the second insulating layer 12 has a first opening H1, and the first opening H1 exposes a portion of the first metal bump M1; wherein the thickness T1 of the first insulating layer 11 is greater than the thickness T2 of the second insulating layer 12.

[0063] More specifically, such as Figure 1BAs shown, in the Z-direction normal of the electronic device, the second insulating layer 12 partially covers the first metal bump M1. Therefore, in subsequent processes, the second insulating layer 12 can be used to protect the first metal bump M1 (for example, the second insulating layer 12 can have the effect of preventing scratches and / or resisting acids and alkalis), reducing damage to the surface of the first metal bump M1 and improving the electrical performance of the electronic device. In one embodiment of this disclosure, the second insulating layer 12 and the first metal bump M1 may partially overlap in the Z-direction normal of the electronic device. In one embodiment of this disclosure, the second insulating layer 12 may partially cover the surface M11 and / or sidewall M12 of the first metal bump M1, which can improve the reliability of the electronic device. In one embodiment of this disclosure, the second insulating layer 12 may directly contact the surface M11 and / or sidewall M12 of the first metal bump M1 to protect the first metal bump M1, but this disclosure is not limited thereto. In one embodiment of this disclosure, the first metal bump M1 includes a first region R1 and a second region R2, wherein a second insulating layer 12 is disposed corresponding to the first region R1, and a first opening H1 corresponds to the second region R2. More specifically, in the normal direction Z of the electronic device, the first region R1 and the second insulating layer 12 may overlap, while the second region R2 and the second insulating layer 12 do not overlap. The surface roughness of the second region R2 is different from that of the first region R1. In one embodiment of this disclosure, the surface roughness of the second region R2 may be greater than that of the first region R1.

[0064] In addition, such as Figure 1A and Figure 1B As shown, the electronic device of this disclosure may further include a first metal layer 13 disposed between the first insulating layer 11 and the first metal bump M1, and the first metal layer 13 and the first metal bump M1 are electrically connected. In one embodiment of this disclosure, the first metal layer 13 and the first metal bump M1 may be in direct contact. In one embodiment of this disclosure, the first metal layer 13 and the second insulating layer 12 may be in direct contact.

[0065] Figure 1C for Figure 1A A partially enlarged view of another embodiment. Among them, Figure 1C and Figure 1B Similar, except for the following differences.

[0066] like Figure 1CAs shown, the second insulating layer 12 can directly contact the surface M11 and sidewall M12 of the first metal bump M1, and can also contact the sidewall 131 of the first metal layer 13. This reduces the contact between the first metal bump M1 and the first metal layer 13 and the external environment (e.g., air, moisture, chemical reagents, stress, etc.), thereby protecting both the first metal bump M1 and the first metal layer 13, and further improving the electrical performance. In one embodiment of this disclosure, the second insulating layer 12 can directly contact the sidewall 131 of the first metal layer 13.

[0067] In this disclosure, the materials of the first insulating layer 11 and the second insulating layer 12 are not particularly limited, and may be organic materials, inorganic materials, or combinations thereof. Examples of suitable organic materials include polyimide (PI), photosensitive polyimide (PSPI), epoxy resin, polybenzoxazole (PBO), benzocyclobutene (ECB), photoresist, polymers, or combinations thereof, but this disclosure is not limited thereto. Examples of suitable inorganic materials include silicon nitride, silicon oxide, silicon oxynitride, silicon carbonitride, or combinations thereof, but this disclosure is not limited thereto. In one embodiment of this disclosure, the material of the first insulating layer 11 may be different from the material of the second insulating layer 12, thereby suppressing warping. In one embodiment of this disclosure, the material of the first insulating layer 11 may contain organic materials, and the material of the second insulating layer 12 may contain inorganic materials, but this disclosure is not limited thereto. In this disclosure, the thickness T1 of the first insulating layer 11 is, for example, greater than or equal to 5 micrometers (μm) and less than or equal to 25 micrometers, and the thickness T2 of the second insulating layer 12 is, for example, greater than or equal to 0.5 micrometers (μm) and less than or equal to 5 micrometers, but this disclosure is not limited thereto. In this disclosure, the hardness of the second insulating layer 12 may be greater than the hardness of the first insulating layer 11 to provide a protective effect.

[0068] In this disclosure, the materials of the first metal bump M1 and the first metal layer 13 are not particularly limited, and may be, for example, gold (Au), silver (Ag), copper (Cu), palladium (Pd), platinum (Pt), ruthenium (Ru), aluminum (Al), cobalt (Co), nickel (Ni), titanium (Ti), molybdenum (Mo), manganese (Mn), zinc (Zn), their alloys, or combinations thereof, but this disclosure is not limited thereto. Furthermore, the same or different materials may be used to prepare the first metal bump M1 and the first metal layer 13 separately. In one embodiment of this disclosure, the first metal bump M1 may contain copper, and the first metal layer 13 may contain titanium, but this disclosure is not limited thereto. Furthermore, although not shown in the figures, in this disclosure, the first metal layer 13 may be a composite layer, for example, a titanium / copper or nickel / copper composite layer, but this disclosure is not limited thereto.

[0069] In this disclosure, the "thickness T1 of the first insulating layer 11" refers to the maximum thickness of the first insulating layer 11 from its lower surface 111 to its upper surface 112 along the normal direction Z of the electronic device. The "thickness T2 of the second insulating layer 12" refers to the maximum thickness of the second insulating layer 12 at the point where it overlaps with the first metal bump M1 along the normal direction Z of the electronic device; or, "thickness T2 of the second insulating layer 12" may also refer to the maximum thickness from the surface M11 of the first metal bump M1 to the surface 121 of the second insulating layer 12. In this disclosure, the first insulating layer 11, the first metal bump M1, and the second insulating layer 12 are stacked along the normal direction Z of the electronic device.

[0070] In this disclosure, such as Figure 1A As shown, the electronic device may further include a third metal layer 14 disposed below the first insulating layer 11; a second metal bump M2 disposed on the third metal layer 14, wherein the second metal bump M2 is electrically connected to the first metal bump M1; and a third insulating layer 15 disposed on the second metal bump M2, wherein the third insulating layer 15 has a second opening H2, and the second opening H2 exposes a portion of the surface of the second metal bump M2. Therefore, the second metal bump M2 can be electrically connected to the first metal bump M1 through the second opening H2 of the third insulating layer 15. In the normal direction Z of the electronic device, the third insulating layer 15 may cover a portion of the second metal bump M2; more specifically, the third insulating layer 15 and the second metal bump M2 may partially overlap. Therefore, in subsequent processes, the third insulating layer 15 can be used to protect the second metal bump M2, reduce damage to the surface of the second metal bump M2, and improve the electrical performance of the electronic device. Furthermore, the third insulating layer 15 may cover the sidewall M21 of the second metal bump M2, thereby improving the protective effect of the second metal bump M2 or enhancing the reliability of the electronic device. In one embodiment of this disclosure, the third insulating layer 15 may be in direct contact with the sidewall M21 of the second metal bump M2, but this disclosure is not limited thereto.

[0071] In this disclosure, the material of the third metal layer 14 is similar to that of the first metal layer 13; the material of the second metal bump M2 is similar to that of the first metal bump M1; and the material of the third insulating layer 15 may be similar to that of the second insulating layer 12, which will not be described in detail here. In one embodiment of this disclosure, the second metal bump M2 may contain copper, and the third metal layer 14 may contain titanium, but this disclosure is not limited thereto. Furthermore, similar to the first metal layer 13, the third metal layer 14 may also be a composite layer, such as a titanium / copper or nickel / copper composite layer, but this disclosure is not limited thereto.

[0072] In this disclosure, such as Figure 1AAs shown, the device may further include multiple third metal bumps M3, disposed between the first metal bump M1 and the second metal bump M2, and the first metal bump M1 can be electrically connected to the second metal bump M2 through the multiple third metal bumps M3. In this embodiment, it may also include an extension M31 connected to the third metal bumps M3, and the multiple third metal bumps M3 can be electrically connected to each other through the extension M31, and the second metal bump M2 is also electrically connected to the third metal bumps M3 through the extension M31. An insulating layer 16 may be provided above one of the multiple third metal bumps M3 or the extension M31 connected to it, and the insulating layer 16 can directly contact one of the multiple third metal bumps M3 or the extension M31 connected to it, and partially cover the surface of one of the multiple third metal bumps M3 or the extension M31 connected to it. In this embodiment, the insulating layer 16 can cover the surface of the third metal bumps M3 and partially cover the surface of the extension M31 connected to the third metal bumps M3. Therefore, the insulating layer 16 can be used to reduce the risk of damage to the surface of the plurality of third metal bumps M3.

[0073] Figure 2 This is a cross-sectional view of an electronic device according to an embodiment of the present disclosure. Wherein, Figure 2 electronic devices and Figure 1A Similar, except for the following differences.

[0074] In one embodiment of this disclosure, the electronic device may further include an electronic component E disposed on the second insulating layer 12, wherein the electronic component E is electrically connected to the first metal bump M1. More specifically, the electronic component E may be electrically connected to the first metal bump M1 through the first opening H1 of the second insulating layer 12. Here, the electronic component E may include a circuit board, an integrated circuit (IC), an active component, a passive component, etc., but this disclosure is not limited thereto. In addition, the electronic device of this disclosure may also include a second metal layer 17 disposed on the first metal bump M1 and located in the first opening H1 of the second insulating layer 12. Therefore, the electronic component E may be electrically connected to the first metal bump M1 through the second metal layer 17. In this disclosure, the second metal layer 17 may include nickel, gold, or a combination thereof, but this disclosure is not limited thereto. Furthermore, similar to the first metal layer 13, the second metal layer 17 may also be a composite layer, for example, a nickel / gold composite layer, but this disclosure is not limited thereto. In one embodiment of this disclosure, the first metal bump M1 may be, for example, a bonding pad electrically connected to the electronic component E, but is not limited thereto. Furthermore, the electronic component E is electrically connected to other components (e.g., circuit boards, redistribution layers, passive components, and other suitable components) via the bonding pad.

[0075] Figure 3 This is a cross-sectional view of an electronic device according to an embodiment of the present disclosure. Wherein, Figure 3 electronic devices and Figure 1A Similar, except for the following differences.

[0076] like Figure 3 As shown, in this disclosure, the electronic device may further include a second metal layer 17 disposed on the first metal bump M1 and located in the first opening H1 of the second insulating layer 12. Therefore, electronic components (not shown) can be electrically connected to the first metal bump M1 through the second metal layer 17. Here, the material of the second metal layer 17 is similar to that of the first metal layer 13, and will not be described again. In one embodiment of this disclosure, the second metal layer 17 may contain nickel, gold, or a combination thereof, but this disclosure is not limited thereto. In this disclosure, similar to the first metal layer 13, the second metal layer 17 may also be a composite layer, for example, a nickel / gold composite layer, but this disclosure is not limited thereto.

[0077] Furthermore, in this disclosure, the electronic device may also include a substrate 18 disposed below the first insulating layer 11. Here, the substrate 18 may be a quartz substrate, glass substrate, wafer, sapphire substrate, rigid-flex PCB, or other rigid substrate. Alternatively, the substrate 18 may also be a flexible substrate or film, and its material may include polycarbonate (PC), polyimide (PI), polypropylene (PP), polyethylene terephthalate (PET), or other plastic materials, but this disclosure is not limited thereto. Although not shown in the figures, in this disclosure, the substrate 18 may also include electronic components such as circuits, transistors, active components, and passive components. Therefore, the substrate 18 of this disclosure can be integrated with the electronic components thereon into a circuit board or integrated circuit, but this disclosure is not limited thereto.

[0078] Figure 4A This is a cross-sectional view of an electronic device according to an embodiment of the present disclosure. Figure 4B for Figure 4A A partially enlarged image. Among them, Figure 4A electronic devices and Figure 3 Similar, except for the following differences.

[0079] like Figure 4A and Figure 4B As shown, a third metal layer 14 is disposed on the substrate 18, wherein the third metal layer 14 extends along the first direction X and extends beyond the sidewall M21 of the second metal bump M2. Furthermore, a third insulating layer 15 may also extend along the first direction X and extend beyond the sidewall M21 of the second metal bump M2. Here, the "first direction" refers to a direction perpendicular to the normal direction Z of the electronic device.

[0080] In addition, such as Figure 4BAs shown, the electronic device of this disclosure further includes a fourth insulating layer 19 disposed on the third insulating layer 15, wherein a portion of the fourth insulating layer 19 extends into the second opening H2 and contacts the second metal bump M2. Here, the material of the fourth insulating layer 19 may be similar to that of the first insulating layer 11, and will not be described in detail here. According to some embodiments of this disclosure, the thickness T3 of the fourth insulating layer 19 is, for example, greater than or equal to 8 micrometers (μm) and less than or equal to 30 micrometers, that is, the thickness T3 of the fourth insulating layer 19 may be different from the thickness T1 of the first insulating layer 11. This design can, for example, improve the warpage of the electronic device, but is not limited thereto. In this disclosure, the "thickness T3 of the fourth insulating layer 19" refers to the maximum thickness of the fourth insulating layer 19 from its lower surface 191 to its upper surface 192 in the normal direction Z of the electronic device.

[0081] Figure 5A This is a cross-sectional view of an electronic device according to an embodiment of the present disclosure. Figure 5B for Figure 5A A partially enlarged image. Among them, Figure 5A electronic devices and Figure 4A Similar, except for the following differences.

[0082] like Figure 5A and Figure 5B As shown, a third metal layer 14 is disposed on the substrate 18, wherein the third metal layer 14 extends along a first direction X, and in the normal direction Z of the electronic device, the third metal layer 14 overlaps with the second metal bump M2 or the third insulating layer 15. More specifically, in the first direction X, the third metal layer 14 extends beyond the sidewall M21 of the second metal bump M2, and the distance D1 from the sidewall M21 of the second metal bump M2 to the edge 141 of the third metal layer 14 is 1 micrometer (μm) to 10 micrometers (μm).

[0083] Figure 5C for Figure 5A A partially enlarged view of another embodiment. Among them, Figure 5C and Figure 5B Similar, except for the following differences. Figure 5C As shown, the fourth insulating layer 19 is disposed on the third insulating layer 15. The fourth insulating layer 19 is not disposed in the second opening H2 and is not in contact with the second metal bump M2. This improves the reliability of the electronic device when there is poor adhesion between the material used in the fourth insulating layer 19 and the second metal bump M2.

[0084] Figure 6A to Figure 6G This is a cross-sectional view of a method for fabricating an electronic component according to an embodiment of the present disclosure.

[0085] like Figure 6AAs shown, a substrate 21 is provided. Next, a metal layer 22 is formed on the substrate 21. In one embodiment of this disclosure, although not shown, when a subsequent step includes removing the substrate 21, a release layer may be formed on the substrate 21 before the step of forming the metal layer 22 on the substrate. Here, the release layer may be an adhesive, epoxy resin, die attach film (DAF), or the like, but this disclosure is not limited thereto. The release layer can be used in the subsequent step of removing the substrate 21. Then, metal bumps M41 are formed on the metal layer 22. Next, an insulating layer 23 is formed on the metal bumps M41 and the metal layer 22.

[0086] Subsequently, as Figure 6B As shown, the patterned insulating layer 23 forms an opening H31 to expose a portion of the metal bump M41 and a portion of the metal layer 22. The insulating layer 23 can cover the surface M411 and sidewalls M412 of the metal bump M41, thus protecting the metal bump M41 in subsequent processes and improving the electrical performance or reliability of the electronic device. For example, the design of the insulating layer 23 can protect the metal bump M41 from scratches and corrosion during electroplating, etching, laser processing, or other electronic device manufacturing processes, preventing increased roughness and thus affecting the electrical characteristics or reliability of the electronic device.

[0087] Next, the patterned metal layer 22 is formed as follows: Figure 6C The structure shown. In some embodiments of this disclosure, the steps of patterning the insulating layer 23 and the patterned metal layer 22 can be omitted, and the resulting electronic device can, for example... Figure 4A As shown. Since the steps of patterning the insulating layer 23 and the metal layer 22 can be omitted, in Figure 4A In the middle, the third metal layer 14 and the third insulating layer 15 can extend along the first direction X and exceed the sidewall M21 of the second metal bump M2.

[0088] Subsequently, as Figure 6D As shown, an insulating layer 24 is formed on the insulating layer 23. In this disclosure, it can be as follows... Figure 5B As shown in the fourth insulating layer 19, the insulating layer 24 can extend into the opening H31 (e.g. Figure 6C As shown), it is in contact with the metal bump M41. Alternatively, it can be as follows: Figure 5C As shown in the fourth insulating layer 19, insulating layer 24 is disposed on insulating layer 23, but not in opening H31 (as shown in the image). Figure 6C As shown in the figure, it is not in contact with the metal bump M41.

[0089] Next, the aforementioned steps can be selectively repeated to form a plurality of metal bumps M42 on the substrate 21, wherein one of the plurality of metal bumps M42 can be electrically connected to a metal bump M41. Furthermore, while forming the plurality of metal bumps M42, extensions M421 connected to the plurality of metal bumps M42 can also be formed, and the plurality of metal bumps M42 can be electrically connected to each other through the extensions M421. In this disclosure, an insulating layer 25 may also be provided above one of the plurality of metal bumps M42 or the extension M421 connected to it. The insulating layer 25 can directly contact one of the plurality of metal bumps M42 or the extension M421 connected to it, and partially cover the surface of one of the plurality of metal bumps M42 or the extension M421 connected to it. In this embodiment, the insulating layer 25 can cover the surface of the metal bumps M42 and partially cover the surface of the extension M421 connected to the metal bumps M42. Therefore, it can be used to protect the surface of the plurality of metal bumps M42, preventing damage to the surface of the plurality of metal bumps M42. Then, as... Figure 6D As shown, an insulating layer 26 is formed on the substrate 21; and a metal layer 27 is formed on the insulating layer 26.

[0090] Next, as Figure 6E As shown, a metal bump M43 is formed on the metal layer 27, wherein the metal bump M43 can be electrically connected to one of a plurality of metal bumps M42. More specifically, the metal bump M43 can be electrically connected to an extension M421 connected to one of the plurality of metal bumps M42 through the metal layer 27. Then, as... Figure 6E As shown, an insulating layer 28 is formed on the metal bump M43 and the metal layer 27. Here, the thickness of the insulating layer 28 may be less than the thickness of the insulating layer 26. Furthermore, although not shown in the figures, in another embodiment of this disclosure, a step of patterning the metal layer 27 may be included before the step of forming the insulating layer 28 on the metal bump M43 and the metal layer 27. Therefore, the subsequently formed insulating layer 28 can contact the sidewalls of the metal layer 27 to form, for example... Figure 1C The electronic device shown.

[0091] Subsequently, as Figure 6F As shown, the patterned insulating layer 28 forms an opening H32 to expose a portion of the metal bump M43; and the patterned metal layer 27 can form as shown in the diagram. Figure 5A The electronic device shown. Here, the insulating layer 28 can cover part of the surface M431 of the metal bump M43 and the sidewall M432 of the metal bump M43. Therefore, the insulating layer 28 can protect the metal bump M43 in the step of patterning the metal layer 27 and improve the electrical performance of the electronic device.

[0092] In one embodiment of the preparation method disclosed herein, such as Figure 6GAs shown, a metal layer 29 may be selectively included in the opening H32 to form as shown. Figure 3 The electronic device shown. Furthermore, although not shown in the figures, in one embodiment of the manufacturing method of this disclosure, the step of removing substrate 21 may also be included to form, for example... Figure 1A The electronic device shown. Furthermore, although not shown in the figures, in another embodiment of the manufacturing method of this disclosure, the method may further include the steps of setting electronic components on the insulating layer 28 and the metal layer 29; and removing the substrate 21 to form, for example... Figure 2 The electronic device shown allows electronic components to be electrically connected to metal bumps M43 via a metal layer 29 disposed in an opening H32.

[0093] In this disclosure, there are no particular limitations on the conditions for forming the metal layers 22, 27, 29 and the metal bumps M41, M42, M43. For example, sputtering, electroplating, chemical plating, chemical vapor deposition, or combinations thereof can be used, but this disclosure is not limited to these methods. Furthermore, different metal layers 22, 27, 29 and / or metal bumps M41, M42, M43 can be prepared using the same or different methods. In this disclosure, there are no particular limitations on the materials used for the metal layers 22, 27, 29 and the metal bumps M41, M42, M43. For example, they can be gold, silver, copper, palladium, platinum, ruthenium, aluminum, cobalt, nickel, titanium, molybdenum, manganese, zinc, their alloys, or combinations thereof, but this disclosure is not limited to these methods. Furthermore, the same or different materials can be used to prepare the metal layers 22, 27, 29 and the metal bumps M41, M42, M43 separately.

[0094] In this disclosure, there are no particular limitations on the methods used to form insulating layers 23, 24, 25, 26, and 28. For example, dip coating, spin coating, roller coating, blade coating, spray coating, deposition, or combinations thereof can be used, but this disclosure is not limited thereto. Furthermore, different insulating layers 23, 24, 25, 26, and 28 can be prepared using the same or different methods. In this disclosure, there are no particular limitations on the materials used for insulating layers 23, 24, 25, 26, and 28. For example, they can be organic materials, inorganic materials, or combinations thereof. Suitable examples of organic materials include polyimide (PI), photosensitive polyimide (PSPI), epoxy resin, polybenzoxazole (PBO), benzocyclobutene (ECB), photoresist, polymers, or combinations thereof, but this disclosure is not limited thereto. Suitable examples of inorganic materials may be silicon nitride, silicon oxide, silicon oxynitride, silicon carbonitride, or combinations thereof, but this disclosure is not limited thereto. In one embodiment of this disclosure, the materials of insulating layers 23, 25, and 28 may differ from the materials of insulating layers 24 and 26, thereby suppressing warping. In one embodiment of this disclosure, the materials of insulating layers 23, 25, and 28 may comprise inorganic materials, and the materials of insulating layers 24 and 26 may comprise organic materials, but this disclosure is not limited thereto.

[0095] In this disclosure, insulating layers 23, 24, 25, 26, and 28 can be patterned using photolithography, but this disclosure is not limited thereto. Furthermore, portions of metal layers 22 and 27 can be removed using etching methods, including wet etching, dry etching, or combinations thereof, but this disclosure is not limited thereto.

[0096] In summary, this disclosure, by forming an insulating layer on the metal bumps, can protect the metal bumps in subsequent processes, thereby improving the electrical performance or reliability of the electronic device.

[0097] In this disclosure, the electronic device may be, for example, an electronic device comprising redistribution layers and packaged elements, such as fan-out panel level package (FOPLP) elements or 2.5D packaged elements, but this disclosure is not limited thereto. The electronic device may include a display device, an antenna device, a sensing device, or a splicing device, but this disclosure is not limited thereto. The manufacturing method of the fan-out panel package element may include a redistribution layer first process and a chip first process.

[0098] The specific embodiments described above should be interpreted as merely illustrative and not as limiting the remainder of this disclosure in any way. Features of different embodiments may be combined and used in combination as long as they do not conflict with each other.

Claims

1. An electronic device, characterized in that, Include: First insulating layer; A first metal bump is disposed on the first insulating layer; as well as A second insulating layer is disposed on the first metal bump, wherein the second insulating layer has a first opening and the first opening exposes a portion of the first metal bump; A third metal layer is disposed below the first insulating layer; A second metal bump is disposed on the third metal layer, wherein the second metal bump is electrically connected to the first metal bump; A third insulating layer is disposed on the second metal bump, wherein the third insulating layer has a second opening, and the second opening exposes a portion of the second metal bump; and A fourth insulating layer is disposed on the third insulating layer, wherein the fourth insulating layer extends into the second opening and contacts the second metal protrusion; The thickness of the first insulating layer is greater than the thickness of the second insulating layer, and the electronic device further includes: A third metal bump and an extension connected to the third metal bump, a fifth insulating layer is provided above the third metal bump, the fifth insulating layer covers the surface of the third metal bump, and the third metal bump is electrically connected to the first metal bump through the extension.

2. The electronic device according to claim 1, characterized in that, The material of the first insulating layer is different from the material of the second insulating layer.

3. The electronic device according to claim 1, characterized in that, It also includes electronic components disposed on the second insulating layer, wherein the electronic components are electrically connected to the first metal bump.

4. The electronic device according to claim 1, characterized in that, The second insulating layer covers the sidewall of the first metal bump.

5. The electronic device according to claim 1, characterized in that, It also includes a first metal layer disposed between the first insulating layer and the first metal bump.

6. The electronic device according to claim 1, characterized in that, It also includes a second metal layer disposed on the first metal bump and located in the first opening of the second insulating layer.

7. A method for manufacturing an electronic device, characterized in that, Includes the following steps: Provide substrate; A third metal layer is formed on the substrate; A second metal bump is formed on the third metal layer; A third insulating layer is formed on the second metal bump, wherein the third insulating layer has a second opening and the second opening exposes a portion of the second metal bump; A fourth insulating layer is formed on the third insulating layer, wherein the fourth insulating layer extends and is disposed in the second opening and contacts the second metal bump; A first insulating layer is formed on the substrate; A first metal bump is formed on the first insulating layer; and A second insulating layer is formed on the first metal bump, wherein the second insulating layer has a first opening and the first opening exposes a portion of the first metal bump; The thickness of the first insulating layer is greater than the thickness of the second insulating layer; The method also includes: Multiple third metal bumps and connecting extensions are formed on the second metal bump; A fifth insulating layer is formed on the third metal bump, which is electrically connected to the first metal bump through the extension.

8. The method according to claim 7, characterized in that, The material of the first insulating layer is different from the material of the second insulating layer.

9. The method according to claim 7, characterized in that, The second insulating layer covers the sidewall of the first metal bump.

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