A gallium nitride Schottky diode integrating a MISFET gate control function and a field plate function and a manufacturing method thereof

Abstract

This invention discloses a gallium nitride Schottky diode integrating MISFET gate control and field plate functions, comprising a substrate layer, a gallium nitride layer, and a barrier layer connected in sequence; a portion of the gallium nitride layer and the barrier layer is removed to form a groove region, within which an insulating layer and an ohmic metal layer are locally distributed; an insulating layer and an ohmic metal layer are disposed above the barrier layer outside the groove region; a Schottky metal layer is disposed above the insulating layer and the ohmic metal layer within the groove region; a Schottky metal layer is disposed above the insulating layer outside the groove region; a passivation layer is disposed above the Schottky metal layer, the barrier layer, and the ohmic metal layer; within the groove region, the Schottky metal layer, the insulating layer, and the gallium nitride layer form a metal-insulator-semiconductor field-effect transistor (MISFET) gate control structure; outside the groove region, the insulating layer and the Schottky metal layer form a field plate structure. This invention reduces the device's turn-on voltage, increases its breakdown voltage, and reduces leakage current, thereby improving the device's electrical performance.

Description

Technical Field

[0001] This invention relates to a gallium nitride Schottky diode integrating MISFET gate control function and field plate function, and its fabrication method, belonging to the field of semiconductor technology. Background Technology

[0002] As a core component of power electronic systems, semiconductor power diodes are widely used in many fields such as wind power, photovoltaics, home appliances, industrial control, and new energy, mainly playing key roles in amplitude modulation and frequency conversion, rectification and amplification, and power control. Compared with traditional silicon-based Schottky diodes, gallium nitride-based Schottky diodes have superior characteristics such as fast switching speed, low on-resistance, and good high-temperature stability, making them ideal components for improving the output power of power electronic systems, reducing power loss, and improving conversion efficiency.

[0003] Due to the advantages of heterogeneous substrates, such as large area and low cost, most gallium nitride Schottky diodes are currently fabricated on heterogeneous substrates, such as sapphire and silicon substrates. However, significant lattice and thermal mismatches exist between the heterogeneous substrate and the gallium nitride material, resulting in numerous defects in the grown gallium nitride epitaxial material and affecting the electrical performance of the device.

[0004] To improve the electrical performance of gallium nitride Schottky diodes, existing technologies utilize trench etching to directly contact the Schottky metal with the two-dimensional electron gas at the gallium nitride heterojunction interface, such as... Figure 1 As shown, although this structure reduces the device's turn-on voltage and on-resistance to some extent, it causes the reverse leakage current of the device to increase sharply and the breakdown voltage to decrease, which cannot meet the actual power application requirements. Summary of the Invention

[0005] The purpose of this invention is to address the shortcomings of the prior art by providing a gallium nitride Schottky diode integrating MISFET gate control and field plate functions, and its fabrication method. By integrating the MISFET gate control structure and the field plate structure into the gallium nitride Schottky diode, the MISFET gate control structure regulates channel electron conduction, and the field plate structure alleviates the electric field at the anode edge. This not only reduces the device's turn-on voltage but also increases its breakdown voltage and reduces leakage current. Furthermore, this structure utilizes the contact between the MISFET gate control structure and the sidewall of the etched groove to mitigate the impact of material damage caused by groove etching on device performance. The fabrication method is simple, providing a solution for improving the electrical performance of gallium nitride Schottky diodes.

[0006] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows:

[0007] A gallium nitride Schottky diode integrating MISFET gate control and field plate functions comprises, from bottom to top, a substrate layer, a gallium nitride layer, and a barrier layer connected in sequence; a portion of the gallium nitride layer and the barrier layer is removed to form a groove region, within which a locally distributed insulating layer and a locally distributed ohmic metal layer are disposed; an insulating layer and an ohmic metal layer are disposed above the barrier layer outside the groove region; a Schottky metal layer is disposed above the insulating layer and the ohmic metal layer within the groove region; a Schottky metal layer is disposed above the insulating layer outside the groove region, and a passivation layer is disposed above the Schottky metal layer, the barrier layer, and the ohmic metal layer; within the groove region, the Schottky metal layer, the insulating layer, and the gallium nitride layer form a metal-insulator-semiconductor field-effect transistor (MISFET) gate control structure; outside the groove region, the insulating layer and the Schottky metal layer form a field plate structure.

[0008] In the above structure, the MISFET gate structure is in contact with the sidewall of the groove region; within the groove region, the ohmic metal layer and the gallium nitride layer form a locally distributed ohmic contact.

[0009] Within the groove area, the insulating layer and the ohmic metal layer completely cover the bottom of the groove area, or the insulating layer and the ohmic metal layer do not completely cover the bottom of the groove area;

[0010] Within the groove region, when the insulating layer and the ohmic metal layer completely cover the bottom of the groove region, the locally distributed ohmic contacts formed by the ohmic metal layer and the gallium nitride layer are connected in parallel with the MISFET gate control structure.

[0011] Within the groove region, when the insulating layer and the ohmic metal layer do not completely cover the bottom of the groove region, the locally distributed ohmic contacts formed by the ohmic metal layer and the gallium nitride layer, the MISFET gate structure, and the locally distributed Schottky contacts formed by the Schottky metal layer and the gallium nitride layer are connected in parallel.

[0012] To further improve the electrical performance of the device, the bottom of the groove extends 1-5 nm into the gallium nitride layer.

[0013] The aforementioned insulating layer is formed by one of the following materials: silicon dioxide, silicon nitride, and aluminum oxide, forming a single insulating layer or multiple materials forming a multilayer insulating layer; the Schottky metal layer is formed by one of the following materials: nickel, gold, tungsten, molybdenum, and platinum, forming a single metal layer or multiple materials forming a multilayer metal layer.

[0014] In this application, "more" means two or more.

[0015] To better improve the electrical performance of the device, the thickness of the insulating layer is 0.1-5 nm, and the thickness of the passivation layer is 500-2000 nm.

[0016] This invention provides a method for fabricating gallium nitride Schottky diodes that integrate MISFET gate control and field plate functions, offering two technical solutions:

[0017] Technical Solution 1, a method for fabricating a gallium nitride Schottky diode integrating MISFET gate control and field plate functions, includes the following steps:

[0018] (1) The epitaxial wafer consists of a substrate layer, a gallium nitride layer and a barrier layer from bottom to top. The inductively coupled plasma dry etching method is used to remove part of the gallium nitride layer and the barrier layer to form a groove region.

[0019] (2) Using photolithography lift-off method, ohmic metal layers with local distribution are deposited simultaneously in the groove area and outside the groove area, and then subjected to high temperature annealing at 800-900℃ to form ohmic contacts.

[0020] (3) An insulating layer is grown. The growing insulating layer is partially removed by photolithography, and an insulating layer is formed locally distributed both inside and outside the groove area.

[0021] (4) Using photolithography to lift off the substrate, a Schottky metal layer is deposited or sputtered in and outside the groove area, and then subjected to low-temperature annealing. After that, a passivation layer is covered to complete the diode fabrication.

[0022] In step (1) above, after the groove area is formed, the etching damage in the groove area needs to be repaired. The repair method is to put the epitaxial wafer into a tetramethylammonium hydroxide solution with a mass concentration of 20-30% and heat it in a water bath at 60-85°C for 100-500 seconds, and / or put the epitaxial wafer into a nitrogen atmosphere at 300-400°C for 60-200 seconds of low-temperature annealing.

[0023] In steps (2), (3), and (4), the photolithography stripping method is as follows: first, the non-patterned area is covered with photoresist, then an insulating layer or metal layer is covered on the entire epitaxial wafer, and the insulating layer or metal layer in the non-patterned area is removed by stripping method, leaving an insulating layer or metal layer in the patterned area.

[0024] In step (3), the insulating layer is grown by atomic layer deposition, plasma-enhanced chemical vapor deposition, or low-pressure chemical vapor deposition.

[0025] In step (4), the annealing conditions for the Schottky metal layer are: annealing at 300-400℃ for 60-200 seconds in a nitrogen atmosphere.

[0026] Technical Solution 2, a method for fabricating a gallium nitride Schottky diode integrating MISFET gate control and field plate functions, includes the following steps:

[0027] Step 1: The epitaxial wafer consists of a substrate layer, a gallium nitride layer, and a barrier layer from bottom to top. The inductively coupled plasma dry etching method is used to remove a portion of the gallium nitride layer and the barrier layer, thereby forming a groove region.

[0028] Step 2: An insulating layer is grown on the entire epitaxial wafer. Photolithography is used to cover the patterned area with photoresist. Inductively coupled plasma dry etching is used to etch the non-patterned areas that are not protected by photoresist. Finally, an insulating layer with localized distribution is formed both inside and outside the groove area.

[0029] Step 3: Using photolithography lift-off, a locally distributed ohmic metal layer is deposited simultaneously in and outside the groove area, and then subjected to high-temperature annealing at 800-900℃ to form an ohmic contact.

[0030] Step 4: Using photolithography to lift off the substrate, deposit or sputter a Schottky metal layer in and outside the groove area, perform low-temperature annealing, and then cover it with a passivation layer to complete the diode fabrication.

[0031] In step one above, after the groove area is formed, the etching damage in the groove area needs to be repaired. The repair method is as follows: put the epitaxial wafer into a tetramethylammonium hydroxide solution with a mass concentration of 20-30% and heat it in a water bath at 60-85°C for 100-500 seconds, and / or put the epitaxial wafer into a nitrogen atmosphere and perform low-temperature annealing treatment at 300-400°C for 60-200 seconds.

[0032] In step two, the insulating layer is grown by atomic layer deposition, plasma-enhanced chemical vapor deposition, or low-pressure chemical vapor deposition.

[0033] In steps three and four, the photolithography stripping method is as follows: first, cover the non-patterned area with photoresist, then cover the entire epitaxial wafer with an insulating layer or metal layer, and use the stripping method to remove the insulating layer or metal layer in the non-patterned area, leaving the insulating layer or metal layer in the patterned area.

[0034] In step four, the annealing conditions for the Schottky metal layer are: annealing at 300-400℃ for 60-200 seconds in a nitrogen atmosphere.

[0035] This invention relates to a gallium nitride Schottky diode that integrates MISFET gate control and field plate functions, effectively solving the problems of high turn-on voltage, low breakdown voltage, and large leakage current in existing gallium nitride Schottky diodes.

[0036] Any techniques not mentioned in this invention are based on existing technologies.

[0037] This invention relates to a gallium nitride Schottky diode that integrates MISFET gate control and field plate functions. By utilizing the MISFET gate control structure to regulate channel electron conduction and the field plate structure to alleviate the electric field at the anode edge, the device's turn-on voltage is reduced, while its breakdown voltage is increased and leakage current is reduced. Furthermore, the structure utilizes the contact between the MISFET gate control structure and the sidewall of the etched groove to mitigate the impact of material damage caused by groove etching on device performance. The fabrication method is simple, providing a solution for improving the electrical performance of gallium nitride Schottky diodes. Attached Figure Description

[0038] Figure 1 This is a schematic diagram of the structure of a gallium nitride Schottky diode in the prior art;

[0039] Figure 2 This is a schematic diagram of the first structure of the gallium nitride Schottky diode integrating MISFET gate control function and field plate function according to the present invention;

[0040] Figure 3 This is a schematic diagram of the second structure of the gallium nitride Schottky diode integrating MISFET gate control function and field plate function according to the present invention;

[0041] Figure 4 This is a schematic diagram of the process for fabricating a gallium nitride Schottky diode integrating MISFET gate control function and field plate function for technical solution one of the present invention;

[0042] Figure 5 A schematic diagram of the process for fabricating a gallium nitride Schottky diode integrating MISFET gate control function and field plate function for technical solution two of the present invention; Detailed Implementation

[0043] To better understand the present invention, the following embodiments further illustrate the content of the present invention, but the content of the present invention is not limited to the following embodiments.

[0044] The directional terms "upper" and "lower" used in this application are based on the orientation or positional relationship shown in the attached drawings and are used only for ease of description. They should not be construed as limitations on this application.

[0045] Example 1

[0046] like Figure 2As shown, a gallium nitride Schottky diode integrating MISFET gate control and field plate functions includes, from bottom to top, a substrate layer 1, a gallium nitride layer 2, and a barrier layer 3 connected in sequence. Partial areas of the gallium nitride layer 2 and the barrier layer 3 are removed to form a groove region. An insulating layer 4 and an ohmic metal layer 5 are locally distributed within the groove region. Outside the groove region, the insulating layer 4 and the ohmic metal layer 5 are disposed above the barrier layer 3. Within the groove region, a Schottky metal layer 6 is disposed above the insulating layer 4 and the ohmic metal layer 5. Outside the groove region, a Schottky metal layer 6 is disposed above the insulating layer 4. A passivation layer 7 is disposed above the Schottky metal layer 6, the barrier layer 3, outside the groove region, and above the ohmic metal layer 5. Within the groove region, the Schottky metal layer 6, the insulating layer 4, and the gallium nitride layer 2 form a metal-insulator-semiconductor field-effect transistor (MISFET) gate control structure. Outside the groove region, the insulating layer 4 and the Schottky metal layer 6 form a field plate structure.

[0047] The MISFET gate structure is in contact with the sidewall of the recessed region; within the recessed region, the ohmic metal layer 5 and the gallium nitride layer 2 form locally distributed ohmic contacts. Within the recessed region, the locally distributed ohmic contacts formed by the ohmic metal layer 5 and the gallium nitride layer 2 are connected in parallel with the MISFET gate structure formed by the Schottky metal layer 6, the insulating layer 4, and the gallium nitride layer 2 within the recessed region.

[0048] like Figure 4 and Figure 5 As shown, the gallium nitride Schottky diode integrating MISFET gate control and field plate functions is fabricated according to two schemes:

[0049] Option 1: The insulating layer 4 is made of silicon nitride, with a thickness of 2 nm. The bottom of the groove region extends 1 nm into the gallium nitride layer 2. The fabrication method includes the following steps:

[0050] Step 1: Etching the groove area, such as... Figure 4 As shown in Figure a, the epitaxial wafer structure includes, from bottom to top, a substrate layer 1, a gallium nitride layer 2, and a barrier layer 3 connected in sequence. The substrate layer 1 is made of silicon (or sapphire or silicon carbide substrates) and has a thickness of 650 μm. The gallium nitride layer 2 has a thickness of 3.3 μm and the barrier layer 3 has a thickness of 23 nm.

[0051] The non-patterned areas were protected with photoresist, and the patterned areas were etched using inductively coupled plasma dry etching with BCl as the etching gas. 3 / Cl2 was used for etching at a power of 60W and a etching rate of 0.6 nm / s. After etching, the bottom of the groove region penetrated 1 nm into the gallium nitride layer 2. To reduce etching damage, the etched epitaxial wafer was placed in a 25% tetramethylammonium hydroxide solution and heated in a water bath at 80°C for 300 seconds, followed by low-temperature annealing at 350°C for 80 seconds in a nitrogen atmosphere.

[0052] Step 2: Deposit an ohmic metal layer 5, such as Figure 4 As shown in b, photoresist is applied to the non-patterned area of ​​the epitaxial wafer, and then Ti / Al / Ni / Au ohmic metal layers 5 with thicknesses of 40 / 220 / 40 / 50 nm are sequentially evaporated on the epitaxial wafer by electron beam. The ohmic metal layer and photoresist in the non-patterned area are removed by a peeling method. Subsequently, the epitaxial wafer is subjected to high-temperature annealing at 850 °C, so that the ohmic metal layer 5 is formed locally distributed both inside and outside the groove area.

[0053] Step 3: Deposit insulating layer 4, such as Figure 4 As shown in c, photoresist is covered in the non-patterned area of ​​the epitaxial wafer, and then a silicon nitride insulating layer 4 with a thickness of 2nm is deposited on the epitaxial wafer by plasma-enhanced chemical vapor deposition. The insulating layer and photoresist in the non-patterned area are removed by a peeling method, so that the insulating layer 4 is formed locally distributed both inside and outside the groove area.

[0054] Step 4: Deposit Schottky metal layer 6, as shown Figure 4 As shown in d, photoresist is applied to the non-patterned area of ​​the epitaxial wafer. Then, a Ni / Au Schottky metal layer 6 with a thickness of 30 / 150nm is sequentially evaporated on the epitaxial wafer using an electron beam. The Schottky metal layer and photoresist in the non-patterned area are removed by a peeling method to form a Schottky contact. The epitaxial wafer is then subjected to a low-temperature annealing treatment at 350℃ in a nitrogen atmosphere for 180 seconds to improve the quality of the Schottky contact. Finally, a passivation layer 7 with a thickness of 3μm is applied to complete the diode fabrication.

[0055] Option 2: The insulating layer 4 is made of silicon dioxide, with a thickness of 5 nm. The bottom of the groove region extends 3 nm into the gallium nitride layer 2. The fabrication method includes the following steps:

[0056] Step 1: Etching the groove area, such as... Figure 5 As shown in Figure a, the epitaxial wafer structure includes, from bottom to top, a substrate layer 1, a gallium nitride layer 2, and a barrier layer 3 connected in sequence. The substrate layer 1 is made of sapphire material and has a thickness of 650 μm. The gallium nitride layer 2 has a thickness of 3.3 μm, and the barrier layer 3 has a thickness of 23 nm.

[0057] The non-patterned areas were protected with photoresist, and the patterned areas were etched using inductively coupled plasma dry etching with BCl as the etching gas.3 / Cl2 was used for etching at a power of 60W and an etching rate of 0.6 nm / s. After etching, the bottom of the groove region penetrated 3 nm into the gallium nitride layer 2. To reduce etching damage, the etched epitaxial wafer was placed in a 25% tetramethylammonium hydroxide solution and heated in a water bath at 80°C for 300 seconds, followed by low-temperature annealing at 350°C for 80 seconds in a nitrogen atmosphere.

[0058] Step 2: Deposit insulating layer 4, such as Figure 5 As shown in b, a silicon dioxide insulating layer 4 with a thickness of 5 nm is deposited on the epitaxial wafer. Photolithography is used to cover the patterned area with photoresist for protection. Inductively coupled plasma dry etching is used to etch the non-patterned area without photoresist protection, so that the insulating layer 4 is formed locally distributed both inside and outside the groove area.

[0059] Step 3: Deposit an ohmic metal layer 5, such as Figure 5 As shown in Figure c, photoresist is applied to the non-patterned area of ​​the epitaxial wafer. Then, Ti / Al / Ni / Au ohmic metal layers 5 with thicknesses of 40 / 220 / 40 / 50 nm are sequentially evaporated on the epitaxial wafer using an electron beam. The ohmic metal layer and photoresist in the non-patterned area are removed by a peeling method. Subsequently, the epitaxial wafer is subjected to high-temperature annealing at 850 °C, so that the ohmic metal layer 5 is formed locally distributed both inside and outside the groove area.

[0060] Step 4: Deposit Schottky metal layer 6, such as Figure 5 As shown in d, photoresist is applied to the non-patterned area of ​​the epitaxial wafer. Then, a Ni / Au Schottky metal layer 6 with a thickness of 30 / 150nm is sequentially evaporated on the epitaxial wafer using an electron beam. The Schottky metal layer and photoresist in the non-patterned area are removed by a peeling method to form a Schottky contact. The epitaxial wafer is then subjected to a low-temperature annealing treatment at 350℃ in a nitrogen atmosphere for 180 seconds to improve the quality of the Schottky contact. Finally, a passivation layer 7 with a thickness of 2μm is applied to complete the diode fabrication.

[0061] Example 2

[0062] like Figure 3As shown, a gallium nitride Schottky diode integrating MISFET gate control and field plate functions includes, from bottom to top, a substrate layer 1, a gallium nitride layer 2, and a barrier layer 3 connected in sequence. Partial areas of the gallium nitride layer 2 and the barrier layer 3 are removed to form a groove region. An insulating layer 4 and an ohmic metal layer 5 are locally distributed within the groove region. Outside the groove region, the insulating layer 4 and the ohmic metal layer 5 are positioned above the barrier layer 3. Within the groove region, a Schottky metal layer 6 is positioned above the insulating layer 4, the ohmic metal layer 5, and the gallium nitride layer 2. Outside the groove region, the Schottky metal layer 6 is positioned above the insulating layer 4, and a passivation layer 7 is positioned above the Schottky metal layer 6, the barrier layer 3, and the ohmic metal layer 5. Within the groove region, the Schottky metal layer 6, the insulating layer 4, and the gallium nitride layer 2 form a metal-insulator-semiconductor field-effect transistor (MISFET) gate control structure. Outside the groove region, the insulating layer 4 and the Schottky metal layer 6 form a field plate structure.

[0063] The MISFET gate structure contacts the sidewall of the recessed region. Within the recessed region, the ohmic metal layer 5 and the gallium nitride layer 2 form locally distributed ohmic contacts. Within the recessed region, the ohmic metal layer 5 and the gallium nitride layer 2 form locally distributed ohmic contacts. The MISFET gate structure formed by the Schottky metal layer 6, the insulating layer 4, and the gallium nitride layer 2 within the recessed region, and the Schottky metal layer 6 and the gallium nitride layer 2 within the recessed region, are connected in parallel. In Example 1, the insulating layer 4 and the ohmic metal layer 5 completely cover the bottom of the recessed region, while in Example 2, the insulating layer 4 and the ohmic metal layer 5 do not completely cover the bottom of the recessed region. Locally distributed Schottky contacts formed by the Schottky metal layer 6 and the gallium nitride layer 2 are added within the recessed region. Verification shows that in the reverse blocking state of the diode, a depletion layer forms around the Schottky contacts, thereby suppressing reverse leakage current and increasing the breakdown voltage. Therefore, the device in Example 2 has superior electrical performance.

[0064] The device in Example 2 was also prepared according to two schemes, specifically referring to the two preparation schemes in Example 1. Parameters not mentioned in this example are also referred to in Example 1.

[0065] Table 1 shows the simulation results of existing technologies (such as...) using Silvaco, a simulation software commonly used in this industry. Figure 1 The comparison data of the electrical performance of gallium nitride diodes prepared by Scheme 1 and Scheme 2 in Example 1 and Scheme 1 and Scheme 2 in Example 2 are simulated, including breakdown voltage, leakage current and turn-on voltage.

[0066] Table 1

[0067]

[0068]

[0069] In the table, the test data in Embodiments 1 and 2 of the present invention are significantly better than the test data of the prior art. Specifically, the breakdown voltage is significantly higher than the value of the prior art, while the leakage current and turn-on voltage are significantly lower than the value of the prior art. This indicates that the technical solution in this example not only reduces the turn-on voltage of the device, but also improves its breakdown voltage and reduces the leakage current. Moreover, the preparation method is simple, providing a solution for improving the electrical performance of gallium nitride Schottky diodes.

Claims

1. A gallium nitride Schottky diode integrating MISFET gate control function and field plate function, characterized in that: The structure comprises, from bottom to top, a substrate layer (1), a gallium nitride layer (2), and a barrier layer (3) connected sequentially; portions of the gallium nitride layer (2) and the barrier layer (3) are removed to form recessed regions, the bottom of which extends 1-5 cm into the gallium nitride layer (2) to a depth of 1-5 cm. nm; An insulating layer (4) and an ohmic metal layer (5) are provided in a localized manner within the groove region; An insulating layer (4) and an ohmic metal layer (5) are provided above the barrier layer (3) outside the groove region; A Schottky metal layer (6) is provided above the insulating layer (4) and the ohmic metal layer (5) within the groove region; A Schottky metal layer (6) is provided above the insulating layer (4) outside the groove region, and a passivation layer (7) is provided above the Schottky metal layer (6), the barrier layer (3), and the ohmic metal layer (5); Within the groove region, the Schottky metal layer (6), the insulating layer (4), and the gallium nitride layer (2) form a metal-insulator-semiconductor field-effect transistor (MISFET) gate structure, and the MISFET gate structure contacts the sidewall of the groove region to weaken the impact of material damage caused by groove etching on device performance; Outside the groove region, the insulating layer (4) and the Schottky metal layer (6) form a field plate structure; the MISFET gate control structure is used to regulate the channel electron conduction and the field plate structure to ease the electric field at the anode edge, thereby reducing the turn-on voltage of the device, increasing the breakdown voltage and reducing the leakage current; the thickness of the insulating layer (4) is 0.1-5 nm.

2. A gallium nitride Schottky diode integrating MISFET gate control function and field plate function according to claim 1, characterized in that: Within the groove region, the ohmic metal layer (5) and the gallium nitride layer (2) form locally distributed ohmic contacts.

3. A gallium nitride Schottky diode integrating MISFET gate control function and field plate function according to claim 2, characterized in that: Within the groove area, the insulating layer (4) and the ohmic metal layer (5) completely cover the bottom of the groove area, or the insulating layer (4) and the ohmic metal layer (5) do not completely cover the bottom of the groove area; Within the groove region, when the insulating layer (4) and the ohmic metal layer (5) completely cover the bottom of the groove region, the locally distributed ohmic contacts formed by the ohmic metal layer (5) and the gallium nitride layer (2) are connected in parallel with the MISFET gate control structure. Within the groove region, when the insulating layer (4) and the ohmic metal layer (5) do not completely cover the bottom of the groove region, the locally distributed ohmic contacts formed by the ohmic metal layer (5) and the gallium nitride layer (2), the MISFET gate structure, and the locally distributed Schottky contacts formed by the Schottky metal layer (6) and the gallium nitride layer (2) are connected in parallel.

4. A gallium nitride Schottky diode integrating MISFET gate control function and field plate function according to any one of claims 1-3, characterized in that: The insulating layer (4) is a single-layer insulating layer formed by one of silicon dioxide, silicon nitride and aluminum oxide, or a multi-layer insulating layer formed by multiple materials; the Schottky metal layer (6) is a single-layer metal formed by one of nickel, gold, tungsten, molybdenum and platinum, or a multi-layer metal formed by multiple materials.

5. A gallium nitride Schottky diode integrating MISFET gate control function and field plate function according to any one of claims 1-3, characterized in that: The thickness of the passivation layer (7) is 500-2000 nm.

6. A method for fabricating a gallium nitride Schottky diode integrating MISFET gate control and field plate functions as described in any one of claims 1-5, characterized in that: Includes the following steps: The epitaxial wafer consists of a substrate layer (1), a gallium nitride layer (2), and a barrier layer (3) from bottom to top. A portion of the gallium nitride layer (2) and the barrier layer (3) are removed using an inductively coupled plasma dry etching method to form a groove region. The etching damage in the groove region is repaired by immersing the epitaxial wafer in a 20-30% tetramethylammonium hydroxide solution and heating it in a water bath at 60-85°C for 100-500 seconds, and / or immersing the epitaxial wafer in a nitrogen atmosphere at 300-400°C for 60-200 seconds. Using photolithography lift-off, ohmic metal layers with localized distribution are deposited simultaneously in and outside the groove area (5), and then subjected to high-temperature annealing at 800-900 °C to form ohmic contacts; An insulating layer (4) is grown, and the grown insulating layer (4) is partially removed by photolithography, so that the insulating layer (4) is formed locally distributed both inside and outside the groove area. Using photolithography lift-off, a Schottky metal layer (6) is deposited or sputtered in and outside the groove area, and then subjected to low-temperature annealing treatment, followed by a passivation layer (7) to complete the diode fabrication.

7. The method for fabricating a gallium nitride Schottky diode integrating MISFET gate control function and field plate function according to claim 6, characterized in that: step , , In this process, the photolithography stripping method is as follows: first, the non-patterned area is covered with photoresist, then the entire epitaxial wafer is covered with an insulating layer or a metal layer, and the insulating layer or metal layer in the non-patterned area is removed by the stripping method, leaving the insulating layer or metal layer in the patterned area. step In the process, the insulating layer (4) is grown by atomic layer deposition, plasma-enhanced chemical vapor deposition or low-pressure chemical vapor deposition; step In the process, the annealing conditions for the Schottky metal layer (6) are: annealing at 300-400 °C for 60-200 seconds in a nitrogen atmosphere.

8. A method for fabricating a gallium nitride Schottky diode integrating MISFET gate control and field plate functions as described in any one of claims 1-5, characterized in that: Includes the following steps: Step 1: The epitaxial wafer consists of a substrate layer (1), a gallium nitride layer (2), and a barrier layer (3) from bottom to top. A portion of the gallium nitride layer (2) and the barrier layer (3) are removed using an inductively coupled plasma dry etching method to form a groove region. The etching damage in the groove region is repaired by immersing the epitaxial wafer in a 20-30% tetramethylammonium hydroxide solution and heating it in a water bath at 60-85°C for 100-500 seconds, and / or immersing the epitaxial wafer in a nitrogen atmosphere at 300-400°C for 60-200 seconds. Step 2: An insulating layer is grown on the entire epitaxial wafer (4). Photolithography is used to cover the patterned area with photoresist. Inductively coupled plasma dry etching is used to etch the non-patterned area without photoresist protection. Finally, an insulating layer (4) is formed in a localized distribution both inside and outside the groove area. Step 3: Using photolithography lift-off method, a locally distributed ohmic metal layer is deposited simultaneously in and outside the groove area (5), and then subjected to high-temperature annealing at 800-900 °C to form an ohmic contact; Step 4: Using photolithography to lift off the substrate, deposit or sputter a Schottky metal layer (6) in and outside the groove area, and perform low-temperature annealing treatment on it, followed by covering with a passivation layer (7) to complete the diode fabrication.

9. The method for fabricating a gallium nitride Schottky diode integrating MISFET gate control function and field plate function according to claim 8, characterized in that: wherein: In step two, the insulating layer (4) is grown by atomic layer deposition, plasma-enhanced chemical vapor deposition, or low-pressure chemical vapor deposition. In steps three and four, the photolithography stripping method is as follows: first, cover the non-patterned area with photoresist, then cover the entire epitaxial wafer with an insulating layer or metal layer, and use the stripping method to remove the insulating layer or metal layer in the non-patterned area, leaving the insulating layer or metal layer in the patterned area. In step four, the annealing conditions for the Schottky metal layer (6) are: annealing at 300-400 °C for 60-200 seconds in a nitrogen atmosphere.

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