Hot electron transistor and method of fabricating the same, method of extracting schottky barrier height

Abstract

The present application relates to the technical field of semiconductor devices, and particularly relates to a hot electron transistor, a preparation method thereof, and a Schottky barrier height extraction method, the hot electron transistor comprising an emitter, a base and a collector, a tunneling barrier layer is arranged between the emitter and the base, and an inorganic semiconductor layer is arranged between the base and the collector. The hot electron transistor of the present application is provided with a tunneling barrier layer between the emitter and the base, and an inorganic semiconductor layer between the base and the collector, the present application uses the tunneling barrier layer to separate the emitter and the base, and achieves the effect of precisely controlling the thickness of the tunneling barrier layer. Compared with the traditional preparation method of Schottky diodes and Schottky thin film transistors, the hot electron transistor adopts a hot electron spectroscopy method to extract the Schottky barrier between the indium gallium zinc oxide inorganic semiconductor layer and the metal base, considers the influence of the interface state and the bulk resistance on the barrier height, and the obtained result is more accurate.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor devices, and particularly relates to a hot electron transistor, a preparation method thereof, and a Schottky barrier height extraction method. BACKGROUND

[0002] With the development of modern science and technology, the demand for flexible transparent electronic technology gradually increases. In order to meet the huge market demand of high-resolution, high-opening speed and large-area size preparation of flat panel displays, a new type of amorphous oxide semiconductor material indium gallium zinc oxide (a-IGZO) has become a research hotspot that can replace amorphous silicon and polycrystalline silicon. Because it has many advantages such as high electron mobility, high on-off ratio, low off-state current, compatibility with flexible substrates, and low-temperature preparation, it has broad application prospects in the next generation of flat panel displays and traditional CMOS devices. In the past 20 years, people have made great efforts in preparing related a-IGZO thin film transistor devices and improving device performance. Although through continuous innovation, new electronic devices based on IGZO have made significant progress and have reached the level of commercial application, the device performance still faces the problems of reliability and stability. Among them, the source-drain metal contact resistance will seriously affect the transport of carriers in the channel, and large contact resistance will reduce the effective electron mobility and increase the power consumption of the device. The height and width of the Schottky barrier at the interface are the main causes of contact resistance, so it is of great significance to extract the intrinsic Schottky barrier height for studying the interface problem between a-IGZO and the contact metal under the premise of considering the interface state.

[0003] So far, there are mainly two methods to extract the Schottky barrier between metal and a-IGZO. The first method is to prepare a Schottky barrier diode, and to explain the current transmission mechanism of the Schottky contact by using the hot electron emission theory. In the hot electron emission model, the inhomogeneity of the barrier height is caused by impurities, defects and mirror force reduction effects on the semiconductor surface; in addition, under forward bias, the high carrier concentration of the semiconductor makes some electrons pass through the barrier by quantum tunneling, so the current transmission model through the metal-semiconductor contact cannot be completely fitted by the hot emission theory, making the current of the Schottky diode deviate from the ideal case.

[0004] The other method is to prepare a Schottky barrier thin film transistor. The Schottky barrier thin film transistor forms a Schottky contact with the source and the semiconductor, and the barrier height formed by the source and the channel is modulated by the field effect generated by the gate voltage, and the electrons injected into the Schottky junction are exponentially related to the barrier height. However, the working mechanism of such devices is more complex than that of traditional thin film transistors, and there is no mature and suitable physical model to deeply study the mechanism of such devices.

[0005] Therefore, the barrier height calculated by the two methods deviates from the actual barrier height, and an accurate value cannot be obtained. SUMMARY

[0006] The present application provides a hot electron transistor and a preparation method thereof, and a Schottky barrier height extraction method, to solve the problem that the barrier height calculated by the existing method for extracting the Schottky barrier between the metal and the a-IGZO deviates from the actual barrier height.

[0007] In a first aspect of the present application, the present application provides a hot electron transistor, comprising an emitter, a base and a collector, a tunneling barrier layer is arranged between the emitter and the base, and an inorganic semiconductor layer is arranged between the base and the collector.

[0008] In the above scheme, the present application solves the problem that the barrier height calculated by the existing method for extracting the Schottky barrier between the metal and the a-IGZO deviates from the actual barrier height. The hot electron transistor of the present application is provided with a tunneling barrier layer between the emitter and the base, and an inorganic semiconductor layer between the base and the collector. The present application uses the tunneling barrier layer to separate the emitter and the base, so as to accurately control the thickness of the tunneling barrier layer. Compared with the traditional method for preparing a Schottky diode and a Schottky thin film transistor, the hot electron transistor is used to extract the Schottky barrier between the indium gallium zinc oxide inorganic semiconductor layer and the metal base by the method of hot electron spectroscopy, the influence of the interface state and the bulk resistance on the barrier height is considered, and the result is more accurate.

[0009] In a possible design, the thickness of the emitter ranges between 20nm and 30nm, and is preferably 20nm; the thickness of the tunneling barrier layer ranges between 1.5nm and 2.5nm, and is preferably 2nm; the thickness of the base ranges between 10nm and 15nm, and is preferably 15nm; the thickness of the inorganic semiconductor layer is 50nm-100nm, and is preferably 50nm; and the thickness of the collector ranges between 50nm and 100nm, and is preferably 50nm.

[0010] It can be understood that the thickness of each layer structure has a substantial influence on the detection accuracy. After the tunneling transport in the tunnel junction and the ballistic transport in the base, the number of electrons will be significantly reduced. When the thickness of the tunnel junction and the base is not suitable, the hot electron current of the collector will be small, resulting in inaccurate detection results. In addition, when the inorganic semiconductor layer is thin, the metal may penetrate during the evaporation of the top electrode, thereby causing the detected signal to be not a hot electron signal. Therefore, the present application proposes to control the thickness of the emitter, the tunneling barrier layer, the base, the inorganic semiconductor layer and the collector, so as to avoid the above problems and improve the detection accuracy.

[0011] In a possible design, the emitter is made of metal aluminum; the tunneling barrier layer is made of an aluminum oxide layer; the base is made of metal gold; the inorganic semiconductor layer is made of an indium gallium zinc oxide semiconductor layer; and the collector is made of titanium-gold alloy or aluminum, preferably aluminum.

[0012] It can be understood that the present application finds that the effect of different material combinations is relatively large when the specific selection of the material of each layer is made, and the test precision is obviously affected. Therefore, the present application controls the material of the emitter to be aluminum; the tunneling barrier layer is an in-situ oxidation formed and solid insulating layer, which can effectively isolate the emitter metal and the base metal, and avoid the influence of the interface state on the barrier height; the base is made of gold Au, which is an inert metal and is not easy to interact with the inorganic semiconductor layer, and is an ideal base material; and the collector is made of titanium-gold alloy or aluminum. Through the above combination, the effect of each layer can be maximized to maintain high test stability and improve the accuracy of detection.

[0013] In a second aspect of the present application, the present application also provides a preparation method of the above-mentioned hot electron transistor, comprising: forming a tunneling barrier layer between the emitter and the base; and forming an inorganic semiconductor layer between the base and the collector.

[0014] The present application adds the preparation of the tunneling barrier layer and the inorganic semiconductor layer on the basis of the preparation process of the existing hot electron transistor, and the obtained new structure of the hot electron transistor can effectively avoid the influence of the interface state and the bulk resistance on the barrier height, and the method of hot electron spectroscopy can accurately extract the Schottky barrier of the inorganic semiconductor layer and the metal base.

[0015] In a possible design, the inorganic semiconductor layer is formed by a magnetron sputtering method under different oxygen partial pressures; and the oxygen flow rate in the sputtering cavity of the magnetron sputtering method is controlled to be between 1.5 sccm and 6 sccm.

[0016] Optionally, the oxygen flow rate in the sputtering cavity of the magnetron sputtering method can be controlled to be 1.5 sccm, 1.8 sccm, 2 sccm, 2.2 sccm, 2.5 sccm, 3 sccm, 3.5 sccm, 4 sccm, 4.5 sccm, 5 sccm, 5.5 sccm or 6 sccm, preferably between 3 sccm and 6 sccm.

[0017] It can be understood that by controlling the oxygen flow rate in the sputtering chamber of the magnetron sputtering method within a reasonable range, the Schottky barrier height of the inorganic semiconductor layer and the metal base can be accurately extracted, especially the Schottky barrier height of IGZO and the metal base. When the oxygen flow rate in the sputtering chamber of the magnetron sputtering method is less than 1.5sccm, the effect of accurately extracting the Schottky barrier height of the inorganic semiconductor layer and the metal base cannot be achieved, and when the oxygen flow rate in the sputtering chamber of the magnetron sputtering method is greater than 6sccm, the hot electron transistor becomes an insulator, and the Schottky barrier height of the inorganic semiconductor layer and the metal base cannot be extracted. In addition, by changing the oxygen partial pressure during the magnetron sputtering of IGZO, different barrier heights can be obtained, which provides guidance for the carrier transport characteristics of the IGZO and metal interface.

[0018] In a possible design, the emitter is formed by rapid thermal evaporation.

[0019] It can be understood that the emitter is formed by rapid thermal evaporation instead of electron beam evaporation, especially for metal aluminum, which can solve the problem of large metal surface roughness leading to perforation.

[0020] In a possible design, the tunnel barrier layer is formed by atomic layer deposition, the base is formed by electron beam evaporation, and the collector layer is formed by electron beam evaporation.

[0021] It can be understood that by selecting appropriate formation methods, the performance of the hot electron transistor is more excellent, and the Schottky barrier height of the inorganic semiconductor layer and the metal base can be accurately extracted. The above formation method is simple and fast.

[0022] In a possible design, at least one of the emitter, the base, the tunnel barrier layer, the collector and the inorganic semiconductor layer is patterned by ultraviolet lithography.

[0023] It can be understood that the ultraviolet lithography is used to form a pattern during the preparation process of the hot electron transistor, which not only can design different emitter and collector areas to achieve high hot electron emission efficiency, but also can realize the advantage of compatibility with large-area integration.

[0024] In a possible design, during the patterning process by ultraviolet lithography, the development time is controlled to be 8s-10s. Alternatively, the development time can be 8s, 9s or 10s, etc.

[0025] It can be understood that it is found in the experiment that aluminum oxide and metal aluminum are easily dissolved in the developing solution, so by controlling the development time within 8s-10s, the problem can be effectively solved.

[0026] In a third aspect, the present application provides a method for extracting the Schottky barrier height, which comprises the following steps: obtaining the thermionic energy spectrum by using the thermionic transistor; and obtaining the Schottky barrier height between the base and the inorganic semiconductor layer by using the thermionic energy spectrum.

[0027] The present application combines the indium gallium zinc oxide semiconductor into the thermionic transistor, reduces the off-state current in the IGZO by changing the oxygen partial pressure in the magnetron process, and obtains the Schottky barrier height between the indium gallium zinc oxide semiconductor and the base metal by using the thermionic energy spectrum.

[0028] Further, the method for obtaining the thermionic energy spectrum by using the thermionic transistor comprises the following steps: testing the electrical characteristics of the thermionic transistor by using a semiconductor analyzer, and testing in a vacuum environment by using a Keithley 4200 semiconductor analyzer. When measuring the current-voltage relationship between the emitter and the base, the base metal is grounded, a scanning negative bias voltage is applied, and a curve of the emission tunneling current Ieb changing with the emission voltage Veb is obtained. When measuring the thermionic emission and collection, the base metal is grounded, the collector voltage is fixed, a scanning emission voltage is applied, and a relationship of the collector current Ic changing with the emission voltage Veb is obtained, which is the thermionic energy spectrum.

[0029] Further, the method for obtaining the Schottky barrier height between the base and the indium gallium zinc oxide inorganic semiconductor layer by using the thermionic energy spectrum comprises the following steps:

[0030] After the emission voltage Veb is applied, the electrons obtain certain energy and become high-energy electrons. Since the injected electrons are high-speed electrons, the transmission time in the base metal is very short, and the transmission is approximately ballistic transport. When the electrons obtain sufficient energy to overcome the barrier height between the metal and the IGZO, the electrons can be collected by the collector. Therefore, the collector current cannot be collected at a small emission voltage, and increases rapidly after the threshold voltage is reached. The intersection of the linear fitting straight line current and the abscissa obtains the numerical value of the Schottky barrier height. After changing the oxygen flux of the magnetron sputtering, the barrier height between the indium gallium zinc oxide inorganic semiconductor layer and the base metal under different oxygen partial pressures can be obtained.

[0031] The thermionic transistor provided by the present application is provided with a tunneling barrier layer between the emitter and the base, and an inorganic semiconductor layer between the base and the collector. The present application uses the tunneling barrier layer to separate the emitter and the base, and achieves the effect of precisely controlling the thickness of the tunneling barrier layer. Compared with the traditional method for preparing the Schottky diode and the Schottky thin film transistor, the thermionic transistor is used to extract the Schottky barrier between the indium gallium zinc oxide inorganic semiconductor layer and the metal base by using the thermionic energy spectrum, avoids the influence of the interface state and the bulk resistance on the barrier height, and obtains more accurate results. BRIEF DESCRIPTION OF DRAWINGS

[0032] In order to more clearly illustrate the technical solutions of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings described below are some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without any creative effort on the basis of these drawings.

[0033] Figure 1 is a structural schematic diagram of a hot electron transistor provided by the present application;

[0034] Figure 2 is a curve of the emission tunneling current Ieb changing with the emission voltage Veb obtained by a semiconductor analyzer for testing the hot electron transistor provided by the present application;

[0035] Figure 3 is linear fitting data of the Ic-Veb curve of the hot electron transistor provided by the embodiment 1 of the present application;

[0036] Figure 4 is linear fitting data of the Ic-Veb curve of the hot electron transistor provided by the embodiment 2 of the present application;

[0037] Figure 5 is linear fitting data of the Ic-Veb curve of the hot electron transistor provided by the embodiment 3 of the present application;

[0038] Figure 6 is linear fitting data of the Ic-Veb curve of the hot electron transistor provided by the embodiment 4 of the present application;

[0039] Figure 7 is an AFM graph of forming metal aluminum by rapid thermal evaporation in the preparation method of the present application;

[0040] Figure 8 is an AFM graph of forming metal aluminum by electron beam evaporation in the preparation method of the present application.

[0041] Figure 9 is an Ic-Veb curve diagram of the hot electron transistor provided by the embodiment 5 of the present application;

[0042] Figure 10 is an energy level position relationship schematic diagram adopted by the ultraviolet photoelectron spectroscopy method in the experimental example of the present application;

[0043] Figure 11 is a band spectrum diagram of the IGZO film under three oxygen flow rates in the embodiment 1, the embodiment 2 and the embodiment 3 of the present application;

[0044] Figure 12This is a graph showing the band gap widths of three types of a-IGZO films, namely, Example 1, Example 2, and Example 3, characterized by UV-Vis analysis of the present invention.

[0045] Reference numerals:

[0046] 1: emitter; 2: tunneling barrier layer; 3: base; 4: inorganic semiconductor layer; 5: collector. DETAILED DESCRIPTION

[0047] To make the objectives, technical solutions, and advantages of the present invention more clear, the technical solutions of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the embodiments described are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0048] Example 1

[0049] This embodiment provides a hot electron transistor, such as Figure 1 As shown, it includes an emitter 1 , a base 3 and a collector 5 , a tunneling barrier layer 2 is provided between the emitter 1 and the base 3 , and an inorganic semiconductor layer 4 is provided between the base 3 and the collector 5 .

[0050] The method for preparing the hot electron transistor of this embodiment includes the following steps:

[0051] (1) A silicon dioxide wafer with a surface thickness of 300 nm was used as the substrate.

[0052] (2) Deposit patterned pad metal on the substrate: Use negative resist 1500 coating, rotation speed 4000rpm, time 60s, 150℃ pre-bake 2min, UV exposure time 11s, 120℃ post-bake 2min, develop in developer for 40s, rinse with plenty of water, and harden the film for 1min. Electron beam evaporation is used to deposit pad metal TiAu 10 / 30nm. When removing the photoresist, soak in acetone for about 30min, then rinse with isopropyl alcohol and water. The emitter, base, and collector are patterned using the same photolithography process.

[0053] (3) Form a patterned emitter 1 on the patterned pad metal: Use negative resist 1500 coating at a speed of 4000 rpm for 60 seconds, pre-bake at 150°C for 2 minutes, UV exposure for 11 seconds, post-bake at 120°C for 2 minutes, develop in developer for 8-10 seconds, rinse with plenty of water, and harden the film for 1 minute. Use a metal thermal evaporator with increased power to quickly evaporate 20nm of metal aluminum. When removing the photoresist, soak in acetone for about 30 minutes, then rinse with isopropyl alcohol and water.

[0054] (4) Forming an isolation tunnel layer 2 on the patterned emitter: 2 nm of aluminum oxide is deposited by atomic layer deposition (ALD).

[0055] (5) Forming a patterned base 3 on the isolation tunnel layer: negative resist 1500 is coated at 4000 rpm for 60 s, pre-baked at 150 °C for 2 min, UV exposed for 11 s, post-baked at 120 °C for 2 min, developed in the developer for 8-10 s, rinsed with plenty of water, and hard-baked for 1 min. A 15 nm thick base metal Au is evaporated by an e-beam evaporator, and the photoresist is removed by soaking in acetone for about 30 min, followed by rinsing with isopropanol and water.

[0056] (6) Forming a patterned inorganic semiconductor layer 4 on the base: negative resist 1500 is coated at 4000 rpm for 60 s, pre-baked at 150 °C for 2 min, UV exposed for 11 s, post-baked at 120 °C for 2 min, developed in the developer for 8-10 s, rinsed with plenty of water, and hard-baked for 1 min. An indium gallium zinc oxide (IGZO) compound semiconductor is sputtered in a magnetron sputtering device with an oxygen flow rate of 6 sccm, to a thickness of 50 nm, and the photoresist is removed by soaking in acetone for about 30 min, followed by rinsing with isopropanol and water.

[0057] (7) Forming a patterned collector 5 on the inorganic semiconductor layer 4: negative resist 1500 is coated at 4000 rpm for 60 s, pre-baked at 150 °C for 2 min, UV exposed for 11 s, post-baked at 120 °C for 2 min, developed in the developer for 8-10 s, rinsed with plenty of water, and hard-baked for 1 min. A 50 nm thick collector 5 metal Al is evaporated by e-beam evaporation at a deposition rate of 1 angstrom per second, and the photoresist is removed by soaking in acetone for about 30 min, followed by rinsing with isopropanol and water. Thus, an Al / Al2O3 / Au / IGZO / Al thermionic transistor is prepared.

[0058] The obtained thermionic transistor is tested for electrical characteristics by a semiconductor analyzer: in a vacuum environment, a Keithley 4200 semiconductor analyzer is used. When measuring the current-voltage relationship between the emitter and the base, the base metal is grounded, a scanning negative bias voltage is applied, and a curve of the emission tunneling current Ieb versus the emission voltage Veb is obtained as shown in Figure 2 . When measuring the thermionic emission and collection, the base metal is grounded, the collector voltage is fixed, a scanning emission voltage is applied, and a relationship of the collector current Ic versus the emission voltage Veb is obtained as shown in Figure 3 , which is the thermionic energy spectrum.

[0059] The Schottky barrier height between the base metal and the inorganic semiconductor layer of indium gallium zinc oxide compound is obtained by using the thermionic electron spectroscopy. After applying the emission voltage Veb, the electrons obtain certain energy and become high-energy electrons. Since the injected electrons are high-speed electrons, the transit time is very short, and the transmission in the base metal is approximately the ballistic transport. When the electrons obtain sufficient energy to overcome the barrier height between the metal and the IGZO, the electrons can be collected by the collector. Therefore, the collector current cannot be collected at a small emission voltage, and rapidly increases after reaching the threshold voltage. As shown in FIG. 4, the intersection of the linear fitting straight line and the abscissa obtains the value of the Schottky barrier height. The threshold voltage of the base and the inorganic semiconductor layer of indium gallium zinc oxide compound of the thermionic transistor in this embodiment is 1.16 V. Figure 3

[0060] Embodiment 2

[0061] This embodiment provides a thermionic transistor, and the structural schematic diagram thereof is the same as that of Embodiment 1.

[0062] The difference between the preparation method of the thermionic transistor in this embodiment and that in Embodiment 1 is that, in step (6), the oxygen flow rate in the chamber is modified to 4.5 sccm in the magnetron sputtering device.

[0063] The obtained thermionic transistor is tested for the electrical characteristics by using the semiconductor analyzer in the same manner as in Embodiment 1. The Schottky barrier height between the base metal and the inorganic semiconductor layer of indium gallium zinc oxide compound is obtained by using the thermionic electron spectroscopy. The threshold voltage between the base and the inorganic semiconductor of indium gallium zinc oxide compound of the thermionic transistor in this embodiment is 0.94 V, as shown in FIG. 5. Figure 4

[0064] Embodiment 3

[0065] This embodiment provides a thermionic transistor, and the structural schematic diagram thereof is the same as that of Embodiment 1.

[0066] The difference between the preparation method of the thermionic transistor in this embodiment and that in Embodiment 1 is that, in step (6), the oxygen flow rate in the chamber is modified to 3 sccm in the magnetron sputtering device.

[0067] The obtained thermionic transistor is tested for the electrical characteristics by using the semiconductor analyzer in the same manner as in Embodiment 1. The Schottky barrier height between the base metal and the inorganic semiconductor layer of indium gallium zinc oxide compound is obtained by using the thermionic electron spectroscopy. The threshold voltage between the base and the inorganic semiconductor layer of indium gallium zinc oxide compound of the thermionic transistor in this embodiment is 0.865 V, as shown in FIG. 6. Figure 5

[0068] Embodiment 4

[0069] ​​​The embodiment provides a hot electron transistor, and a structure diagram thereof is the same as that of the embodiment 1.

[0070] The difference between the preparation method of the hot electron transistor of the embodiment and the embodiment 1 is that in step (6), the oxygen flow rate in the chamber is modified to 1.5 sccm in a magnetron sputtering device.

[0071] The obtained hot electron transistor is used for testing electrical characteristics by using a semiconductor analyzer in the same manner as that of the embodiment 1, and the Schottky barrier height of the base metal and the indium gallium zinc oxide inorganic semiconductor layer is obtained by using a hot electron spectrum, but because the carrier concentration in the IGZO is large under the oxygen flow rate of 1.5 sccm, the off-state current is too large, the tunneling current is not matched in order of magnitude, and the hot electron current cannot be accurately observed, and the threshold voltage of the collector current and the emission voltage of the hot electron transistor of the embodiment is not the real Schottky barrier height, as shown in Figure 6 .

[0072] Embodiment 5

[0073] The embodiment provides a hot electron transistor, and a structure diagram thereof is the same as that of the embodiment 1.

[0074] The difference between the preparation method of the hot electron transistor of the embodiment and the embodiment 1 is that in step (3), an electron beam evaporation method is used to replace a rapid thermal evaporation method to form a patterned emitter.

[0075] It is found that, as shown in Figure 7 and Figure 8 , Figure 7 is an AFM diagram of the rapid thermal evaporation of the metal aluminum, Figure 8 is an AFM diagram of the electron beam evaporation of the metal aluminum, and by comparing Figure 7 and Figure 8 , it can be seen that, compared to the electron beam evaporation method for forming the patterned emitter metal aluminum, the rapid thermal evaporation method for forming the patterned emitter metal aluminum can reduce the roughness of the metal aluminum from 1.78 nm to 0.842 nm, can solve the problem of the large surface roughness of the aluminum leading to the perforation, and can further achieve the effect of accurately extracting the Schottky barrier height of the inorganic semiconductor layer and the metal base, as shown in Figure 9 .

[0076] Experimental example

[0077] In order to prove the accuracy of the method for extracting the Schottky barrier height of the hot electron transistor, the energy level position of the Au and the IGZO is characterized by using a traditional ultraviolet photoelectron spectrum and an ultraviolet absorption spectrum. As shown in Figure 10The position of the energy level is shown in the figure. Ultraviolet photoelectron spectroscopy (UPS) can obtain various information about the valence electron structure, including the valence band position and the work function of the material, by measuring the energy distribution of the valence electrons. When the sample has good electrical contact with the instrument, the Fermi level E F of the sample material corresponds to the Fermi level of the instrument. The position of the Fermi level in the metal is determined by observing the Fermi step of the energy spectrum. The E F of the semiconductor material is usually located between the band gap, and there is an energy difference between the highest energy position that can be filled by valence electrons, the valence band maximum (VBM). The IGZO in Examples 1-3 corresponds to the same valence band maximum position. The usual method for determining the VBM position is to linearly extrapolate along the steeply rising portion of the valence band spectrum, and take the intersection with the noise floor baseline. The energy of this intersection is the difference between the VBM and E F . Ultraviolet absorption spectroscopy (UV-Vis) can obtain the absorption of IGZO at different wavelengths, and the band gap width value Eg of IGZO in Examples 1-3 can be quantitatively obtained according to the relationship between the absorption coefficient and the wavelength. According to Figure 10 , the position of the conduction band minimum (CBM) can be determined from the position of the VBM and the band gap width. The Schottky barrier height φ b of the intrinsic metal and semiconductor contact is the difference between the CBM and the Fermi level EF of the metal. First, the work function of the metal Au and the position of the valence band maximum of the IGZO were measured by ultraviolet photoelectron spectroscopy (UPS). As shown in Figure 11 , the energy band spectrum of the IGZO thin film at three oxygen flow rates in Examples 1-3 is shown. The abscissa corresponds to the Fermi level of gold, and the work function of the sample can be obtained from the position of the quadratic cutoff edge in Figure 10 . The difference between the valence band maximum of the a-IGZO and the Fermi level can be obtained from the linear fitting of the curve in Figure 11 to the abscissa, which is 2.94 eV. Therefore, the position of the VBM of the IGZO from the vacuum level is 4.7 + 2.94 = 7.64 eV. In addition, in order to obtain the conduction band minimum level position of the IGZO under different preparation conditions, the inventors characterized the band gap width of the three types of a-IGZO thin films by UV-Vis, as shown in Figure 12 . The fitting curve obtained the band gap widths of Example 3, Example 2, and Example 1 to be 3.69 eV, 3.75 eV, and 3.85 eV, respectively. According to Figure 10The positions of the energy levels of the gold in example 3, example 2 and example 1 and the conduction band top of IGZO are 3.95eV, 3.89eV and 3.79eV respectively, and the barrier heights are 0.75eV, 0.81eV and 0.91eV respectively. However, since this method can only simply measure the difference between the Fermi level of the metal and the conduction band bottom of IGZO, and does not consider the complexity of the interface and the process of electron transmission, the data obtained are all relatively low, and are only used as reference values for extracting the barrier height of the hot electron transistor.

[0078] It can be seen that the difference between the Schottky barrier height of the indium gallium zinc oxide compound and the metal extracted by the Schottky barrier height extraction method of the present application and the Schottky barrier height of the indium gallium zinc oxide compound and the metal extracted by the photoelectron absorption spectrum extraction method is 0.1V-0.25V. The photoelectron absorption spectrum extraction method only considers the relationship between the energy levels, and cannot consider the complexity of the interface and the complexity of the process of electron transmission, so there is the problem of inaccurate extraction results. However, the Schottky barrier height extraction method of the present application can effectively avoid the influence of the interface state and the bulk resistance on the barrier height, so that it can well fit the current-voltage relationship, thereby achieving the effect of accurately extracting the Schottky barrier of the indium gallium zinc oxide inorganic semiconductor layer and the metal base.

[0079] Finally, it should be pointed out that: the above examples are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing examples, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing examples, or make equivalent replacement for part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A hot electron transistor, characterized in that It includes an emitter, a base and a collector, wherein a tunneling barrier layer is provided between the emitter and the base, and an inorganic semiconductor layer is provided between the base and the collector; The emitter is metal aluminum; the tunnel barrier layer is an aluminum oxide layer; the base is metal gold; the inorganic semiconductor layer is an indium gallium zinc oxide compound semiconductor layer; and the collector is a titanium gold alloy or aluminum.

2. The hot electron transistor according to claim 1, wherein The thickness of the emitter ranges from 20nm to 30nm; the thickness of the tunneling barrier layer ranges from 1.5nm to 2.5nm; the thickness of the base ranges from 10nm to 15nm; the thickness of the inorganic semiconductor layer is 50nm to 100nm; and the thickness of the collector ranges from 50nm to 100nm.

3. The method for preparing a hot electron transistor according to any one of claims 1 to 2, characterized in that: The method comprises: forming a tunneling barrier layer between the emitter and the base; and forming an inorganic semiconductor layer between the base and the collector.

4. The method for preparing a hot electron transistor according to claim 3, wherein: The inorganic semiconductor layer is formed by magnetron sputtering under different oxygen partial pressures; in the magnetron sputtering method, the oxygen flow rate in the sputtering cavity is controlled between 1.5 sccm and 6 sccm.

5. The method for preparing a hot electron transistor according to claim 3, wherein: The emitter is formed by rapid metal thermal evaporation.

6. The method for preparing a hot electron transistor according to claim 3, wherein: The tunneling barrier layer is formed by atomic layer deposition; the base electrode is formed by electron beam evaporation; and the collector electrode is formed by electron beam evaporation.

7. The method for preparing a hot electron transistor according to claim 3, wherein: At least one of the emitter, the base, the tunneling barrier layer, the collector and the inorganic semiconductor layer is patterned using ultraviolet lithography.

8. The method for preparing a hot electron transistor according to claim 7, wherein: During the patterning process using ultraviolet lithography, the development time is controlled at 8s-10s.

9. A method for extracting Schottky barrier height, characterized in that: A hot electron spectrum is obtained using the hot electron transistor according to any one of claims 1 to 2; and a Schottky barrier height between the base and the inorganic semiconductor layer is obtained using the hot electron spectrum.

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