A method for manufacturing a DBR flip chip

Abstract

The application relates to the field of semiconductor electronic technology, in particular to a manufacturing method of a DBR flip chip. The manufacturing method comprises the following steps: sequentially growing a N-type semiconductor layer, a multi-quantum well layer and a P-type semiconductor layer of a gallium nitride-based material on a substrate; sequentially preparing a current blocking layer, an ITO layer and a Mesa step surface; synchronously performing photoetching and etching on a Mesa cutting path and an ISO cutting path; and sequentially preparing a current expansion layer, a DBR reflection layer and a metal electrode pad layer. The Mesa cutting path and the ISO cutting path are photoetched together, so that the exposure deviation is reduced, and the area of the GaN layer and the area of the ITO (transparent conductive layer) on the GaN layer are maximally reserved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor electronic technology, in particular to a DBR flip chip manufacturing method. BACKGROUND

[0002] Light emitting diode (LED) is a kind of solid-state light emitting device which converts electrical energy into light energy, and GaN-based LED chip has been developed and applied greatly. In order to improve the light extraction efficiency, a distributed Bragg reflector (DBR) structure is usually grown in the chip. The reflectivity of the DBR can reach more than 99%, and it has no absorption problem of the metal reflection layer, and the energy gap position can be adjusted by changing the refractive index or thickness of the material.

[0003] A flip LED chip manufacturing method of PECVD deposition DBR is disclosed in Chinese patent CN106409991A. N-type GaN layer, quantum well and P-type GaN layer are sequentially grown on sapphire substrate; part of the N-type GaN layer is exposed by etching; N-type extension bar is formed on the exposed part of the N-type GaN layer; conductive metal layer is made on the surface of the P-type GaN layer; DBR layer is deposited by PECVD, the DBR layer is a dielectric film of Si3N4 layer and SiO2 layer deposited alternately; N electrode and P electrode windows are respectively formed on the N-type extension bar and the conductive metal layer by BOE6 wet etching; metal layer is deposited in the electrode window to form negative pad and positive pad electrodes; the chip is polished, thinned and cut to complete the chip manufacturing; the present application uses PECVD to alternately deposit Si3N4 layer and SiO2 layer as DBR layer, and uses BOE wet etching to etch the DBR layer. The DBR layer formed by the method has good insulation, high optical reflectivity, simple manufacturing, low cost and short time consumption, and can solve the problems encountered in the existing flip LED chip technology.

[0004] However, the preparation method needs to be subjected to multiple photoetchings, and is affected by the exposure machine alignment accuracy. About 4 μm photoetching offset window needs to be set for each photoetching, otherwise it is easy to cause electric leakage or other electrical problems, so the more the number of photoetchings, the more difficult the manufacturing is. Moreover, the photoetching offset window needs to be reserved for each layer of film, which causes great waste of light emitting area. SUMMARY

[0005] In order to overcome the defects of the prior art, the technical problem to be solved by the present application is to provide a DBR flip chip manufacturing method. The LED flip chip prepared by the method has less photoetching times and large light emitting area.

[0006] In order to solve the above technical problems, the technical scheme adopted by the present application is a DBR flip chip manufacturing method, comprising the following steps:

[0007] S1: sequentially growing a N-type semiconductor layer, a multi-quantum well layer, and a P-type semiconductor layer on a substrate;

[0008] S2: depositing a layer of SiO2 on the surface of the P-type semiconductor layer;

[0009] S3: making a current blocking layer and a first set of etching by first lithography and BOE etching,

[0010] S4: evaporating an ITO layer above the current blocking layer;

[0011] S5: obtaining a Mesa opening pattern and a set of etching required by the remaining procedures after the second lithography;

[0012] S6: etching by using ITO etching liquid first, and then etching to obtain a Mesa step surface;

[0013] S7: obtaining a Mesa cutting path pattern and an ISO cutting path pattern by third lithography;

[0014] S8: etching by using ITO etching liquid first, and then etching to obtain a Mesa cutting path and an ISO cutting path;

[0015] S9: forming a current spreading layer on the exposed part of the N-type semiconductor layer and the P-type semiconductor layer by evaporation;

[0016] S10: forming a DBR reflection layer above the P-type semiconductor layer by evaporation and etching;

[0017] S11: evaporating P-type pads and N-type pads to obtain a metal electrode pad layer, and injecting a DBR etching hole connected to the current spreading layer to conduct.

[0018] The DBR flip chip manufacturing method has the advantages that the Mesa cutting path and the ISO cutting path are etched together by lithography, thereby reducing the number of lithography, reducing exposure deviation, maximizing the area of the GaN layer and the area of the ITO (transparent conductive layer) thereon, increasing the light-emitting efficiency, and improving the brightness. Separating the inner opening (step surface) and the outer opening (cutting path) for etching can more effectively control the etching depth of the outer opening, and can prevent over-etching of the N-Gan in the Mesa inner opening, thereby preventing abnormal electrical properties. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figure 1 Fig. 3 shows a product structure schematic diagram of S3 of the DBR flip chip manufacturing method of the embodiment of the present application;

[0020] Figure 2 Fig. 4 shows a product structure schematic diagram of S4 of the DBR flip chip manufacturing method of the embodiment of the present application;

[0021] Figure 3 Fig. 6 shows a product structure schematic diagram of S6 of the DBR flip chip manufacturing method according to the embodiment of the present application;

[0022] Figure 4 Fig. 7 shows a product structure schematic diagram of S8 of the DBR flip chip manufacturing method according to the embodiment of the present application;

[0023] Figure 5 Fig. 8 shows a product structure schematic diagram of S9 of the DBR flip chip manufacturing method according to the embodiment of the present application;

[0024] Figure 6 Fig. 9 shows a product structure schematic diagram of S10 of the DBR flip chip manufacturing method according to the embodiment of the present application;

[0025] Figure 7 Fig. 10 shows a product structure schematic diagram of S11 of the DBR flip chip manufacturing method according to the embodiment of the present application;

[0026] Label explanation: 1, substrate; 2, N-type semiconductor layer; 3, multi-quantum well layer; 4, P-type semiconductor layer; 5, current blocking layer; 6, ITO layer; 7, current spreading layer; 8, DBR reflection layer; 9, metal electrode pad layer; 10, Mesa cutting path; 11, ISO cutting path. DETAILED DESCRIPTION

[0027] To make the technical content of the present application, the purposes achieved and the effects clear, the following will be described in conjunction with the embodiments and the accompanying drawings.

[0028] The most key idea of the present application is to photoetch the Mesa cutting path and the ISO cutting path together to reduce the exposure deviation and maximize the area of the GaN layer and the area of the ITO (transparent conductive layer) thereon.

[0029] Please refer to Figures 1 to 7 Fig. 1 shows a DBR flip chip manufacturing method, which comprises the following steps:

[0030] S1: sequentially growing a GaN-based N-type semiconductor layer, a multi-quantum well layer, and a P-type semiconductor layer on a substrate;

[0031] S2: depositing a layer of SiO2 on the surface of the P-type semiconductor layer;

[0032] S3: making a current blocking layer and a first set of etching by first photoetch and BOE etching,

[0033] S4: evaporating an ITO layer on the current blocking layer;

[0034] S5: Mesa opening pattern after the second photoetching and the overlay required for the remaining processes;

[0035] S6: Etching using ITO etching solution, then etching to obtain Mesa step surface;

[0036] S7: Third photoetching to obtain Mesa cutting path pattern and ISO cutting path pattern;

[0037] S8: Etching using ITO etching solution, then etching to obtain Mesa cutting path and ISO cutting path;

[0038] S9: Forming current expansion layer on the exposed part of N-type semiconductor layer and P-type semiconductor layer by evaporation;

[0039] S10: Forming DBR (distributed Bragg reflector) reflective layer on the top of P-type semiconductor layer by evaporation and etching;

[0040] S11: Evaporating P-type pad and N-type pad to obtain metal electrode pad layer, and injecting DBR etching hole connected with current expansion layer to conduct.

[0041] As can be seen from the above description, Mesa cutting path and ISO cutting path are photoetched and etched synchronously, thereby reducing the etched P-type semiconductor layer and ITO, maximizing the area of GaN layer and the area of ITO (transparent conductive layer) thereon, increasing the light emitting efficiency and improving the brightness. Reducing the number of photoetching can also reduce the multi-path processing flow, shorten the processing time, and save labor and equipment costs.

[0042] The present application etches the inner opening (step surface) and the outer opening (cutting path) separately, which can better control the etching depth of the outer opening, prevent over-etching of N-Gan in the Mesa inner opening, and cause electrical abnormalities; the present application uses ITO etching for the inner opening and the outer opening, which can better control the inner and outer ITO etching line width.

[0043] Further, the deposition thickness of SiO2 in S2 is

[0044] As can be seen from the above description, which can meet the demand of current blocking effect, and over-thick deposition time causes waste of production capacity.

[0045] Further, the thickness of ITO layer is

[0046] Further, the specific steps of the second photoetching are: coating 22-26 μm of positive photoresist, and then preparing the Mesa opening hole pattern and the required overlaying of the remaining procedures by successively undergoing exposure with 80-100 mj exposure amount and development.

[0047] From the above description, it is known that,

[0048] Further, the specific steps of the third photoetching are: coating 34-38 μm of positive photoresist, and then preparing the Mesa cutting path pattern and the ISO cutting path pattern by successively undergoing exposure with 100-120 mj exposure amount and development.

[0049] From the above description, it is known that the thickness of the photoresist of the second photoetching and the third photoetching is different, because the etching depth and the photoresist etching mask are different. The etching depth of the inner opening hole is 2.4 μm, and the etching depth of the outer opening hole is 5 μm.

[0050] Further, the width of the ISO cutting path pattern is 3.5-4.5 μm.

[0051] Further, the side etching amount of the ITO etching solution is 5-7 μm.

[0052] From the above description, it is known that the core particle spacing of the ITO obtained by the prior art is 34 μm, but under the photoetching process of the present application, the spacing can be reduced to 18-22 μm, i.e. the single-side ITO is enlarged by 7 μm, and the light-emitting area of the chip is increased.

[0053] Further, the width of the ISO cutting path is 14-18 μm.

[0054] Further, the current spreading layer is composed of a metal electrode composed of an N-type semiconductor layer and a P-type semiconductor layer.

[0055] Further, the DBR reflection layer is composed of SiO2 and Ti3O5 arranged alternately.

[0056] Further, the DBR reflection layer is composed of SiO2 and Ti3O5 arranged alternately in the ABAB mode.

[0057] Please refer to Figures 1 to 7 The embodiment one of the present application is: a manufacturing method of a DBR flip chip, comprising the following steps:

[0058] S1: using metal organic chemical vapor deposition method to grow N-type semiconductor layer 2, multi-quantum well layer 3 and P-type semiconductor layer 4 on sapphire substrate 1 in sequence;

[0059] S2: using PECVD machine to deposit a layer of SiO2 on the surface of P-type semiconductor layer;

[0060] S3: making current blocking layer 5 and first set of etching by first lithography and BOE etching,

[0061] S4: evaporating ITO layer 6 on the top of current blocking layer;

[0062] S5: second lithography: coating 24μm positive photoresist, baking at 110℃ for 90s, then exposing with 90mj exposure amount, developing at 150℃ for 90s to prepare Mesa opening pattern and set of etching required in the remaining process;

[0063] S6: first using ITO etching solution to etch ITO at Mesa opening, then using ICP to etch Mesa step surface; the side etching amount of ITO etching solution is 6μm;

[0064] S7: third lithography: coating 36μm positive photoresist, baking at 110℃ for 90s, then exposing with 110mj exposure amount, developing at 135℃ for 90s to prepare Mesa cutting path pattern and ISO cutting path pattern; the width of ISO cutting path pattern is 4μm;

[0065] S8: first using ITO etching solution to etch ITO at Mesa cutting path pattern and ISO cutting path pattern, then using ICP to etch ISO deep groove, etching all GaN in the groove completely to obtain Mesa cutting path 10 and ISO cutting path 11; the side etching amount of ITO etching solution is 6μm; the width of ISO cutting path 11 is 16μm;

[0066] S9: forming current spreading layer 7 on the exposed part of N-type semiconductor layer and P-type semiconductor layer by evaporation; the current spreading layer is composed of metal electrode of N-type semiconductor layer 2 and P-type semiconductor layer 4;

[0067] S10: forming DBR (distributed Bragg reflector) reflecting layer 8 on the top of P-type semiconductor layer 4 by evaporation and etching; the DBR reflecting layer is composed of SiO2 and Ti3O5 arranged alternately in ABAB mode;

[0068] S11: evaporating P-type pad and N-type pad to obtain metal electrode pad layer 9, and injecting DBR etching hole to connect and conduct with current spreading layer. ​​

[0069] The DBR flip chip of the embodiment one is tested for performance, and the test result is that the ITO interval is 20 mu m, and the ITO overall area is 86400 mu m 2 .

[0070] Therefore, the ITO interval of the conventional LED flip chip is generally 34 mu, and the ITO overall area is about 77356 mu m 2 Compared with the conventional LED flip chip, the ITO overall area of the obtained LED flip chip of the application is expanded by 9044 mu m 2 (about 11.7%), and the brightness ratio is improved by about 3.44%.

[0071] The embodiment two of the application is a manufacturing method of a DBR flip chip, comprising the following steps:

[0072] S1: a metal organic chemical vapor deposition method is used to sequentially grow a N-type semiconductor layer, a multi-quantum well layer and a P-type semiconductor layer of gallium nitride on a substrate;

[0073] S2: a PECVD machine is used to deposit a layer of SiO2 on the surface of the P-type semiconductor layer;

[0074] S3: a current blocking layer and a first set of etching are made by first photoetching and BOE etching,

[0075] S4: a layer of ITO is evaporated on the current blocking layer;

[0076] S5: second photoetching: 22 mu m of positive photoresist is coated, baked at 110 DEG C for 90 s, then exposed by 80 mj, and developed at 150 DEG C for 90 s to prepare a Mesa opening pattern and a set of etching required in the remaining procedures;

[0077] S6: ITO etching liquid is used to etch the ITO at the Mesa opening, and ICP etching is used to obtain a Mesa step surface; the side etching amount of the ITO etching liquid is 5 mu m;

[0078] S7: third photoetching: 34-38 mu m of positive photoresist is coated, baked at 110 DEG C for 90 s, then exposed by 100 mj, and developed at 135 DEG C for 90 s to prepare a Mesa cutting path pattern and an ISO cutting path pattern; the width of the ISO cutting path pattern is 3.5 mu m;

[0079] ​​S8: etching ITO of Mesa cutting path pattern and ISO cutting path pattern by using ITO etching liquid first, and then etching ISO deep groove by ICP to etch all GaN in the groove completely, so as to obtain Mesa cutting path and ISO cutting path; the side etching amount of ITO etching liquid is 5 μm; the width of ISO cutting path is 14 μm;

[0080] S9: forming a current spreading layer on the exposed part of the N-type semiconductor layer and the P-type semiconductor layer by evaporation; the current spreading layer is composed of a metal electrode of the N-type semiconductor layer and the P-type semiconductor layer;

[0081] S10: forming a DBR (distributed Bragg reflector) reflective layer above the P-type semiconductor layer by evaporation and etching; the DBR reflective layer is composed of SiO2 and Ti3O5 arranged alternately in ABAB mode;

[0082] S11: evaporating P-type pads and N-type pads to obtain a metal electrode pad layer, and injecting DBR etching holes to be connected and conductive with the current spreading layer.

[0083] Embodiment three of the application is a manufacturing method of a DBR flip chip, comprising the following steps:

[0084] S1: growing a GaN-based N-type semiconductor layer, a multi-quantum well layer and a P-type semiconductor layer on a substrate in sequence by using a metal organic chemical vapor deposition method;

[0085] S2: depositing a layer of SiO2 on the surface of the P-type semiconductor layer by using a PECVD machine;

[0086] S3: making a current blocking layer and a first set of etching by first photolithography and BOE etching,

[0087] S4: evaporating an ITO layer on the current blocking layer;

[0088] S5: second photolithography: coating 26 μm of positive photoresist, baking at 110 DEG C for 90 s, then exposing at an exposure amount of 80-100 mj, and developing at 150 DEG C for 90 s to prepare a Mesa opening pattern and a set of etching required in the remaining processes;

[0089] S6: etching ITO of the Mesa opening by using ITO etching liquid first, and then etching to obtain a Mesa step surface; the side etching amount of ITO etching liquid is 5-7 μm;

[0090] ​​S7: Third photoetching: 38 mu m of positive photoresist is coated, baked at 110 DEG C for 90s, and then exposed by 120 mj exposure, and developed at 135 DEG C for 90s to prepare Mesa cutting path pattern and ISO cutting path pattern; the width of ISO cutting path pattern is 4.5 mu m;

[0091] S8: ITO etching liquid is used for etching first, and ITO of Mesa cutting path pattern and ISO cutting path pattern is etched, then ICP is used for etching ISO deep groove, and GaN in the groove is etched completely to obtain Mesa cutting path and ISO cutting path; the side etching amount of ITO etching liquid is 7 mu m; the width of ISO cutting path is 18 mu m;

[0092] S9: A current spreading layer is formed on the exposed part of the N-type semiconductor layer and the P-type semiconductor layer by evaporation; the current spreading layer is composed of a metal electrode composed of the N-type semiconductor layer and the P-type semiconductor layer;

[0093] S10: A DBR (distributed Bragg reflector) reflective layer is formed on the P-type semiconductor layer by evaporation and etching; the DBR reflective layer is composed of SiO2 and Ti3O5 arranged alternately in ABAB mode;

[0094] S11: P-type pads and N-type pads are evaporated to obtain a metal electrode pad layer, and DBR etching holes are injected to be connected and conductive with the current spreading layer.

[0095] In summary, the manufacturing method of the DBR flip chip provided by the application simultaneously photoetches the Mesa cutting path and the ISO cutting path, and synchronously etches them, thereby reducing the etched P-type semiconductor layer and ITO, maximizing the area of the GaN layer and the area of the ITO (transparent conductive layer) thereon, increasing the light-emitting efficiency, and improving the brightness. Reducing the number of photoetching can also reduce the multi-path processing flow, shorten the processing time, and save labor and equipment costs.

[0096] The application etches the inner opening (step surface) and the outer opening (cutting path) separately, which can more effectively control the etching depth of the outer opening, and can prevent over-etching of N-Gan in the Mesa inner opening, thereby causing abnormal electrical properties; the application uses ITO etching for the inner opening and the outer opening, which can better control the inner and outer ITO etching line width.

[0097] The above description is only an embodiment of the application, and does not limit the patent range of the application, and any equivalent transformation or direct or indirect application in related technical fields based on the content of the specification and drawings of the application is also included in the patent protection range of the application.

Claims

1. A method of manufacturing a DBR flip chip, characterized by, The method comprises the following steps: S1: sequentially growing a N-type semiconductor layer, a multi-quantum well layer and a P-type semiconductor layer on a substrate; S2: depositing a layer of SiO2 on the surface of the P-type semiconductor layer; S3: making a current blocking layer and a first set of etching by first photoetching and BOE etching, S4: evaporating an ITO layer on the current blocking layer; S5: obtaining a Mesa opening pattern and a set of etching required by the remaining procedures after second photoetching; S6: etching by using ITO etching liquid first, and then etching to obtain a Mesa step surface; S7: third photoetching to obtain a Mesa cutting path pattern and an ISO cutting path pattern; S8: etching by using ITO etching liquid first, and then etching to obtain a Mesa cutting path and an ISO cutting path; S9: forming a current spreading layer on the exposed part of the N-type semiconductor layer and the P-type semiconductor layer by evaporation; S10: forming a DBR reflection layer on the P-type semiconductor layer by evaporation and etching; S11: evaporating P-type pads and N-type pads to obtain a metal electrode pad layer, and injecting a DBR etching hole connected with the current spreading layer to conduct.

2. The DBR flip chip fabrication method according to claim 1, wherein The specific steps of the second photoetching are: coating 22-26 μm of positive photoresist, and then preparing a Mesa opening pattern and a set of etching required by the remaining procedures after 80-100 mj exposure and development.

3. The DBR flip chip fabrication method according to claim 1, wherein The specific steps of the third photoetching are: coating 34-38 μm of positive photoresist, and then preparing a Mesa cutting path pattern and an ISO cutting path pattern after 100-120 mj exposure and development.

4. The DBR flip chip fabrication method according to claim 1, wherein The width of the ISO cutting path pattern is 3.5-4.5 μm.

5. The DBR flip chip fabrication method according to claim 1, wherein The side etching amount of the ITO etching liquid is 5-7 μm.

6. The DBR flip-chip fabrication method according to claim 1, wherein The width of the ISO cutting path is 14-18 μm.

7. The DBR flip-chip fabrication method according to claim 1, wherein The current spreading layer is composed of a metal electrode composed of the N-type semiconductor layer and the P-type semiconductor layer.

8. The DBR flip chip fabrication method according to claim 1, wherein The DBR reflection layer is composed of SiO2 and Ti3O5 arranged alternately.

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