An RS-485 / 422 transmitter driver circuit based on low-voltage CMOS process

Abstract

The present invention discloses an RS-485 / 422 transmitter driver circuit implemented based on a low-voltage CMOS process, including: a logic control circuit, a pull-up drive circuit, and a pull-down drive circuit, wherein: the first input terminal of the logic control circuit is connected to the first output terminal of the pull-up drive circuit, the second input terminal of the logic control circuit is connected to a data signal, the third input terminal of the logic control circuit is connected to the second output terminal of the pull-down drive circuit, the first output terminal of the logic control circuit is connected to the first input terminal of the pull-up drive circuit, the second output terminal of the logic control circuit is connected to the first input terminal of the pull-down drive circuit, the second output terminal of the pull-up drive circuit is the A / B pin of the chip, which is used to connect the RS-485 / 422 bus, and the first output terminal of the pull-down drive circuit is the A / B pin of the chip, which is used to connect the RS-485 / 422 bus. It adopts a low-voltage CMOS process and has the advantages of high voltage resistance, high scalability, and reduced manufacturing costs.

Description

Technical Field

[0001] The present invention relates to an RS-485 / 422 transmitter driver circuit implemented based on a low-voltage CMOS process. Background Art

[0002] RS-485 / 422 is a low-cost and reliable communication specification, which can be used in industrial, civil, and military fields such as control systems and microcomputer systems. RS-485 / 422 defines the corresponding interface electrical characteristics. Generally, the withstand voltage range of the A port and B port of the transmitter is usually -7.5V to +12.5V. This poses a high requirement for the withstand voltage of the MOS transistors in the driver circuit.

[0003] Currently, the MOS transistors in the RS-485 / 422 transmitter circuit usually use high-voltage MOS devices such as DMOS as an example. However, the feature size of such devices is usually larger than that of ordinary CMOS processes. Considering the manufacturing cost, it is necessary to design a driver circuit that can be applied to ordinary low-voltage CMOS processes. Summary of the Invention

[0004] The purpose of the present invention is to provide an RS-485 / 422 transmitter driver circuit, which adopts a low-voltage CMOS process, can withstand high voltage, reduce manufacturing costs, and has scalability. It can be implemented based on processes with different voltages, solving the problems in the prior art.

[0005] To achieve the above purpose, the present invention provides the following technical solutions:

[0006] An RS-485 / 422 transmitter driver circuit for driving the A / B pins of a chip and protecting the chip within a relatively large voltage range of -7.5V to +12.5V. The RS-485 / 422 transmitter driver circuit includes: a logic control circuit, a pull-up drive circuit, and a pull-down drive circuit, where:

[0007] The first input terminal of the logic control circuit is connected to the first output terminal of the pull-up drive circuit. The second input terminal of the logic control circuit is connected to a data signal. The third input terminal of the logic control circuit is connected to the second output terminal of the pull-down drive circuit. The first output terminal of the logic control circuit is connected to the first input terminal of the pull-up drive circuit. The second output terminal of the logic control circuit is connected to the first input terminal of the pull-down drive circuit. The second output terminal of the pull-up drive circuit is the A / B pin of the chip for connecting the RS-485 / 422 bus. The first output terminal of the pull-down drive circuit is the A / B pin of the chip for connecting the RS-485 / 422 bus.

[0008] Preferably, the logic control circuit indirectly detects the voltage of the A / B pins by connecting to the pull-up drive circuit. When the voltage is lower than the first preset voltage, the first output terminal outputs a second voltage signal to turn off the drive transistor in the pull-up drive circuit; when the voltage is higher than the first preset voltage, the first output terminal outputs a data signal; when the voltage is higher than the preset second voltage, the second output terminal outputs a first voltage signal to turn off the drive transistor in the pull-down drive circuit; when the voltage is lower than the preset second voltage, the second output terminal outputs a data signal.

[0009] Preferably, the pull-up drive circuit is used to transmit data signals and protect the circuit when the voltage of the A / B pins is too high or too low. When the second voltage signal is input to the first input terminal of the pull-up drive circuit, the drive circuit is turned off; when the data signal is input to the first input terminal of the pull-up drive circuit and the voltage of the A / B pins is between the first preset voltage and the second preset voltage, the drive circuit works normally and outputs a data signal; when the data signal is input to the first input terminal of the pull-up drive circuit and the voltage of the A / B pins is higher than the second preset voltage, the drive circuit is turned off.

[0010] Preferably, the pull-down drive circuit is used to transmit data signals and protect the circuit when the voltage of the A / B pins is too high or too low. When the first voltage signal is input to the first input terminal of the pull-down drive circuit, the drive circuit is turned off; when the data signal is input to the first input terminal of the pull-up drive circuit and the voltage of the A / B pins is between the first preset voltage and the second preset voltage, the drive circuit works normally and outputs a data signal; when the data signal is input to the first input terminal of the pull-down drive circuit and the voltage of the A / B pins is lower than the first preset voltage, the drive circuit is turned off.

[0011] Preferably, the logical control circuit is composed as follows: the gates of the twenty-second NMOS transistor and the twenty-third NMOS transistor are connected, serving as the third input terminal of the logical control circuit; the drains of the twenty-second NMOS transistor and the twenty-third NMOS transistor are connected to the power supply voltage; the sources of the twenty-second NMOS transistor and the twenty-third NMOS transistor are connected and then connected to the gate of the twenty-fourth PMOS transistor; the substrates of the twenty-second NMOS transistor and the twenty-third NMOS transistor are connected to their sources; the source of the twenty-fourth PMOS transistor is connected to the power supply voltage, and the drain is connected to the input terminal of the first inverter and the source of the twenty-fifth PMOS transistor; the drain and the gate of the twenty-fifth PMOS transistor are connected to the ground potential; the input terminal of the second inverter is the second input terminal of the logical control circuit; the output terminals of the first and second inverters are respectively connected to the two inputs of the first NAND gate; the output of the first NAND gate is the first output terminal of the logical control circuit; the gates of the twenty-second PMOS transistor and the twenty-third PMOS transistor are connected, serving as the first input terminal of the logical control circuit; the drains of the twenty-second PMOS transistor and the twenty-third PMOS transistor are connected to the ground potential; the sources of the twenty-second PMOS transistor and the twenty-third PMOS transistor are connected and then connected to the gate of the twenty-fourth NMOS transistor; the substrates of the twenty-second PMOS transistor and the twenty-third PMOS transistor are connected to their sources; the source of the twenty-fourth NMOS transistor is connected to the ground potential, and the drain is connected to the input terminal of the first buffer and the source of the twenty-fifth NMOS transistor; the drain and the gate of the twenty-fifth NMOS transistor are connected to the power supply voltage; the two inputs of the first AND gate are respectively the output terminal of the first buffer and the second input terminal of the logical control circuit; the output of the first AND gate is the second output terminal of the logical control circuit.

[0012] Preferably, the pull-up driving circuit is composed as follows: the gate of the fifth PMOS transistor is the first input terminal of the pull-up driving circuit, the source is connected to the power supply voltage and the first input terminal of the first floating well circuit, the drain is connected to the source of the fourth PMOS transistor, the second input terminal of the first floating well circuit and the second input terminal of the second floating well circuit, and the substrate is connected to the output terminal of the first floating well circuit; the gate of the fourth PMOS transistor is connected to the ground potential and the first input of the first basic stacking unit, the drain is connected to the second input terminal of the second floating well circuit and the second input of the first basic stacking unit. Between different basic stacking units, the first and second outputs of the previous one are connected to the first and second inputs of the next one, and the number of basic units is determined by the maximum withstand voltage of the process. The first output of the last basic stacking unit is connected to one end of the second resistor and the gates of the nineteenth NMOS transistor and the sixth PMOS transistor, the other end of the second resistor is connected to the source of the first PMOS transistor, the drains of the nineteenth NMOS transistor and the sixth PMOS transistor, the source of the nineteenth NMOS transistor is connected to the source of the sixth PMOS transistor through the first resistor, the second output of the last basic stacking unit is connected to the source of the first PMOS transistor and the first input terminal of the third floating well circuit, the substrate is connected to the output terminal of the floating well circuit, and the drain is connected to the second input terminal of the third floating well circuit, which is the second output of the pull-up driving circuit.

[0013] Preferably, the floating well circuit in the pull-up driving circuit is composed as follows: the gates of the seventeenth PMOS transistor and the drain of the eighteenth PMOS transistor are connected together, which is the first input terminal of the floating well circuit; the drain of the seventeenth PMOS transistor and the gate of the eighteenth PMOS transistor are connected together, which is the second input terminal of the floating well circuit; the sources and substrate electrodes of the seventeenth PMOS transistor and the eighteenth PMOS transistor are connected together, which is the first output terminal of the floating well circuit. Its function is to compare the magnitudes of the voltages of the two inputs and output the larger voltage.

[0014] Preferably, the basic stacking circuit in the pull-up driving circuit is composed as follows: one end of the fourth resistor is the first input terminal of the basic stacking circuit, and the other end is connected to the gate of the third PMOS transistor and the source of the twelfth PMOS transistor, which is the first output terminal of the basic stacking circuit; the source of the third PMOS transistor is connected to the gate of the twelfth PMOS transistor and the first input terminal of the fourth floating well circuit, which is the second input terminal of the basic stacking circuit; the drain of the third PMOS transistor is connected to the second input terminal of the fourth floating well circuit and the drain of the twelfth PMOS transistor, and the substrates of the third PMOS transistor and the twelfth PMOS transistor are connected to the first output terminal of the fourth floating well circuit, which is the second output terminal of the basic stacking circuit. According to the maximum withstand voltage values of MOS transistors in different processes, the number of basic stacking units is selected to meet the withstand voltage requirements of the circuit.

[0015] Preferably, the structure of the pull-down driving circuit is symmetrical to that of the pull-up driving circuit, that is, the PMOS in the pull-up driving circuit is changed to NMOS, the NMOS is changed to PMOS, the ground potential is changed to the power supply voltage, and the power supply voltage is changed to the ground potential.

[0016] Compared with the prior art, the beneficial effects of the present invention are as follows: By adopting the low-voltage CMOS process, it can withstand high voltage, reduce the manufacturing cost, and has scalability, and can be implemented based on processes with different voltages. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a schematic block diagram of the RS-485 / 422 transmitter driver circuit according to Embodiment 1 of the present invention.

[0018] Figure 2 It is a circuit connection diagram of the logic control circuit of the RS-485 / 422 transmitter driver circuit according to Embodiment 1 of the present invention.

[0019] Figure 3 It is a circuit connection diagram of the pull-up driving circuit of the RS-485 / 422 transmitter driver circuit according to Embodiment 1 of the present invention.

[0020] Figure 4 It is a circuit connection diagram of the pull-down driving circuit of the RS-485 / 422 transmitter driver circuit according to Embodiment 1 of the present invention.

[0021] In the figure: 1 - logic control circuit, 2 - pull-up driving circuit, 3 - pull-down driving circuit, 201 - first inverter, 202 - second inverter, 203 - first NAND gate, 204 - first AND gate, 205 - first buffer DETAILED DESCRIPTION OF THE EMBODIMENTS

[0022] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0023] Embodiment:

[0024] Please refer to Figure 1 , an RS-485 / 422 transmitter driver circuit based on a 5V CMOS process, requiring that when the A / B pins are in the range of -7.5V to 12.5V, the gate-source, gate-drain, and drain-source voltages of each MOS transistor do not exceed 5V. As Figure 1 shown, the RS-485 / 422 transmitter driver circuit of this embodiment includes a logic control circuit 1, a pull-up driving circuit 2, and a pull-down driving circuit 3, where:

[0025] The composition of the logic control circuit is as follows: the gate of the twenty-second NMOS transistor is connected to the drain of the twenty-third NMOS transistor, which serves as the third input terminal of the logic control circuit; the drain of the twenty-second NMOS transistor and the gate of the twenty-third NMOS transistor are connected to the power supply voltage; the sources of the twenty-second NMOS transistor and the twenty-third NMOS transistor are connected together and connected to the gate of the twenty-fourth PMOS transistor; the substrates of the twenty-second NMOS transistor and the twenty-third NMOS transistor are connected to their sources; the source of the twenty-fourth PMOS transistor is connected to the power supply voltage, and the drain is connected to the input terminal of the first inverter and the source of the twenty-fifth PMOS transistor; the drain and the gate of the twenty-fifth PMOS transistor are connected to the ground potential; the input terminal of the second inverter is the second input terminal of the logic control circuit; the output terminals of the first and second inverters are respectively connected to the two inputs of the first NAND gate; the output of the first NAND gate is the first output terminal of the logic control circuit; the gate of the twenty-second PMOS transistor is connected to the drain of the twenty-third PMOS transistor, which serves as the first input terminal of the logic control circuit; the drain of the twenty-second PMOS transistor and the gate of the twenty-third PMOS transistor are connected to the ground potential; the sources of the twenty-second PMOS transistor and the twenty-third PMOS transistor are connected together and connected to the gate of the twenty-fourth NMOS transistor; the substrates of the twenty-second PMOS transistor and the twenty-third PMOS transistor are connected to their sources; the source of the twenty-fourth NMOS transistor is connected to the ground potential, and the drain is connected to the input terminal of the first buffer and the source of the twenty-fifth NMOS transistor; the drain and the gate of the twenty-fifth NMOS transistor are connected to the power supply voltage; the two inputs of the first AND gate are respectively the output terminal of the first buffer and the second input terminal of the logic control circuit; the output of the first AND gate is the second output terminal of the logic control circuit.

[0026] The composition of the pull-up driving circuit is as follows: The gate of the fifth PMOS transistor is the first input terminal of the pull-up driving circuit. The source is connected to the power supply voltage and the first input terminal of the first floating well circuit. The drain is connected to the source of the fourth PMOS transistor, the second input terminal of the first floating well circuit, and the second input terminal of the second floating well circuit. The substrate is connected to the output terminal of the first floating well circuit. The gate of the fourth PMOS transistor is connected to the ground potential and the first input of the first basic stacking unit. The drain is connected to the second input terminal of the second floating well circuit and the second input of the first basic stacking unit. Between different basic stacking units, the first and second outputs of the previous one are connected to the first and second inputs of the subsequent one. The number of basic units is determined by the maximum breakdown voltage of the process. The first output of the last basic stacking unit is connected to one end of the second resistor, and the gates of the nineteenth NMOS transistor and the sixth PMOS transistor. The other end of the second resistor is connected to the source of the first PMOS transistor, the drains of the nineteenth NMOS transistor and the sixth PMOS transistor. The source of the nineteenth NMOS transistor is connected to the source of the sixth PMOS transistor through the first resistor. The second output of the last basic stacking unit is connected to the source of the first PMOS transistor and the first input terminal of the third floating well circuit. The substrate is connected to the output terminal of the floating well circuit. The drain is connected to the second input terminal of the third floating well circuit, which is the second output of the pull-up driving circuit.

[0027] Preferably, the composition of the floating well circuit in the pull-up driving circuit is as follows: The gates of the seventeenth PMOS transistor and the drain of the eighteenth PMOS transistor are connected together, which is the first input terminal of the floating well circuit. The drain of the seventeenth PMOS transistor and the gate of the eighteenth PMOS transistor are connected together, which is the second input terminal of the floating well circuit. The sources and substrate electrodes of the seventeenth PMOS transistor and the eighteenth PMOS transistor are connected together, which is the first output terminal of the floating well circuit. Its function is to compare the magnitudes of the voltages of the two inputs and output the larger voltage.

[0028] Preferably, the composition of the basic stacking circuit in the pull-up driving circuit is as follows: One end of the fourth resistor is the first input terminal of the basic stacking circuit, and the other end is connected to the gate of the third PMOS transistor and the source of the twelfth PMOS transistor, which is the first output terminal of the basic stacking circuit. The source of the third PMOS transistor is connected to the gate of the twelfth PMOS transistor and the first input terminal of the fourth floating well circuit, which is the second input terminal of the basic stacking circuit. The drain of the third PMOS transistor is connected to the second input terminal of the fourth floating well circuit and the drain of the twelfth PMOS transistor. The substrates of the third PMOS transistor and the twelfth PMOS transistor are connected to the first output terminal of the fourth floating well circuit, which is the second output terminal of the basic stacking circuit. According to the maximum breakdown voltage values of MOS transistors with different processes, the number of basic stacking units is selected to meet the breakdown voltage requirements of the circuit.

[0029] The structure of the pull-down driving circuit is symmetrical to that of the pull-up driving circuit, that is, the PMOS in the pull-up driving circuit is changed to NMOS, the NMOS is changed to PMOS, the ground potential is changed to the power supply voltage, and the power supply voltage is changed to the ground potential.

[0030] The first input end of the logic control circuit is connected to the first output end of the pull-up driving circuit, the second input end of the logic control circuit is connected to the data signal, the third input end of the logic control circuit is connected to the second output end of the pull-down driving circuit, the first output end of the logic control circuit is connected to the first input end of the pull-up driving circuit, the second output end of the logic control circuit is connected to the first input end of the pull-down driving circuit, the second output end of the pull-up driving circuit is the A / B pin of the chip for connecting the RS-485 / 422 bus, and the first output end of the pull-down driving circuit is the A / B pin of the chip for connecting the RS-485 / 422 bus.

[0031] The logic control circuit indirectly detects the voltage of the A / B pin through the connection with the pull-up driving circuit. When the voltage is lower than the first preset voltage, the first output end outputs a second voltage signal to turn off the driving transistor in the pull-up driving circuit; when the voltage is higher than the first preset voltage, the first output end outputs a data signal; when the voltage is higher than the preset second voltage, the second output end outputs a first voltage signal to turn off the driving transistor in the pull-down driving circuit; when the voltage is lower than the preset second voltage, the second output end outputs a data signal.

[0032] The pull-up driving circuit is used to transmit data signals and protect the circuit when the voltage of the A / B pin is too high or too low. When the second voltage signal is input to the first input end of the pull-up driving circuit, the driving circuit is turned off; when the data signal is input to the first input end of the pull-up driving circuit and the voltage of the A / B pin is between the first preset voltage and the second preset voltage, the driving circuit works normally and outputs data signals; when the data signal is input to the first input end of the pull-up driving circuit and the voltage of the A / B pin is higher than the second preset voltage, the driving circuit is turned off.

[0033] The pull-down driving circuit is used to transmit data signals and protect the circuit when the voltage of the A / B pin is too high or too low. When the first voltage signal is input to the first input end of the pull-down driving circuit, the driving circuit is turned off; when the data signal is input to the first input end of the pull-up driving circuit and the voltage of the A / B pin is between the first preset voltage and the second preset voltage, the driving circuit works normally and outputs data signals; when the data signal is input to the first input end of the pull-down driving circuit and the voltage of the A / B pin is lower than the first preset voltage, the driving circuit is turned off.

[0034] For convenience of description, the first preset voltage is set to 0V and the second preset voltage is set to 3.3V below. Of course, it does not mean that the first preset voltage and the second preset voltage are limited to this.

[0035] Specifically, the circuit connection of the logic control circuit 1 is as Figure 2 shown, and its four working conditions are introduced:

[0036] (1) When the voltage of the A / B pin is lower than 0V, BELOW_GS is a voltage value less than 3.3V. Therefore, the twenty-third NMOS transistor NM23 conducts, and transmits the signal of BELOW_GS to the gate terminal of the twenty-fourth PMOS transistor PM24. At this time, PM24 also conducts, pulling up the input terminal of the first inverter 201, so that the output of 201 is low. Therefore, the output of the first NAND gate 203 is at a high potential, that is, VCTRL_P is at a high potential.

[0037] (2) When the voltage of the A / B pin is higher than 0V, BELOW_GS is a voltage value greater than or equal to 3.3V. Therefore, the twenty-second NMOS transistor NM22 conducts, and transmits the power supply voltage signal to the gate terminal of the twenty-fourth PMOS transistor PM24. At this time, PM24 does not conduct. The twenty-fifth PMOS transistor PM25 pulls down the input terminal of 201, so that the output of 201 is high. Therefore, the output of 203 depends on the data signal DATA, that is, VCTRL_P is consistent with the DATA signal.

[0038] (3) When the voltage of the A / B pin is higher than 3.3V, OVER_VS is a voltage value greater than 0V. Therefore, the twenty-third PMOS transistor PM23 conducts, and transmits the signal of OVER_VS to the gate terminal of the twenty-fourth NMOS transistor NM24. At this time, NM24 also conducts, pulling down the input terminal of the second inverter 202, so that the output of 202 is low. Therefore, the output of the second NAND gate 204 is at a low potential, that is, VCTRL_N is at a low potential.

[0039] (4) When the voltage of the A / B pin is lower than 3.3V, OVER_VS is a voltage value less than or equal to 0V. Therefore, the twenty-second PMOS transistor PM22 conducts, and transmits the power supply voltage signal to the gate terminal of the twenty-fourth NMOS transistor NM24. At this time, NM24 does not conduct. The twenty-fifth NMOS transistor NM25 pulls up the input terminal of 202, so that the output of 202 is high. Therefore, the output of 204 depends on the data signal DATA, that is, VCTRL_N is consistent with the DATA signal.

[0040] The circuit connection of the pull-up driving circuit 2 is as Figure 3 shown, and its three working conditions are introduced:

[0041] (1) When the voltage of the A / B pins of the RS-485 / 422 chip is greater than 3.3V, the nineteenth NMOS transistor NM19 is not conducting, and the sixth PMOS transistor PM6, the ninth PMOS transistor PM9, and the twelfth PMOS transistor PM12 are conducting. At this time, the first PMOS transistor PM1, the second PMOS transistor PM2, and the third PMOS transistor PM3 are connected in a diode form, and the gate potential is high, so they are not conducting. And the voltage differences across the two ends of the diodes respectively depend on the voltages across the second resistor RP2, the third resistor RP3, and the fourth resistor RP4. Adjust the resistance values of RP2, RP3, and RP4 as needed, and here make them equal. Considering the worst case, assume the voltage of the A / B pins is 12.5V, and the voltages across RP2, RP3, and RP4 are 12.5 / 3≈4.2V. Therefore, the voltages of PM1, PM2, and PM3 also meet the requirements in the worst case. The seventh PMOS transistor PM7 and the eighth PMOS transistor PM8 will compare the drain and source voltages of PM1 and connect the substrate potential to the lower potential to prevent leakage current in the substrate. The same goes for the tenth PMOS transistor PM10 and the eleventh PMOS transistor PM11, the thirteenth PMOS transistor PM13 and the fourteenth PMOS transistor PM14, and the fifteenth PMOS transistor PM15 and the sixteenth PMOS transistor PM16. Whether VCTRL_P is at a high potential or a low potential, since PM1, PM2, and PM3 are not conducting and there is no current in PM4 and PM5, it is easy to obtain that the voltages of PM4 and PM5 also meet the requirements. And at this time, the current in the pull-up drive circuit is very small, and there is only one path through RP2, RP3, and RP4. OVER_VS outputs a signal greater than the NMOS threshold voltage, and VCTRL_N outputs a low level.

[0042] (2) When the voltage of the A / B pins of the RS-485 / 422 chip is between 0 - 3.3V, NM19, PM9, and PM12 are not conducting, PM6 is conducting, but OVER_VS outputs a signal less than the NMOS threshold voltage. The voltages across RP2, RP3, and RP4 are all very small. Therefore, PM1, PM2, and PM3 are conducting, and the output signal of the A / B pin voltage depends on VCTRL_P.

[0043] (3) When the voltages of the A / B pins of the RS-485 / 422 chip are less than 0V, PM6, PM9, and PM12 are not conducting, VCTRL_P is at a high level, so PM5 is also not conducting. There is no current in PM1, PM2, and PM3. Thus, it can be obtained that the source voltages of PM1, PM2, PM3, and PM4 are approximately equal to their gate voltages. NM19 is conducting, so the source and drain voltages of PM1, PM2, PM3, and PM4 are approximately equal to the voltage dividers across RP1, RP2, RP3, and RP4 respectively. Adjust the resistance values of RP1, RP2, RP3, and RP4 as needed. Here, make them equal. Considering the worst case, assume the voltage of the A / B pins is -7.5V. The voltage across RP1, RP2, RP3, and RP4 is 7.5 / 4 ≈ 1.9V. Therefore, the voltages of PM1, PM2, PM3, and PM4 also meet the requirements in the worst case. And at this time, the current in the pull-up drive circuit is very small, and there is only one path through RP1, RP2, RP3, and RP4.

[0044] The circuit connection of the pull-down drive circuit 3 is as Figure 4 shown. Three working conditions of it are introduced as follows:

[0045] (1) When the voltage of the A / B pins of the RS-485 / 422 chip is less than 0V, the nineteenth PMOS transistor PM19 is not conducting, while the sixth NMOS transistor NM6, the ninth NMOS transistor NM9, and the twelfth NMOS transistor NM12 are conducting. At this time, the first NMOS transistor NM1, the second NMOS transistor NM2, and the third NMOS transistor NM3 are connected in a diode form, and the gate potential is low, so they are not conducting. And the voltage differences across the two ends of the diodes respectively depend on the voltages across the sixth resistor RN2, the seventh resistor RN3, and the eighth resistor RN4. Adjust the resistance values of RN2, RN3, and RN4 as needed, and here they are made equal. Considering the worst case, assume the voltage of the A / B pins is -7.5V, and the voltages across RN2, RN3, and RN4 are 7.5 / 3 = 2.5V. Therefore, the voltages of NM1, NM2, and NM3 also meet the requirements in the worst case. The seventh NMOS transistor NM7 and the eighth NMOS transistor NM8 will compare the drain and source voltages of NM1 and connect the substrate potential to the lower potential to prevent leakage current in the substrate. The same applies to the tenth NMOS transistor NM10 and the eleventh NMOS transistor NM11, the thirteenth NMOS transistor NM13 and the fourteenth NMOS transistor NM14, and the fifteenth NMOS transistor NM15 and the sixteenth NMOS transistor NM16. Whether VCTRL_N is at a high potential or a low potential, since NM1, NM2, and NM3 are not conducting and there is no current in NM4 and NM5, it is easy to obtain that the voltages of NM4 and NM5 also meet the requirements. And at this time, the current in the pull-up drive circuit is very small, and there is only one path through RN2, RN3, and RN4. The BELOW_GS output is a signal lower than VS and the voltage difference is greater than the NMOS threshold voltage, making VCTRL_P at a high level.

[0046] (2) When the voltage of the A / B pins of the RS-485 / 422 chip is between 0 - 3.3V, PM19, NM9, and NM12 are not conducting, NM6 is conducting, but the BELOW_GS output is a signal lower than VS but the voltage difference from VS is less than the PMOS threshold voltage. The voltages across RN2, RN3, and RN4 are all very small. Therefore, NM1, NM2, and NM3 are conducting, and the output signal of the A / B pin voltage depends on VCTRL_N.

[0047] (3) When the voltages of the A / B pins of the RS-485 / 422 chip are greater than 3.3V, NM6, NM9, and NM12 are not conducting, VCTRL_N is at a low level, so NM5 is also not conducting. There is no current in NM1, NM2, and NM3. From this, it can be obtained that the source voltages of NM1, NM2, NM3, and NM4 are approximately equal to their gate voltages. PM19 is conducting, so the source and drain voltages of NM1, NM2, NM3, and NM4 are approximately equal to the voltage dividers across RN1, RN2, RN3, and RN4 respectively. Adjust the resistance values of RN1, RN2, RN3, and RN4 as needed. Here, make them equal. Considering the worst-case scenario, assume the voltage of the A / B pins is 12.5V. The voltages across RN1, RN2, RN3, and RN4 are (12.5 - 3.3) / 4 ≈ 3V. Therefore, the voltages of NM1, NM2, NM3, and NM4 also meet the requirements in the worst-case scenario. And at this time, the current in the pull-down drive circuit is very small, and there is only one path through RN1, RN2, RN3, and RN4.

[0048] Although the embodiments of the present invention have been shown and described, for those of ordinary skill in the art, it can be understood that various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principles and spirit of the present invention. The scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. An RS-485 / 422 transmitter driver circuit based on a low-voltage CMOS process, characterized in that: It includes a logic control circuit, a pull-up driving circuit, and a pull-down driving circuit; The first input terminal of the logic control circuit is connected to the first output terminal of the pull-up driving circuit. The second input terminal of the logic control circuit is connected to a data signal. The third input terminal of the logic control circuit is connected to the second output terminal of the pull-down driving circuit. The first output terminal of the logic control circuit is connected to the first input terminal of the pull-up driving circuit. The second output terminal of the logic control circuit is connected to the first input terminal of the pull-down driving circuit. The second output terminal of the pull-up driving circuit is the A / B pin of the chip, which is used to connect to the RS-485 / 422 bus. The first output terminal of the pull-down driving circuit is the A / B pin of the chip, which is used to connect to the RS-485 / 422 bus; The composition of the logic control circuit is as follows: The gate of the twenty-second NMOS transistor and the drain of the twenty-third NMOS transistor are connected together, serving as the third input terminal of the logic control circuit. The drain of the twenty-second NMOS transistor and the gate of the twenty-third NMOS transistor are connected to the power supply voltage. The sources of the twenty-second NMOS transistor and the twenty-third NMOS transistor are connected together and connected to the gate of the twenty-fourth PMOS transistor. The substrates of the twenty-second NMOS transistor and the twenty-third NMOS transistor are connected to their sources. The source of the twenty-fourth PMOS transistor is connected to the power supply voltage, and the drain is connected to the input terminal of the first inverter and the source of the twenty-fifth PMOS transistor. The drain and gate of the twenty-fifth PMOS transistor are connected to the ground potential. The input terminal of the second inverter is the second input terminal of the logic control circuit. The output terminals of the first and second inverters are respectively connected to the two inputs of the first NAND gate. The output of the first NAND gate is the first output terminal of the logic control circuit; The gate of the twenty-second PMOS transistor and the drain of the twenty-third PMOS transistor are connected together, serving as the first input terminal of the logic control circuit. The drain of the twenty-second PMOS transistor and the gate of the twenty-third PMOS transistor are connected to the ground potential. The sources of the twenty-second PMOS transistor and the twenty-third PMOS transistor are connected together and connected to the gate of the twenty-fourth NMOS transistor. The substrates of the twenty-second PMOS transistor and the twenty-third PMOS transistor are connected to their sources. The source of the twenty-fourth NMOS transistor is connected to the ground potential, and the drain is connected to the input terminal of the first buffer and the source of the twenty-fifth NMOS transistor. The drain and gate of the twenty-fifth NMOS transistor are connected to the power supply voltage. The two inputs of the first AND gate are respectively the output terminal of the first buffer and the second input terminal of the logic control circuit. The output of the first AND gate is the second output terminal of the logic control circuit.

2. The RS-485 / 422 transmitter driver circuit based on a low-voltage CMOS process according to claim 1, wherein: The composition of the pull-up driving circuit is as follows: The gate of the fifth PMOS transistor is the first input terminal of the pull-up driving circuit. The source is connected to the power supply voltage and the first input terminal of the first floating well circuit. The drain is connected to the source of the fourth PMOS transistor, the second input terminal of the first floating well circuit, and the second input terminal of the second floating well circuit. The substrate is connected to the output terminal of the first floating well circuit. The gate of the fourth PMOS transistor is connected to the ground potential and the first input of the first basic stack unit. The drain is connected to the second input terminal of the second floating well circuit and the second input of the first basic stack unit. Between different basic stack units, the first and second outputs of the previous one are connected to the first and second inputs of the subsequent one. The number of basic units is determined by the maximum breakdown voltage of the process. The first output of the last basic stack unit is connected to one end of the second resistor, and the gates of the nineteenth NMOS transistor and the sixth PMOS transistor. The other end of the second resistor is connected to the source of the first PMOS transistor, the drains of the nineteenth NMOS transistor and the sixth PMOS transistor. The source of the nineteenth NMOS transistor is connected to the source of the sixth PMOS transistor through the first resistor. The second output of the last basic stack unit is connected to the source of the first PMOS transistor and the first input terminal of the third floating well circuit. The substrate is connected to the output terminal of the floating well circuit. The drain is connected to the second input terminal of the third floating well circuit, which is the second output of the pull-up driving circuit.

3. The RS-485 / 422 transmitter driver circuit based on the low-voltage CMOS process according to claim 2, wherein: The composition of the floating well circuit in the pull-up driving circuit is as follows: The gate of the seventeenth PMOS transistor is connected to the drain of the eighteenth PMOS transistor, which is the first input terminal of the floating well circuit. The drain of the seventeenth PMOS transistor is connected to the gate of the eighteenth PMOS transistor, which is the second input terminal of the floating well circuit. The sources and substrates of the seventeenth PMOS transistor and the eighteenth PMOS transistor are connected together, which is the first output terminal of the floating well circuit. Its function is to compare the magnitudes of the voltages of the two inputs and output the larger voltage.

4. The RS-485 / 422 transmitter driver circuit based on low-voltage CMOS process according to claim 2, characterized in that: The composition of the basic stack circuit in the pull-up driving circuit is as follows: One end of the fourth resistor is the first input terminal of the basic stack circuit, and the other end is connected to the gate of the third PMOS transistor and the source of the twelfth PMOS transistor, which is the first output terminal of the basic stack circuit. The source of the third PMOS transistor is connected to the gate of the twelfth PMOS transistor and the first input terminal of the fourth floating well circuit, which is the second input terminal of the basic stack circuit. The drain of the third PMOS transistor is connected to the second input terminal of the fourth floating well circuit and the drain of the twelfth PMOS transistor. The substrates of the third PMOS transistor and the twelfth PMOS transistor are connected to the first output terminal of the fourth floating well circuit, which is the second output terminal of the basic stack circuit. According to the maximum breakdown voltage values of MOS transistors in different processes, the number of basic stack units is selected to meet the breakdown voltage requirements of the circuit.

5. The RS-485 / 422 transmitter driver circuit based on low-voltage CMOS process according to claim 1, characterized in that: The structure of the pull-down driving circuit is symmetric to the structure of the pull-up driving circuit, that is, the PMOS transistors in the pull-up driving circuit are changed to NMOS transistors, the NMOS transistors are changed to PMOS transistors, the ground potential is changed to the power supply voltage, and the power supply voltage is changed to the low potential.

6. The RS-485 / 422 transmitter driver circuit based on low-voltage CMOS process according to claim 1, characterized in that: The logic control circuit indirectly detects the voltage of the A / B pins through connection with the pull-up driving circuit. When the voltage is lower than the first preset voltage, the first output terminal outputs a second voltage signal to turn off the driving transistor in the pull-up driving circuit; when the voltage is higher than the first preset voltage, the first output terminal outputs a data signal; when the voltage is higher than the second preset voltage, the second output terminal outputs a first voltage signal to turn off the driving transistor in the pull-down driving circuit; when the voltage is lower than the second preset voltage, the second output terminal outputs a data signal.

7. A RS-485 / 422 transmitter driver circuit based on low-voltage CMOS process according to claim 1, characterized in that: The pull-up driving circuit is used to transmit data signals and protect the circuit when the voltage of the A / B pins is too high or too low. When the second voltage signal is input to the first input terminal of the pull-up driving circuit, the driving circuit is turned off; when the data signal is input to the first input terminal of the pull-up driving circuit and the voltage of the A / B pins is between the first preset voltage and the second preset voltage, the driving circuit works normally and outputs data signals; when the data signal is input to the first input terminal of the pull-up driving circuit and the voltage of the A / B pins is higher than the second preset voltage, the driving circuit is turned off.

8. The RS-485 / 422 transmitter driver circuit based on low-voltage CMOS process according to claim 1, wherein: The pull-down driving circuit is used to transmit data signals and protect the circuit when the voltage of the A / B pins is too high or too low. When the first voltage signal is input to the first input terminal of the pull-down driving circuit, the driving circuit is turned off; when the data signal is input to the first input terminal of the pull-up driving circuit and the voltage of the A / B pins is between the first preset voltage and the second preset voltage, the driving circuit works normally and outputs data signals; when the data signal is input to the first input terminal of the pull-down driving circuit and the voltage of the A / B pins is lower than the first preset voltage, the driving circuit is turned off.

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