Manufacturing process of multi-layer HDI printed circuit board and printed circuit board

Abstract

The present invention relates to a manufacturing process of a multi-layer HDI printed circuit board and a printed circuit board. The manufacturing process includes the following steps: Step S1, cutting the inner layer board and forming blind vias, graphic circuits and alignment targets; Step S2, laminating the sub-outer layer board, opening windows on the sub-outer layer board, and forming alignment blind rings on the sub-outer layer board according to the alignment targets on the inner layer board; Step S3, forming blind vias on the sub-outer layer board according to the alignment targets on the inner layer board, forming graphic circuits on the sub-outer layer board according to the alignment blind rings on the sub-outer layer board, and forming alignment targets on the sub-outer layer board; Step S4, laminating the outer layer board, opening windows on the outer layer board, and forming composite targets on the outer layer board according to the alignment targets on the sub-outer layer board; Step S5, forming blind vias on the outer layer board according to the alignment targets on the sub-outer layer board, and forming graphic circuits and through holes on the outer layer board according to the composite targets. This process can reduce the offset of blind vias and graphic circuits on each layer and has high manufacturing accuracy.

Description

Technical Field

[0001] The present invention relates to the technical field of printed circuit board engineering design and production processes, and particularly relates to a manufacturing process for a multi-layer high density interconnection (HDI) printed circuit board and a printed circuit board. Background Art

[0002] A printed circuit board (also known as a PCB) is a core component of various electronic products. With the development trend of miniaturization, portability, and multi-functionality of printed circuit boards, the application of multi-layer high density interconnection (HDI) printed circuit board technology is becoming increasingly widespread. Since a multi-layer HDI printed circuit board generally needs to undergo multiple hot presses to obtain the corresponding number of layers, that is, multiple core boards are laminated to form a multi-layer circuit board. During production, blind vias and graphic circuits need to be formed on each core board, and through vias need to be formed on the laminated multi-layer circuit board to achieve electrical interconnection between any layers. Due to different degrees of expansion and contraction of each core board after lamination, the blind vias, graphic circuits, etc. on each core board cannot be aligned in the thickness direction of the multi-layer circuit board, thereby affecting the quality and performance of the printed circuit board. Summary of the Invention

[0003] An object of the present invention is to provide a manufacturing process for a multi-layer HDI printed circuit board, in which the offset of blind vias and graphic circuits on each layer is small and the manufacturing accuracy is high.

[0004] Another object of the present invention is to provide a printed circuit board, in which the offset of blind vias and graphic circuits on each layer is small and the manufacturing accuracy is high.

[0005] To achieve this purpose, the present invention adopts the following technical solutions:

[0006] A manufacturing process for a multi-layer HDI printed circuit board is provided, including the following steps:

[0007] Step S1: Cut the inner layer board, form blind vias and graphic circuits on the inner layer board, and form alignment targets in the process edge area of the inner layer board;

[0008] Step S2: Laminate the sub-outer layer board on the inner layer board, open a window on the sub-outer layer board to expose the alignment targets on the inner layer board, and form alignment blind rings in the process edge area of the sub-outer layer board according to the alignment targets on the inner layer board;

[0009] Step S3: Form blind vias on the sub-outer layer board according to the alignment targets on the inner layer board, form graphic circuits on the sub-outer layer board according to the alignment blind rings on the sub-outer layer board, and form alignment targets in the process edge area of the sub-outer layer board;

[0010] Step S4: Press the outer layer board on the secondary outer layer board so that the inner layer board, the secondary outer layer board, and the outer layer board are stacked together to form a multilayer board. Open a window on the outer layer board to expose the alignment target points on the secondary outer layer board. Form an alignment blind loop and mechanical holes in the process edge area of the outer layer board according to the alignment target points on the secondary outer layer board. The alignment blind loop and the mechanical holes on the outer layer board form a composite target point.

[0011] Step S5: Form blind holes on the outer layer board according to the alignment target points on the secondary outer layer board, form graphic circuits on the outer layer board according to the composite target points on the outer layer board, and form through holes on the multilayer board according to the composite target points on the outer layer board.

[0012] Further, there are multiple secondary outer layer boards between the inner layer board and the outer layer board. Among two adjacent secondary outer layer boards, form an alignment blind loop on the secondary outer layer board closer to the outer layer board according to the alignment target points on the secondary outer layer board closer to the inner layer board, and form a graphic circuit according to the corresponding alignment blind loop on the secondary outer layer board.

[0013] Further, in step S1, when cutting the inner layer board, perform shrinkage compensation according to the material characteristics of the inner layer board.

[0014] Further, four alignment target points are formed in the process edge area of the inner layer board and the secondary outer layer board, and the four alignment target points are respectively located at the four corners of the inner layer board or the secondary outer layer board.

[0015] Further, one of the alignment target points is an anti-fooling target point, and the relative position of the anti-fooling target point on the inner layer board or the secondary outer layer board is different from the relative positions of the other alignment target points on the inner layer board or the secondary outer layer board.

[0016] Further, in step S4, form the mechanical holes within the alignment blind loop on the outer layer board, and the mechanical holes are concentric with the alignment blind loop.

[0017] Further, the diameter of the mechanical holes is 1.2 - 1.7 mm.

[0018] Further, in step S5, the shrinkage coefficients of the graphic circuits on the outer layer board and the through holes on the multilayer board are comprehensively matched according to the alignment blind loop and the mechanical holes in the composite target points, and the matching ratio of the alignment blind loop and the mechanical holes each accounts for 50%.

[0019] Further, form the blind holes on the inner layer board, the secondary outer layer board, and the outer layer board by means of laser.

[0020] A printed circuit board is also provided, which is made by the above-mentioned manufacturing process of the multi-layer HDI printed circuit board.

[0021] Advantages of the present invention compared with the prior art:

[0022] For the manufacturing process of the multi-layer HDI printed circuit board and the printed circuit board of the present invention, the manufacturing process of the multi-layer HDI printed circuit board realizes the sequential transplantation of the positioning marks on each layer of core board from the inside to the outside by setting corresponding alignment target points, alignment blind rings or mechanical holes on each layer of core board. So that in two adjacent core boards, the blind holes and graphic circuits made on the core board closer to the outer layer can be aligned as much as possible with the blind holes and graphic circuits made on the core board closer to the inner layer, reducing the offset of the blind holes and graphic circuits on each layer of core board and improving the manufacturing accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a cross-sectional view of the multi-layer HDI printed circuit board according to an embodiment of the present invention.

[0024] Figure 2 It is a partial schematic view of the multi-layer HDI printed circuit board according to an embodiment of the present invention.

[0025] Figure 3 It is a schematic view of the inner layer board according to an embodiment of the present invention.

[0026] Figure 4 It is a schematic view of the sub-outer layer board according to an embodiment of the present invention.

[0027] Figure 5 It is a schematic view of the outer layer board according to an embodiment of the present invention.

[0028] In the figure:

[0029] 1. Inner layer board; 11. First blind hole; 12. First alignment target point; 13. Anti-fooling target point; 2. Sub-outer layer board; 21. Second blind hole; 22. Second alignment target point; 23. Sub-outer layer alignment blind ring; 2a. First sub-outer layer board; 21a. First sub-outer layer blind hole; 2b. Second sub-outer layer board; 21b. Second sub-outer layer blind hole; 3. Outer layer board; 31. Third blind hole; 32. Mechanical hole; 33. Outer layer alignment blind ring;

[0030] 100. Through hole; 200. Process edge area; 300. Window; 400. Graphic circuit. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0031] To make the technical problems solved by the present invention, the technical solutions adopted and the achieved technical effects clearer, the technical solutions of the present invention will be further described below with reference to the drawings and through specific embodiments.

[0032] As Figures 1 to 5As shown in the figure, the present invention provides a manufacturing process for a multi - order HDI printed circuit board, which is used to manufacture a printed circuit board. The printed circuit board is formed by laminating multiple core boards. The multiple core boards are, from the inside to the outside, an inner layer board 1, a sub - outer layer board 2, and an outer layer board 3. Blind vias and graphic circuits 400 are provided on each core board. After lamination, the printed circuit board is also provided with through - holes 100 to enable the graphic circuits 400 on each layer of core board to achieve electrical interconnection through the through - holes 100. The manufacturing process of this multi - order HDI printed circuit board includes the following steps:

[0033] Step S1: Cut the inner layer board 1. A first blind via 11 is formed on the inner layer board 1 by laser, and a graphic circuit 400 is formed on the inner layer board 1 by etching. There is a process edge area 200 around the inner layer board 1. The process edge area 200 is only used during the manufacturing process and needs to be cut off after the printed circuit board is manufactured. Four first alignment target points 12 are burned out by laser in the process edge area 200 of the inner layer board 1. The four first alignment target points 12 are respectively located at the four corner positions of the inner layer board 1.

[0034] The first alignment target points 12 are used for alignment when manufacturing the core board adjacent to the inner layer board 1, that is, the first alignment target points 12 serve as the positioning reference when manufacturing the sub - outer layer board 2. Among the four first alignment target points 12 on the inner layer board 1, one of the first alignment target points 12 is used as an anti - misalignment target point 13. By setting the anti - misalignment target point 13, the direction can be positioned when manufacturing the sub - outer layer board 2. Specifically, the distance from the anti - misalignment target point 13 to the edge of the process edge area 200 is different from the distances from the other three first alignment target points 12 to the edge of the process edge area 200, that is, the relative position of the anti - misalignment target point 13 on the inner layer board 1 is different from the relative positions of the other three first alignment target points 12 on the inner layer board 1, so as to distinguish the direction position of the inner layer board 1.

[0035] Step S2: Laminate the sub - outer layer board 2 on the inner layer board 1. After laminating the sub - outer layer board 2, corresponding blind vias and graphic circuits 400 need to be made on the sub - outer layer board 2. As shown in the figure, windows 300 are formed on the sub - outer layer board 2 by laser. The number and positions of the windows 300 correspond one - to - one with the first alignment target points 12 on the inner layer board 1, so that the first alignment target points 12 on the inner layer board 1 are exposed. Then, secondary outer layer alignment blind rings 23 are formed in the process edge area 200 of the sub - outer layer board 2 according to the four first alignment target points 12 on the inner layer board 1. Each first alignment target point 12 corresponds to form a secondary outer layer alignment blind ring 23, and each secondary outer layer alignment blind ring 23 is arranged close to the corresponding first alignment target point 12. Figure 4 As shown in the figure, windows 300 are formed on the sub - outer layer board 2 by laser. The number and positions of the windows 300 correspond one - to - one with the first alignment target points 12 on the inner layer board 1, so that the first alignment target points 12 on the inner layer board 1 are exposed. Then, secondary outer layer alignment blind rings 23 are formed in the process edge area 200 of the sub - outer layer board 2 according to the four first alignment target points 12 on the inner layer board 1. Each first alignment target point 12 corresponds to form a secondary outer layer alignment blind ring 23, and each secondary outer layer alignment blind ring 23 is arranged close to the corresponding first alignment target point 12.

[0036] It can be understood that both the alignment target point and the alignment blind loop play a role in alignment marking. The alignment blind loop is used as a positioning reference transplanted from the alignment target point on the core board closer to the inner layer to the core board closer to the outer layer.

[0037] Step S3: Form a second blind hole 21 on the sub-outer layer board 2 by laser according to the first alignment target point 12 on the inner layer board 1. Form a graphic circuit 400 on the sub-outer layer board 2 by etching according to the sub-outer layer alignment blind loop 23 on the sub-outer layer board 2, and form a second alignment target point 22 in the process edge area 200 of the sub-outer layer board 2. Among them, the first alignment target point 12 and the sub-outer layer alignment blind loop 23 have the same function and are both used as positioning references. Specifically, use a CCD industrial camera to obtain the position coordinate data of the first alignment target point 12 and the sub-outer layer alignment blind loop 23, and calculate information such as the shrinkage and expansion ratio and position coordinates of the second blind hole 21 and the graphic circuit 400 according to their position coordinate data, so as to form the second blind hole 21 and the graphic circuit 400 on the sub-outer layer board 2, and make the second blind hole 21 and the graphic circuit 400 on the sub-outer layer board 2 able to align with the first blind hole 11 and the graphic circuit 400 on the inner layer board 1.

[0038] It can be understood that during the lamination process of the inner layer board 1 and the sub-outer layer board 2, due to the influence of material properties, the inner layer board 1 will shrink and expand. As a result, the position and size data of the first alignment target point 12 on the inner layer board 1 before lamination are different from the position and size data of the first alignment target point 12 on the inner layer board 1 after lamination. The position and size data of the first alignment target point 12 are used to reflect the position and size data of other elements (such as the first blind hole 11) on the inner layer board 1. To ensure that the second blind hole 21 and the graphic circuit 400 on the sub-outer layer board 2 can correspond to the first blind hole 11 and the graphic circuit 400 on the inner layer board 1, therefore, by opening a window on the sub-outer layer board 2 and transplanting the first alignment target point 12 on the inner layer board 1 to the sub-outer layer board 2, the first alignment target point 12 on the inner layer board 1 can be used as a positioning reference when forming the second blind hole 21 and the graphic circuit 400 on the sub-outer layer board 2.

[0039] At the same time, a second alignment target point 22 is set in the process edge area 200 of the sub-outer layer board 2, and the second alignment target point 22 is used as a positioning reference for the production of the outer layer board 3.

[0040] Specifically, when the inner layer board 1 is cut, shrinkage and expansion compensation are performed according to the material properties of the inner layer board 1 to ensure that the positions and sizes of various elements (such as the first blind hole 11 and the graphic circuit 400) manufactured on the inner layer board 1 can meet the design requirements.

[0041] Step S4. Press the outer layer board 3 onto the sub-outer layer board 2 so that the inner layer board 1, the sub-outer layer board 2, and the outer layer board 3 are laminated together to form a multi-layer board. After pressing the outer layer board 3, corresponding blind vias and graphic circuits 400 need to be fabricated on the outer layer board 3. Refer to Figure 5 As shown, laser is used to open windows on the outer layer board 3 to form windows 300. The number and positions of the windows 300 correspond one-to-one with the second alignment target points 22 on the sub-outer layer board 2, so that the second alignment target points 22 on the sub-outer layer board 2 are exposed. Then, outer layer alignment blind rings 33 are formed in the process edge area 200 of the outer layer board 3 according to the four second alignment target points 22 on the sub-outer layer board 2. Each second alignment target point 22 corresponds to form an outer layer alignment blind ring 33, and each outer layer alignment blind ring 33 is arranged at a position close to the corresponding second alignment target point 22. And mechanical holes 32 are formed in the outer layer alignment blind rings 33 according to the second alignment target points 22. The mechanical holes 32 are formed by mechanical drilling. The mechanical holes 32 are concentric with the outer layer alignment blind rings 33, and the diameter of the mechanical holes 32 is 1.2 - 1.7 mm. The outer layer alignment blind rings 33 and the mechanical holes 32 on the outer layer board 3 form composite target points.

[0042] Step S5. Third blind vias 31 are formed on the outer layer board 3 by laser according to the second alignment target points 22 on the sub-outer layer board 2. Graphic circuits 400 are formed on the outer layer board 3 according to the composite target points on the outer layer board 3, and through holes 100 are formed on the multi-layer board according to the composite target points on the outer layer board 3.

[0043] It can be understood that the outer layer alignment blind rings 33 and the mechanical holes 32 serve as positioning references transplanted from the sub-outer layer board 2 to the outer layer board 3. During the pressing process of the sub-outer layer board 2 and the outer layer board 3, due to the influence of material properties, the sub-outer layer board 2 will expand and contract. As a result, the position and size data of the second alignment target points 22 on the sub-outer layer board 2 before pressing are different from the position and size data of the second alignment target points 22 on the sub-outer layer board 2 after pressing. The position and size data of the second alignment target points 22 are used to reflect the position and size data of other elements (such as: the second blind vias 21) on the sub-outer layer board 2. To ensure that the third blind vias 31 and the graphic circuits 400 on the outer layer board 3 can correspond to the second blind vias 21 and the graphic circuits 400 on the sub-outer layer board 2, the second alignment target points 22 on the sub-outer layer board 2 are transplanted to the outer layer board 3 by opening windows on the outer layer board 3, so that the second alignment target points 22 on the sub-outer layer board 2 can be used as positioning references when forming the third blind vias 31 and the graphic circuits 400 on the outer layer board 3.

[0044] The composite target is used as a positioning mark for transplanting the second alignment target 22 on the sub-outer layer board 2 to the outer layer board 3. The position and size data information of the composite target correspond to the position and size data information of the second alignment target 22. When forming the graphic circuit 400 and the through hole 100 on the outer layer board 3, the composite target is used as the positioning reference. When forming the graphic circuit 400 on the outer layer board 3 and the through hole 100 on the multilayer board formed after lamination, the expansion and contraction coefficients of the graphic circuit 400 and the through hole 100 are comprehensively matched according to the outer layer alignment blind ring 33 and the mechanical hole 32 in the composite target. The matching ratio of the outer layer alignment blind ring 33 and the mechanical hole 32 each accounts for 50%. This method is beneficial to improving the manufacturing precision of the graphic circuit 400 and the through hole 100. Specifically, when collecting the data information of the composite target, the expansion and contraction coefficients during the manufacturing of the graphic circuit 400 and the through hole 100 can be obtained by acquiring the diameter size of the mechanical hole 32 and the inner diameter or outer diameter size of the outer layer alignment blind ring 33.

[0045] It should be noted that, as shown in Figure 3 , the blind hole on the inner layer board 1 is the first blind hole 11, and the alignment target on the inner layer board 1 is the first alignment target 12; as shown in Figure 4 , the blind hole on the sub-outer layer board 2 is the second blind hole 21, the alignment target on the sub-outer layer board 2 is the second alignment target 22, and the alignment blind ring on the sub-outer layer board 2 is the sub-outer layer alignment blind ring 23; as shown in Figure 5 , the blind hole on the outer layer board 3 is the third blind hole 31, and the alignment blind ring on the outer layer board 3 is the outer layer alignment blind ring 33.

[0046] Optionally, as shown in Figure 2As shown, there are multiple sub - outer layers 2 between the inner layer board 1 and the outer layer board 3. Among two adjacent sub - outer layers 2, according to the alignment target points on the sub - outer layer 2 close to the inner layer board 1, alignment blind rings are formed on the sub - outer layer 2 close to the outer layer board 3, and graphic circuits 400 are formed according to the corresponding alignment blind rings on the sub - outer layer 2. In this embodiment, there are two sub - outer layers 2 between the inner layer board 1 and the outer layer board 3, and the two sub - outer layers 2 are the first sub - outer layer 2a and the second sub - outer layer 2b respectively. The manufacturing method of the sub - outer layer 2 is as follows: The first step is to laminate the first sub - outer layer 2a on the inner layer board 1, open a window on the first sub - outer layer 2a, and transplant the first alignment target points 12 on the inner layer board 1 to the first sub - outer layer 2a, that is, form alignment blind rings and alignment target points on the first sub - outer layer 2a, form graphic circuits 400 according to the alignment blind rings on the first sub - outer layer 2a, and form the first outer blind holes 21a on the first sub - outer layer 2a according to the first alignment target points 12. The second step is to laminate the second sub - outer layer 2b on the first sub - outer layer 2a, open a window on the second sub - outer layer 2b, and transplant the alignment target points on the first sub - outer layer 2a to the second sub - outer layer 2b, that is, form alignment blind rings and alignment target points on the second sub - outer layer 2b, form graphic circuits 400 according to the alignment blind rings on the second sub - outer layer 2b, and form the second outer blind holes 21b on the second sub - outer layer 2b according to the alignment target points on the first sub - outer layer 2a.

[0047] A printed circuit board is also provided, which is made by the manufacturing process of the multi - layer HDI printed circuit board described above. Since when making blind holes and graphic circuits 400 on each layer of core board, the alignment target points on an adjacent core board close to the inner layer are used as the positioning reference, and positioning marks such as alignment blind rings and mechanical holes 32 are transplanted sequentially from the inside to the outside, so that in two adjacent core boards, the blind holes and graphic circuits 400 made on the core board close to the outer layer can correspond to the blind holes and graphic circuits 400 made on the core board close to the inner layer, thereby improving the alignment accuracy of the blind holes and graphic circuits 400 on each layer of core board and ensuring the quality and performance of the printed circuit board.

[0048] The remarkable effect of this embodiment is that: in the manufacturing process of the multi - layer HDI printed circuit board, by setting corresponding alignment target points, alignment blind rings or mechanical holes 32 on each layer of core board, the positioning marks on each layer of core board are transplanted sequentially from the inside to the outside. So that in two adjacent core boards, the blind holes and graphic circuits 400 made on the core board close to the outer layer can be aligned as much as possible with the blind holes and graphic circuits 400 made on the core board close to the inner layer, reducing the offset of the blind holes and graphic circuits 400 on each layer of core board and improving the manufacturing accuracy.

[0049] The above content is only a preferred embodiment of the present invention. For those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation manner and application scope. The content of this specification should not be construed as a limitation to the present invention.

Claims

1. A manufacturing process for a multi-layer HDI printed circuit board, characterized in that, It includes the following steps: Step S1: Cut the inner layer board, form blind vias and graphic circuits on the inner layer board, and form alignment targets in the process edge area of the inner layer board; Step S2: Press the sub-outer layer board on the inner layer board, open windows on the sub-outer layer board to expose the alignment targets on the inner layer board, and form alignment blind rings in the process edge area of the sub-outer layer board according to the alignment targets on the inner layer board; Step S3: Form blind vias on the sub-outer layer board according to the alignment targets on the inner layer board, form graphic circuits on the sub-outer layer board according to the alignment blind rings on the sub-outer layer board, and form alignment targets in the process edge area of the sub-outer layer board; Step S4: Press the outer layer board on the sub-outer layer board to stack the inner layer board, the sub-outer layer board and the outer layer board together to form a multi-layer board, open windows on the outer layer board to expose the alignment targets on the sub-outer layer board, and form alignment blind rings and mechanical holes in the process edge area of the outer layer board according to the alignment targets on the sub-outer layer board. The alignment blind rings and the mechanical holes on the outer layer board form composite targets; Step S5: Form blind vias on the outer layer board according to the alignment targets on the sub-outer layer board, form graphic circuits on the outer layer board according to the composite targets on the outer layer board, and form through holes on the multi-layer board according to the composite targets on the outer layer board; In Step S5, the expansion and contraction coefficients of the graphic circuits on the outer layer board and the through holes on the multi-layer board are comprehensively matched according to the alignment blind rings and the mechanical holes in the composite targets, and the matching ratio of the alignment blind rings and the mechanical holes each accounts for 50%.

2. The manufacturing process of the multi-layer HDI printed circuit board according to claim 1, wherein There are multiple sub-outer layer boards between the inner layer board and the outer layer board. Among two adjacent sub-outer layer boards, alignment blind rings are formed on the sub-outer layer board closer to the outer layer board according to the alignment targets on the sub-outer layer board closer to the inner layer board, and graphic circuits are formed according to the corresponding alignment blind rings on the sub-outer layer board.

3. The manufacturing process of the multi-layer HDI printed circuit board according to claim 1, characterized in that, In Step S1, when cutting the inner layer board, expansion and contraction compensation is performed according to the material characteristics of the inner layer board.

4. The manufacturing process of the multi - layer HDI printed circuit board according to claim 1, characterized in that, Four alignment targets are formed in the process edge areas of the inner layer board and the sub-outer layer board, and the four alignment targets are respectively located at the four corners of the inner layer board or the sub-outer layer board.

5. The manufacturing process of the multi - layer HDI printed circuit board according to claim 4, characterized in that, One of the alignment targets is an anti-fooling target, and the relative position of the anti-fooling target on the inner layer board or the sub-outer layer board is different from the relative positions of the other alignment targets on the inner layer board or the sub-outer layer board.

6. The manufacturing process of the multi - layer HDI printed circuit board according to claim 1, characterized in that, In Step S4, the mechanical hole is formed inside the alignment blind ring on the outer layer board, and the mechanical hole is concentric with the alignment blind ring.

7. The manufacturing process of the multi - layer HDI printed circuit board according to claim 6, characterized in that, The diameter of the mechanical hole is 1.2 - 1.7 mm.

8. The manufacturing process of the multi-layer HDI printed circuit board according to any one of claims 1 to 7, characterized in that, The blind vias are formed on the inner layer board, the sub-outer layer board and the outer layer board by laser.

9. A printed circuit board, characterized in that, It is made by the manufacturing process of the multi-order HDI printed circuit board according to any one of claims 1 to 8.

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