Contact structure preparation method and contact structure

Abstract

The present disclosure provides a method for preparing a contact structure and a contact structure. The method for preparing a contact structure provided by the present disclosure includes: providing a substrate, on the surface of which a first polysilicon layer and a first mask layer are sequentially arranged; performing a first etching process on the first polysilicon layer and the first mask layer to form a step-type structure in which the width of the first mask layer is smaller than the width of the first polysilicon layer; performing a second etching process on the substrate using the first polysilicon layer as a mask to form a groove; depositing a second polysilicon layer in the groove, wherein the top height of the second polysilicon layer is not higher than the bottom height of the first mask layer; and performing an annealing process to form a contact structure. The present disclosure improves the problem of excessive pores in the polysilicon layer by adopting a step-type structure in the preparation process of the contact structure, and further improves the voids generated by the growth of polysilicon through an annealing process, thereby improving the quality of the contact structure and improving the defect problem.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductors, and in particular to a method for preparing a contact structure and the contact structure. Background Art

[0002] In the prior art, defect mitigation methods for integrated circuit (IC) process steps are a key issue in the manufacturing of integrated circuits and electronic components. In semiconductor manufacturing, particularly in the production of dynamic random access memory (DRAM), the presence of voids and pores in the polysilicon layer poses a significant challenge, impacting the performance and lifespan of semiconductor devices. Summary of the Invention

[0003] The present disclosure provides a method for preparing a contact structure, comprising: providing a substrate, on the surface of which a first polysilicon layer and a first mask layer are sequentially arranged; performing a first etching process on the first polysilicon layer and the first mask layer to form a step-type structure in which the width of the first mask layer is smaller than the width of the first polysilicon layer; performing a second etching process on the substrate 20 using the first polysilicon layer as a mask to form a groove; depositing a second polysilicon layer in the groove, wherein the top height of the second polysilicon layer is not higher than the bottom height of the first mask layer; and performing an annealing process to form a contact structure.

[0004] In some embodiments, in the method for preparing the contact structure, the substrate includes a shallow trench isolation structure, and the shallow trench isolation structure includes one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0005] In some embodiments, in the method for preparing the contact structure, an etching rate of the first polysilicon layer in the first etching process is lower than that of the first mask layer.

[0006] In some embodiments, in the method for preparing the contact structure, the surface of the substrate includes an insulating layer, and the insulating layer is located below the first polysilicon layer.

[0007] In some embodiments, in the method for preparing the contact structure, the second etching process includes: etching the insulating layer and the substrate to form a trench.

[0008] In some embodiments, in the method for preparing the contact structure, the step of forming the second polysilicon layer further includes: depositing polysilicon on the surface of the step-type structure and the groove to form a first polysilicon preparatory layer; depositing polysilicon on the surface of the first polysilicon preparatory layer to form a second polysilicon preparatory layer, and the second polysilicon preparatory layer fills the gap between the groove and the step-type structure; and etching the second polysilicon preparatory layer to form a second polysilicon layer.

[0009] In some embodiments, in the method for preparing the contact structure, the steps before sequentially setting the first polysilicon layer and the first mask layer on the surface of the substrate are: providing a substrate, forming a stack on the surface of the substrate, the stack including, from bottom to top, an insulating layer, a third polysilicon preparatory layer, a first sacrificial layer, a second mask layer, a second sacrificial layer, and a third mask layer; etching the second sacrificial layer and the third mask layer to form a first groove; forming a third sacrificial layer in the first groove, covering the second mask layer, the second sacrificial layer and the third mask layer; removing part of the third sacrificial layer to the same height as the third mask layer; removing the second sacrificial layer and the third mask layer; etching the second mask layer, the first sacrificial layer, and the third polysilicon preparatory layer using the third sacrificial layer as a mask to form a second groove, a first mask layer, and a first polysilicon layer; removing the third sacrificial layer and the second mask layer.

[0010] In some embodiments, in the method for preparing the contact structure, the materials used for the first sacrificial layer and the second sacrificial layer include SOH and / or SOC.

[0011] In some embodiments, in the method for preparing the contact structure, the materials of the second mask layer and the third mask layer include one or more of SiN, SiON, and SiCN materials.

[0012] In some embodiments, in the method for preparing the contact structure, the third sacrificial layer includes oxide.

[0013] In some embodiments, in the method for preparing the contact structure, the temperature of the annealing process is 600° C.-800° C., and the time of the annealing process is 3 hours-6 hours.

[0014] In some embodiments, in the method for preparing the contact structure, the annealing process includes an ion implantation process, and ion implantation is performed on the first polysilicon layer and / or the second polysilicon layer.

[0015] In some embodiments, in the method for preparing the contact structure, after the annealing process is completed, a rapid thermal annealing process is further included, and the temperature of the rapid thermal annealing process is higher than that of the annealing process.

[0016] In some embodiments, in the method for preparing the contact structure, the insulating layer is made of SiN material.

[0017] In some embodiments, in the method for preparing the contact structure, a ZIVIS machine is used in the process of forming a step-type structure in which the width of the first mask layer is smaller than the width of the first polysilicon layer by the first etching process. The first etching process adopts a wet etching process, and the etching gas includes H2 and / or N2.

[0018] In some embodiments, in the method for preparing the contact structure, after the annealing process is completed, a rapid thermal annealing process is further included, and the temperature of the rapid thermal annealing process is higher than that of the annealing process.

[0019] The present disclosure also provides a contact structure, which is prepared by any one of the methods described above.

[0020] The present invention utilizes a stepped mask structure and multiple deposition processes during the fabrication of the contact structure to address the problem of voids and cavities in the bitline contact structure, which is caused by a higher deposition rate at the top of the bitline contact structure than in the middle. This reduces voids in the polysilicon layer of the contact structure, improves the quality of the contact structure, and mitigates defects in the contact structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Attachment Figure 1 Shown is a schematic diagram of the steps of a method for preparing a contact structure according to a specific embodiment of the present disclosure.

[0022] Attachment Figures 2A-2D The attached diagram of a specific embodiment of the present disclosure is shown. Figure 1 Schematic diagram of the process of steps S10-S13.

[0023] Attachment Figure 3 Schematic diagram of the step of forming a second polysilicon layer in the method for preparing a contact structure according to a specific embodiment of the present disclosure.

[0024] Attachment Figures 4A-4C The attached diagram of a specific embodiment of the present disclosure is shown. Figure 3 Schematic diagram of the process of steps S31-S33.

[0025] Attachment Figure 5 The figure shows a schematic diagram of the steps before sequentially disposing a first polysilicon layer and a first mask layer on the surface of the substrate in the method for preparing the contact structure according to a specific embodiment of the present disclosure.

[0026] Attachment Figures 6A-6G The attached diagram of a specific embodiment of the present disclosure is shown. Figure 5 Schematic diagram of the process of steps S50-S56.

[0027] Attachment Figures 7A-7C The attached diagram of a specific embodiment of the present disclosure is shown. Figure 3 Schematic diagram of the process of steps S31-S33.

[0028] Attachment Figures 8A-8CShown is a schematic diagram of the effect of the annealing process described in a specific embodiment of the present disclosure.

[0029] Attachment Figures 9A-9D The attached diagram of a specific embodiment of the present disclosure is shown. Figure 1 Schematic diagram of the process of steps S10-S13.

[0030] Attachment Figures 10A-10C The attached diagram of a specific embodiment of the present disclosure is shown. Figure 3 Schematic diagram of the process of steps S31-S33. DETAILED DESCRIPTION

[0031] The following describes in detail the method for preparing the contact structure provided by the present disclosure and the specific implementation of the contact structure with reference to the accompanying drawings.

[0032] Attachment Figure 1 The figure shows a schematic diagram of the steps of a method for preparing a contact structure described in a specific embodiment of the present disclosure, including: step S10, providing a substrate, and sequentially arranging a first polysilicon layer and a first mask layer on the surface of the substrate; step S11, performing a first etching process on the first polysilicon layer and the first mask layer to form a step-type structure in which the width of the first mask layer is smaller than the width of the first polysilicon layer; step S12, performing a second etching process on the substrate using the first polysilicon layer as a mask to form a groove; step S13, depositing a second polysilicon layer in the groove, wherein the top height of the second polysilicon layer is not higher than the bottom of the first mask layer; step S14, performing an annealing process to form a contact structure.

[0033] Attachment Figures 2A-2D The attached diagram of a specific embodiment of the present disclosure is shown. Figure 1 Schematic diagram of the process of steps S10-S13.

[0034] Attachment Figure 2A As shown, referring to step S10, a substrate 20 is provided, and a first polysilicon layer 211 and a first mask layer 212 are sequentially arranged on the surface of the substrate 20. In a specific embodiment of the present disclosure, the substrate 20 includes a shallow trench isolation structure, and the shallow trench isolation structure 202 includes one or more of silicon oxide, silicon nitride, and silicon oxynitride. That is, the material used in the shallow trench isolation structure 202 includes one or more of silicon oxide, silicon nitride, and silicon oxynitride. In this specific embodiment, the shallow trench isolation structure 202 uses silicon oxide material, and the substrate 20 also includes a silicon substrate 201. In a specific embodiment of the present disclosure, the surface of the substrate 20 includes an insulating layer 203, and the insulating layer 203 is located below the first polysilicon layer 211. The insulating layer 203 uses SiN material.

[0035] Attachment Figure 5 The figure shows a schematic diagram of the steps before sequentially providing the first polysilicon layer 211 and the first mask layer 212 on the surface of the substrate 20 in the method for preparing the contact structure according to a specific embodiment of the present disclosure, including: step S50, providing a substrate, forming a stack of layers on the surface of the substrate, the stack of layers including, from bottom to top, an insulating layer, a third polysilicon preparatory layer, a first sacrificial layer, a second mask layer, a second sacrificial layer, and a third mask layer; step S51, etching the second sacrificial layer and the third mask layer to form a first groove; step S52, etching the first sacrificial layer and the third mask layer to form a first groove; A third sacrificial layer is formed in the groove, covering the second mask layer, the second sacrificial layer and the third mask layer; step S53, removing part of the third sacrificial layer to the same height as the third mask layer; step S54, removing the second sacrificial layer and the third mask layer; step S55, etching the second mask layer, the first sacrificial layer, and the third polysilicon preparatory layer using the third sacrificial layer as a mask to form a second groove, a first mask layer, and a first polysilicon layer; step S56, removing the third sacrificial layer and the second mask layer.

[0036] Attachment Figures 6A-6G The attached diagram of a specific embodiment of the present disclosure is shown. Figure 5 Schematic diagram of the process of steps S50-S56.

[0037] Attachment Figure 6A As shown, referring to step S50, a substrate 20 is provided, and a stack of layers is formed on the surface of the substrate 20. The stack of layers includes, from bottom to top, an insulating layer 203, a third polysilicon preparatory layer 601, a first sacrificial layer 602, a second mask layer 603, a second sacrificial layer 604, and a third mask layer 605. In a specific embodiment of the present disclosure, the materials used for the first sacrificial layer 602 and the second sacrificial layer 604 include SOH and / or SOC. The materials used for the second mask layer 603 and the third mask layer 605 include one or more of SiN, SiON, and SiCN. In a specific embodiment of the present disclosure, the substrate 20 includes a shallow trench isolation structure, and the materials used for the shallow trench isolation structure 202 include one or more of silicon oxide, silicon nitride, and silicon oxynitride. In this specific embodiment, the shallow trench isolation structure 202 is made of silicon oxide material, and the substrate 20 also includes a silicon substrate 201. In a specific embodiment of the present disclosure, the surface of the substrate 20 includes an insulating layer 203, and the insulating layer 203 is located below the third polysilicon preliminary layer 601. The insulating layer 203 is made of SiN material, and the material of the third polysilicon preliminary layer 601 is polysilicon.

[0038] Attachment Figure 6BAs shown, referring to step S51, the second sacrificial layer 604 and the third mask layer 605 are etched to form a first groove 61. Accurate positioning and etching are the key to this step. The second sacrificial layer 604 and the third mask layer 605 will also be removed in subsequent steps.

[0039] Attachment Figure 6C As shown, referring to step S52, a third sacrificial layer 606 is formed in the first groove 61, covering the second mask layer 603, the second sacrificial layer 604 and the third mask layer 605. In a specific embodiment of the present disclosure, the third sacrificial layer 606 is made of an oxide material, including but not limited to silicon oxide.

[0040] Attachment Figure 6D As shown, referring to step S53, a portion of the third sacrificial layer 606 is removed to the same height as the third mask layer 605. The third mask layer 605 is exposed so that the second sacrificial layer 604 and the third mask layer 605 can be removed in subsequent steps.

[0041] Attachment Figure 6E As shown, referring to step S54, the second sacrificial layer 604 and the third mask layer 605 are removed. In a specific embodiment of the present disclosure, the removal of the second sacrificial layer 604 and the third mask layer 605 is performed by one or more of dry removal and wet removal.

[0042] Attachment Figure 6F As shown, referring to step S55 , the second mask layer 603 , the first sacrificial layer 602 , and the third polysilicon preliminary layer 601 are etched using the third sacrificial layer 606 as a mask to form a second groove 62 , a first mask layer 212 , and a first polysilicon layer 211 .

[0043] Attachment Figure 6G As shown, referring to step S56 , the third sacrificial layer 606 and the second mask layer 603 are removed. In this embodiment, the insulating layer 203 , the first polysilicon layer 211 , and the first mask layer 212 are retained on the substrate 20 .

[0044] By adopting a stepped structure during the fabrication of the contact structure, the above technical solution improves the problem of pores and voids forming in the bitline contact structure holes during the deposition process, which is caused by the growth rate at the top of the bitline contact structure hole being faster than the growth rate in the middle of the hole. This reduces the pores in the polysilicon layer of the contact structure, improves the quality of the contact structure, and alleviates the defect problem in the contact structure.

[0045] After completing the above steps, you will get the attached Figure 2AThe structure shown includes: a substrate 20, on the surface of which a first polysilicon layer 211 and a first mask layer 212 are sequentially arranged. In a specific embodiment of the present disclosure, the substrate 20 includes a shallow trench isolation structure, and the material used in the shallow trench isolation structure 202 includes one or more of silicon oxide, silicon nitride, and silicon oxynitride. In this specific embodiment, the shallow trench isolation structure 202 is made of silicon oxide material, and the substrate 20 also includes a silicon substrate 201. In a specific embodiment of the present disclosure, the surface of the substrate 20 includes an insulating layer 203, and the insulating layer 203 is located below the first polysilicon layer 211. The insulating layer 203 is made of SiN material. In the attached Figure 2A Based on the structure shown, continue to implement the following steps.

[0046] Attachment Figure 2B As shown, referring to step S11, a first etching process is performed on the first polysilicon layer 211 and the first mask layer 212 to form a step-type structure in which the width of the first mask layer 212 is smaller than the width of the first polysilicon layer 211. In a specific embodiment of the present disclosure, the etching rate of the first polysilicon layer 211 in the first etching process is smaller than that of the first mask layer 212. Since the material used for the first mask layer 212 includes SOH and / or SOC, and the material used for the first polysilicon layer 211 is polysilicon, when a wet etching process is used, it has a higher selectivity, and can achieve the etching rate of the first polysilicon layer 211 in the first etching process to be smaller than that of the first mask layer 212, forming a step-type structure with a small top and a large bottom. In this specific embodiment, the ZIVIS machine is used in the process of forming the step-type structure in which the width of the first mask layer 212 is smaller than that of the first polysilicon layer 211 by the first etching process, and the first etching process adopts a wet etching process, and the etching gases include H2 and N2. The stepped structure formed by etching using the ZIVIS tool can leave a larger window on the top of the contact structure during the subsequent contact structure deposition process to alleviate the problems of pores and voids.

[0047] Attachment Figure 2C As shown, referring to step S12, a second etching process is performed on the substrate 20 using the first polysilicon layer 211 as a mask to form a trench 22. In a specific embodiment of the present disclosure, the second etching process includes: etching the insulating layer 203 and the substrate 20 to form the trench 22.

[0048] Attachment Figure 2DAs shown, referring to step S13, a second polysilicon layer 219 is deposited in the trench 22, and the top height of the second polysilicon layer 219 is not higher than the bottom of the first mask layer 212. In this embodiment, the top height of the second polysilicon layer 219 is flush with the top height of the original first polysilicon layer 211. In other embodiments of the present disclosure, the top height of the second polysilicon layer 219 may also be lower than the top height of the original first polysilicon layer 211.

[0049] By adopting a stepped structure during the fabrication of the contact structure, the above technical solution improves the problem of pores and voids forming in the bitline contact structure holes during the deposition process, which is caused by the growth rate at the top of the bitline contact structure hole being faster than the growth rate in the middle of the hole. This reduces the pores in the polysilicon layer of the contact structure, improves the quality of the contact structure, and alleviates the defect problem in the contact structure.

[0050] In other specific embodiments of the present disclosure, Figures 9A-9D Another example is shown Figure 1 Schematic diagram of the process of steps S10-S13.

[0051] Attachment Figure 9A As shown, referring to step S10, a substrate 20 is provided, and a first polysilicon layer 211 and a first mask layer 212 are sequentially provided on the surface of the substrate 20. In a specific embodiment of the present disclosure, the substrate 20 includes a shallow trench isolation structure, and the material used for the shallow trench isolation structure 202 includes one or more of silicon oxide, silicon nitride, and silicon oxynitride. In this specific embodiment, the shallow trench isolation structure 202 is made of silicon oxide material, and the substrate 20 also includes a silicon substrate 201. In a specific embodiment of the present disclosure, the surface of the substrate 20 includes an insulating layer 203, and the insulating layer 203 is located below the first polysilicon layer 211. The insulating layer 203 is made of SiN material.

[0052] Attachment Figure 9BAs shown, referring to step S11, a first etching process is performed on the first polysilicon layer 211 and the first mask layer 212 to form a step-type structure in which the width of the first mask layer 212 is smaller than the width of the first polysilicon layer 211. In a specific embodiment of the present disclosure, the etching rate of the first polysilicon layer 211 in the first etching process is smaller than that of the first mask layer 212. Since the material used for the first mask layer 212 includes SOH and / or SOC, and the material used for the first polysilicon layer 211 is polysilicon, when a wet etching process is used, it has a higher selectivity, and can achieve the etching rate of the first polysilicon layer 211 in the first etching process to be smaller than that of the first mask layer 212, forming a step-type structure with a small top and a large bottom. In this specific embodiment, the ZIVIS machine is used in the process of forming the step-type structure in which the width of the first mask layer 212 is smaller than that of the first polysilicon layer 211 by the first etching process, and the first etching process adopts a wet etching process, and the etching gases include H2 and N2. The stepped structure formed by etching using the ZIVIS tool can leave a larger window on the top of the contact structure during the subsequent contact structure deposition process to alleviate the problems of pores and voids.

[0053] Attachment Figure 9C As shown, referring to step S12, a second etching process is performed on the substrate 20 using the first polysilicon layer 211 as a mask to form a trench 22. In a specific embodiment of the present disclosure, the second etching process includes: etching the insulating layer 203 and the substrate 20 to form the trench 22.

[0054] Attachment Figure 9D As shown, referring to step S13, a second polysilicon layer 219 is deposited in the trench 22. The top of the second polysilicon layer 219 is no higher than the bottom of the first mask layer 212. In this embodiment, the top of the second polysilicon layer 219 is lower than the top of the original first polysilicon layer 211. This allows for the exposure of any holes and voids, which can be eliminated in a subsequent annealing step.

[0055] By adopting a stepped structure during the fabrication of the contact structure, the above technical solution improves the problem of pores and voids forming in the bitline contact structure holes during the deposition process, which is caused by the growth rate at the top of the bitline contact structure hole being faster than the growth rate in the middle of the hole. This reduces the pores in the polysilicon layer of the contact structure, improves the quality of the contact structure, and alleviates the defect problem in the contact structure.

[0056] The step of forming the second polysilicon layer 219 in the above steps is further as follows.

[0057] Attachment Figure 3FIG2 is a schematic diagram illustrating the steps of forming a second polysilicon layer 219 in a method for fabricating a contact structure according to a specific embodiment of the present disclosure. The steps of forming the second polysilicon layer further include: step S31, depositing polysilicon on the surface of the stepped structure and the trench to form a first polysilicon preparatory layer; step S32, depositing polysilicon on the surface of the first polysilicon preparatory layer to form a second polysilicon preparatory layer, wherein the second polysilicon preparatory layer fills the gap between the trench and the stepped structure; and step S33, etching the second polysilicon preparatory layer to form a second polysilicon layer.

[0058] Attachment Figures 4A-4C The attached diagram of a specific embodiment of the present disclosure is shown. Figure 3 Schematic diagram of the process of steps S31-S33.

[0059] Attachment Figure 4A As shown, referring to step S31, polysilicon is deposited on the surface of the stepped structure and the trench 22 to form a first polysilicon preliminary layer 217. In a specific embodiment of the present disclosure, the first polysilicon preliminary layer 217 and the second polysilicon layer 219 are made of different polysilicon materials.

[0060] Attachment Figure 4B As shown, referring to step S32, polysilicon is deposited on the surface of the first polysilicon preliminary layer 217 to form a second polysilicon preliminary layer 218. The second polysilicon preliminary layer 218 fills the gap between the trench 22 and the stepped structure. In one embodiment of the present disclosure, the second polysilicon preliminary layer 218 and the first polysilicon preliminary layer 217 are made of different polysilicon materials.

[0061] Attachment Figure 4C As shown, referring to step S33, the second polysilicon preliminary layer 218 is etched to form a second polysilicon layer 219. The top height of the second polysilicon layer 219 is not higher than the bottom of the first mask layer 212. In this embodiment, the top height of the second polysilicon layer 219 is flush with the top height of the original first polysilicon layer 211. In other embodiments of the present disclosure, the top height of the second polysilicon layer 219 may also be lower than the top height of the original first polysilicon layer 211.

[0062] Attachment Figures 7A-7C The attached diagram of a specific embodiment of the present disclosure is shown. Figure 3 FIG. 5 is a process diagram of another specific implementation of steps S31-S33.

[0063] Attachment Figure 7AAs shown, referring to step S31, polysilicon is deposited on the surface of the stepped structure and the trench 22 to form a first polysilicon preliminary layer 217. In one embodiment of the present disclosure, the first polysilicon preliminary layer 217 and the second polysilicon layer 219 are made of the same polysilicon material. The deposited polysilicon and the second polysilicon layer 219 together form the first polysilicon preliminary layer 217.

[0064] Attachment Figure 7B As shown, referring to step S32, polysilicon is deposited on the surface of the first polysilicon preliminary layer 217 to form a second polysilicon preliminary layer 218. The second polysilicon preliminary layer 218 fills the gap between the trench 22 and the stepped structure. In a specific embodiment of the present disclosure, the second polysilicon preliminary layer 218 and the first polysilicon preliminary layer 217 are made of the same polysilicon material. The deposited polysilicon and the first polysilicon preliminary layer 217 together form the second polysilicon preliminary layer 218.

[0065] Attachment Figure 7C As shown, referring to step S33, the second polysilicon preliminary layer 218 is etched to form a second polysilicon layer 219. The top height of the second polysilicon layer 219 is not higher than the bottom of the first mask layer 212. In this embodiment, the top height of the second polysilicon layer 219 is flush with the top height of the original first polysilicon layer 211. In other embodiments of the present disclosure, the top height of the second polysilicon layer 219 may also be lower than the top height of the original first polysilicon layer 211.

[0066] By adopting a stepped structure during the fabrication of the contact structure, the above technical solution improves the problem of pores and voids forming in the bitline contact structure holes during the deposition process, which is caused by the growth rate at the top of the bitline contact structure hole being faster than the growth rate in the middle of the hole. This reduces the pores in the polysilicon layer of the contact structure, improves the quality of the contact structure, and alleviates the defect problem in the contact structure.

[0067] In other specific embodiments of the present disclosure, Figures 10A-10C Another example is shown Figure 3 Schematic diagram of the process of steps S31-S33.

[0068] Attachment Figure 10A As shown, referring to step S31, polysilicon is deposited on the surface of the stepped structure and the trench 22 to form a first polysilicon preliminary layer 217. In one embodiment of the present disclosure, the first polysilicon preliminary layer 217 and the second polysilicon layer 219 are made of the same polysilicon material. The deposited polysilicon and the second polysilicon layer 219 together form the first polysilicon preliminary layer 217.

[0069] Attachment Figure 10B As shown, referring to step S32, polysilicon is deposited on the surface of the first polysilicon preliminary layer 217 to form a second polysilicon preliminary layer 218. The second polysilicon preliminary layer 218 fills the gap between the trench 22 and the stepped structure. In a specific embodiment of the present disclosure, the second polysilicon preliminary layer 218 and the first polysilicon preliminary layer 217 are made of the same polysilicon material. The deposited polysilicon and the first polysilicon preliminary layer 217 together form the second polysilicon preliminary layer 218.

[0070] Attachment Figure 10C As shown, referring to step S33, the second polysilicon preliminary layer 218 is etched to form a second polysilicon layer 219. The top height of the second polysilicon layer 219 is no higher than the bottom of the first mask layer 212. In this specific embodiment, the top height of the second polysilicon layer 219 is lower than the top height of the original first polysilicon layer 211.

[0071] By adopting a stepped structure during the fabrication of the contact structure, the above technical solution improves the problem of pores and voids forming in the bitline contact structure holes during the deposition process, which is caused by the growth rate at the top of the bitline contact structure hole being faster than the growth rate in the middle of the hole. This reduces the pores in the polysilicon layer of the contact structure, improves the quality of the contact structure, and alleviates the defect problem in the contact structure.

[0072] After the above steps are completed, an annealing process is performed to form a contact structure. In a specific embodiment of the present disclosure, the annealing process includes ion implantation. The temperature of the annealing process includes 600°C-800°C, and the time of the annealing process includes 3h-6h. The annealing process includes an ion implantation process, in which ions are implanted into the first polysilicon layer and / or the second polysilicon layer. After the annealing process is completed, a rapid thermal annealing process is further included, and the temperature of the rapid thermal annealing process is higher than that of the annealing process.

[0073] In this specific embodiment, Ge is used for ion implantation. Annealing polysilicon at high temperature for a long time activates the thermal activation energy of Si, causing diffusing atoms to transition within the crystal. Since the concentration of Si in voids is relatively low, downhill diffusion causes high-concentration Si to diffuse toward low-concentration Si, thereby uniformizing the Si concentration and improving the porosity and void issues. During the process of cooling from high temperature to low temperature, the diffusion process is frozen, preserving the structure and state of dynamic recovery or dynamic recrystallization, thereby eliminating the porosity and void issues in the first polysilicon layer 211.

[0074] Attachment Figures 8A-8C FIG2 is a schematic diagram showing the effect of the annealing process according to a specific embodiment of the present disclosure. Figure 8A FIG. 8 is a schematic diagram showing the generation of pores 80 in the first polysilicon layer 211 in the aforementioned step; FIG. Figure 8B FIG2 is a schematic diagram showing a process of removing a portion of the second polysilicon layer 219 to expose the gap 80; FIG3 is a schematic diagram showing a process of removing a portion of the second polysilicon layer 219 to expose the gap 80; FIG4 is a schematic diagram showing a process of removing a portion of the second polysilicon layer 219 to expose the gap 80; Figure 8C The schematic diagram shows the disappearance of the pores 80 after the annealing process is completed. The step-shaped structure in the above technical solution has greatly reduced the pores and voids generated during the deposition of polysilicon. If a small amount of pores and voids still occur, they can be eliminated in the subsequent annealing process.

[0075] After the annealing process is completed, a rapid thermal annealing process is further included, wherein the temperature of the rapid thermal annealing process is higher than that of the annealing process. The time of the rapid thermal annealing process is within 10 seconds, and the activity of the ion implanted element is activated by a short-term high-temperature rapid annealing process. In this specific embodiment, the Ge activity is activated by a short-term high-temperature rapid annealing process.

[0076] By employing a stepped structure during the fabrication of the contact structure, the above technical solution addresses the problem of pores and voids forming in the bitline contact structure during the deposition process, which is caused by the faster growth rate at the top of the bitline contact structure than in the middle. Furthermore, an annealing process further improves the pores and voids generated by polysilicon growth, thereby improving the quality of the contact structure and addressing defects in the contact structure.

[0077] After the above steps are completed, the contact structure disclosed in the present invention is obtained, and the contact structure is prepared by any one of the methods described above.

[0078] The above technical solution improves the problem of excessive pores in the polysilicon layer by adopting a step-type structure during the preparation of the contact structure, and further improves the pores and voids generated by polysilicon growth through an annealing process, thereby improving the quality of the contact structure and improving the defect problem in the contact structure.

[0079] The above is only a preferred embodiment of the present disclosure. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principles of the present disclosure. These improvements and modifications should also be regarded as within the scope of protection of the present disclosure.

Claims

1. A method for preparing a contact structure, characterized in that: include: Providing a substrate, forming a stack of layers on a surface of the substrate, the stack of layers comprising, from bottom to top, an insulating layer, a third polysilicon preparatory layer, a first sacrificial layer, a second mask layer, a second sacrificial layer, and a third mask layer; etching the second sacrificial layer and the third mask layer to form a first groove; forming a third sacrificial layer in the first groove, covering the second mask layer, the second sacrificial layer and the third mask layer; removing a portion of the third sacrificial layer until it is flush with the top of the third mask layer; removing the second sacrificial layer and the third mask layer; Using the third sacrificial layer as a mask, etching the second mask layer, the first sacrificial layer, and the third polysilicon preparatory layer to form a second groove, a first mask layer, and a first polysilicon layer; removing the third sacrificial layer and the second mask layer; performing a first etching process on the first polysilicon layer and the first mask layer to form a step-type structure in which the width of the first mask layer is smaller than the width of the first polysilicon layer; performing a second etching process on the substrate using the first polysilicon layer as a mask to form a trench; depositing a second polysilicon layer in the trench, wherein the top of the second polysilicon layer is no higher than the bottom of the first mask layer; An annealing process is performed to form a contact structure.

2. The method according to claim 1, characterized in that In the first etching process, an etching rate of the first polysilicon layer is lower than that of the first mask layer.

3. The method according to claim 1, characterized in that The second etching process includes: etching the insulating layer and the substrate to form the trench.

4. The method according to claim 1, wherein The step of forming the second polysilicon layer includes: Depositing polysilicon on the surface of the stepped structure and the groove to form a first polysilicon preparatory layer; Depositing polysilicon on the surface of the first polysilicon preliminary layer to form a second polysilicon preliminary layer, wherein the second polysilicon preliminary layer fills the gap between the trench and the stepped structure; The first polysilicon preliminary layer and the second polysilicon preliminary layer are etched to form the second polysilicon layer.

5. The method according to claim 1, wherein The substrate includes a shallow trench isolation structure, and the shallow trench isolation structure includes one or more of silicon oxide, silicon nitride, and silicon oxynitride.

6. The method according to claim 1, wherein The second mask layer and the third mask layer include one or more of SiN, SiON, and SiCN.

7. The method according to claim 1, characterized in that The third sacrificial layer includes silicon oxide.

8. The method according to claim 1, characterized in that The temperature of the annealing process is 600° C.-800° C., and the time of the annealing process is 3 hours-6 hours.

9. The method according to claim 1 or 8, characterized in that The annealing process includes an ion implantation process, wherein ions are implanted into the first polysilicon layer and / or the second polysilicon layer.

10. The method according to claim 1 or 8, characterized in that After the annealing process is completed, a rapid thermal annealing process is further included, and the temperature of the rapid thermal annealing process is higher than that of the annealing process.

11. The method according to claim 1, wherein The insulating layer includes one or more of SiN, SiO2, and SiON.

12. The method according to claim 1, characterized in that The first etching process adopts a wet etching process, and the etching gas includes H2 and / or N2.

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