Method for manufacturing semiconductor device and semiconductor device

Abstract

The present invention provides a method for manufacturing a semiconductor device and a semiconductor device. The manufacturing method includes: providing a semiconductor substrate, the substrate having a first region and a second region; forming an initial mask layer on the upper surface of the substrate; patterning the initial mask layer, forming a first pattern mask having a first height on the first region, and forming a second pattern mask having a second height on the second region, wherein the pattern density of the first pattern mask is greater than the pattern density of the second pattern mask, and the first height is greater than the second height; etching the substrate based on the first pattern mask and the second pattern mask, transferring the pattern of the first pattern mask to the first region, and transferring the pattern of the second pattern mask to the second region. The solution of the present application forms different mask thicknesses in regions with different mask pattern densities, balancing the etching load effect caused by different pattern densities during the etching process, improving the etching capability of high aspect ratio structures, and reducing defect sources.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit and electronic component manufacturing, and in particular to a method for manufacturing a semiconductor device and a semiconductor device. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a semiconductor memory device commonly used in computers. It consists of many repeated memory cells. Each memory cell typically includes a capacitor and a transistor. Currently, DRAM uses a stacked capacitor structure, in which the capacitors are pillar capacitors with a high aspect ratio. The manufacturing process used to create the capacitor structure directly affects its performance. Summary of the Invention

[0003] In view of this, embodiments of the present application provide a method for manufacturing a semiconductor device and a semiconductor device.

[0004] According to a first aspect of an embodiment of the present application, there is provided a method for manufacturing a semiconductor device, comprising:

[0005] Providing a semiconductor substrate, the substrate having a first region and a second region;

[0006] forming an initial mask layer on the upper surface of the substrate;

[0007] Patterning the initial mask layer to form a first pattern mask having a first height on the first area, and forming a second pattern mask having a second height on the second area, wherein the pattern density of the first pattern mask is greater than the pattern density of the second pattern mask, and the first height is greater than the second height;

[0008] The substrate is etched based on the first pattern mask and the second pattern mask, the pattern of the first pattern mask is transferred to the first region, and the pattern of the second pattern mask is transferred to the second region.

[0009] Furthermore, the first area is a memory array area, and the second area is a peripheral circuit area.

[0010] Furthermore, the step of patterning the initial mask layer includes:

[0011] Providing a first graphic template, forming a first graphic mask in the initial mask layer on the first area, and forming a second graphic mask in the initial mask layer on the second area, wherein the pattern density of the first graphic mask is greater than the pattern density of the second graphic mask;

[0012] The second pattern mask is partially etched so that a height of the second pattern mask is smaller than a height of the first pattern mask.

[0013] Furthermore, the initial mask layer includes a second initial mask layer and a first initial mask layer stacked sequentially from bottom to top;

[0014] The forming of a first pattern mask in the initial mask layer on the first area and forming a second pattern mask in the initial mask layer on the second area comprises:

[0015] patterning the first initial mask layer based on the first graphic template to form a first initial mask;

[0016] etching the second initial mask layer based on the first initial mask to form the first pattern mask and the second pattern mask;

[0017] The first initial mask is removed.

[0018] Furthermore, the step of partially etching the second pattern mask includes:

[0019] depositing an intermediate dielectric material to form an intermediate dielectric layer filling the first pattern mask and the second pattern mask;

[0020] Providing a second pattern template, and forming a mask pattern exposing the second pattern mask in the intermediate dielectric layer on the second area;

[0021] etching and removing a portion of the second pattern mask based on the mask pattern;

[0022] The intermediate dielectric layer is removed.

[0023] Furthermore, the step of patterning the initial mask layer includes:

[0024] Providing a third pattern template to form a mask pattern of the initial mask layer that exposes the second area on the initial mask layer;

[0025] Partially etching the initial mask layer based on the mask pattern so that a height of the initial mask layer in the second region is smaller than a height of the initial mask layer in the first region;

[0026] A fourth graphic template is provided, a first graphic mask is formed in the initial mask layer in the first area, and a second graphic mask is formed in the initial mask layer in the second area, wherein the graphic density of the first graphic mask is greater than the graphic density of the second graphic mask.

[0027] Furthermore, the substrate includes a base and a laminated structure on the base;

[0028] The stacked structure includes a first sacrificial layer, a first supporting layer, a second sacrificial layer and a second supporting layer stacked in sequence from bottom to top.

[0029] Furthermore, the first graphic mask is a capacitor hole pattern, and a contact structure corresponding to the capacitor hole pattern is formed in the substrate.

[0030] Furthermore, etching the substrate based on the first pattern mask and the second pattern mask to transfer the pattern of the first pattern mask to the first region includes:

[0031] Based on the first pattern mask, sequentially etching the second supporting layer, the second sacrificial layer, the first supporting layer, and the first sacrificial layer to transfer the capacitor hole pattern to the stacked structure, thereby forming a plurality of capacitor holes and etched pillars located between the capacitor holes in the stacked structure;

[0032] Wherein, the capacitor hole exposes a portion of the contact structure.

[0033] Furthermore, the method further comprises:

[0034] After forming the capacitor hole, the first pattern mask is removed.

[0035] Furthermore, the method further comprises:

[0036] The etched pillars are processed to form capacitor structures.

[0037] Furthermore, the processing of the etched pillar to form a capacitor structure includes:

[0038] forming a first electrode layer on the inner wall of the capacitor hole and the surface of the etched column;

[0039] forming a first opening in the second supporting layer;

[0040] removing the second sacrificial layer through the first opening;

[0041] forming a second opening in the first supporting layer;

[0042] removing the first sacrificial layer through the second opening;

[0043] A dielectric layer and a second electrode layer are sequentially deposited on the surface of the first electrode layer to form the capacitor structure.

[0044] According to a second aspect of an embodiment of the present application, a semiconductor device is provided. The semiconductor device is manufactured by the above-mentioned method for manufacturing a semiconductor device, and the semiconductor device at least includes: a substrate and a capacitor structure;

[0045] The substrate includes a contact structure; the capacitor structure is located on a surface of the substrate, and the capacitor structure is in contact with the contact structure.

[0046] The technical solutions provided by the embodiments of this application have the following beneficial effects:

[0047] Different mask thicknesses are formed in areas with different pattern densities of the mask, balancing the etching load effect brought about by different pattern densities during the etching process, improving the etching ability of high aspect ratio structures, reducing defect sources; improving the integrity and stability of the pattern, and improving the performance of semiconductor devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In the accompanying drawings (which are not necessarily drawn to scale), like reference numerals may describe similar components in different views. Like reference numerals with different letter suffixes may represent different examples of similar components. The accompanying drawings generally illustrate various embodiments discussed herein by way of example and not limitation.

[0049] Figures 1a to 1c A schematic structural diagram of a semiconductor device formation process provided in one embodiment of the present application.

[0050] Figure 2 A schematic flow chart of a method for manufacturing a semiconductor device provided in accordance with another embodiment of the present application.

[0051] Figures 3a to 3q A schematic structural diagram of a semiconductor device manufacturing process provided in one embodiment of the present application.

[0052] Figure 4 A cross-sectional view of a semiconductor device provided in accordance with an embodiment of the present application.

[0053] Description of reference numerals:

[0054] 100 / 200 - substrate; 101 / 201 - stacked structure; 101-1 / B - peripheral region; 100-2 / A - array region; 101a - capacitor pattern; 102 - first hard mask layer; 103 - second hard mask layer; 102a - first hard mask layer after first etching; 102b - first hard mask layer after second etching; 200a - contact structure; 200b - insulating layer; 201a - first sacrificial layer; 201b / 213 - first supporting layer; 201c - second sacrificial layer; 201d / 214 - second supporting layer; 202 - second initial mask layer; 202a - first pattern mask; 2 02b-second graphic mask; 203a-first initial mask; 204-intermediate dielectric layer; 204a-part of the intermediate dielectric layer; 205-second mask layer; 205a-dielectric anti-reflective coating; 205b-bottom anti-reflective coating; 205c-photoresist layer; 206c-patterned photoresist layer; 206b-patterned bottom anti-reflective coating; 206a-patterned dielectric anti-reflective coating; 207-capacitor hole; 208-etched column; 209-first electrode layer; 210-dielectric layer; 211-second electrode layer; 212-conductive material; 40-semiconductor device; D-first opening; E-second opening. DETAILED DESCRIPTION

[0055] The exemplary embodiments disclosed herein will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the specific embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the present application to those skilled in the art.

[0056] In the following description, numerous specific details are provided to provide a more thorough understanding of the present application. However, it will be apparent to those skilled in the art that the present application can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present application; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0057] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0058] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part. And when the second element, component, region, layer, or part is discussed, it does not necessarily mean that the first element, component, region, layer, or part is present in the present application.

[0059] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present application. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0060] Before introducing in detail the method for forming a semiconductor device provided in an embodiment of the present application, the formation process of a semiconductor device in the related art is first described.

[0061] Figures 1a to 1c A schematic diagram of the structure of a semiconductor device forming process provided in one embodiment of the present application. Figure 1a As shown, a stacked structure 101 is formed on the surface of a substrate 100, and a first hard mask layer 102 and a second hard mask layer 103 are formed on the surface of the stacked structure 101, wherein the second hard mask layer 103 has a pattern for forming capacitor holes. The substrate 100 includes a peripheral region 100-1 and an array region 100-2, wherein the pattern density of the capacitor hole pattern in the second hard mask layer in the array region 100-2 is greater than the pattern density of the capacitor hole pattern in the second hard mask layer in the peripheral region 100-1.

[0062] The formation process of the semiconductor device includes two pattern transfer processes. The first pattern transfer process is: etching the first hard mask layer through the second hard mask layer to achieve the transfer of the capacitor hole pattern in the second hard mask layer to the first hard mask layer. Figure 1b As shown, the first hard mask layer 102a is obtained after the first etching by the first pattern transfer. During the first pattern transfer process, due to the etching load effect, the thickness t1 of the second hard mask layer located on the array region 100-2 is less than the thickness t2 of the second hard mask layer located on the peripheral region 100-1.

[0063] The second pattern transfer process is: etching the stacked structure through the etched first hard mask layer to transfer the capacitor hole pattern to the stacked structure 101; before the second pattern transfer, the second hard mask layer 103 needs to be removed. Figure 1c As shown, the second pattern transfer process forms a capacitor pattern 101a and the first hard mask layer 102b after the second etching, wherein the capacitor pattern 101a has a top size B and a height D, and the distance between two adjacent capacitor patterns is S.

[0064] After the capacitor hole pattern is transferred to the stacked structure, the first hard mask layer 102 b after the second etching needs to be removed.

[0065] Since the pattern density of the capacitor hole pattern in the first hard mask layer on the array region 100-2 is greater than the pattern density of the capacitor hole pattern in the first hard mask layer on the peripheral region 100-1, during the first pattern transfer and the second pattern transfer, due to the etching load effect, the thickness t3 of the first hard mask layer located on the array region 100-2 is less than the thickness t4 of the first hard mask layer located on the peripheral region 100-1. In addition, the first hard mask layer on the array region 100-2 and the first hard mask layer on the peripheral region 100-1 have different roughnesses, which may even damage the stacked structure 101 below the first mask layer 102b, thereby affecting the performance of the semiconductor device.

[0066] Figure 2 FIG1 is a flow chart of a method for manufacturing a semiconductor device provided in another embodiment of the present application. Figure 2 As shown, the method includes the following steps:

[0067] Step 201: Provide a semiconductor substrate, wherein the substrate has a first region and a second region.

[0068] like Figure 3a In some embodiments, the substrate includes a base 200 and a stacked structure 201 on the base 200 .

[0069] The stacked structure 201 is used to form a capacitor structure and includes a first sacrificial layer 201a, a first supporting layer 201b, a second sacrificial layer 201c, and a second supporting layer 201d stacked in order from bottom to top. The first sacrificial layer 201a and the second sacrificial layer 201c may be oxide layers, such as silicon oxide layers; and the first supporting layer 201b and the second supporting layer 201d may be silicon nitride layers.

[0070] In some embodiments, the substrate includes an array region A and a peripheral region B. The array region is used to form a memory device of the semiconductor memory cell, such as a storage capacitor; the peripheral region is used to form a peripheral control circuit. The first region is the memory array region A, and the second region is the peripheral circuit region B.

[0071] It should be noted that the solution of the present application is not limited to the array area and the peripheral area, and the solution is applicable to graphic processes with different pattern densities.

[0072] In the embodiment of the present application, a contact structure 200a and an insulating layer 200b covering the contact structure 200a are formed in the substrate 200. The contact structure 200a is used to electrically connect to the formed capacitor structure. The material of the contact structure 200a can be any conductive material, such as tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof.

[0073] Step 202: forming an initial mask layer on the upper surface of the substrate.

[0074] In the embodiment of the present application, the initial mask layer may be any hard mask layer, for example, a polysilicon layer, a silicon nitride layer, or a spin-on carbon layer.

[0075] In some embodiments, the initial mask layer includes a second initial mask layer 202 and a first initial mask layer 203a stacked sequentially from bottom to top, wherein the first initial mask layer 203a is made of an oxide material, and the second initial mask layer 202 is made of a polysilicon material.

[0076] Step 203: Patterning the initial mask layer to form a first graphic mask having a first height on the first area, and a second graphic mask having a second height on the second area, wherein the graphic density of the first graphic mask is greater than the graphic density of the second graphic mask, and the first height is greater than the second height.

[0077] In some embodiments, the first pattern mask may be a capacitor hole pattern or other patterns.

[0078] There are two possible patterning processes for the initial mask layer. The first is to first form a first pattern mask and a second pattern mask, and then remove a portion of the second pattern mask; the second is to remove a portion of the initial mask layer on the second area before the initial mask layer is patterned, and then form the first pattern mask and the second pattern mask.

[0079] In some embodiments, when the first method is adopted, the step of patterning the initial mask layer in step 203 includes:

[0080] Step 2031: providing a first pattern template, forming a first pattern mask in the initial mask layer on the first area, and forming a second pattern mask in the initial mask layer on the second area, wherein the pattern density of the first pattern mask is greater than the pattern density of the second pattern mask;

[0081] In some embodiments, step 2031 may include the following steps:

[0082] like Figure 3b As shown, the first initial mask layer is patterned based on the first graphic template to form a first initial mask 203a.

[0083] like Figure 3c As shown, the second initial mask layer 202 is etched based on the first initial mask 203a to form the first pattern mask 202a and the second pattern mask 202b.

[0084] like Figure 3d As shown, the first initial mask 203a is removed.

[0085] It is worth noting that in the process of etching the second initial mask layer 202 through the first initial mask 203a, due to the etching load effect caused by the different pattern densities of the patterns on the array area A and the peripheral area B, the residual thickness h1 of the first initial mask 203a on the array area A is smaller than the residual thickness h2 of the first initial mask 203a on the peripheral area B.

[0086] Step 2032: Partially etch the second pattern mask 202b so that the height of the second pattern mask 202b is smaller than the height of the first pattern mask 202a.

[0087] In some embodiments, the step of partially etching the second pattern mask 202b in step 2032 includes:

[0088] like Figure 3e As shown, an intermediate dielectric material is deposited to form an intermediate dielectric layer 204 filling the first pattern mask 202a and the second pattern mask 202b.

[0089] In the embodiment of the present application, the intermediate dielectric layer 204 may be a spin-on hard mask layer (SOH), a spin-on carbon layer, or other hard mask layers; the intermediate dielectric layer 204 may be formed by any suitable deposition process.

[0090] like Figure 3f As shown, a second mask layer 205 is formed on the intermediate dielectric layer 204. The second mask layer 205 includes a dielectric anti-reflective coating 205a, a bottom anti-reflective coating 205b, and a photoresist layer 205c stacked sequentially from bottom to top. In the embodiment of the present application, the dielectric anti-reflective coating 205a, the bottom anti-reflective coating 205b, and the photoresist layer 205c can be formed by any suitable deposition process.

[0091] like Figure 3g As shown, a second pattern template is provided, and a mask pattern exposing the second pattern mask is formed in the intermediate dielectric layer on the second area.

[0092] In the embodiment of the present application, a preset second pattern template C is used to expose the photoresist layer 205c on the peripheral area B to obtain a patterned photoresist layer 206c, exposing the various layer structures on the peripheral area B.

[0093] like Figure 3h As shown, a portion of the second pattern mask 202b is removed by etching based on the mask pattern.

[0094] In the embodiment of the present application, the patterned photoresist layer 206c is etched downward to sequentially remove the bottom anti-reflective coating layer 206b, the dielectric anti-reflective coating layer 206a, the intermediate dielectric layer 204, and a portion of the second initial mask layer 202 above the peripheral region B. The photoresist layer 206c and the bottom anti-reflective coating layer 206b above the array region A are then removed, leaving only the dielectric anti-reflective coating layer 206a and the intermediate dielectric layer 204 above the array region A.

[0095] like Figure 3i As shown, the intermediate dielectric layer 204 is removed.

[0096] In the embodiment of the present application, it is necessary to remove the remaining dielectric anti-reflective coating 206a and the intermediate dielectric layer 204 above the array area A; thereby exposing the first pattern mask 202a and the second pattern mask 202b, and at this time, the height H1 of the first pattern mask 202a is greater than the height H2 of the second pattern mask 202b.

[0097] Since the height H1 of the first pattern mask 202a located on the array area A is greater than the height H2 of the second pattern mask 202b located on the peripheral area B, the etching load effect caused by different pattern densities during the etching process can be balanced. In this way, when the remaining first pattern mask 202a is subsequently etched away, the etched pillars will not be damaged, and the capacity of the formed capacitor structure will not be affected.

[0098] In some other embodiments, when the second method is adopted, the step of patterning the initial mask layer in step 203 includes:

[0099] like Figure 3j and 3k As shown, a third pattern template is provided to form a mask pattern of the initial mask layer exposing the second area on the initial mask layer;

[0100] like Figure 3l As shown, the initial mask layer is partially etched based on the mask pattern, so that the height of the initial mask layer in the second area is smaller than the height of the initial mask layer in the first area;

[0101] like Figure 3m As shown, a fourth graphic template is provided, a first graphic mask is formed in the initial mask layer in the first area, and a second graphic mask is formed in the initial mask layer in the second area, and the graphic density of the first graphic mask is greater than the graphic density of the second graphic mask.

[0102] It should be noted that the first pattern template used in the first method is identical to the fourth pattern template used in the second method, and the second pattern template is identical to the third pattern template. Furthermore, the second and third pattern templates are not additional pattern templates, but are pattern templates used in the previous process, eliminating the need for additional pattern templates. The pattern templates referred to here can be photomasks.

[0103] Step 204 : Etching the substrate based on the first pattern mask and the second pattern mask, transferring the pattern of the first pattern mask to the first region, and transferring the pattern of the second pattern mask to the second region.

[0104] In some embodiments, the first pattern mask 202 a is a capacitor hole pattern, and a contact structure 200 a corresponding to the capacitor hole pattern is formed in the substrate 200 .

[0105] In an embodiment of the present application, step S204 may include the following steps:

[0106] Based on the first pattern mask, the second supporting layer, the second sacrificial layer, the first supporting layer, and the first sacrificial layer are sequentially etched to transfer the capacitor hole pattern to the stacked structure, thereby forming a plurality of capacitor holes and etched pillars located between the capacitor holes in the stacked structure. The capacitor holes expose a portion of the contact structure.

[0107] like Figure 3i and Figure 3n As shown, based on the first pattern mask 202a, the second supporting layer 201d, the second sacrificial layer 201c, the first supporting layer 201b, the first sacrificial layer 201a, and a portion of the insulating layer 200b are sequentially etched to form a plurality of capacitor holes 207 and etched pillars 208 located between two adjacent capacitor holes. Each capacitor hole 207 exposes a corresponding contact structure 200a.

[0108] In some embodiments, after forming the capacitor hole, the method for manufacturing a semiconductor device further includes: removing the first pattern mask 202 a .

[0109] like Figure 3o As shown, after the capacitor hole 207 is formed, the first pattern mask 202 a remaining on the array region A and the second pattern mask 202 b remaining on the peripheral region B are removed by a dry etching process, exposing the top surface of the etched pillar 208 .

[0110] In the embodiment of the present application, since the height H1 of the first pattern mask 202a located on the array area A is greater than the height H2 of the second pattern mask 202b located on the peripheral area B, the etching load effect brought about by different pattern densities during the etching process can be balanced. In this way, when the remaining first pattern mask 202a is subsequently etched away, the etched pillars will not be damaged, and the formed capacitor structure will not be affected, thereby reducing the source of defects.

[0111] In some embodiments, after removing the first pattern mask 202 a , the method for manufacturing a semiconductor device further includes: processing an etched pillar to form a capacitor structure.

[0112] In some embodiments, processing the etched pillar to form a capacitor structure includes:

[0113] Step S20 , forming a first electrode layer on the inner wall of the capacitor hole and the surface of the etched column.

[0114] The first electrode layer may be a titanium nitride layer.

[0115] Step S21 : forming a first opening in the second supporting layer.

[0116] Step S22 : removing the second sacrificial layer through the first opening.

[0117] Step S23: forming a second opening in the first supporting layer.

[0118] Step S24 , removing the first sacrificial layer through the second opening.

[0119] like Figure 3p As shown, a first electrode layer 209 is formed on the inner wall of the capacitor hole 207 and the surface of the etched column; a first opening D is formed in the second supporting layer, and the second sacrificial layer is removed through the first opening D; a second opening E is formed in the first supporting layer, and the first sacrificial layer is removed through the first opening E.

[0120] In the embodiment of the present application, a dry etching technology, for example, a plasma etching technology, may be used to form the first opening D and the second opening E.

[0121] In the embodiment of the present application, a wet etching technology may be used, for example, using corrosive solutions such as sulfuric acid, hydrofluoric acid, and nitric acid to remove the second sacrificial layer and the first sacrificial layer.

[0122] Step S25 : depositing a dielectric layer and a second electrode layer in sequence on the surface of the first electrode layer to form a capacitor structure.

[0123] like Figure 3q As shown, a dielectric layer 210 and a second electrode layer 211 are formed on the surface of the first electrode layer 209. In the embodiment of the present application, the dielectric layer 210 can be a zirconium oxide layer and / or an aluminum oxide layer, or a layer of other high dielectric constant materials; the second electrode layer 211 can be the same as or different from the first electrode layer 209.

[0124] In some embodiments, the method for forming a semiconductor device further includes: depositing a conductive material between the second electrode layers. The conductive material may be polysilicon or any other suitable conductive material, such as tungsten, cobalt, or doped polysilicon.

[0125] The manufacturing method of the semiconductor device provided in the embodiment of the present application forms different mask thicknesses in areas of different mask pattern densities to balance the etching load effect brought about by different pattern densities during the etching process, improve the etching stability of high aspect ratio structures, and reduce the source of defects; improve the integrity and stability of the capacitor pattern, and improve the performance of the semiconductor device.

[0126] In addition, an embodiment of the present application further provides a semiconductor device, which is manufactured by the semiconductor device manufacturing method provided by the above embodiment. Figure 4 A cross-sectional view of a semiconductor device provided in one embodiment of the present application, such as Figure 4As shown, the semiconductor device 40 includes: a substrate 200 and a capacitor structure; wherein the substrate 200 includes a contact structure 200a and an insulating layer covering the contact structure 200a, and the contact structure 200a is used to be electrically connected to the formed capacitor structure.

[0127] In the embodiment of the present application, the substrate 200 includes an array region A and a peripheral region B, and the capacitor structure is located on the surface of the array region A of the substrate 200 .

[0128] Please continue to see Figure 4 The capacitor structure includes a first electrode layer 209 , a dielectric layer 210 and a second electrode layer 211 stacked in sequence, and conductive material 212 is filled between adjacent second electrode layers 211 .

[0129] In an embodiment of the present application, the capacitor structure is a cup-shaped structure, and the capacitor structure also includes a first support layer 213 and a second support layer 214 arranged in parallel; wherein the first support layer 213 is arranged on the middle periphery of the capacitor structure, and the second support layer 214 is arranged on the top periphery of the capacitor structure, and the first support layer 213 and the second support layer 214 are jointly used to support the capacitor structure.

[0130] In some embodiments, the thickness h3 of the second supporting layer 214 is greater than the thickness h4 of the first supporting layer 213 , so as to achieve a better supporting effect.

[0131] The manufacturing method of the semiconductor device in the embodiment of the present application is similar to that of the semiconductor device in the above embodiment. For the technical features not fully disclosed in the embodiment of the present application, please refer to the above embodiment for understanding, and no further details will be given here.

[0132] The semiconductor device provided in the embodiment of the present application balances the etching load effect brought about by different pattern densities during the etching process through different mask thicknesses, thereby improving the etching stability of high aspect ratio structures and reducing the source of defects; improving the integrity and stability of the capacitor pattern, and improving the performance of the semiconductor device.

[0133] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in non-targeted ways. The device embodiments described above are merely illustrative. For example, the division of units is merely a logical functional division. In actual implementation, other division methods may be used, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not implemented. In addition, the components shown or discussed are coupled or directly coupled to each other.

[0134] The units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units; some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0135] The features disclosed in the several method or device embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0136] The above are only some implementation methods of the embodiments of this application, but the scope of protection of the embodiments of this application is not limited thereto. Any person skilled in the art can easily conceive of changes or substitutions within the technical scope disclosed in the embodiments of this application, and they should be included in the scope of protection of the embodiments of this application. Therefore, the scope of protection of the embodiments of this application should be based on the scope of protection of the claims.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: Providing a semiconductor substrate, the substrate having a first region and a second region; forming an initial mask layer on the upper surface of the substrate; Patterning the initial mask layer includes: providing a first pattern template, forming a first pattern mask in the initial mask layer on the first area, and forming a second pattern mask in the initial mask layer on the second area, wherein the pattern density of the first pattern mask is greater than the pattern density of the second pattern mask; and partially etching the second pattern mask so that the height of the second pattern mask is less than the height of the first pattern mask; The substrate is etched based on the first pattern mask and the second pattern mask, the pattern of the first pattern mask is transferred to the first region, and the pattern of the second pattern mask is transferred to the second region.

2. The method according to claim 1, characterized in that The first area is a memory array area, and the second area is a peripheral circuit area.

3. The method according to claim 1, characterized in that The initial mask layer includes a second initial mask layer and a first initial mask layer stacked sequentially from bottom to top; The forming of a first pattern mask in the initial mask layer on the first area and forming a second pattern mask in the initial mask layer on the second area comprises: patterning the first initial mask layer based on the first graphic template to form a first initial mask; etching the second initial mask layer based on the first initial mask to form the first pattern mask and the second pattern mask; The first initial mask is removed.

4. The method according to claim 1, wherein The step of partially etching the second pattern mask comprises: depositing an intermediate dielectric material to form an intermediate dielectric layer filling the first pattern mask and the second pattern mask; Providing a second pattern template, and forming a mask pattern exposing the second pattern mask in the intermediate dielectric layer on the second area; etching and removing a portion of the second pattern mask based on the mask pattern; The intermediate dielectric layer is removed.

5. The method according to claim 1, characterized in that The step of patterning the initial mask layer includes: Providing a third pattern template to form a mask pattern of the initial mask layer that exposes the second area on the initial mask layer; Partially etching the initial mask layer based on the mask pattern so that a height of the initial mask layer in the second region is smaller than a height of the initial mask layer in the first region; A fourth graphic template is provided, a first graphic mask is formed in the initial mask layer in the first area, and a second graphic mask is formed in the initial mask layer in the second area, wherein the graphic density of the first graphic mask is greater than the graphic density of the second graphic mask.

6. The method according to any one of claims 1 to 5, characterized in that The substrate comprises a base and a stacked structure on the base; The stacked structure includes a first sacrificial layer, a first supporting layer, a second sacrificial layer and a second supporting layer stacked in sequence from bottom to top.

7. The method according to claim 6, characterized in that The first graphic mask is a capacitor hole pattern, and a contact structure corresponding to the capacitor hole pattern is formed in the substrate.

8. The method according to claim 7, characterized in that The etching of the substrate based on the first pattern mask and the second pattern mask to transfer the pattern of the first pattern mask to the first area includes: Based on the first pattern mask, sequentially etching the second supporting layer, the second sacrificial layer, the first supporting layer, and the first sacrificial layer to transfer the capacitor hole pattern to the stacked structure, thereby forming a plurality of capacitor holes and etched pillars located between the capacitor holes in the stacked structure; Wherein, the capacitor hole exposes a portion of the contact structure.

9. The method according to claim 8, characterized in that The method further comprises: After forming the capacitor hole, the first pattern mask is removed.

10. The method according to claim 9, characterized in that The method further comprises: The etched pillars are processed to form capacitor structures.

11. The method according to claim 10, characterized in that The processing of the etched pillar to form a capacitor structure includes: forming a first electrode layer on the inner wall of the capacitor hole and the surface of the etched column; forming a first opening in the second supporting layer; removing the second sacrificial layer through the first opening; forming a second opening in the first supporting layer; removing the first sacrificial layer through the second opening; A dielectric layer and a second electrode layer are sequentially deposited on the surface of the first electrode layer to form the capacitor structure.

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