Display device and driving method thereof

Abstract

A display device according to an embodiment of the present disclosure includes: a display panel including pixels, wherein the pixels include a driving element and a light-emitting device; a host system configured to render image data to be applied to the pixels, change the length of a vertical blanking period, and output a rendering completion signal before outputting the rendered image data; a timing controller configured to set a sensing period in the vertical blanking period based on the rendering completion signal; and a sensing circuit configured to sense electrical characteristics of the driving element in the sensing period, wherein the sensing period starts at a first moment, the first moment is a predetermined time earlier than the end time of the vertical blanking period, and the length of the predetermined time is fixed regardless of the change in the length of the vertical blanking period.

Description

Technical Field

[0001] The present disclosure relates to an electroluminescent display device. Background Art

[0002] According to the material of the light-emitting layer, electroluminescent display devices are divided into inorganic light-emitting display devices and organic light-emitting display devices. Each of the plurality of pixels of the electroluminescent display device includes a self-luminous light-emitting device and controls the amount of light emitted by the light-emitting device to adjust the brightness by using a data voltage based on the grayscale of image data.

[0003] Electroluminescent display devices use external compensation technology to improve image quality. The external compensation technology senses pixel voltage or current based on the electrical characteristics of the pixel and modulates the data of the input image based on the sensing result, thereby compensating for the electrical characteristic deviation between pixels.

[0004] However, in conventional external compensation techniques, when the frame rate changes rapidly, the brightness deviation between the compensated pixels and the non-compensated pixels increases, and thus the position of the compensated pixels in the display panel may be perceived by the user. Summary of the invention

[0005] Technical issues

[0006] Therefore, the present disclosure provides a display device and a driving method thereof, which can prevent a user from perceiving the position of a compensation pixel even when a frame rate varies based on an input image in the process of compensating for an electrical characteristic deviation between pixels based on an external compensation method.

[0007] Technical Solution

[0008] A display device according to an embodiment of the present disclosure includes: a display panel including pixels, wherein the pixels include a driving element and a light-emitting device; a host system configured to render image data to be applied to the pixels, change the length of a vertical blanking period, and output a rendering completion signal before outputting the rendered image data; a timing controller configured to set a sensing period in the vertical blanking period based on the rendering completion signal; and a sensing circuit configured to sense electrical characteristics of the driving element in the sensing period, wherein the sensing period starts at a first moment, the first moment is a predetermined time earlier than the end time of the vertical blanking period, and the length of the predetermined time is fixed regardless of the change in the length of the vertical blanking period.

[0009] Beneficial Effects

[0010] In the present embodiment, even when the frame rate varies based on the input image in the process of compensating for the electric characteristic deviation between pixels based on the external compensation method, the user does not perceive the position of the compensation pixel.

[0011] The effects according to the present embodiment are not limited to the above examples, and other various effects may also be included in the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a diagram showing an electroluminescent display device according to an embodiment of the present disclosure.

[0013] Figure 2 It is shown that the Figure 1 Diagram of a pixel array in an electroluminescent display device.

[0014] Figure 3 yes Figure 2 An equivalent circuit diagram of pixels included in a pixel array.

[0015] Figure 4 is a diagram showing a configuration of a host system for changing a frame rate.

[0016] Figure 5 This is a diagram for explaining the memory control operation at the time when the processing of the N-th frame image is completed.

[0017] Figure 6 It is a diagram for explaining the memory control operation at the time of executing the processing of the N+1-th frame image.

[0018] Figure 7 is a diagram showing an example of transmitting and receiving a signal based on a variable frame rate between a host system and a timing controller.

[0019] Figure 8 and 9 A diagram for explaining a variable refresh rate (VRR) technique for changing a frame rate based on an input image.

[0020] Fig.10 and 11 is a diagram for explaining an example in which the length of a luminance recovery period varies based on the position of a pixel group line including a sensing pixel in an external compensation technique.

[0021] Fig. 12A and 12B is a diagram illustrating an example of differently setting a brightness compensation gain for compensating for a brightness loss based on sensing based on a length of a brightness recovery period.

[0022] Fig.13 is a diagram showing an example of setting a sensing period in a vertical blanking period with reference to a last data enable signal of a vertical active period in a comparative example of the present disclosure.

[0023] Fig.14 It shows that Fig.13A diagram showing an example in which the length of the luminance recovery period corresponding to the same pixel group line changes based on a change in the frame rate when the sensing period is set.

[0024] Fig.15 is a diagram showing an example of setting a sensing period in a vertical blanking period with reference to a rendering completion signal in an embodiment of the present disclosure.

[0025] Fig.16 It shows that Fig.15 This is a diagram showing an example in which, when the sensing period is set, the length of the brightness recovery period corresponding to the same pixel group line is fixed regardless of changes in the frame rate.

[0026] Fig.17 It shows that Fig.15 This is a diagram showing another example in which the length of the brightness recovery period corresponding to the same pixel group line is fixed when the sensing period is set, regardless of changes in the frame rate.

[0027] Fig.18 is a diagram showing driving timings of scan signals and data voltages applied to a sensing pixel group line.

[0028] Fig.19 is a diagram showing a control data packet transmitted from a host system to a timing controller in a vertical blanking period. DETAILED DESCRIPTION

[0029] The advantages and features of the present disclosure and methods for implementing the same will become clear through the embodiments described below with reference to the accompanying drawings. However, the present disclosure is not limited to the exemplary embodiments disclosed herein, but will be implemented in various forms. These exemplary embodiments are provided only by way of example so that those skilled in the art can fully understand the disclosure of the present disclosure and the scope of the present disclosure. Further, the present disclosure is limited only by the scope of the claims.

[0030] The shapes, sizes, ratios, angles, quantities, etc. disclosed in the accompanying drawings for describing various embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto. The same reference numerals generally represent the same elements. Throughout the specification, the same elements are indicated by the same reference numerals. Terms such as "including", "having" and "comprising" used herein are generally intended to allow the addition of other components unless these terms are used together with "only". Unless the context clearly indicates otherwise, the singular form here is also intended to include the plural form.

[0031] Even if not explicitly stated, the elements in each embodiment of the specification are construed as including a range of errors.

[0032] When describing a positional relationship, for example, when the positional relationship between two parts is described as “on,” “over,” “below,” and “beside,” one or more other parts may be set between the two parts, unless “immediately next to” or “directly” is used.

[0033] It is to be understood that although the terms "first", "second", etc. are used herein to describe various components, these components are not limited by these terms. These terms are merely used to distinguish one component from other components. For example, within the scope of the present invention, a first component may be named a second component, and similarly, a second component may be named a first component.

[0034] Like reference numerals refer to like elements throughout the application.

[0035] In the specification, the gate drive circuit provided on the substrate of the display panel can be implemented with a thin film transistor (TFT) having an n-type metal oxide semiconductor field effect transistor (MOSFET) structure, but is not limited thereto, and can also be implemented with a TFT having a p-type MOSFET structure. The TFT can be a three-electrode element including a gate, a source, and a drain. The source can be an electrode that provides carriers to the transistor. In the TFT, the carriers can flow from the source. The drain can be an electrode from which the carriers flow out of the TFT. That is, in the MOSFET, the carriers flow from the source to the drain. In the n-type TFT (NMOS), since the carriers are electrons, the source voltage can be lower than the drain voltage, so that the electrons flow from the source to the drain. In the n-type TFT, since the electrons flow from the source to the drain, the current will flow from the drain to the source. On the other hand, in the p-type TFT (PMOS), since the carriers are holes, the source voltage can be higher than the drain voltage, so that the holes flow from the source to the drain. In a p-type TFT, since holes flow from the source to the drain, current flows from the source to the drain. It should be noted that the source and drain of a MOSFET are not fixed but interchangeable. For example, the source and drain of a MOSFET are interchangeable. Therefore, when describing an embodiment of the present disclosure, one of the source and drain will be described as a first electrode, and the other of the source and drain will be described as a second electrode.

[0036] In the following description, when the detailed description of related known functions or configurations is determined to unnecessarily obscure the key points of the specification, the detailed description will be omitted. Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0037] Figure 1 is a diagram showing an electroluminescent display device according to an embodiment of the present disclosure. Figure 2 It is shown that the Figure 1 Diagram of a pixel array in an electroluminescent display device. Figure 3 yes Figure 2 An equivalent circuit diagram of pixels included in a pixel array. Figure 4 is a diagram showing a configuration of a host system for changing a frame rate. Figure 5 This is a diagram for explaining the memory control operation at the time when the processing of the N-th frame image is completed. Figure 6 It is a diagram for explaining the memory control operation at the time of executing the processing of the N+1-th frame image.

[0038] refer to Figures 1 to 3 , the electroluminescent display device according to an embodiment of the present disclosure may include a display panel 10, a timing controller 11, a plurality of panel driving circuits 121 and 13, and a sensing circuit 122. The panel driving circuits 121 and 13 may include a digital-to-analog converter (DAC) 121 connected to a plurality of data lines 15 of the display panel 10 and a gate driver 13 connected to a plurality of gate lines 17 of the display panel 10. The panel driving circuits 121 and 13 and the sensing circuit 122 may be equipped in a data integrated circuit (IC) 12.

[0039] The display panel 10 may include a plurality of data lines 15, a plurality of readout lines 16, and a plurality of gate lines 17. Also, a plurality of pixels PXL may be respectively disposed in a plurality of pixel regions defined by intersections of the data lines 15, the readout lines 16, and the gate lines 17. Based on the pixels PXL arranged in a matrix type, the display area AA of the display panel 10 may be provided. Figure 2 The pixel array shown.

[0040] In the pixel array, the pixels PXL may be grouped into pixel group lines in one direction. Each pixel group line (Line1 to Line4) may include a plurality of pixels PXL adjacent to each other in the extension direction (or horizontal direction) of the gate line 17. A pixel group line may represent a group of pixels PXL arranged adjacent to each other in a horizontal direction, rather than a physical signal line. Therefore, the pixels PXL configured with the same pixel group line may be connected to the same gate line 17. The pixels PXL configured with the same pixel group line may be connected to different data lines 15, but are not limited thereto. The pixels PXL configured with the same pixel group line may be connected to different readout lines 16, but are not limited thereto, and a plurality of pixels PXL for realizing different colors may share one readout line 16.

[0041] In the pixel array, each pixel PXL may be connected to the DAC 121 through the data line 15 and may be connected to the sensing circuit 122 through the readout line 16. The DAC 121 and the sensing circuit 122 may be embedded in the data integrated circuit 12, but are not limited thereto. The sensing circuit 122 may be mounted on a control printed circuit board (PCB) (not shown) outside the data integrated circuit 12.

[0042] In the pixel array, each pixel PXL may be connected to a high-level pixel power source EVDD through a high-level power source line 18. Also, each pixel PXL may be connected to a gate driver 13 through gate lines 17(1) to 17(4).

[0043] In the pixel array, the pixel PXL may include a plurality of pixels for realizing a first color, a plurality of pixels for realizing a second color, and a plurality of pixels for realizing a third color, and further, the pixel PXL may include a plurality of pixels for realizing a fourth color. Each of the first to fourth colors may be a color selected from red, green, blue, and white.

[0044] Each pixel PXL can be Figure 3 , but is not limited thereto. One pixel PXL disposed in the kth (k is an integer) pixel group line may include a light emitting device EL, a driving thin film transistor (TFT) DT, a storage capacitor Cst, a first switching TFT ST1 and a second switching TFT ST2. The first switching TFT ST1 and the second switching TFT ST2 may be connected to the same gate line 17 (k).

[0045] The light emitting device EL may emit light based on the pixel current. The light emitting device EL may include an anode connected to a source node Ns, a cathode connected to a low-level pixel power source EVSS, and an organic or inorganic compound layer disposed between the anode and the cathode. The organic or inorganic compound layer may include a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). When the voltage applied to the anode is higher than the low-level pixel power source EVSS applied to the cathode by an operating point voltage, the light emitting device EL may be turned on. When the light emitting device EL is turned on, holes passing through the hole transport layer (HIL) and electrons passing through the electron transport layer (ETL) may move to the emission layer (EML) to generate excitons, and therefore, the emission layer (EML) may emit light.

[0046] The driving TFT DT may be a driving element. The driving TFT DT may generate a pixel current flowing in the light emitting device EL based on a voltage difference between a gate node Ng and a source node Ns. The driving TFT DT may include a gate connected to the gate node Ng, a first electrode connected to a high-level pixel power source EVDD, and a second electrode connected to the source node Ns. The storage capacitor Cst may be connected between the gate node Ng and the source node Ns and may store a gate-source voltage of the driving TFT DT.

[0047] The first switching TFT ST1 may allow current to flow between the data line 15 and the gate node Ng based on the gate signal SCAN(k), and may apply a data voltage charged in the data line 15 to the gate node Ng. The first switching TFT ST1 may include a gate connected to the gate line 17(k), a first electrode connected to the data line 15, and a second electrode connected to the gate node Ng. The second switching TFT ST2 may allow current to flow between the readout line 16 and the source node Ns based on the gate signal SCAN(k), and may transfer a voltage based on the pixel current of the source node Ns to the readout line 16. The second switching TFT ST2 may include a gate connected to the gate line 17(k), a first electrode connected to the source node Ns, and a second electrode connected to the readout line 16.

[0048] Such a pixel structure is only one embodiment, and the technical spirit of the present disclosure is not limited to this pixel structure. It should be noted that the technical spirit of the present disclosure can be applied to various pixel structures for sensing the electrical characteristics (eg, threshold voltage or electron mobility) of the driving TFT DT.

[0049] The host system 14 can be connected to the timing controller 11 through various interface circuits, and can transmit various signals DATA, DE and SC-FLAG required for driving the panel to the timing controller 11. Figure 4 As shown, the host system 14 may include a graphics processing unit GPU and a memory DDR, and may process the input image source based on a predetermined application and according to a purpose to transmit the processed image source to the timing controller 11. The image source may be input in a streaming manner, so the image source needs to be temporarily stored in the memory DDR for data processing. The image source is generally processed in units of one frame, which is to reduce the complexity and cost of data processing.

[0050] The graphics processing unit GPU performs rendering operations using a method of processing image data in units of one frame based on various image processing commands, and stores the frame data after image processing in the memory DDR using a drawing command. Figure 5 and 6 As shown in , the memory DDR is divided into two areas A and B so that rendering operations and transmission operations are performed simultaneously in different areas. When the rendering operation is being performed on the Nth frame image data in area A, the N-1th frame image data can be transmitted from area B in synchronization with the data enable signal DE. When the rendering operation of the Nth frame image data is completed, the graphics processing unit GPU synchronizes the Nth frame image data with the data enable signal DE and transmits the Nth frame image data from area A to the timing controller 11. At this time, the graphics processing unit GPU performs image processing on the N+1th frame image data in area B and performs a rendering operation on the N+1th frame image data.

[0051] The complexity of the input image can change in real time. Complex images take more time to render than simple images. For this reason, the time spent transmitting data in the first area of ​​the memory DDR may not match the time spent rendering data in the second area. For example, when the N+1th frame image data is more complex than the Nth frame image data, the graphics processing unit GPU will still perform a rendering operation on the N+1th frame image data in area B, while the transmission of the Nth frame image data in area A has been completed. At this time, the graphics processing unit GPU extends the vertical blanking period until the rendering operation of the N+1th frame image data is completed, thereby preventing the N+1th frame image data from being transmitted in an unstable rendering state. During the vertical blanking period, since the data enable signal DE is only transmitted in a logic low state without transition, the image data cannot be transmitted.

[0052] As described above, the graphics processing unit GPU can change the length of the vertical blanking period based on the complexity of the image, thereby ensuring data rendering time. When the length of the vertical blanking period in a frame changes, the frame rate also changes, which is called variable refresh rate (VRR) technology. VRR technology is used to change the frame rate according to the input image to prevent image tearing and provide a smoother image screen. In a variable frame rate environment, the length of the vertical blanking period varies according to the frame rate, but the length of the vertical active period is fixed. The vertical blanking period can be set to be the shortest in the fastest frame rate within a predetermined variable frame rate range, and increase as the frame rate becomes slower.

[0053] When the data rendering operation is completed in the first area or the second area, the graphics processing unit GPU transmits a rendering completion signal SC-FLAG in a vertical blanking period before transmitting the rendered image data. After a specific time has passed after the graphics processing unit GPU transmits the rendering completion signal SC-FLAG, the graphics processing unit GPU synchronizes the data enable signal DE having a transition state with the rendered image data of the subsequent frame, and transmits the rendered image data and the data enable signal DE to the timing controller 11. Regardless of how the frame rate changes, the length of the specific time is fixed.

[0054] The host system 14 may be implemented as an application processor, a personal computer, a set-top box, etc., but is not limited thereto. The host system 14 may be mounted on a system board, but is not limited thereto. The host system 14 may further include an input unit for receiving user commands / data and a main power supply unit for generating a main power supply.

[0055] The timing controller 11 receives a data enable signal DE synchronized with a variable frame rate, input image data DATA, and a rendering completion signal SC-FLAG from the host system 14 .

[0056] The timing controller 11 sets the sensing period in the vertical blanking period based on the rendering completion signal SC-FLAG. The timing controller 11 can implement sensing drive based on the rendering completion signal SC-FLAG, thereby preventing the length of the brightness recovery period corresponding to the same pixel group line from changing due to changes in the frame rate, and increasing the reliability of sensing. The timing controller 11 can fix the length of the brightness recovery period corresponding to the same pixel group line regardless of how the frame rate changes, thereby solving the problem that the position of the compensation pixel is perceived by the user due to the brightness deviation between the compensation pixel and the non-compensation pixel when the frame rate changes rapidly. This will refer to Figures 15 to 19 Detailed description.

[0057] The timing controller 11 may control the operation timings of the panel driving circuits 121 and 13 and the sensing circuit 122 so that the display driving, the sensing driving, and the brightness recovery driving are separated in time.

[0058] Display driving is an operation of applying a first data voltage (hereinafter referred to as display data voltage) for display driving to a pixel group line in a vertical active period of one frame to reproduce an input image in the display panel 10. Sensing driving is an operation of applying a second data voltage (hereinafter referred to as sensing data voltage) to a pixel PXL arranged in a specific pixel group line (hereinafter referred to as sensing pixel group line) in a vertical blanking period of one frame to sense and compensate for the electrical characteristics of the corresponding pixel PXL. In addition, brightness recovery driving is an operation of applying a third data voltage (hereinafter referred to as brightness recovery data voltage) to which a brightness compensation gain is applied to the pixel PXL of the sensing pixel group line that has completed the sensing operation to compensate for the brightness loss caused by the sensing operation. Because the third data voltage is a voltage in which the brightness compensation gain is applied to the first data voltage, the third data voltage may be different from the first data voltage. Brightness recovery driving is performed until the second data voltage of a subsequent frame is applied to the pixel PXL arranged in the sensing pixel group line.

[0059] In display driving, the timing controller 11 may generate a first data control signal DDC for controlling the operation timing of the data integrated circuit 12 and a first gate control signal GDC for controlling the operation timing of the gate driver 13 based on a timing signal, such as a data enable signal DE. In sensing driving, the timing controller 11 may generate a second data control signal DDC for controlling the operation timing of the data integrated circuit 12 and a second gate control signal GDC for controlling the operation timing of the gate driver 13 based on a timing signal, such as a data enable signal DE. In addition, in brightness recovery driving, the timing controller 11 may generate a third data control signal DDC for controlling the operation timing of the data integrated circuit 12 and a third gate control signal GDC for controlling the operation timing of the gate driver 13 based on a timing signal, such as a data enable signal DE.

[0060] The timing controller 11 can individually control the display drive timing, sensing drive timing and brightness recovery drive timing of each pixel group line of the display panel 10 based on the gate control signal GDC and the data control signal DDC. Therefore, in the process of displaying an image, the electrical characteristics of each pixel PXL can be sensed and compensated in real time in units of pixel group lines.

[0061] The timing controller 11 can control the operation of each of the panel driving circuits 121 and 13 so that the display driving is performed in the vertical active period of one frame; and can control the operation of each of the sensing circuit 122 and the panel driving circuits 121 and 13 so that the sensing driving is performed in the vertical blanking period before the vertical active period of one frame. In addition, the timing controller 11 can control the operation of the panel driving circuits 121 and 13 so that for the sensing pixel group line, the brightness recovery driving is performed between the end time of the sensing driving and the start time of the display driving.

[0062] The vertical active period corresponds to the transition period of the data enable signal DE and is a period in which the display data voltage is applied to the pixels PXL set in all pixel group lines. The vertical blanking period corresponds to the non-transition period of the data enable signal DE and is a period in which the application of the display data voltage is stopped, and the vertical blanking period may include a sensing period and may partially include a brightness recovery period. In the sensing period, the sensing data voltage may be applied to the pixels PXL set in the sensing pixel group line; in the brightness recovery period after the sensing period, the brightness recovery data voltage may be applied to the pixels PXL set in the sensing pixel group line.

[0063] Based on the control of the timing controller 11 , the gate driver 13 generates a display scan signal SCAN, a sensing scan signal, and a brightness recovery scan signal, respectively.

[0064] In order to implement display driving, in the vertical active period, the gate driver 13 may generate a display scanning signal according to the first gate control signal GDC, and sequentially provide the display scanning signal to the gate lines 17 connected to the pixel group lines.

[0065] To implement sensing driving, in the vertical blanking period, the gate driver 13 may generate a sensing scanning signal according to the second gate control signal GDC, and provide the sensing scanning signal to the gate line 17 connected to the sensing pixel group line. Subsequently, to implement brightness recovery driving, the gate driver 13 may generate a brightness recovery scanning signal according to the third gate control signal GDC, and may further provide the brightness recovery scanning signal to the gate line 17 connected to the sensing pixel group line.

[0066] In the case of sensing and driving one pixel group line in each vertical blanking period, the positions of the sensing pixel group lines can be randomly distributed based on the operations in multiple vertical blanking periods. When the positions of the sensing pixel group lines are randomly distributed, the adverse effects of the positions of the sensing pixel group lines being perceived can be minimized on the overall visual effect.

[0067] The gate driver 13 may be disposed in the non-display area NA of the display panel 10 based on a gate driver in panel (GIP) type.

[0068] The DAC 121 may be connected to the data line 15. The DAC 121 may generate a display data voltage Vdata, a sensing data voltage, and a brightness recovery data voltage, respectively, based on the control of the timing controller 11.

[0069] To implement display driving, in a vertical active period, the DAC 121 may convert the rendered image data DATA into a display data voltage based on a first data control signal DDC, and provide the display data voltage to the data line 15 in synchronization with a display scan signal SCAN.

[0070] In order to implement the sensing drive, in the vertical blanking period, the DAC 121 may generate a sensing data voltage having a specific level based on the second data control signal DDC and provide the sensing data voltage to the data line 15 in synchronization with the sensing scan signal.

[0071] To implement brightness recovery driving, the DAC 121 may convert the image data DATA reflecting the brightness compensation gain into a brightness recovery data voltage based on the third data control signal DDC, and may further provide the brightness recovery data voltage to the data line 15 in synchronization with the brightness recovery scan signal.

[0072] In the sensing drive, the sensing circuit 122 may be connected to the target pixel PXL of the sensing pixel group line through the readout line 16. In the sensing period included in the vertical blanking period, the sensing circuit 122 may sense the electrical characteristics of the driving TFT DT included in each target pixel PXL through the readout line 16. The sensing circuit 122 may be implemented as a voltage sensing type, or may be implemented as a current sensing type.

[0073] The voltage sensing type sensing circuit 122 may include a sampling circuit and an analog-to-digital converter (ADC). The sampling circuit may directly sample a specific node voltage of the target pixel PXL stored in the parasitic capacitance of the readout line 16. The ADC may convert the analog voltage sampled by the sampling circuit into a digital sensing value, and may transmit the digital sensing value to the timing controller 11.

[0074] The current sensing type sensing circuit 122 may include a current integrator, a sampling circuit, and an ADC. The current integrator may integrate the pixel current flowing in the target pixel PXL to output a sensing voltage. The sampling circuit may sample the sensing voltage output by the current integrator. The ADC may convert the analog voltage sampled by the sampling circuit into a digital sensing value, and transmit the digital sensing value to the timing controller 11.

[0075] Figure 7 is a diagram showing an example of transmitting and receiving a signal based on a variable frame rate between a host system and a timing controller. Figure 8 and 9 A diagram for explaining a variable refresh rate (VRR) technique for changing a frame rate based on an input image.

[0076] refer to Figure 7 , the host system 14 changes the length of the vertical blanking period (i.e., the length of the non-transition period of the data enable signal) based on the rendering time of the input image. Problems such as screen breakage, screen jitter, and input delay caused by rapid image changes can be solved by changing the frame rate. Based on the data rendering time of the input image, the host system 14 can adjust the frame rate within a frequency range of 40 Hz to 240 Hz, or in a still image, the host system 14 can adjust the frame rate within a frequency range of 1 Hz to 10 Hz, but is not limited thereto. The range of the variable frame rate can be set differently based on the model and specifications.

[0077] The host system 14 may be Figure 8 The length of the vertical active period Vactive is fixed as shown, and the length of the vertical blanking period Vblank can be adjusted based on the data rendering time of the input image, thereby changing the frame rate. Fig. 9 As shown, the host system 14 may include a first vertical blanking period Vblank1 to implement a 144 Hz mode. The host system 14 may include a second vertical blanking period Vblank2 that adds an "X" period from the first vertical blanking period Vblank1 to implement a 100 Hz mode. The host system 14 may include a third vertical blanking period Vblank3 that adds a "Y" period from the first vertical blanking period Vblank1 to implement an 80 Hz mode. The host system 14 may include a fourth vertical blanking period Vblank4 that adds a "Z" period from the first vertical blanking period Vblank1 to implement a 60 Hz mode.

[0078] Figures 10 to 12B 1 is a diagram for explaining a sensing pixel group line compensation (SLC) technique for compensating for a length deviation of a brightness recovery period with respect to a position of a sensing pixel group line in an external compensation technique.

[0079] The following case will be described: When the frame rate environment is as follows: Fig.10In the fixed frame rate environment of X Hz shown in the figure, the pixels of the m-1th pixel group line (i.e., the pixels of the pixel group line provided with SCAN (m-1)) are sensed in the vertical blanking period Vblank of the N-1th frame, and the pixels of the fourth pixel group line (i.e., the pixels of the pixel group line provided with SCAN (4)) are sensed in the vertical blanking period Vblank of the N-th frame (X Hz).

[0080] In the first display period DTME1, the pixels of the m-1th pixel group line may be charged with the display data voltage based on the m-1th display scan signal SCAN(m-1) (WT-DIS operation), and then, may maintain the light emitting state based on the display data voltage (HLD-DIS operation) at the rest of the first display period DTME1. The first display period DTME1 may partially overlap the vertical active period Vactive and the vertical blanking period Vblank of the N-1th frame.

[0081] In the sensing period STME after the first display period DTME1, the pixels of the m-1 pixel group line may be charged with a sensing data voltage (WT-SEN operation) based on a sensing scan signal and then may be sensed in a non-luminescent state. The sensing period STME may be in the vertical blanking period Vblank of the N-1 frame.

[0082] In the first brightness recovery period RTME1 after the sensing period STME, the pixels of the m-1th pixel group line may be charged with the brightness recovery data voltage (WT-RCV operation) based on the brightness recovery scanning signal, and then, the light emitting state based on the brightness recovery data voltage may be maintained at other times of the first brightness recovery period RTME1 (HLD-RCV operation). The first brightness recovery period RTME1 may partially overlap with the vertical blanking period Vblank of the N-1th frame and the vertical active period Vactive of the Nth frame.

[0083] In the second display period DTME2, the pixels of the fourth pixel group line may be charged with the display data voltage based on the fourth display scan signal SCAN(4) (WT-DIS operation), and then may maintain the light emitting state based on the display data voltage (HLD-DIS operation) at other times of the second display period DTME2. The second display period DTME2 may partially overlap with the vertical active period Vactive and the vertical blanking period Vblank of the Nth frame.

[0084] In the sensing period STME after the second display period DTME2, the pixels of the fourth pixel group line may be charged with the sensing data voltage (WT-SEN operation) based on the sensing scan signal and then may be sensed in the non-luminescent state. The sensing period STME may be in the vertical blanking period Vblank of the Nth frame.

[0085] In the second brightness recovery period RTME2 after the sensing period STME, the pixels of the fourth pixel group line may be charged with the brightness recovery data voltage (WT-RCV operation) based on the brightness recovery scanning signal, and then, the light emitting state based on the brightness recovery data voltage may be maintained at other times of the second brightness recovery period RTME2 (HLD-RCV operation). The second brightness recovery period RTME2 may partially overlap with the vertical blanking period Vblank of the Nth frame and the vertical active period Vactive of the N+1th frame.

[0086] Since the frame rate environment is a fixed frame rate environment, the length of the vertical blanking period Vblank of the N-1 frame can be the same as the length of the vertical blanking period Vblank of the N frame. In addition, in each of the vertical blanking period Vblank of the N-1 frame and the vertical blanking period Vblank of the N frame, the sensing period STME can have the same time length. In addition, since the frame rate environment is a fixed frame rate environment, the length of one frame required for performing a display drive operation, a sensing drive operation, and a brightness recovery drive operation on the pixels of the m-1 pixel group line can be the same as the length of one frame required for performing a display drive operation, a sensing drive operation, and a brightness recovery drive operation on the pixels of the fourth pixel group line.

[0087] In the vertical active period Vactive of the N-1th frame, the phase of the m-1th display scan signal SCAN(m-1) may be later than the phase of the fourth display scan signal SCAN(4). Therefore, for the pixels of the m-1th pixel group line, the first display period DTME1 may be relatively short, and the first brightness recovery period RTME1 may be relatively long.

[0088] In the vertical active period Vactive of the Nth frame, the phase of the fourth display scan signal SCAN(4) may be later than the phase of the m-1th display scan signal SCAN(m-1). Therefore, for the pixels of the fourth pixel group line, the second display period DTME2 may be relatively long, and the second brightness recovery period RTME2 may be relatively short.

[0089] However, if Fig.11 As shown, in the case where all pixels in one screen display an image with the same brightness, during the sensing period STME of the vertical blanking period Vblank, the pixels of the sensing pixel group line PXL-B may not emit light, and thus may achieve a brightness lower by "ΔL" than the pixels of the non-sensing pixel group line PXL-A. The sensing pixel group line PXL-B may be Fig.10 The m-1th and fourth pixel group lines in the implementation manner.

[0090] exist Fig.10In an embodiment, the first brightness recovery period RTME1 and the second brightness recovery period RTME2 may be used to compensate for brightness loss. The first brightness recovery period RTME1 and the second brightness recovery period RTME2 may have different time lengths, and thus, brightness compensation gains may be applied differently. Fig.11 As shown, when the brightness compensation gain is applied, the brightness in the brightness recovery period can be relatively higher than the brightness in the display period, and therefore, all pixels in one screen can achieve substantially the same brightness.

[0091] There may be an inverse relationship between the magnitude of the brightness compensation gain and the time length of the brightness recovery period. Regardless of the relative positions of the sensing pixel group lines, all sensing pixel group lines may have the same length of sensing period and thus may have the same brightness loss. However, the sensing pixel group lines may have brightness recovery periods of different lengths based on the relative positions therebetween, and therefore, the magnitude of the brightness compensation gain for compensating for the brightness loss may be applied differently to the sensing pixel group lines.

[0092] like Fig. 12A As shown, the size of the brightness compensation gain can be set differently for each brightness recovery period block grouped based on a specific time length. Therefore, the brightness compensation gain logic can be simplified and the compensation processing speed can be improved.

[0093] like Fig. 12B As shown, the magnitude of the brightness compensation gain can be set differently for each brightness recovery period that is different for each sensing pixel group line. Therefore, the accuracy of compensation can be improved.

[0094] The correction operation performed on the image data based on the brightness compensation gain may be performed by the timing controller. The timing controller may further include an SLC compensation logic circuit for applying the brightness compensation gain to the image data to be applied to the pixels of the sensing pixel group line.

[0095] As mentioned above Figures 10 to 12B The SLC technology described can be implemented with simple logic in a fixed frame rate environment. The position of the sensing pixel group line can be predetermined for each frame, but since the frame rate environment is a fixed frame rate environment, the length of the brightness recovery period corresponding to the same sensing pixel group line does not change with the frame rate. That is, since the frame rate environment is a fixed frame rate environment, the brightness recovery period can be pre-mapped to the position of the sensing pixel group line, thereby having different fixed lengths. In addition, the brightness compensation gain can be pre-set differently for brightness recovery periods with different fixed lengths.

[0096] Fig.13 is a diagram showing an example of setting a sensing period in a vertical blanking period with reference to a last data enable signal of a vertical active period in a comparative example of the present disclosure. Fig.14 It shows that Fig.13 A diagram showing an example in which the length of the luminance recovery period corresponding to the same pixel group line changes based on a change in the frame rate when the sensing period is set.

[0097] refer to Fig.13 , the timing controller may set a sensing period in the vertical blanking period Vblank relative to the falling edge FE of the last data enable signal (last DE) of the vertical active period, wherein the length of the vertical blanking period Vblank varies based on the rate of the frame rate. For example, the timing controller may set the sensing period from the moment t1 delayed by ΔT relative to the falling edge FE to the moment t2. At this time, the length of the brightness recovery period starting from the moment t2 varies according to the rate of the frame rate.

[0098] In such Fig.13 In the case of setting the sensing period in the variable frame rate environment shown, it is difficult to apply the above-mentioned SLC technology. This is because the length of the brightness recovery period corresponding to the same sensing pixel group line varies based on the change of the frame rate.

[0099] For example, Fig.14 As shown, it is assumed that in the N-1th frame with a frame rate of J Hz and the Nth frame with a frame rate of K Hz higher than J Hz, the pixels of the fourth pixel group line (ie, the pixels of the pixel group line to which SCAN(4) is provided) are continuously sensed.

[0100] The vertical blanking period Vblank is set to be longer in the N-1 frame, which has a lower frame rate than the N frame. The lengths of the brightness recovery periods in the N-1 frame and the N frame are determined by the vertical blanking period Vblank. Therefore, for the same fourth pixel group line, the first brightness recovery period RTME1 of the N-1 frame can be longer than the second brightness recovery period RTME2 of the N frame.

[0101] In a variable frame rate environment, the length of the brightness recovery period varies more based on the frame rate and the relative position of the sensing pixel group line, and since the length change of the brightness recovery period cannot be predicted according to the change of the frame rate, the SLC technology cannot be applied. This will be described further below.

[0102] The timing controller may determine the frame rate of each frame with reference to the input data enable signal DE transmitted from the host system, rather than receiving information about the variable frame rate separately from the host system. In a specific frame, the timing controller may determine the transition period of the input data enable signal DE (i.e., the period in which pulses are alternately generated between a logic low voltage and a logic high voltage) as the vertical active period Vactive of the corresponding frame, and may determine the non-transition period of the input data enable signal DE (i.e., the period in which only a logic low voltage is maintained without a pulse) as the vertical blanking period Vblank of the corresponding frame.

[0103] However, the timing controller may not know the vertical blanking period Vblank of the N-1 frame until the first pulse of the input data enable signal DE starts to rise in the N frame, and may not know the vertical blanking period Vblank of the N frame until the first pulse of the input data enable signal DE starts to rise in the N+1 frame. In other words, the timing controller may not be able to predict the length change of the first brightness recovery period RTME1 based on the frame rate (J Hz) of the N-1 frame, and therefore, it is difficult to apply an appropriate brightness compensation gain to the first brightness recovery period RTME1. Similarly, the timing controller may not be able to predict the length change of the second brightness recovery period RTME2 based on the frame rate (K Hz) of the N frame, and therefore, it is difficult to apply an appropriate brightness compensation gain to the second brightness recovery period RTME2.

[0104] When the length deviation of the first brightness recovery period RTME1 and the second brightness recovery period RTME2 corresponding to the same sensing pixel group line is not compensated based on the appropriate brightness compensation gain, the sensing pixel group line may be perceived as a line dim.

[0105] Fig.15 is a diagram showing an example of setting a sensing period in a vertical blanking period with reference to a rendering completion signal in an embodiment of the present disclosure. Fig.16 It shows that Fig.15 This diagram shows an example in which the length of the luminance recovery period corresponding to the same pixel group line is fixed regardless of changes in the frame rate when the sensing period is set.

[0106] refer to Fig.15, the timing controller according to the embodiment of the present disclosure sets the sensing period in the vertical blanking period Vblank of the N-1 frame based on the rendering completion signal SC-FLAG transmitted from the host system. The rendering completion signal SC-FLAG is a pulse that is a specific time TC earlier than the end time of the vertical blanking period Vblank, and the sensing period is set based on the pulse edge of the rendering completion signal SC-FLAG. Here, the pulse edge represents a rising edge or a falling edge, and the end time of the vertical blanking period Vblank is synchronized with the rising edge RE of the first data enable signal of the Nth frame. In addition, the length of the specific time TC is fixed, regardless of the change in the frame rate, and has a front cycle and a rear cycle.

[0107] The timing controller allocates the front period to1 to to2 as the sensing period and the rear period to2 to RE as the brightness recovery period in a specific time TC of a fixed length. Therefore, Fig.16 As shown, the length of the brightness recovery period corresponding to the same pixel group line does not change with the change of the frame rate. The first time to1 may be synchronized with the falling edge FE of the rendering completion signal SC-FLAG.

[0108] The timing controller allocates a period other than the fixed specific time TC in the vertical blanking period Vblank as an image holding period. The start time of the image holding period in the vertical blanking period Vblank may be synchronized with the falling edge FE of the last data enable signal of the N-1th frame.

[0109] The length of the image holding period may vary based on the rate of the frame rate, and thus may be defined as a variable period in the vertical blanking period Vblank. On the other hand, the length of the specific time TC including the sensing period may be fixed regardless of the rate of the frame rate, and thus the specific time TC may be defined as a fixed period in the vertical blanking period Vblank. The variable period may be set between the falling edge FE of the last data enable signal in the N-1th frame and the falling edge FE of the rendering completion signal SC-FLAG, and the fixed period may be set between the falling edge FE of the rendering completion signal SC-FLAG and the rising edge RE of the first data enable signal in the Nth frame.

[0110] Fig.17 It shows that Fig.15 FIG. 1 is a diagram showing another example of setting the sensing period so that the length of the brightness recovery period corresponding to the same pixel group line is fixed regardless of changes in the frame rate. Fig.18 is a diagram showing driving timings of scan signals and data voltages applied to a sensing pixel group line.

[0111] refer to Fig.17 and 18, in the process of compensating the electrical characteristic deviation between pixels based on the external compensation method, the electroluminescent display device according to the embodiment of the present disclosure can prevent the user from perceiving the position of the compensated pixel even if the frame rate changes based on the input image. In other words, in the case of applying the SLC technology in a variable frame rate environment in the electroluminescent display device according to the embodiment of the present disclosure, regardless of the change in the frame rate, the length of the brightness recovery period corresponding to the same pixel group line can be constant, thereby preventing the sensing pixel group line from being perceived as a line dim.

[0112] like Fig.17 and 18 As shown, in a variable frame rate environment where the N-1th frame to the N+1th frame have different frame rates (e.g., "1 Hz", "K Hz", and "L Hz"), the timing controller can set the length of the first brightness recovery period RTME1 in the Nth frame and the length of the second brightness recovery period RTME2 in the N+1th frame to be constant regardless of the change in the frame rate. This is achievable because the sensing period STME is set in a specific time TC relative to the rendering completion signal SC-FLAG.

[0113] The following will refer to Fig.17 and 18 Combination Figure 1 The operation of the electroluminescent display device in a variable frame rate environment is briefly described. Here, it is assumed that the target pixel disposed in the fourth pixel group line is sense-driven.

[0114] The timing controller 11 receives a rendering completion signal SC-FLAG from the host system 14 in the vertical blanking period Vblank1 of the N-1th frame, sets a sensing period STME in the vertical blanking period Vblank1 according to the rendering completion signal SC-FLAG, and outputs a second gate control signal GDC and a second data control signal DDC required for the sensing drive and a third gate control signal GDC and a third data control signal DDC required for the brightness recovery drive of the panel driving circuits 121 and 13.

[0115] In the sensing period STME, the panel driving circuits 121 and 13 generate a second data voltage Vdata2 for sensing driving and a sensing scan signal P2 synchronized with the second data voltage Vdata2 based on the second gate control signal GDC and the second data control signal DDC. In the sensing period STME, the panel driving circuits 121 and 13 apply the second gate control signal GDC, the second data control signal DDC, and the sensing scan signal P2 (WT-SEN operation) to the target pixel to perform sensing driving of the target pixel. In the sensing driving, the driving element included in the target pixel performs a turn-on operation based on the second data voltage Vdata2, but the light-emitting device included in the target pixel does not emit light. In the sensing period STME, the sensing circuit 122 senses the electrical characteristics (threshold voltage and / or mobility) of the driving element included in the target pixel.

[0116] The panel driving circuits 121 and 13 generate a third data voltage Vdata3 for brightness recovery driving and a brightness recovery scanning signal P3 synchronized with the third data voltage Vdata3 based on the third gate control signal GDC and the third data control signal DDC in the first brightness recovery period RTME1 after the sensing period STME. The third data voltage Vdata3 for brightness recovery driving is a data voltage to which a brightness compensation gain is applied to compensate for the brightness loss caused by non-light emission during the sensing period STME. The brightness compensation gain is based on Fig. 12A and 12B The method shown is pre-set in units of one or more pixel group lines. The panel driving circuits 121 and 13 provide the target pixel with the third data voltage Vdata3 and the brightness recovery scan signal P3 (WT-RCV operation) applied with the brightness compensation gain in the brightness recovery period RTME of the Nth frame to perform the brightness recovery drive (HLD-RCV operation) of the target pixel. Such a WT-RCV operation is performed in the first vertical blanking period Vblank1 of the N-1th frame, and the HLD-RCV operation is performed in the vertical active period Vactive of the Nth frame until the display scan signal P1 is applied to the target pixel.

[0117] The timing controller 11 receives the data enable signal DE and the rendering image data DATA of the Nth frame from the host system 14 in the vertical active period Vactive of the Nth frame, and generates the first gate control signal GDC and the first data control signal DDC required for the display driving of the panel driving circuits 121 and 13. The timing controller 11 outputs the first gate control signal GDC, the first data control signal DDC and the rendering image data DATA of the Nth frame to the panel driving circuits 121 and 13. In the vertical active period Vactive of the Nth frame, the panel driving circuits 121 and 13 provide the first data voltage Vdata1 and the display scanning signal P1 (WT-DIS operation) to the target pixel to perform the display driving (HLD-DIS operation) of the target pixel. Such a WT-DIS operation is performed in the vertical active period Vactive of the Nth frame, and the HLD-DIS operation is maintained in the vertical blanking period Vblank2 of the N+1th frame until the rendering completion signal SC-FLAG is received.

[0118] According to this embodiment, no matter how the frame rate changes, the length of the brightness recovery period RTME1 or RTME2 corresponding to the same pixel group line can be constant. This is because the timing controller 11 controls the panel driving circuit based on the rendering completion signal SC-FLAG so that the sensing drive is performed in a fixed period of the vertical blanking period.

[0119] According to the present embodiment, since the length of the brightness recovery period changes only based on the supply order of the display scanning signals SCAN(1) to SCAN(m) and not based on the change of the frame rate, the timing controller 11 can be based on Fig. 12A and 12B The method shown selects a brightness compensation gain suitable for the length of the brightness recovery period, and can provide the brightness compensation gain to the panel driving circuits 121 and 13. Therefore, the panel driving circuits 121 and 13 can generate a third data voltage to which an appropriate brightness compensation gain is applied and can apply the generated third data voltage to the pixels of the sensing pixel group line, thereby preventing the sensing pixel group line from being perceived as line dimming.

[0120] According to this embodiment, when the frame rates of the consecutive first frame and the second frame are different, the lengths of the vertical active periods in which the data enable signal is pulsed in one frame are the same in the first frame and the second frame. On the other hand, the lengths of the vertical blanking periods in which the data enable signal is not pulsed in one frame are different in the first frame and the second frame.

[0121] In this embodiment, the sensing period STME is set between the display period DTME and the brightness recovery period RTME1 or RTME2. Here, the sensing period STME and the brightness recovery period RTME1 or RTME2 correspond to the same pixel. The display period DTME can be called the first light-emitting period, and the brightness recovery period RTME1 or RTME2 can be called the second light-emitting period. The brightness of the second light-emitting period is higher than the brightness of the first light-emitting period, thereby compensating for the brightness loss during the sensing period STME. This is achievable because a brightness compensation gain is applied. Based on this differential brightness implementation, the brightness deviation between the sensing pixel and the non-sensing pixel is reduced. In other words, based on the overall perception effect of the differential brightness implementation, the sensing pixel group line is not perceived as a dim line.

[0122] Fig.19 is a diagram showing a control data packet transmitted from a host system to a timing controller in a vertical blanking period.

[0123] refer to Fig.19 The host system may process the rendering completion signal SC-FLAG into a control data packet and may transmit the processed rendering completion signal SC-FLAG. The rendering completion signal SC-FLAG may be packaged by a packet start signal and a packet end signal and transmitted, thereby minimizing signal distortion occurring during transmission.

[0124] Through the above description, those skilled in the art can make various changes and modifications within the scope of the technical concept of the present disclosure. Therefore, the technical scope of the present disclosure should not be limited to the contents in the specification, but should be determined according to the scope of the claims.

Claims

1. A display device, include: A display panel comprising pixels, wherein the pixels include a driving element and a light emitting device; a host system configured to render image data to be applied to the pixel, change the length of a vertical blanking period, and output a rendering completion signal before outputting the rendered image data; a timing controller configured to divide the vertical blanking period into a variable period and a fixed period based on the rendering completion signal, the length of the variable period varying based on the rate of a frame frequency, the length of the fixed period being fixed regardless of the rate of the frame frequency, and to set a sensing period in the fixed period; and a sensing circuit configured to sense an electrical characteristic of the driving element during the sensing period, The sensing period starts at a first moment, the first moment is a predetermined time earlier than an end time of the vertical blanking period, and the length of the predetermined time is constant regardless of the change in the length of the vertical blanking period.

2. The display device according to claim 1, wherein The host system is configured to fix the length of a vertical active period during which the data enable signal is pulsed in one frame, The host system is configured to change the length of the vertical blanking period during which the data enable signal is not pulsed in a frame.

3. The display device according to claim 1, in, The sensing period is set based on a pulse edge of the rendering completion signal synchronized with the first timing.

4. The display device according to claim 2, further comprising a panel driving circuit, The panel driving circuit is configured to provide the pixel with a first data voltage for display driving and a display scanning signal synchronized with the first data voltage in the vertical active period, The panel driving circuit is configured to provide the pixel with a second data voltage for sensing driving and a sensing scan signal synchronized with the second data voltage in the sensing period.

5. The display device according to claim 4, wherein A brightness recovery period is also provided between the pulse edge of the display scanning signal and the second moment when the sensing period ends, for compensating for the brightness loss caused by non-light emission during the sensing period. Regardless of how the vertical blanking period changes, the length of the brightness recovery period corresponding to the pixel is fixed.

6. The display device according to claim 5, in, The panel driving circuit is further configured to provide the pixel with a third data voltage to which a brightness compensation gain is further applied and a brightness recovery scanning signal synchronized with the third data voltage in the brightness recovery period.

7. The display device according to claim 6, wherein The pixel is included in one of a plurality of pixel group lines to which the display scanning signal is sequentially supplied, In the same frame, the length of the brightness recovery period of the second pixel group line is longer than the length of the brightness recovery period of the first pixel group line, The display scanning signals of the first pixel group line are provided earlier than the display scanning signals of the second pixel group line.

8. The display device according to claim 7, in, The brightness compensation gain corresponding to the first pixel group line is greater than the brightness compensation gain corresponding to the second pixel group line.

9. The display device according to claim 2, in, The end time of the vertical blanking period is set based on a rising edge of a first data enable signal of a subsequent frame.

10. A display device, include: A display panel comprising pixels, wherein the pixels include a driving element and a light emitting device; a timing controller configured to set a sensing period in a vertical blanking period based on a rendering completion signal; and a sensing circuit configured to sense an electrical characteristic of the driving element during the sensing period, wherein The vertical blanking period includes a variable period and a fixed period, the length of the variable period varies based on the rate of the frame frequency, and the length of the fixed period is fixed regardless of the rate of the frame frequency, The sensing period is included in the fixed period.

11. The display device according to claim 10, further comprising a host system configured to render image data to be applied to the pixels, change the rate of the frame rate, and output the rendering completion signal before outputting the rendered image data.

12. The display device according to claim 10, wherein The variable period is set between the pulse edge of the rendering completion signal and the falling edge of the last data enable signal of the first frame. The fixed period is set between the pulse edge of the rendering completion signal and the rising edge of the first data enable signal of the second frame, The second frame follows the first frame.

13. The display device according to claim 12, wherein In the first frame and the second frame, the length of the vertical active period during which the data enable signal is pulsed in one frame is the same, In the first frame and the second frame, the length of the vertical blanking period in which the data enable signal is not pulsed in one frame is different.

14. The display device according to claim 12, in, The frame rate of the first frame is different from the frame rate of the second frame.

15. The display device according to claim 14, wherein A first light emitting period and a second light emitting period corresponding to the pixel are also provided, and the sensing period is located between the first light emitting period and the second light emitting period. The lengths of the first light emitting periods in the first frame and the second frame are different, The lengths of the second light-emitting periods in the first frame and the second frame are the same.

16. The display device according to claim 15, in, The brightness of the second light emitting period is higher than the brightness of the first light emitting period.

17. A method for driving a display device, the display device comprising a pixel, the pixel comprising a driving element and a light emitting device, the driving method include: rendering image data to be applied to the pixel, changing the length of a vertical blanking period, and outputting a rendering completion signal before outputting the rendered image data; dividing the vertical blanking period into a variable period and a fixed period based on the rendering completion signal, the length of the variable period varies based on the rate of the frame frequency, the length of the fixed period is fixed regardless of the rate of the frame frequency, and setting a sensing period in the fixed period; and sensing an electrical characteristic of the driving element during the sensing period, The sensing period starts at a first moment, the first moment is a predetermined time earlier than an end time of the vertical blanking period, and the length of the predetermined time is fixed regardless of the change of the length of the vertical blanking period.

18. A method for driving a display device, the display device comprising a pixel, the pixel comprising a driving element and a light emitting device, the driving method include: setting a sensing period in a vertical blanking period based on the rendering completion signal; and sensing an electrical characteristic of the driving element during the sensing period, in The vertical blanking period includes a variable period and a fixed period, the length of the variable period varies based on the rate of the frame frequency, and the length of the fixed period is fixed regardless of the rate of the frame frequency, The sensing period is set within the fixed period.

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