Nitride semiconductor device and method of manufacturing the same

Abstract

A nitride semiconductor device includes: a first light-emitting portion including a first n-side semiconductor layer, a first active layer provided on the first n-side semiconductor layer, and a first p-side semiconductor layer provided on the first active layer; a second light-emitting portion including a second n-side semiconductor layer provided on the first p-side semiconductor layer, a second active layer provided on the second n-side semiconductor layer, and a second p-side semiconductor layer provided on the second active layer; a first layer that is grounded to the first p-side semiconductor layer and provided between the first light-emitting portion and the second light-emitting portion, containing an n-type impurity with a first concentration; a second layer that is provided between the first layer and the second n-side semiconductor layer, containing an n-type impurity with a second concentration, the second n-side semiconductor layer containing an n-type impurity with a third concentration, the first concentration and the second concentration being greater than the third concentration, the first concentration being greater than the second concentration, and the thickness of the second layer being thicker than the thickness of the first layer.

Description

Technical Field

[0001] The present disclosure relates to a nitride semiconductor device and a method for manufacturing a nitride semiconductor device. Background Art

[0002] In recent years, the development of nitride semiconductor devices having a tunnel junction has been booming. For example, Patent Document 1 discloses a method for manufacturing a nitride semiconductor device including a group III nitride semiconductor layer having a tunnel junction.

[0003] Prior Art Documents

[0004] Patent Documents

[0005] Patent Document 1: Japanese Patent Application Laid-Open No. 2019-522356 Summary of the Invention

[0006] Problems to be Solved by the Invention

[0007] A nitride semiconductor device including such a nitride semiconductor layer having a tunnel junction has a tendency for the forward voltage to increase.

[0008] Therefore, an object of the present disclosure is to provide a nitride semiconductor device and a method for manufacturing the nitride semiconductor device, the nitride semiconductor device being capable of reducing the forward voltage.

[0009] Technical Means for Solving the Problems

[0010] The present disclosure provides a nitride semiconductor device including: a first light-emitting portion including a first n-side semiconductor layer, a first active layer provided on the first n-side semiconductor layer, and a first p-side semiconductor layer provided on the first active layer; a second light-emitting portion including a second n-side semiconductor layer provided on the first p-side semiconductor layer, a second active layer provided on the second n-side semiconductor layer, and a second p-side semiconductor layer provided on the second active layer; a first layer grounded to the first p-side semiconductor layer and provided between the first light-emitting portion and the second light-emitting portion, containing an n-type impurity at a first concentration; a second layer provided between the first layer and the second n-side semiconductor layer, containing an n-type impurity at a second concentration, the second n-side semiconductor layer containing an n-type impurity at a third concentration, the first concentration and the second concentration being greater than the third concentration, the first concentration being greater than the second concentration, and the thickness of the second layer being thicker than the thickness of the first layer.

[0011] In addition, the present disclosure provides a method for manufacturing a nitride semiconductor device, including: a step of preparing a first light-emitting section including a first n-side semiconductor layer, a first active layer formed on the first n-side semiconductor layer, and a first p-side semiconductor layer formed on the first active layer; a step of introducing an element serving as an n-type impurity to form a first layer containing an n-type impurity at a first concentration on the first p-side semiconductor layer; a step of introducing an element serving as an n-type impurity to form a second layer containing an n-type impurity at a second concentration that is thicker than the first layer and smaller than the first concentration on the first layer; and a step of forming a second light-emitting section including a second n-side semiconductor layer containing an n-type impurity at a third concentration smaller than the first concentration and the second concentration and formed on the second layer, a second active layer formed on the second n-side semiconductor layer, and a second p-side semiconductor layer formed on the second active layer.

[0012] Advantages of the Invention

[0013] According to a nitride semiconductor device and a method for manufacturing the same according to an embodiment of the present disclosure, it is possible to provide a nitride semiconductor device and a method for manufacturing the same, and the nitride semiconductor device can reduce the forward voltage. Description of the Drawings

[0014] Figure 1 is a cross-sectional view of a nitride semiconductor device according to an embodiment of the present disclosure.

[0015] Figure 2A is a schematic cross-sectional view showing Figure 1 an example of the manufacturing process of the nitride semiconductor device shown in

[0016] Figure 2B is a schematic cross-sectional view showing Figure 1 an example of the manufacturing process of the nitride semiconductor device shown in

[0017] Figure 2C is a schematic cross-sectional view showing Figure 1 an example of the manufacturing process of the nitride semiconductor device shown in

[0018] Figure 2D is a schematic cross-sectional view showing Figure 1 an example of the manufacturing process of the nitride semiconductor device shown in

[0019] Figure 2E is a schematic cross-sectional view showing Figure 1 an example of the manufacturing process of the nitride semiconductor device shown in

[0020] Figure 2F is a schematic cross-sectional view showing Figure 1Schematic cross-sectional view of an example of a manufacturing process of a nitride semiconductor device shown.

[0021] Figure 2G It shows Figure 1 Schematic cross-sectional view of an example of a manufacturing process of a nitride semiconductor device shown.

[0022] Figure 2H It shows Figure 1 Schematic cross-sectional view of an example of a manufacturing process of a nitride semiconductor device shown.

[0023] Figure 3 Cross-sectional view of a light-emitting device including a nitride semiconductor device 100 according to an embodiment of the present disclosure.

[0024] Figure 4 Graph showing the results of SIMS analysis related to Si concentration and Mg concentration. Detailed Description

[0025] Hereinafter, embodiments or examples for implementing the present disclosure will be described with reference to the drawings. It should be noted that the nitride semiconductor device and the method for manufacturing a nitride semiconductor device described below are for embodying the technical idea of the present disclosure, and the present disclosure is not limited to the following contents unless otherwise specified.

[0026] In each of the drawings, components having the same function may be denoted by the same reference numeral. For ease of explanation or understanding, sometimes for convenience, they are shown as embodiments or examples, but the structures shown by different embodiments or examples can be partially replaced or combined. In the following embodiments or examples, descriptions of the same cases as those above are omitted, and only different points are described. In particular, the same effects brought about by the same structure are not repeatedly mentioned in each embodiment or example. The sizes or positional relationships of the components shown in each drawing are sometimes exaggerated for clarity of explanation.

[0027] Embodiment

[0028] Hereinafter, a nitride semiconductor device and a method for manufacturing the nitride semiconductor device according to the present embodiment will be described with reference to the drawings. It should be noted that in each of the drawings, the same reference numerals are assigned to the same elements.

[0029] As Figure 1 shown, the nitride semiconductor device 100 according to the present embodiment includes a substrate 2, a semiconductor structure 1 disposed on the substrate 2, a first electrode 3, and a second electrode 4.

[0030] The semiconductor structure 1 of this embodiment includes a first light-emitting portion 10, a second light-emitting portion 20, a first layer 31 disposed between the first light-emitting portion 10 and the second light-emitting portion 20 and containing an n-type impurity with a first concentration, and a second layer 32 disposed between the first layer 31 and the second light-emitting portion 20 and containing an n-type impurity with a second concentration.

[0031] The first light-emitting portion 10 includes a first n-side semiconductor layer 11 disposed on a substrate 2, a first active layer 12 disposed on the first n-side semiconductor layer 11, and a first p-side semiconductor layer 13 disposed on the first active layer 12. A first electrode 3 is electrically connected to the first n-side semiconductor layer 11.

[0032] The first layer 31 is disposed on the first p-side semiconductor layer 13 in contact therewith. The first layer 31 contains an n-type impurity with a first concentration.

[0033] The second layer 32 is disposed on the first layer 31. The second layer 32 contains an n-type impurity with a second concentration smaller than the first concentration. In addition, the thickness of the second layer 32 is thicker than the thickness of the first layer 31.

[0034] The second light-emitting portion 20 includes a second n-side semiconductor layer 21 disposed on the first layer 31, a second active layer 22 disposed on the second n-side semiconductor layer 21, and a second p-side semiconductor layer 23 disposed on the second active layer 22. The second n-side semiconductor layer 21 contains an n-type impurity with a third concentration. The third concentration is smaller than the first concentration and the second concentration. A second electrode 4 is electrically connected to the second p-side semiconductor layer 23 via a conductive layer 5.

[0035] The nitride semiconductor device 100 of this embodiment can be used for either a surface-mounted nitride semiconductor device or a flip-chip-mounted nitride semiconductor device. In the case of the flip-chip mounting type, the light emitted from the first active layer 12 and the second active layer 22 is extracted from the substrate 2 side. That is, the first electrode 3 and the second electrode 4 are on the same side, and the light emitted from the first active layer 12 and the second active layer 22 can be extracted from the side where these electrodes are not provided.

[0036] Hereinafter, the nitride semiconductor device 100 will be described in detail.

[0037] <Substrate>

[0038] The material of the substrate 2 is, for example, sapphire, Si, SiC, GaN, etc. A buffer layer may be provided between the substrate 2 and the first n-side semiconductor layer 11.

[0039] <First Light-Emitting Portion>

[0040] The first light-emitting section 10 includes a first n-side semiconductor layer 11, a first active layer 12, and a first p-side semiconductor layer, with multiple semiconductor layers made of nitride semiconductors stacked. The nitride semiconductor may include all compositions in which the composition ratios x and y vary within respective ranges in the chemical formula composed of In x Al y Ga 1－x－y N (0 ≤ x ≤ 1, 0 ≤ y ≤ 1, x + y ≤ 1). In the first light-emitting section 10, the first n-side semiconductor layer 11, the first active layer 12, and the first p-side semiconductor layer 13 are arranged in sequence from the substrate 2 side.

[0041] <First n-side semiconductor layer>

[0042] The first n-side semiconductor layer 11 has a nitride semiconductor layer containing n-type impurities such as silicon (Si) and germanium (Ge). The first n-side semiconductor layer 11 includes one or more n-type nitride semiconductor layers. The first n-side semiconductor layer 11 may also partly include an undoped semiconductor layer. Here, the undoped semiconductor layer refers to a layer in which n-type impurities and / or p-side impurities are not intentionally added. The concentrations of n-type impurities and p-type impurities in the undoped semiconductor layer are, for example, below the detection limit in the analysis results of Secondary Ion Mass Spectroscopy (SIMS) or the like. For example, when the undoped semiconductor layer contains Si as an n-type impurity, the n-type impurity concentration is 1×10 16 cm －3 or less, and when it contains Ge as an n-type impurity, the n-type impurity concentration is 1×10 17 cm －3 or less. The first n-side semiconductor layer 11, for example, includes an n-type GaN layer, and the thickness of the n-type GaN layer can be set to 5 μm or more and 15 μm or less. When the n-type GaN layer contains Si as an n-type impurity, the impurity concentration of the n-type GaN layer can be set to 1×10 18 cm －3 or more and 1×10 19 cm －3 or less.

[0043] <First active layer>

[0044] The first active layer 12 is disposed between the first n-side semiconductor layer 11 and the first p-side semiconductor layer 13 and includes a light-emitting layer. The first active layer 12 is, for example, a nitride semiconductor layer that emits light with a peak emission wavelength range of 365 nm or more and 760 nm or less. The first active layer 12 has, for example, a multi-quantum well structure having a plurality of well layers and a plurality of barrier layers. When the first active layer 12 is a quantum well structure that emits light in the above wavelength range, the well layer is, for example, GaN or InGaN, and the barrier layer is, for example, AlGaN or GaN.

[0045] <First p-side semiconductor layer>

[0046] The first p-side semiconductor layer 13 is a nitride semiconductor layer containing a p-type impurity such as magnesium (Mg), for example. The first p-side semiconductor layer 13 includes one or more p-type nitride semiconductor layers. In order to form a tunnel junction with the first layer 31 described later, it is preferable that at least the layer in contact with the first layer 31 is a nitride semiconductor layer containing a p-type impurity. The nitride semiconductor constituting the p-type nitride semiconductor layer is, for example, a p-type GaN layer, and may also contain In and / or Al. The thickness of the p-type GaN layer can be set to 0.04 μm or more and 0.2 μm or less. In addition, when the p-type GaN layer contains Mg as a p-type impurity, the impurity concentration of the p-type GaN layer can be set to, for example, 1×10 19 cm －3 or more and 3×10 20 cm －3 or less. In addition, the first p-side semiconductor layer 13 may also include an undoped semiconductor layer, for example.

[0047] <First layer>

[0048] The first layer 31 is a nitride semiconductor layer containing an n-type impurity such as Si, Ge, etc. The first layer 31 is formed in contact with the first p-side semiconductor layer 13. The first layer 31 is, for example, an n-type GaN layer, and may also contain In and / or Al.

[0049] The concentration of the n-type impurity (first concentration) in the first layer 31 is greater than the concentration of the n-type impurity (second concentration) in the second layer 32 described later. In addition, the first concentration is greater than the concentration of the n-type impurity (third concentration) in the second n-side semiconductor layer 21 described later. The first concentration of the first layer 31 can be, for example, 2×10 20 cm －3 or more and 1×10 22 cm －3 or less. By setting the first concentration within such a range, the forward voltage can be reduced. The first concentration is preferably 2×10 20 cm －3 or more and 1×10 21 cm －3Hereinafter, it is more preferably 2×10 20 cm －3 or more and 5×10 20 cm －3 or less. Thereby, it is possible to reduce the deterioration of the crystallinity of the first layer 31 caused by a large impurity concentration, and to suppress the degradation of the characteristics of the nitride semiconductor device. In addition, the first concentration is, for example, 1.5 times or more and 100 times or less, preferably 1.5 times or more and 75 times or less, more preferably 2 times or more and 50 times or less of the maximum value of the second concentration described later.

[0050] <Second layer>

[0051] The second layer 32 is a nitride semiconductor layer in contact with the first layer 31 and contains an n-type impurity. As the n-type impurity, for example, Si, Ge, etc. are contained. The second layer 32 is, for example, an n-type GaN layer, and may also contain In and / or Al. In addition, the second layer 32 is also in contact with the second n-side semiconductor layer 21.

[0052] The concentration of the n-type impurity (second concentration) in the second layer 32 is less than the first concentration of the first layer 31. The second concentration is, for example, 0.09 times or more and 0.38 times or less of the first concentration. The second concentration is, for example, 0.09 times or more and 0.38 times or less of the maximum value of the first concentration. In addition, the second concentration of the second layer 32 is greater than the concentration of the n-type impurity (third concentration) in the second n-side semiconductor layer 21. The second concentration is less than the first concentration, and is, for example, 1×10 19 cm －3 or more and 2×10 20 cm －3 or less.

[0053] The first layer 31 and the second layer 32 form a pn junction with the first p-side semiconductor layer 13. Here, the pn junction formed by the first layer 31 and the second layer 32 and the first p-side semiconductor layer 13 in the present embodiment can form a so-called tunnel junction. The tunnel junction can be formed by setting at least one of the p-type impurity in the p-type semiconductor layer and the n-type impurity in the n-type semiconductor layer to a high concentration. In this tunnel junction, in order to increase the probability of electrons passing through the depletion layer, it is preferable that the width of the depletion layer formed by the pn junction of the first layer 31 and the second layer 32 and the first p-side semiconductor layer 13 is narrow. The higher at least one of the p-type impurity concentration and the n-type impurity concentration, the narrower the width of the depletion layer can be. Therefore, in the present embodiment, by increasing the n-type impurity concentration of the first layer 31 forming the tunnel junction, the width of the depletion layer of the pn junction is made narrow, and electrons can easily pass through the depletion layer.

[0054] Since the first layer 31 is an n-type nitride semiconductor layer with a very high impurity concentration, it is sometimes difficult to form the first layer 31 thick enough while maintaining crystallinity. When the first layer 31 cannot be made thick enough, the amount of n-type impurities contained in the first layer 31 is small, and the depletion layer width becomes wider. Therefore, as the layer adjacent to the first layer 31, the second layer 32 having a second concentration smaller than the first concentration is made thicker than the first layer 31, whereby it is possible to provide a supply source of electrons that may be insufficient with only the first layer 31. Since the second concentration is smaller than the first concentration, the amount of n-type impurities per unit volume contained in the second layer 32 is smaller than that in the first layer 31. By making the second layer 32 thicker than the first layer 31, the volume of the second layer 32 can be increased, and many electrons can be used for tunnel junction formation. Thereby, a tunnel junction with a narrow depletion layer width can be formed from the first layer 31, the second layer 32, and the first p-side semiconductor layer 13, and thus the forward voltage of the nitride semiconductor device can be reduced.

[0055] In addition, by making the second layer 32 thicker than the first layer 31, the effects described below are expected. It is considered that if the p-type impurities in the first p-side semiconductor layer diffuse into the second n-side semiconductor layer 21 and / or the second active layer 22, the width of the depletion layer becomes wider, and the probability of electrons passing through the depletion layer decreases. However, by providing the second layer 32 on the first layer 31, the distance between the first p-side semiconductor layer 13 and the second n-side semiconductor layer 21 and / or the second active layer 22 is increased. Thereby, the distance required for the p-type impurities contained in the first p-side semiconductor layer 13 to diffuse into the second n-side semiconductor layer 21 and / or the second active layer 22 can be increased, and the diffusion of the p-type impurities into the second n-side semiconductor layer 21 and / or the second active layer 22 can be reduced. Thereby, widening of the depletion layer width can be suppressed, and thus the probability of electrons passing through the depletion layer can be increased. Since the probability of electrons passing through the depletion layer is increased, the number of electrons contributing to light emission can be increased, and the light output can be improved.

[0056] In addition, by providing the second layer 32 having a second concentration smaller than the first concentration, the crystallinity or the surface morphology of the second layer 32 is improved as compared with the first layer 31, and the second light-emitting portion 20 can be laminated with good crystallinity.

[0057] In one embodiment of the present disclosure, the thickness of the first layer 31 is thinner than the thickness of the second layer 32. Thus, the forward voltage of the nitride semiconductor element 100 including the first light-emitting portion 10 and the second light-emitting portion 20 can be reduced. The ratio of the thickness of the second layer 32 to the thickness of the first layer 31 is, for example, 5 or more and 60 or less, preferably 5 or more and 25 or less. Thus, the forward voltage can be further reduced. The thickness of the first layer 31 is, for example, 1 nm or more and 10 nm or less, preferably 1 nm or more and 6 nm or less, more preferably 1 nm or more and 5 nm or less, and further preferably 1 nm or more and 4 nm. The thickness of the first layer 31 is particularly preferably 1 nm or more and 3 nm or less. Thus, the forward voltage can be further reduced. In addition, the thickness of the second layer 32 is, for example, 15 nm or more and 60 nm or less. The forward voltage can be further reduced. It should be noted that the thickness of the first layer 31 can be analyzed in detail, for example, by using a combination of STEM (scanning transmission electron microscopy) and EDS (energy dispersive X-ray spectroscopy).

[0058] In addition, when the thickness of the first layer 31 is 1 nm or more and 3 nm or less, the thickness of the second layer 32 is preferably 15 nm or more and 50 nm or less. The thickness of the second layer 32 is more preferably 20 nm or more and 45 nm or less. By setting the first layer 31 and the second layer 32 within these ranges, the width of the depletion layer can be narrowed, the forward voltage can be reduced, and the light output can be increased.

[0059] The sum of the thickness of the first layer 31 and the thickness of the second layer 32 is preferably 20 nm or more and 50 nm or less, and more preferably 30 nm or more and 45 nm or less. Thus, the width of the depletion layer can be narrowed, the forward voltage can be reduced, and the light output can be increased.

[0060] The thicknesses of the first layer 31 and the second layer 32 and their ratio can be estimated by quantitatively analyzing the impurity concentration using SIMS. The n-type impurity concentration of the first layer 31 is larger than that of the second layer 32, and the second layer 32 is a layer in which the n-type impurity concentration is larger than that of the second n-side semiconductor layer. Therefore, if SIMS analysis is performed, portions with relatively large n-type impurity concentrations can be observed in the order of the first layer 31, the second layer 32, and the second n-side semiconductor layer. The n-type impurity concentrations of the first layer 31 and the second layer 32 sometimes change abruptly before and after each layer, and sometimes change stepwise. In the latter case, regions with the n-type impurity concentration within a specified range can be estimated as the first layer 31 and the second layer 32. For example, the first layer 31 can be estimated as the thickness of the portion in which the n-type impurity concentration is included in the range of 2×10 20 cm －3 or more and 1×10 21 cm －3 or less, and the second layer 32 can be estimated as the thickness of the portion in which the n-type impurity concentration is included in the range of 1×10 19 cm－3 above and less than 2×10 20 cm －3 for the thickness of the portion within the range of. In addition, the p-type impurity concentration can also be quantitatively analyzed by SIMS. The p-type impurity concentration contained in the second layer 32 can be less than the p-type impurity concentration contained in the first layer 31. The p-type impurity concentration contained in the second layer 32 can be, for example, 0.005 times or more and 0.2 times or less with respect to the peak value of the p-type impurity concentration contained in the first p-side semiconductor layer 13. Specifically, the p-type impurity concentration of the second layer 32 is, for example, 1×10 18 cm －3 or more and 4×10 19 cm －3 or less.

[0061] Next, the relationship between the second layer 32 and the second n-side semiconductor layer 21 described later will be described. The second concentration of the second layer 32 is greater than the n-type impurity concentration (third concentration) of the second n-side semiconductor layer 21. Thus, similar to the first layer 31, if a current is injected into the nitride semiconductor element 100, carriers (electrons) can be supplied to the second active layer 22. Thereby, the forward voltage of the nitride semiconductor element 100 can be reduced.

[0062] <Second light-emitting portion>

[0063] The second light-emitting portion 20 includes a second n-side semiconductor layer 21, a second active layer 22, and a second p-side semiconductor layer 23, and a plurality of semiconductor layers made of a nitride semiconductor are stacked. The nitride semiconductor may include all compositions in which the composition ratios x and y vary within respective ranges in the chemical formula composed of In x Al y Ga 1－x－y N (0≤x≤1, 0≤y≤1, x + y≤1). In the semiconductor laminate, the second n-side semiconductor layer 21, the second active layer 22, and the second p-side semiconductor layer 23 are arranged in order from the substrate 2 side.

[0064] <Second n-side semiconductor layer>

[0065] The second n-side semiconductor layer 21 is in contact with the second layer 32 and the second active layer 22, and has a nitride semiconductor layer doped with an n-type impurity such as Si, Ge, etc. The second n-side semiconductor layer 21 includes one or more n-type nitride semiconductor layers. The second n-side semiconductor layer 21 may also include an undoped semiconductor layer in a part.

[0066] The concentration (third concentration) of the n-type impurities in the second n-side semiconductor layer 21 is less than the concentration (first concentration) of the n-type impurities in the first layer 31. Additionally, the third concentration of the second n-side semiconductor layer 21 is less than the concentration (second concentration) of the n-type impurities in the second layer 32. The third concentration refers to the highest concentration in the second n-side semiconductor layer. The third concentration is less than the first concentration and the second concentration, and is, for example, 1×10 18 cm －3 or more and 2×10 19 cm －3 or less. The thickness of the second n-side semiconductor layer 21 can also be estimated by SIMS analysis, similar to the first layer 31 and the second layer 32. Additionally, the concentration of the p-type impurities contained in the second n-side semiconductor layer 21 can also be estimated by SIMS analysis. The concentration of the p-type impurities contained in the second n-side semiconductor layer 21 can be less than the concentration of the p-type impurities contained in the second layer 32. The concentration of the p-type impurities contained in the second n-side semiconductor layer 21 can be, for example, 0.002 times or more and 0.045 times or less with respect to the peak value of the concentration of the p-type impurities contained in the first p-side semiconductor layer 13. Specifically, the concentration of the p-type impurities contained in the second n-side semiconductor layer 21 is, for example, 4×10 17 cm －3 or more and 9×10 18 cm －3 or less.

[0067] The thickness of the second n-side semiconductor layer 21 is thicker than that of the first layer 31. Additionally, the thickness of the second n-side semiconductor layer 21 is thicker than that of the second layer 32. The thickness of the second n-side semiconductor layer 21 is, for example, 0.03 μm to 0.2 μm.

[0068] <Second Active Layer>

[0069] The second active layer 22 is disposed between the second n-side semiconductor layer 21 and the second p-side semiconductor layer 23 and includes a light-emitting layer. The second active layer 22 is, for example, a nitride semiconductor layer that emits light having a peak emission wavelength range of 365 nm or more and 760 nm or less. The second active layer 22 has, for example, a multiple quantum well structure having a plurality of well layers and a plurality of barrier layers. In the case where the second active layer 22 is a quantum well structure that emits light in the above wavelength range, the well layer is, for example, GaN or InGaN, and the barrier layer is, for example, AlGaN or GaN.

[0070] Due to the unintentional diffusion of p-type impurities, the second active layer 22 sometimes contains p-type impurities. The concentration of p-type impurities contained in the second active layer 22 can also be estimated by SIMS analysis in the same manner as the second n-side semiconductor layer 21. The concentration of p-type impurities contained in the second active layer 22 can be, for example, 0.0015 times or more and 0.015 times or less with respect to the peak value of the concentration of p-type impurities contained in the first p-side semiconductor layer 13. Specifically, the concentration of p-type impurities contained in the second active layer 22 is, for example, 3×10 17 cm －3 or more and 3×10 18 cm －3 or less.

[0071] The emission color of the second active layer 22 can be the same as or different from the emission color of the first active layer 12. If the emission colors of the first active layer 12 and the second active layer 22 are the same, the output of the same color per unit area can be increased compared to a light-emitting element having one active layer, and thus it is preferable. For example, the nitride semiconductor element 100 according to an embodiment of the present disclosure emits blue light or green light. Here, in the present specification, blue light means a case where the peak emission wavelength is in the range of 435 nm or more and 460 nm or less. In addition, green light means a case where the peak emission wavelength is in the range of 500 nm or more and 560 nm or less.

[0072] <Second p-side semiconductor layer>

[0073] The second p-side semiconductor layer 23 has a nitride semiconductor layer containing p-type impurities such as Mg, for example. The second p-side semiconductor layer 23 includes one or more p-type nitride semiconductor layers. The nitride semiconductor constituting the p-type nitride semiconductor layer is, for example, p-type GaN, and may contain In and / or Al. The thickness of the p-type GaN layer can be set to 0.04 μm or more and 0.2 μm or less. In addition, when Mg is contained as a p-type impurity in the p-type GaN layer, the impurity concentration of the p-type GaN layer can be set to 1×10 19 cm －3 or more and 3×10 20 cm －3 or less. In addition, the second p-side semiconductor layer 23 may partially include an undoped semiconductor layer, for example.

[0074] <First electrode and second electrode>

[0075] In the present embodiment, the first electrode 3 is formed on the first n-side semiconductor layer 11. The first electrode 3 is electrically connected to the first n-side semiconductor layer 11.

[0076] In the present embodiment, the second electrode 4 is electrically connected to the second p-side semiconductor layer 23 via a conductive layer 5 formed on the second p-side semiconductor layer 23.

[0077] <Manufacturing Method>

[0078] Next, an example of the manufacturing method of the nitride semiconductor device 100 according to the present embodiment will be described. The nitride semiconductor device 100 is manufactured by MOCVD (metal organic chemical vapor deposition) method in a furnace where pressure and temperature can be adjusted. Each nitride semiconductor layer can be formed by introducing a carrier gas and a source gas into the furnace. As the carrier gas, hydrogen (H 2 ) gas or nitrogen (N 2 ) gas can be used. As the source gas for the N source, ammonia (NH 3 ) gas can be used. As the source gas for the Ga source, trimethylgallium (TMG) gas or triethylgallium (TEG) gas can be used. As the source gas for the In source, trimethylindium (TMI) gas can be used. As the source gas for the Al source, trimethylaluminum (TMA) gas can be used. As the source gas for the Si source, silane (SiH 4 ) gas can be used. As the source gas for the Mg source, bis(cyclopentadienyl)magnesium (Cp 2 Mg) gas can be used. An example of the manufacturing method described below is a method of epitaxially growing each layer by MOCVD.

[0079] <Step of Preparing a Substrate>

[0080] First, as Figure 2A shown, for example, a substrate 2 made of sapphire is prepared.

[0081] <Step of Preparing a First Light-Emitting Portion>

[0082] Next, as Figure 2B shown, a first light-emitting portion 10 is formed on the substrate 2.

[0083] First, a first n-side semiconductor layer 11 is formed on the substrate 2 for the first light-emitting portion 10. The first n-side semiconductor layer 11 is formed, for example, by sequentially growing an n-type contact layer and an n-type clad layer from the substrate 2 side. It should be noted that a buffer layer may be provided on the substrate 2 before forming the first n-side semiconductor layer 11. In addition, an undoped semiconductor layer may be provided between the buffer layer and the n-type contact layer.

[0084] Next, a first active layer 12 is formed on the first n-side semiconductor layer 11. For example, when the first active layer 12 is a multi-quantum well structure, a desired number of barrier layers and well layers are alternately formed in sequence from the substrate 2 side to form the first active layer 12. It should be noted that, in this case, the step of forming the first active layer 12 is completed by the step of forming the barrier layer.

[0085] Next, on the first active layer 12, a first p-side semiconductor layer 13 is formed, for example, by growing a p-type cladding layer.

[0086] Through such a process, a first light-emitting portion 10 having a first n-side semiconductor layer 11, a first active layer 12, and a first p-side semiconductor layer 13 is prepared on the substrate 2.

[0087] <Process of forming the first layer>

[0088] Next, as Figure 2C shown, a first layer 31 containing an n-type impurity with a first concentration is formed on the first p-side semiconductor layer 13. The first layer 31 is, for example, n-type GaN and may also contain In and / or Al. The first concentration is, for example, 2 × 10 20 cm －3 or more and 1 × 10 22 cm －3 or less, preferably 2 × 10 20 cm －3 or more and 1 × 10 21 cm －3 or less, and more preferably 2 × 10 20 cm －3 or more and 5 × 10 20 cm －3 or less.

[0089] The first layer 31 containing an n-type impurity with a first concentration can be formed by introducing a carrier gas, a source gas for forming the first layer 31, and a source gas containing an element that becomes an n-type impurity. For example, when the n-type impurity is Si, by supplying a source gas containing Si to the source gas for forming the first layer 31 at a specified flow rate, the first layer 31 containing an n-type impurity with a first concentration can be formed. At this time, for example, the first molar ratio of Si to Ga (first Si / Ga ratio) in the source gas may also be in the range of 1.1 × 10 －2 or more and 1.6 × 10 －2 or less.

[0090] The thickness of the first layer 31 is preferably formed to be thinner than the thickness of the second layer 32 and thinner than the thickness of the second n-side semiconductor layer 21. The first layer 31 is formed to have a thickness of, for example, 1 nm or more and 10 nm or less.

[0091] <Process of forming the second layer>

[0092] Next, as Figure 2D shown, a second layer 32 containing an n-type impurity with a second concentration is formed on the first layer 31. The second layer 32 is, for example, n-type GaN and may also contain In and / or Al. The second concentration is, for example, 2 × 10 19 cm－3 2×10 or less 20 cm －3 Hereinafter.

[0093] The second layer 32 containing the n-type impurity of the second concentration can be formed by introducing an element that becomes the n-type impurity into the source gas for forming the second layer 32. For example, when the n-type impurity is Si, the second layer 32 containing the n-type impurity of the second concentration can be formed by supplying a source gas containing Si to the source gas for forming the second layer 32 at a predetermined flow rate. For example, at this time, the second molar ratio (second Si / Ga ratio) of Si in the source gas to Ga is set to be smaller than the first molar ratio. The second molar ratio is less than the first molar ratio, and for example, it can also be in the range of 1.5×10 or more and 1.6×10 or less. －3 1.6×10 or more －2 Hereinafter.

[0094] The second layer 32 is preferably formed to be thinner than the thickness of the second n-side semiconductor layer 21. The second layer 32 is formed, for example, to have a thickness of 15 nm or more and 60 nm or less.

[0095] In addition, the second layer 32 is formed such that the ratio of the thickness of the second layer 32 to the thickness of the first layer 31 is, for example, 5 or more and 60 or less.

[0096] In addition, the sum of the thickness of the first layer 31 and the thickness of the second layer 32 is formed, for example, to be 20 nm or more and 50 nm or less.

[0097] It should be noted that when the thickness of the first layer 31 is formed to be 1 nm or more and 3 nm or less, the thickness of the second layer 32 is preferably formed in the range of 20 nm or more and 45 nm or less.

[0098] <Process for forming the second light-emitting portion>

[0099] Next, as Figure 2E shown, the second light-emitting portion 20 is formed on the second layer 32.

[0100] The second light-emitting portion 20 first forms the second n-side semiconductor layer 21 on the second layer 32. The second n-side semiconductor layer 21 is formed, for example, by growing an n-type contact layer and an n-type cladding layer.

[0101] The concentration (third concentration) of the n-type impurity in the second n-side semiconductor layer 21 is less than the second concentration, and for example, it is 1×10 or more and 2×10 or less. 18 cm －3 2×10 or more 19 cm －3 Hereinafter.

[0102] The second n-side semiconductor layer 21 is formed to be thicker than the first layer 31 and thicker than the second layer 32. The thickness of the second n-side semiconductor layer 21 is, for example, 0.03 μm or more and 0.2 μm or less.

[0103] Next, a second active layer 22 is formed over the second n-side semiconductor layer 21.

[0104] For example, when the second active layer 22 is a multi-quantum well structure, a desired number of barrier layers and well layers are alternately formed in sequence from the second n-side semiconductor layer 21 side to form the second active layer 22. It should be noted that, in this case, the process of forming the second active layer 22 ends with the process of forming the barrier layer.

[0105] Next, over the second active layer 22, for example, by growing a p-type cladding layer and a p-type contact layer, a second p-side semiconductor layer 23 including a p-type cladding layer and a p-type contact layer in sequence from the second active layer 22 side is formed.

[0106] Through such a process, a second light-emitting portion 20 having a second n-side semiconductor layer 21, a second active layer 22, and a second p-side semiconductor layer 23 is formed over the second layer 32.

[0107] Through the above processes, a semiconductor laminate 1a including a first light-emitting portion 10, a first layer 31, a second layer 32, and a second light-emitting portion 20 is formed over the substrate 2.

[0108] <Process of removing a part of the semiconductor laminate>

[0109] Next, as Figure 2F shown, a part of the second light-emitting portion 20, the second layer 32, the first layer 31, and the first light-emitting portion 10 is removed to expose the n-type contact layer of the first n-side semiconductor layer 11. The removal of a part of the semiconductor laminate 1a is performed by dry etching such as reactive ion etching, for example.

[0110] <Process of forming a conductive layer>

[0111] Next, as Figure 2G shown, a conductive layer 5 is formed on the upper surface of the second p-side semiconductor layer 23.

[0112] The conductive layer 5 may be formed by appropriately using a known method. The conductive layer 5 may also be formed, for example, by patterning a conductive member through a lift-off process. The conductive member can use a metal film or a transparent conductive film. The material of the metal film is, for example, Ag or Al. The material of the transparent conductive film is, for example, ITO (Indium Tin Oxide).

[0113] <Process of forming a first electrode and a second electrode>

[0114] Next, as Figure 2H shown, a first electrode 3 with a prescribed pattern is formed on the upper surface of the first n-side semiconductor layer 11, and a second electrode 4 with a prescribed pattern is formed on the upper surface of the second p-side semiconductor layer 23. Similar to the formation method of the above-mentioned conductive layer 5, the first electrode 3 and the second electrode 4 can be formed by a lift-off process or an etching process using a resist.

[0115] <Monolithic process>

[0116] Finally, the semiconductor laminate 1a is monolithically divided into nitride semiconductor elements 100 of a desired size. This monolithic division is performed along the Figure 2H prescribed monolithic division position CL shown. Laser scribing is a method in which a laser is focused inside the substrate to form a modified region, and the wafer is divided starting from the crack extended therefrom.

[0117] By the above manufacturing method, the nitride semiconductor element 100 of the present embodiment can be manufactured.

[0118] Modification

[0119] The nitride semiconductor element of the above-described embodiment includes two light-emitting portions, but may include three or more light-emitting portions. In this case, a tunnel junction is formed between the light-emitting portions, and the first layer 31 and the second layer 32 are disposed between the light-emitting portions. In addition, when the nitride semiconductor element 100 includes three or more light-emitting portions, the wavelength regions of the light emitted from the light-emitting portions may be the same in all the light-emitting portions, may be different in all the light-emitting portions, or may be the same in some of the light-emitting portions.

[0120] <Light-emitting device>

[0121] Figure 3 is a cross-sectional view of a light-emitting device including the nitride semiconductor element 100 of an embodiment of the present disclosure.

[0122] The nitride semiconductor device 100 of the above-described embodiment is flip-chip mounted on wiring electrodes or the like formed on the mounting substrate 40. The flip-chip mounting is performed by connecting the wiring electrodes formed on the mounting substrate 40 and the first electrode 3 and the second electrode 4 with the connecting members 70a and 70b. The connecting members 70a and 70b are formed by bumps or plating or the like. A wavelength conversion member 50 is provided on the substrate 2. For the wavelength conversion member 50, for example, a sintered body containing a phosphor can be used. A resin layer 60 having a reflective property is formed so as to cover the side surfaces of the nitride semiconductor device 100 and the wavelength conversion member 50. The first light emitting portion 10 and the second light emitting portion 20 are exposed to the side surface of the nitride semiconductor device 100, but as a light emitting device, the side surfaces of the first light emitting portion 10 and the second light emitting portion 20 are covered by the resin layer 60. Particles having a refractive index different from that of the resin layer 60 are contained inside the resin layer 60. As such particles, alumina or titanium oxide or the like can be used. Light from the nitride semiconductor device 100 is mainly extracted from the upper surface side of the wavelength conversion member 50 exposed from the resin layer 60. The conductive layer 5 includes a metal film such as Ag or Al and can reflect light from the nitride semiconductor device 100. At this time, at least a part of the light emitted from the first light emitting portion 10 and / or the second light emitting portion 20 toward the mounting substrate 40 side is reflected toward the wavelength conversion member 50 side through any one of the conductive layer 5, the first electrode 3, the second electrode 4, the resin layer 60, and the connecting members 70a and 70b.

[0123] (Example 1)

[0124] The nitride semiconductor device of Example 1 was fabricated as follows.

[0125] First, a substrate 2 made of sapphire was prepared, and an n-type contact layer and an n-type cladding layer were grown thereon using the MOCVD method to form a first n-side semiconductor layer 11 including an n-type contact layer and an n-type cladding layer in this order from the substrate 2 side.

[0126] Next, a first active layer 12 having a multi-quantum well structure and having a peak wavelength at 440 nm was formed on the first n-side semiconductor layer 11.

[0127] Next, a first p-side semiconductor layer 13 including a p-type cladding layer was formed on the first active layer 12 to prepare a first light emitting portion 10. Mg was introduced as a p-type impurity into the first p-side semiconductor layer 13.

[0128] Next, a first layer 31 made of GaN and having a thickness of 2 nm was formed on the first p-side semiconductor layer 13. It should be noted that the thickness referred to here is the set thickness of the grown nitride semiconductor layer. Si was introduced as an n-type impurity into the first layer 31.

[0129] Next, a second layer 32 made of GaN with a thickness of 28 nm is formed on the first layer 31. Si is introduced into the second layer 32 as an n-type impurity.

[0130] Next, on the second layer 32, by growing an n-type contact layer and an n-type cladding layer, a second n-side semiconductor layer 21 including an n-type contact layer and an n-type cladding layer in this order from the second layer 32 side is formed. The thickness of the second n-side semiconductor layer 21 is formed to be 0.08 μm.

[0131] Next, a second active layer 22 having a multi-quantum well structure and having a peak wavelength at 440 nm is formed on the second n-side semiconductor layer 21.

[0132] Next, a second p-side semiconductor layer 23 including a p-type cladding layer and a p-type contact layer is formed on the second active layer 22, and a second light-emitting portion 20 is formed.

[0133] Next, a part of the second light-emitting portion 20, the second layer 32, the first layer 31, and the first light-emitting portion 10 is removed to form a region where the n-type contact layer contained in the first n-side semiconductor layer 11 is exposed.

[0134] Next, a conductive layer 5 is formed on the second p-side semiconductor layer 23. A second electrode 4 is formed on the conductive layer 5. Further, a first electrode 3 is formed on the first n-side semiconductor layer 11.

[0135] Finally, the substrate 2 and the semiconductor laminate 1a are singulated at a desired position to fabricate a nitride semiconductor device 100.

[0136] (Example 2)

[0137] In the nitride semiconductor device 100 of Example 1, the thickness of the first layer 31 is set to 3 nm, and the thickness of the second layer 32 is set to 27 nm. Except for this, the nitride semiconductor device 100 of Example 2 is fabricated in the same manner as the nitride semiconductor device 100 of Example 1.

[0138] (Example 3)

[0139] In the nitride semiconductor device 100 of Example 1, the thickness of the first layer 31 is set to 4 nm, and the thickness of the second layer 32 is set to 26 nm. Except for this, the nitride semiconductor device 100 of Example 3 is fabricated in the same manner as the nitride semiconductor device 100 of Example 1.

[0140] (Example 4)

[0141] In the nitride semiconductor device 100 of Example 1, the thickness of the first layer 31 was set to 6 nm, and the thickness of the second layer 32 was set to 24 nm. Except for this, the nitride semiconductor device 100 of Example 4 was fabricated in the same manner as the nitride semiconductor device 100 of Example 1.

[0142] (Example 5)

[0143] In the nitride semiconductor device 100 of Example 1, the thickness of the second layer 32 was set to 18 nm. Except for this, the nitride semiconductor device 100 of Example 5 was fabricated in the same manner as the nitride semiconductor device 100 of Example 1.

[0144] (Example 6)

[0145] In the nitride semiconductor device 100 of Example 1, the thickness of the second layer 32 was set to 43 nm. Except for this, the nitride semiconductor device 100 of Example 6 was fabricated in the same manner as the nitride semiconductor device 100 of Example 1.

[0146] (Example 7)

[0147] In the nitride semiconductor device 100 of Example 1, the thickness of the first layer 31 was set to 4 nm, and the thickness of the second layer 32 was set to 56 nm. Except for this, the nitride semiconductor device 100 of Example 7 was fabricated in the same manner as the nitride semiconductor device 100 of Example 1.

[0148] (Comparative Example 1)

[0149] In the nitride semiconductor device 100 of Example 1, the first layer 31 was not provided, and the thickness of the second layer 32 was set to 30 nm. Except for this, the nitride semiconductor device 100 of Comparative Example 1 was fabricated in the same manner as the nitride semiconductor device 100 of Example 1.

[0150] <Positive voltage evaluation>

[0151] A current with a current density of 28.4 A / cm 2 was passed through the nitride semiconductor devices 100 of Examples 1 to 7 and the nitride semiconductor device 100 of Comparative Example 1, and the forward voltage Vf (V) at this time was evaluated. The results are shown in Tables 1, 2, and 3. It should be noted that the forward voltage Vf in Comparative Example 1 exceeded the measurement upper limit (10.00 V) of the device used in this measurement and could not be measured. Therefore, it is recorded as ">10" in Table 1.

[0152] <Optical output evaluation>

[0153] In addition, the nitride semiconductor elements 100 of Examples 1 to 7 were mounted on a package, and the light output (mW) was evaluated using an integrating sphere. The results are shown in Tables 1, 2, and 3.

[0154] [Table 1]

[0155]

[0156] [Table 2]

[0157]

[0158]

[0159] [Table 3]

[0160]

[0161] From the results shown in Table 1, it was confirmed that by providing the first layer 31 and the second layer 32 thicker than the first layer 31, the forward voltage of the nitride semiconductor element 100 was reduced.

[0162] In addition, from the results shown in Tables 1 and 2, it was confirmed that Examples 1, 2, 5, and 6, in which the thickness of the first layer 31 was 1 nm or more and 3 nm or less and the thickness of the second layer 32 was 15 nm or more and 50 nm or less, had a higher light output than other examples.

[0163] In addition, from the results shown in Tables 1 and 2, it was confirmed that in Examples 1 to 3 and 5 to 6, in which the ratio of the thickness of the second layer 32 to the thickness of the first layer 31 was 5 or more and 60 or less, the forward voltage was reduced compared to Example 4.

[0164] In addition, from the results shown in Table 3, it was confirmed that in Examples 1 and 6, in which the total thickness of the first layer 31 and the second layer 32 was 20 nm or more and 50 nm or less, the forward voltage of the nitride semiconductor element 100 was reduced and the light output was high compared to Example 7.

[0165] <Flatness of the surface of the second layer>

[0166] In addition, in order to clarify the improvement of the surface roughness generated on the crystal plane of the first layer 31 by making the thickness of the first layer 31 thinner than that of the second layer 32, the following two laminated body structures were fabricated, and the surface roughness of the crystal plane of the second layer 32 was measured. The surface roughness was measured using an atomic force microscope (AFM). The laminated body structure includes the first light-emitting portion 10, the first layer 31 formed on the first light-emitting portion 10, and the second layer 32 formed on the first layer 31.

[0167] (Stacked structure A)

[0168] The stacked structure A is fabricated on a substrate 2 made of sapphire. The stacked structure A is formed by the same method as that for forming the first light-emitting portion 10, the first layer 31, and the second layer 32 in Example 1. However, the thickness of the first layer 31 is 2 nm, and the thickness of the second layer 32 is 48 nm.

[0169] The surface roughness Ra of the crystal plane of the second layer 32 of the stacked structure A formed as described above is measured using AFM. As a result, the surface roughness Ra is 0.43 nm.

[0170] (Stacked structure B)

[0171] The stacked structure B is fabricated by the same method as the stacked structure A, except that the thickness of the second layer 32 is changed to 2 nm. That is, the stacked structure B is fabricated by setting the thicknesses of the first layer 31 and the second layer 32 to be the same.

[0172] The surface roughness Ra of the crystal plane of the second layer 32 of the stacked structure B formed as above is measured using AFM. As a result, the surface roughness Ra is 0.83 nm.

[0173] From the above measurement results, it can be seen that the stacked structure A in which the thickness of the first layer 31 is thinner than that of the second layer 32 can reduce the surface roughness Ra of the crystal plane of the second layer 32 compared with the stacked structure B in which the thicknesses of the second layer 32 and the first layer 31 are the same. Considering the case where the first concentration of the first layer 31 is higher than the second concentration of the second layer 32 and the surface roughness measurements of the stacked structure A and the stacked structure B, when the thickness of the second layer 32 is thicker than that of the first layer 31, there is a tendency for the surface roughness of the second layer 32 to be improved compared with the surface roughness of the first layer 31.

[0174] (SIMS analysis)

[0175] SIMS analysis is performed on a nitride semiconductor device 100 having the following structure. The nitride semiconductor device 100 for analysis has a substrate 2 made of sapphire and a plurality of nitride semiconductor layers fabricated thereon using the MOCVD method. The nitride semiconductor device 100 includes a first light-emitting portion 10 and a second light-emitting portion 20. The first light-emitting portion 10 includes a first n-side semiconductor layer 11, a first active layer 12, and a first p-side semiconductor layer 13. The second light-emitting portion 20 includes a second n-side semiconductor layer 21, a second active layer 22, and a second p-side semiconductor layer 23. A first layer 31 and a second layer 32 are provided between the first light-emitting portion 10 and the second light-emitting portion 20. Figure 4 is a chart showing the results of SIMS analysis related to the Si concentration and the Mg concentration. According to Figure 4The positions of the first layer 31, the second layer 32, and the second n-side semiconductor layer 21 are estimated from the peak positions of the Si concentration and the peak positions of the Mg concentration shown. In addition, based on the results of the SIMS analysis, multiple portions where the Si concentration changes sharply were observed. It is estimated that one of the portions near the sharp change in the Si concentration is near the boundary between the first layer 31 and the second layer 32, and the other is near the boundary between the second layer 32 and the second n-side semiconductor layer 21. In Figure 4 the ranges estimated to be the first layer 31 and the second layer 32 are shown. Boundary lines representing these ranges are set such that the portions where the Si concentration is maximum within each range are located approximately in the middle of each range. The maximum value of the Si concentration within the range estimated to be the second layer 32 shows approximately 1.1×10 20 cm －3 . In addition, it was confirmed that the maximum value of the Si concentration within the range estimated to be the first layer 31 is greater than the maximum value of the Si concentration within the range estimated to be the second layer 32. In addition, the thickness of the first layer estimated by reading the readings of the Figure 4 chart is about 5 nm to 7 nm. In addition, the thickness of the second layer estimated by reading the readings of the Figure 4 chart is about 21 nm. In addition, based on the results of the SIMS analysis, it can be confirmed that in the nitride semiconductor element 100, among the Si concentrations in the first layer 31, the second layer 32, and the second n-side semiconductor layer 21, the first layer 31 is the highest and the second n-side semiconductor layer 21 is the lowest.

[0176] As described above, the embodiments, modification examples, and examples of the present disclosure have been described. However, the disclosed content may also vary in the details of the structure, and changes in the combination or order of elements in the embodiments, modification examples, and examples can be achieved without departing from the scope and spirit of the claimed present disclosure.

[0177] Description of Reference Numerals

[0178] 1 Semiconductor structure

[0179] 1a Semiconductor laminate

[0180] 2 Substrate

[0181] 3 First electrode

[0182] 4 Second electrode

[0183] 5 Conductive layer

[0184] 10 First light-emitting portion

[0185] 11 First n-side semiconductor layer

[0186] 12 First active layer

[0187] 13 First p-side semiconductor layer

[0188] 20 Second light-emitting section

[0189] 21 Second n-side semiconductor layer

[0190] 22 Second active layer

[0191] 23 Second p-side semiconductor layer

[0192] 100 Nitride semiconductor element

Claims

1. A nitride semiconductor device comprising: a first light-emitting portion including a first n-side semiconductor layer, a first active layer provided on the first n-side semiconductor layer, and a first p-side semiconductor layer provided on the first active layer; a second light-emitting portion including a second n-side semiconductor layer provided on the first p-side semiconductor layer, a second active layer provided on the second n-side semiconductor layer, and a second p-side semiconductor layer provided on the second active layer; a first layer that is provided between the first light-emitting portion and the second light-emitting portion in contact with the first p-side semiconductor layer and contains a first concentration of n-type impurities; a second layer that is provided between the first layer and the second n-side semiconductor layer and contains a second concentration of n-type impurities, wherein the second n-side semiconductor layer contains a third concentration of n-type impurities, wherein the first concentration and the second concentration are greater than the third concentration, wherein the first concentration is greater than the second concentration, wherein the thickness of the second layer is thicker than the thickness of the first layer.

2. The nitride semiconductor device according to claim 1, wherein the ratio of the thickness of the second layer to the thickness of the first layer is 5 or more and 60 or less.

3. The nitride semiconductor device according to claim 1 or 2, wherein the thickness of the first layer is 1 nm or more and 10 nm or less.

4. The nitride semiconductor device according to any one of claims 1 to 3, wherein the thickness of the second layer is 15 nm or more and 60 nm or less.

5. The nitride semiconductor device according to any one of claims 1 to 4, wherein the sum of the thickness of the first layer and the thickness of the second layer is 20 nm or more and 50 nm or less.

6. The nitride semiconductor device according to any one of claims 1 to 5, wherein the thickness of the first layer is thinner than the thickness of the second n-side semiconductor layer, the thickness of the second layer is thinner than the thickness of the second n-side semiconductor layer.

7. The nitride semiconductor device according to any one of claims 1 to 6, wherein The first concentration is 2×10 20 cm －3 or more and 1×10 22 cm －3 or less. The second concentration is 1×10 19 cm －3 or more and 2×10 20 cm －3 or less.

8. The nitride semiconductor device according to any one of claims 1 to 7, wherein the emission color of the first active layer is the same as the emission color of the second active layer.

9. A method of manufacturing a nitride semiconductor device, comprising: a step of preparing a first light-emitting portion including a first n-side semiconductor layer, a first active layer formed on the first n-side semiconductor layer, and a first p-side semiconductor layer formed on the first active layer; a step of introducing an element that becomes an n-type impurity to form a first layer containing a first concentration of n-type impurities on the first p-side semiconductor layer; a step of introducing an element that becomes an n-type impurity to form a second layer that is thicker than the first layer and contains a second concentration of n-type impurities smaller than the first concentration on the first layer; a step of forming a second light-emitting portion including a second n-side semiconductor layer that contains a third concentration of n-type impurities smaller than the first concentration and the second concentration and is formed on the second layer, a second active layer formed on the second n-side semiconductor layer, and a second p-side semiconductor layer formed on the second active layer.

10. The method for manufacturing a nitride semiconductor device according to claim 9, wherein, The first concentration is 2×10 20 cm －3 or more and 1×10 22 cm －3 or less. The second concentration is 1×10 19 cm －3 or more and 2×10 20 cm －3 or less.

11. The method for manufacturing a nitride semiconductor device according to claim 9 or 10, wherein, the ratio of the thickness of the second layer to the thickness of the first layer is 5 or more and 60 or less.

12. The method for manufacturing a nitride semiconductor device according to any one of claims 9 to 11, wherein, in the step of forming the first layer, the first layer is formed to have a thickness of 1 nm or more and 10 nm or less.

13. The method for manufacturing a nitride semiconductor device according to any one of claims 9 to 12, wherein, in the step of forming the second layer, the second layer is formed to have a thickness of 15 nm or more and 60 nm or less.

14. The method for manufacturing a nitride semiconductor device according to any one of claims 9 to 13, wherein, the second layer is formed such that the total of the thickness of the first layer and the thickness of the second layer is 20 nm or more and 50 nm or less.

15. The method for manufacturing a nitride semiconductor device according to any one of claims 9 to 14, wherein, the thickness of the first layer is thinner than the thickness of the second n-side semiconductor layer, the thickness of the second layer is thinner than the thickness of the second n-side semiconductor layer.

Images