Circuit for generating a bias voltage for a source - free mixer

Abstract

The present disclosure provides a circuit for generating a bias voltage for a passive mixer, including: a bias module for providing a bias current; a bias voltage generation module for generating a gate bias voltage required for the PMOS transistor of the subsequent-stage passive mixer and the source-drain common-mode level of the NMOS and PMOS transistors of the subsequent-stage passive mixer under the action of the bias current; and a compensation module for compensating the bias voltage and the source-drain common-mode level, so that the RF input impedance of the subsequent-stage passive mixer during operation does not change with temperature, process, and power supply voltage; wherein, the gate bias voltage required for the NMOS transistor of the subsequent-stage passive mixer is directly provided by the power supply voltage VDD.

Description

Technical Field

[0001] The present disclosure relates to the field of analog integrated circuit technologies, and particularly to a circuit for generating a bias voltage of a passive self-mixer. Background Art

[0002] The wake-up receiver is in an always-on state with extremely low power consumption and is responsible for monitoring the channel. When the wake-up receiver does not receive a data communication request signal (i.e., the wake-up signal), the main receiver is in a sleep state. Once the wake-up signal is received, the wake-up receiver will wake up and activate the main receiver. This method can effectively reduce the power consumption of the wireless communication system. Since the wake-up receiver is in an always-on state, very strict requirements are imposed on its own power consumption, generally in the order of microwatts (μW) or nanowatts (nW). In the existing wake-up receiver architectures, the direct envelope detection architecture can meet such strict power consumption requirements. In the wake-up receiver using the direct envelope detection architecture applied in the present disclosure, the radio frequency input signal directly enters the passive self-mixer through the matching network and is down-converted to the intermediate frequency. Since power-hungry units such as the active mixer, local oscillator, and radio frequency low-noise amplifier are omitted, and the self-mixer is passive, the power consumption of the wake-up receiver using this architecture can be very low. However, currently, the bias voltage of the passive self-mixer in the wake-up receiver based on this architecture is usually provided by an external off-chip voltage source, which is not suitable for actual product applications. Or even when other methods for generating the bias voltage required by the passive self-mixer on-chip are used, there are problems such as high system complexity, high power consumption, or poor performance. Summary of the Invention

[0003] Based on the above problems, the present disclosure provides a circuit for generating a bias voltage of a passive self-mixer to alleviate the above technical problems in the prior art.

[0004] The present disclosure provides a circuit for generating a bias voltage of a passive self-mixer, including a bias module, a bias voltage generation module, and a compensation module.

[0005] The bias module is used to provide a bias current; the bias voltage generation module is used to generate the gate bias voltage required for the PMOS transistor of the subsequent passive self-mixer and the source-drain common-mode level of the NMOS transistor and PMOS transistor of the subsequent passive self-mixer under the action of the bias current; the compensation module is used to compensate the bias voltage and the source-drain common-mode level so that the radio frequency input impedance of the subsequent passive self-mixer during operation does not change with temperature, process, and power supply voltage; wherein, the gate bias voltage required for the NMOS transistor of the subsequent passive self-mixer is directly provided by the power supply voltage VDD.

[0006] According to an embodiment of the present disclosure, the bias module includes: a reference current source I R , and a second NMOS transistor M2.

[0007] Reference current source I R For providing bias current I REF wherein the bias current I REF does not change with temperature, process corner, and power supply voltage; the gate and drain of the second NMOS transistor M2 are connected together and are connected to the lower end of the on-chip reference current source I R The source of the second NMOS transistor M2 is grounded; the upper end of the reference current source I R is connected to the power supply voltage VDD.

[0008] According to an embodiment of the present disclosure, the bias voltage generation module includes: a first NMOS transistor unit, a first PMOS transistor unit, and a third NMOS transistor M3.

[0009] The first NMOS transistor unit includes a plurality of NMOS transistors connected in series, wherein the source of the previous NMOS transistor is connected to the drain of the next NMOS transistor, the drain of the first NMOS transistor is connected to the power supply voltage VDD, the source of the last NMOS transistor is connected to the first node CN1, and the gates of the plurality of NMOS transistors connected in series are commonly connected to the power supply voltage VDD; the first PMOS transistor unit includes a plurality of PMOS transistors connected in series, wherein the source of the previous PMOS transistor is connected to the drain of the next PMOS transistor, the drain of the first PMOS transistor is connected to the second node CN2 and then connected to the drain of the third NMOS transistor M3, the source of the last PMOS transistor is connected to the first node CN1, and the gates of the plurality of PMOS transistors connected in series are commonly connected to the drain of the third NMOS transistor M3; the gate of the third NMOS transistor M3 is connected to the gate of the second NMOS transistor M2, and the source of the third NMOS transistor M3 is grounded.

[0010] According to an embodiment of the present disclosure, the plurality of NMOS transistors connected in series in the first NMOS transistor unit have the same size and are equal to the size of the NMOS transistor for frequency conversion in the subsequent passive mixer; the plurality of PMOS transistors connected in series in the first PMOS transistor unit have the same size and are equal to the size of the PMOS transistor for frequency conversion in the subsequent passive mixer; the size of the third NMOS transistor M3 is the same as the size of the second NMOS transistor M2 in the bias module, but the third NMOS transistor M3 is equivalent to the parallel connection of M second NMOS transistors M2, so that the drain-source current of the third NMOS transistor M3 is M times the drain-source current of the second NMOS transistor M2, where M≥1.

[0011] According to an embodiment of the present disclosure, the compensation module includes: a first PMOS transistor M1, a first operational amplifier OP1, a second NMOS transistor unit, a fourth NMOS transistor M4, a second PMOS transistor unit, and a resistor R REF, the second operational amplifier OP2, the fifth NMOS transistor M5, and the sixth NMOS transistor M6.

[0012] The source of the first PMOS transistor M1 is connected to the power supply voltage VDD, and the drain is connected to the third node CN3; the inverting input terminal of the first operational amplifier OP1 is connected to the first node CN1, the non-inverting input terminal is connected to the third node CN3, and the output terminal is connected to the gate of the first PMOS transistor M1; the second NMOS transistor unit includes a plurality of NMOS transistors connected in series, wherein the drain of the previous NMOS transistor is connected to the source of the next NMOS transistor, the source of the first NMOS transistor is connected to the fourth node CN4, and the drain of the last NMOS transistor is connected to the third node CN3. The gates of the plurality of NMOS transistors connected in series are commonly connected to the power supply voltage VDD; the drain of the fourth NMOS transistor M4 is connected to the fourth node CN4, the gate is connected to the gate of the third NMOS transistor M3, and the source is grounded; the second PMOS transistor unit includes a plurality of PMOS transistors connected in series, wherein the source of the previous PMOS transistor is connected to the drain of the next PMOS transistor, the drain of the first PMOS transistor is connected to the fourth node CN4, and the source of the last PMOS transistor is connected to the third node CN3. The gates of the plurality of PMOS transistors connected in series are commonly connected to the second node CN2; the upper end of the resistor R REF is connected to the third node CN3; the inverting input terminal of the second operational amplifier OP2 is connected to the fourth node CN4, and the non-inverting input terminal is connected to the fifth node CN5 and then connected to the lower end of the resistor R REF ; the drain of the fifth NMOS transistor M5 is connected to the non-inverting input terminal of the second operational amplifier OP2, the source is grounded, and the gate is connected to the gate of the fourth NMOS transistor M4; the gate of the sixth NMOS transistor M6 is connected to the output terminal of the second operational amplifier OP2, the drain is connected to the second node CN2, and the source is grounded.

[0013] According to an embodiment of the present disclosure, the plurality of NMOS transistors in the second NMOS transistor unit have the same size and are equal to the size of the NMOS transistor used for frequency conversion in the subsequent passive mixer. The plurality of PMOS transistors in the second PMOS transistor unit have the same size and are equal to the size of the PMOS transistor used for frequency conversion in the subsequent passive mixer.

[0014] According to an embodiment of the present disclosure, the size of the fourth NMOS transistor M4 is the same as the size of the second NMOS transistor M2 in the bias module, but the fourth NMOS transistor M4 is equivalent to the parallel connection of N second NMOS transistors M2, so that the drain-source current of the fourth NMOS transistor M4 is N times the drain-source current of the second NMOS transistor M2, where N≥1.

[0015] According to an embodiment of the present disclosure, the size of the fifth NMOS transistor M5 is the same as that of the second NMOS transistor M2 in the bias module. However, the fifth NMOS transistor M5 is equivalent to the parallel connection of P second NMOS transistors M2, such that the drain-source current of the fifth NMOS transistor M5 is P times that of the second NMOS transistor M2, where P ≥ 1.

[0016] According to an embodiment of the present disclosure, clamping is performed by the first operational amplifier OP1 to make the potentials of the first node CN1 and the third node CN3 equal.

[0017] According to an embodiment of the present disclosure, clamping is performed by the second operational amplifier OP2 to make the potentials of the non-inverting input terminal and the inverting input terminal of the second operational amplifier OP2 equal. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a schematic circuit diagram of a typical passive self-mixer in the prior art;

[0019] Figure 2 is a schematic circuit diagram of an adjustable-gate-voltage differential passive self-mixer in the prior art;

[0020] Figure 3 is a schematic circuit diagram of a method for generating the gate terminal bias voltage V G_BN of the NMOS transistor in the passive self-mixer of the wake-up receiver in a on-chip manner; G_BP and the gate terminal bias voltage V

[0021] Figure 4 is a schematic circuit diagram of a method for generating the gate terminal bias voltage V BN of the NMOS transistor and the gate terminal bias voltage V BP of the PMOS transistor in the passive self-mixer of the wake-up receiver in a on-chip manner, and the common source-drain common-mode level V CM1 of the NMOS transistor and the PMOS transistor is generated by an on-chip bandgap reference source;

[0022] Figure 5 is a schematic circuit diagram of a method for generating the bias voltage of the passive self-mixer in an embodiment of the present disclosure in a on-chip manner. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0023] The present disclosure provides a circuit for generating the bias voltage of a passive self-mixer, specifically a circuit for generating the gate terminal bias voltage of the NMOS transistor, the gate terminal bias voltage of the PMOS transistor, and the common source-drain common-mode level of the NMOS transistor and the PMOS transistor in the passive self-mixer of the wake-up receiver. For example, this circuit can provide the gate terminal bias voltage VDD of the NMOS transistor, the gate terminal bias voltage V GP, the common source-drain common-mode level V of the NMOS transistor and the PMOS transistor CM，COPY . And the circuit includes a temperature, process corner, and power supply voltage compensation module to ensure that when the temperature changes, as well as under process differences and power supply voltage changes, the RF input impedance of the subsequent passive mixer when it is operating, determined by the generated bias voltage, remains basically unchanged, can be applicable to a large temperature range, adapt to process differences and power supply voltage changes, has strong robustness, and has extremely low power consumption (in the order of nW). At the same time, the RF input impedance of the subsequent passive mixer determined by the bias voltage generated by this invention can have a large adjustment range, which indicates that this invention can be used in the passive mixers of wake-up receivers with different requirements for various indicators.

[0024] When the passive mixer is operating normally, the MOS transistors used for frequency conversion all operate in the weak inversion region. The most important circuit element parameter of the passive mixer is the small-signal output impedance R of the MOS transistors used for frequency conversion out , for R out there is: where V ds is the drain-source voltage of the MOS transistor, I ds is the drain-source current of the MOS transistor, and V gs is the gate-source voltage of the MOS transistor. R out determines the RF input impedance, output noise power, charging time, etc. of the passive mixer. By adjusting the value of R out , the performance of the passive mixer can be effectively optimized. Since in a wake-up receiver using a direct envelope detection architecture, the passive mixer is directly connected to the matching network as the next stage of the matching network, the RF input impedance of the passive mixer directly affects the passive voltage gain of the matching network, and thus affects important indicators such as the sensitivity of the wake-up receiver. In the design of a wake-up receiver with a direct envelope detection architecture, it is extremely important to adjust the value of the small-signal output impedance R out of the MOS transistors used for frequency conversion in the passive mixer so as to adjust the RF input impedance of the passive mixer to an appropriate value.

[0025] Such as Figure 1is a circuit structure diagram of a typical passive mixer. This circuit is from: Moody, J and Bowers, SM. "Triode-mode Envelope Detectors for Near Zero Power Wake-up Receivers," IEEE MTT-S INTERNATIONAL MICROWAVE SYMPOSIUM (IMS), 2019, pp. 1499-1502. When designing this passive mixer, the small-signal output impedance R of its MOS transistors is mainly adjusted by adjusting the size of the MOS transistors and using MOS transistors with different threshold voltages out . However, this adjustment method has many drawbacks: on the one hand, it will cause the MOS transistors to have a large size, introducing a large input parasitic capacitance. This parasitic capacitance will affect the passive voltage gain of the pre-stage matching network, deteriorating the performance of the wake-up receiver; on the other hand, this adjustment method is affected by factors such as temperature and process, and the overall robustness of the circuit is poor

[0026] Such as Figure 2 is a circuit structure diagram of a tunable-gate-voltage differential passive mixer. This circuit is from: Moody, J and Bowers, SM. "Triode-mode Envelope Detectors for Near Zero Power Wake-up Receivers," IEEE MTT-S INTERNATIONAL MICROWAVE SYMPOSIUM (IMS), 2019, pp. 1499-1502. The value of the small-signal output impedance R of the MOS transistors in this tunable-gate-voltage differential passive mixer can be adjusted by changing the gate terminal bias voltage of the NMOS transistors, the gate terminal bias voltage of the PMOS transistors, and the common source-drain common-mode level of the NMOS and PMOS transistors. Compared with the typical passive mixer shown in out , the circuit shown in Figure 1 has a larger adjustment range for the value of the small-signal output impedance R of the MOS transistors; and MOS transistors with a very small size can be selected, reducing the input parasitic capacitance and the impact of the input parasitic capacitance on the passive voltage gain of the matching network; through a suitable bias voltage generation circuit, the value of the small-signal output impedance R of the MOS transistors can be made independent of temperature, process, and power supply voltage, having good robustness. In the circuit shown in Figure 2 , these three bias voltages, namely the NMOS gate bias, the PMOS gate bias, and the source-drain common-mode level, determine the small-signal output impedance R of the NMOS and PMOS transistors out . out . Figure 2 In the circuit shown, out, which directly determines the RF input impedance of the adjustable-gate-voltage differential passive self-mixer during operation, thus affecting important indicators such as the sensitivity of the wake-up receiver.

[0027] In most existing designs, these three bias voltages required for the passive self-mixer are often provided by an off-chip external voltage source. However, this method is not suitable for actual product applications. In the prior art, there are also examples of generating the bias voltages of the MOS transistors of the passive self-mixer on-chip, such as Figure 3 shown. This circuit is from: V. Mangal and P. R. Kinget, “An ultra-low-power Wake-Up Receiver with Voltage-Multiplying Self-Mixer and Interferer-Enhanced Sensitivity,” in IEEE Custom Integrated Circuits Conference (CICC), 2017, PP. 1-4. But in this example, the gate terminal bias voltage V G_BN of the NMOS transistor and the gate terminal bias voltage V G_BP generated by the circuit are both the voltages at the output terminal of the operational amplifier. This makes the generated bias voltages limited by the voltage swing at the output terminal of the operational amplifier. In some applications or under specific process or temperature conditions, it may be required that the value of V G_BN is close to the power supply voltage while the value of V G_BP is close to 0. This increases the complexity and power consumption in the design of the operational amplifier, and may cause the circuit to fail to work due to the deterioration of the DC operating point of the operational amplifier, resulting in a large difference between the RF input impedance of the subsequent-stage differential passive self-mixer and the required value, and ultimately leading to the deterioration of the performance of the wake-up receiver. And in this example, the common source-drain common-mode level V C of the NMOS transistor and the PMOS transistor needs to be provided by an off-chip external voltage source or generated by an on-chip bandgap reference voltage source, increasing the complexity and power consumption of the system.

[0028] Such as Figure 4 shown, this circuit can also be used to generate the bias voltages of the MOS transistors of the passive self-mixer on-chip. This circuit is from the patent with the patent number CN201810259599. This circuit can generate the gate terminal bias voltage V BN of the NMOS transistor of the subsequent-stage passive self-mixer, the gate terminal bias voltage V BP of the PMOS transistor, and the common source-drain common-mode level V CM1Generated by an on-chip bandgap reference source. Since the MOS transistors of the passive mixer operate in the weak inversion region, the small-signal output impedance of the NMOS transistors of the subsequent passive mixer determined by the bias voltage generated by this circuit is proportional to V t / I B , and the small-signal output impedance of the PMOS transistors is also proportional to V t / I B , and its specific value is related to the circuit process parameters. V t is the thermal voltage, V t = kT / q, where k is the Boltzmann constant, T is the thermodynamic temperature, and q is the electric charge of an electron. This indicates that the RF input impedance of the subsequent passive mixer determined by this bias voltage will vary with temperature and be affected by the circuit process. Moreover, this circuit can only adjust the small-signal output impedances of the NMOS and PMOS transistors of the subsequent passive mixer simultaneously by changing the bias current I B , and cannot adjust them separately, which will limit the performance of the subsequent passive mixer.

[0029] Therefore, the present disclosure provides a circuit for generating a bias voltage for a passive mixer to improve some technical problems existing in the prior art.

[0030] To make the purpose, technical solution, and advantages of the present disclosure clearer and more understandable, the following further details the present disclosure in conjunction with specific embodiments and with reference to the accompanying drawings.

[0031] In an embodiment of the present disclosure, a circuit for generating a bias voltage for a passive mixer is provided. As Figure 5 shown, the circuit for generating a bias voltage for a passive mixer includes:

[0032] A bias module 1 for providing a bias current I REF ;

[0033] A bias voltage generation module 2 for generating the gate terminal bias voltage V GP required for the PMOS transistors of the subsequent passive mixer under the action of the bias current, and a level (VCM, equal to V CM，COPY ) equal to the source-drain common-mode level of the NMOS and PMOS transistors of the subsequent passive mixer; and

[0034] A compensation module 3 for compensating the bias voltage V GP and the source-drain common-mode level V CM，COPY so that the RF input impedance of the subsequent passive mixer during operation does not vary with temperature, process, and supply voltage.

[0035] Among them, the gate terminal bias voltage required for the NMOS transistors of the subsequent passive mixer is directly provided by the power supply voltage VDD.

[0036] According to an embodiment of the present disclosure, the bias voltage generation module includes:

[0037] A first NMOS transistor unit, including a plurality of NMOS transistors connected in series, wherein the source of the previous NMOS transistor is connected to the drain of the next NMOS transistor, the drain of the first NMOS transistor is connected to the power supply voltage VDD, the source of the last NMOS transistor is connected to the first node CN1, and the gates of the plurality of NMOS transistors connected in series are commonly connected to the power supply voltage VDD;

[0038] A first PMOS transistor unit, including a plurality of PMOS transistors connected in series, wherein the source of the previous PMOS transistor is connected to the drain of the next PMOS transistor, the drain of the first PMOS transistor is connected to the second node CN2 and then connected to the drain of the third NMOS transistor M3, the source of the last PMOS transistor is connected to the first node CN1, and the gates of the plurality of PMOS transistors connected in series are commonly connected to the drain of the third NMOS transistor M3;

[0039] The gate of the third NMOS transistor M3 is connected to the gate of the second NMOS transistor M2, and the source of the third NMOS transistor M3 is grounded.

[0040] According to an embodiment of the present disclosure, the plurality of NMOS transistors connected in series in the first NMOS transistor unit have the same size and are equal to the size of the NMOS transistor for frequency conversion in the subsequent passive mixer; the plurality of PMOS transistors connected in series in the first PMOS transistor unit have the same size and are equal to the size of the PMOS transistor for frequency conversion in the subsequent passive mixer; the size of the third NMOS transistor M3 is the same as the size of the second NMOS transistor M2 in the bias module, but the third NMOS transistor M3 is equivalent to the parallel connection of M second NMOS transistors M2, so that the drain-source current of the third NMOS transistor M3 is M times the drain-source current of the second NMOS transistor M2, where M≥1.

[0041] According to an embodiment of the present disclosure, the compensation module includes:

[0042] A first PMOS transistor M1, with the source connected to the power supply voltage VDD and the drain connected to the third node CN3;

[0043] A first operational amplifier OP1, with the inverting input terminal connected to the first node CN1, the non-inverting input terminal connected to the third node CN3, and the output terminal connected to the gate of the first PMOS transistor M1;

[0044] The second NMOS transistor unit includes a plurality of NMOS transistors connected in series, wherein the drain of the previous NMOS transistor is connected to the source of the next NMOS transistor, the source of the first NMOS transistor is connected to the fourth node CN4, and the drain of the last NMOS transistor is connected to the third node CN3. The gates of the plurality of NMOS transistors connected in series are commonly connected to the power supply voltage VDD;

[0045] The fourth NMOS transistor M4 has its drain connected to the fourth node CN4, its gate connected to the gate of the third NMOS transistor M3, and its source grounded;

[0046] The second PMOS transistor unit includes a plurality of PMOS transistors connected in series, wherein the source of the previous PMOS transistor is connected to the drain of the next PMOS transistor, the drain of the first PMOS transistor is connected to the fourth node CN4, and the source of the last PMOS transistor is connected to the third node CN3. The gates of the plurality of PMOS transistors connected in series are commonly connected to the second node CN2;

[0047] Resistor R REF whose upper end is connected to the third node CN3;

[0048] The second operational amplifier OP2 has its inverting input terminal connected to the fourth node CN4, its non-inverting input terminal connected to the fifth node CN5 and also connected to the lower end of the resistor R REF ;

[0049] The fifth NMOS transistor M5 has its drain connected to the non-inverting input terminal of the second operational amplifier OP2, its source grounded, and its gate connected to the gate of the fourth NMOS transistor M4; and

[0050] The sixth NMOS transistor M6 has its gate connected to the output terminal of the second operational amplifier OP2, its drain connected to the second node CN2, and its source grounded.

[0051] According to an embodiment of the present disclosure, the plurality of NMOS transistors in the second NMOS transistor unit have the same size and are equal to the size of the NMOS transistor used for frequency conversion in the subsequent passive mixer. The plurality of PMOS transistors in the second PMOS transistor unit have the same size and are equal to the size of the PMOS transistor used for frequency conversion in the subsequent passive mixer.

[0052] According to an embodiment of the present disclosure, the fourth NMOS transistor M4 has the same size as the second NMOS transistor M2 in the bias module, but the fourth NMOS transistor M4 is equivalent to the parallel connection of N second NMOS transistors M2, such that the drain-source current of the fourth NMOS transistor M4 is N times the drain-source current of the second NMOS transistor M2, where N≥1.

[0053] According to an embodiment of the present disclosure, the size of the fifth NMOS transistor M5 is the same as that of the second NMOS transistor M2 in the bias module, but the fifth NMOS transistor M5 is equivalent to the parallel connection of P second NMOS transistors M2, so that the drain-source current of the fifth NMOS transistor M5 is P times that of the second NMOS transistor M2, where P≥1.

[0054] According to an embodiment of the present disclosure, clamping is performed by the first operational amplifier OP1 so that the potentials of the first node CN1 and the third node CN3 are equal. Clamping is performed by the second operational amplifier OP2 so that the potentials of the non-inverting input terminal and the inverting input terminal of the second operational amplifier OP2 are equal.

[0055] As Figure 5 shown, the bias module 1 is used to provide a bias current for the bias voltage generation module 2 and the compensation module 3. The unit bias current is I REF , which is given by an on-chip ultra-low power consumption (nW level) reference current source I R , and I REF does not change with temperature, process corner, and power supply voltage. The bias voltage generation module 2 is used to generate the gate terminal bias voltage V GP of the PMOS transistor required by the subsequent passive mixer, and the source-drain common-mode level V CM，COPY equal to that of the NMOS transistor and the PMOS transistor of the subsequent passive mixer, and the level V CM . The gate terminal bias voltage of the NMOS transistor required by the subsequent passive mixer is directly provided by the power supply voltage VDD. The compensation module 3 is used to perform temperature, process corner, and power supply voltage compensation on the small-signal output impedance of the NMOS transistor and the PMOS transistor of the subsequent passive mixer determined by the bias voltage generated by the bias voltage generation module 2. If the compensation module 3 is not used for compensation, the radio frequency input impedance of the subsequent passive mixer during operation will change significantly with temperature and process corner and will be affected by the power supply voltage, which will seriously affect the performance of the wake-up receiver. When the bias voltage generation module 2 and the compensation module 3 cooperate, the radio frequency input impedance of the subsequent passive mixer during operation can be made not to change with temperature, process corner, and power supply voltage, so that the overall circuit has strong robustness.

[0056] As Figure 5 shown, the compensation module 3 includes a first operational amplifier OP1, whose non-inverting input terminal and inverting input terminal are respectively connected to the first node CN1 (the potential is equal to V CM ) and the third node CN3 (the potential is equal to V CM，COPY ), and the first operational amplifier OP1 is used for clamping to make the potentials of the first node and the third node equal; it also includes a second operational amplifier OP2, whose non-inverting input terminal and inverting input terminal are respectively connected to the fifth node CN5 (the potential is equal to V+ ) and the fourth node CN4 (the potential is equal to V - ), the second operational amplifier OP2 described above is used for clamping to make V + and V - have equal potentials.

[0057] In the bias module 1, the gate and drain of the second NMOS transistor M2 are connected together and connected to the lower end of the reference current source I R , the source of the second NMOS transistor M2 is grounded, and the upper end of the reference current source I R is connected to the power supply voltage VDD. The drain-source current of the second NMOS transistor M2 is I REF . The gate terminal bias voltage required for the subsequent passive mixer is directly provided by the power supply voltage VDD.

[0058] In the bias voltage generation module 2 described above, the first NMOS transistor unit includes N2 NMOS transistors, N2≥1, and the first PMOS transistor unit includes P2 PMOS transistors, P2≥1. Among them, the drain of the NMOS transistor M N2，1 is connected to the power supply voltage, the source is connected to the drain of the NMOS transistor M N2，2 , the source of the NMOS transistor M N2，2 is connected to the drain of the NMOS transistor M N2，3 , and so on. The source of the NMOS transistor M N2，N2-1 is connected to the drain of the NMOS transistor M N2，N2 , the gates of the NMOS transistors M N2，1 , M N2，2 ......M N2，N2 are connected together, and then their gates are connected to the power supply voltage VDD. Denote the source level of the NMOS transistor M N2，N2 as V CM . The source of the third NMOS transistor M3 is grounded, the gate is connected to the gate of the second NMOS transistor M2 in the bias module 1, and the drain is connected to the drain of the PMOS transistor M P2，1 . The drain of the PMOS transistor M P2，1 is connected to the drain of the third NMOS transistor M3, the source of the PMOS transistor M P2，1 is connected to the drain of the PMOS transistor M P2，2 , the source of the PMOS transistor M P2，2 is connected to the drain of the PMOS transistor M P2，3 , and so on. The source of the PMOS transistor M P2，P2-1 is connected to the drain of the PMOS transistor M P2，P2 , the gates of the PMOS transistors M P2，1 , M P2，2 ......M P2，P2 are connected together, and then their gates are connected to the gate of the PMOS transistor M P2，1The drain of, denote the PMOS transistor M P2，1 The drain level of is V GP , the NMOS transistor M N2，N2 The source of is connected to the source of the PMOS transistor M P2，P2 .

[0059] In the bias voltage generation module 2, the N2 NMOS transistors M in the first NMOS transistor unit N2，1 , M N2，2 ......M N2，N2 Have the same size, and are equal to the size of the NMOS transistor used for frequency conversion in the subsequent passive mixer. The P2 PMOS transistors M in the first PMOS transistor unit P2，1 , M P2，2 ......M P2，P2 Have the same size, and are equal to the size of the PMOS transistor used for frequency conversion in the subsequent passive mixer. The size of the third NMOS transistor M3 is the same as that of the second NMOS transistor M2 in the bias module 1, but the third NMOS transistor M3 is equivalent to the parallel connection of M second NMOS transistors M2, so the drain-source current of the third NMOS transistor M3 is M times that of the second NMOS transistor M2, that is, M×I REF .

[0060] The principle of the bias voltage generation module 2 is as follows: Denote n as the subthreshold slope coefficient of the MOS transistor. The typical value of n is between 1.2 and 1.5, and the value of n is related to both process parameters and the bias voltage of the MOS transistor. When not considering the effect of the compensation module 3, and VDD - V CM > 100mV, V CM -V GP > 100mV, and the value of n is close to 1, the bias voltages generated by the bias voltage generation module 2 (the gate bias voltage VDD of the NMOS transistor, the gate bias voltage V GP , the common source-drain common-mode level V of the NMOS transistor and the PMOS transistor CM ) determine the small-signal output impedance of the NMOS transistor in the subsequent passive mixer ≈ (λ·V t ) / (N2·M·I REF ), the small-signal output impedance of the PMOS transistor ≈ (β·V t ) / (P2·M·I REF ), where V t is the thermal voltage, and λ and β are process correction coefficients respectively, which are related to process parameters. By adjusting the values of N2, P2, M, and I REF , the small-signal output impedances of the NMOS transistor and the PMOS transistor in the subsequent passive mixer can be adjusted, and then the radio frequency input impedance during the operation of the subsequent passive mixer can be adjusted to the required value at a certain temperature.

[0061] In the compensation module 3 described above, the second NMOS transistor unit includes N3 NMOS transistors, where N3 ≥ 1, and the second PMOS transistor unit includes P3 PMOS transistors, where P3 ≥ 1. Among them, the source of the first PMOS transistor M1 is connected to the power supply voltage, the gate is connected to the output terminal of the first operational amplifier OP1, and the drain is connected to the non-inverting input terminal of OP1. Denote the drain level of the first PMOS transistor M1 as V CM，COPY . The inverting input terminal of the first operational amplifier OP1 is connected to the source of the NMOS transistor M N2，N2 in the bias voltage generation module 2. The source of the fourth NMOS transistor M4 is grounded, the gate is connected to the gate of the third NMOS transistor M3 in the bias voltage generation module 2, and the drain is connected to the source of the NMOS transistor M N3，1 . The source of the NMOS transistor M N3，1 is connected to the drain of the fourth NMOS transistor M4, and the drain is connected to the source of the NMOS transistor M N3，2 . The drain of the NMOS transistor M N3，2 is connected to the source of the NMOS transistor M N3，3 , and so on. The drain of the NMOS transistor M N3，N3-1 is connected to the source of the NMOS transistor M N3，N3 . The drain of the NMOS transistor M N3，N3 is connected to the drain of the first PMOS transistor M1. The gates of the NMOS transistors M N3，1 , M N3，2 ......M N3，N3 are connected together and then their gates are connected to the power supply voltage. The drain of the PMOS transistor M P3，1 is connected to the source of the NMOS transistor M N3，1 . The source of the PMOS transistor M P3，1 is connected to the drain of the PMOS transistor M P3，2 . The source of the PMOS transistor M P3，2 is connected to the drain of the PMOS transistor M P3，3 , and so on. The source of the PMOS transistor M P3，P3-1 is connected to the drain of the PMOS transistor M P3，P3 . The gates of the PMOS transistors M P3，1 , M P3，2 ......M P3，P3 are connected together and then connected to the gate of the PMOS transistor M P2，1 in the bias voltage generation module 2. The source of the PMOS transistor M P3，P3 is connected to the drain of the NMOS transistor M N3，N3 . The source of the fifth NMOS transistor M5 is grounded, the gate is connected to the gate of the fourth NMOS transistor M4, and the drain is connected to the lower end of the resistor R REF . The upper end of the resistor R REF is connected to the PMOS transistor MP3，P3 The source connection of. The non-inverting input terminal of the second operational amplifier OP2 is connected to the drain of the fifth NMOS transistor M5, and the inverting input terminal is connected to the PMOS transistor M P3，1 The drain connection of. The output terminal is connected to the gate of the NMOS transistor M6. Denote the level of the non-inverting input terminal of the second operational amplifier OP2 as V + , and the level of the inverting input terminal as V-. The source of the NMOS transistor M6 is grounded, and the drain is connected to the gate of the PMOS transistor M P3，1 .

[0062] In the compensation module 3 described above, the N3 NMOS transistors M N3，1 , M N3，2 ......M N3，N3 have the same size, and are equal to the size of the NMOS transistor used for frequency conversion in the subsequent passive mixer. The P3 PMOS transistors M P3，1 , M P3，2 ......M P3，P3 have the same size, and are equal to the size of the PMOS transistor used for frequency conversion in the subsequent passive mixer. The size of the fourth NMOS transistor M4 is the same as that of the second NMOS transistor M2 in the bias module 1, but the fourth NMOS transistor M4 is equivalent to the parallel connection of N second NMOS transistors M2. Therefore, the drain-source current of the fourth NMOS transistor M4 is N times that of the second NMOS transistor M2, that is, N×I REF . The size of the fifth NMOS transistor M5 is the same as that of the second NMOS transistor M2 in the bias module 1, but the fifth NMOS transistor M5 is equivalent to the parallel connection of P second NMOS transistors M2. Therefore, the drain-source current of the fifth NMOS transistor M5 is P times that of the second NMOS transistor M2, that is, P×I REF .

[0063] The working principle of the compensation module 3 is as follows: Due to the virtual short characteristic of the first operational amplifier OP1, V CM = V CM，COPY ; Due to the virtual short characteristic of the second operational amplifier OP2, V + = V - . R REF is a near-zero temperature drift resistor, and its resistance value hardly changes with temperature, process, etc. At this time, the voltage drop across the resistor R REF is equal to the drain-source voltage drop across the N3 NMOS transistors M N3，1 , M N3，2 ......M N3，N3 , and is also equal to the source-drain voltage drop across the P3 PMOS transistors M P3，1 , M P3，2 ......M P3，P3 , and is equal to V CM，COPY - V + . Adjust the resistor RREF The resistance value is related to the current flowing through resistor R REF The current value P×I REF V can be adjusted CM，COPY -V + When the wake-up receiver is working properly, the source-drain voltage drop of the NMOS and PMOS transistors used for frequency conversion in the subsequent passive mixer is extremely small. At this time, its small-signal output impedance is approximately equal to its DC on-resistance. Assume that the absolute values of the drain-source voltages of the NMOS and PMOS transistors used for frequency conversion in the subsequent passive mixer are V dsn and V dsp . Then N3 = (V CM，COPY -V + ) / V dsn = P×I REF ×R REF / V dsn . Similarly, P3 = (V CM，COPY -V + ) / V dsp = P×I REF ×R REF / V dsp . At this time, the operating points of NMOS transistors M N3，1 , M N3，2 ......M N3，N3 and PMOS transistors M P3，1 , M P3，2 ......M P3，P3 are respectively equivalent to the operating points of the NMOS and PMOS transistors used for frequency conversion in the subsequent passive mixer. Therefore, changing the small-signal output impedance of NMOS transistors M N3，1 , M N3，2 ......M N3，N3 and PMOS transistors M P3，1 , M P3，2 ......M P3，P3 is equivalent to changing the small-signal output impedance of the NMOS and PMOS transistors used for frequency conversion in the subsequent passive mixer, and thus changing the RF input impedance of the subsequent passive mixer. The impedance obtained by paralleling the sum of the small-signal output impedances of NMOS transistors M N3，1 , M N3，2 ......M N3，N3 with the sum of the small-signal output impedances of PMOS transistors M P3，1 , M P3，2 ......M P3，P3 is P×R REF / N. When the bias voltage generation module 2 and the compensation module 3 work together, the small-signal output impedance of the NMOS transistor used for frequency conversion in the subsequent passive mixer is: (2·V dsn ) / (N·I REF) The small-signal output impedance of the PMOS transistor is: (2·V dsp ) / (N·I REF ). The second operational amplifier OP2 regulates the gate level of the NMOS transistor M6 to regulate the current flowing through the N2 NMOS transistors M N2，1 、M N2，2 ......M N2，N2 and the P2 PMOS transistors M P2，1 、M P2，2 ......M P2，P2 to regulate the values of V CM and V GP . Furthermore, the small-signal output impedance of the NMOS transistor used for frequency conversion in the subsequent passive mixer is: (2·V dsn ) / (N·I REF ), and the small-signal output impedance of the PMOS transistor is: (2·V dsp ) / (N·I REF ). Since the values of V dsn and V dsp are determined by the design specifications of the wake-up receiver and the subsequent passive mixer, according to the requirements of the wake-up receiver's design specifications, by adjusting the values of I REF and N, the optimal small-signal output impedance of the NMOS and PMOS transistors in the subsequent passive mixer can be obtained, and then the optimal RF input impedance of the subsequent passive mixer can be obtained. And since I REF and N do not change with temperature, process, and power supply voltage, the compensation module 3 makes the RF input impedance of the subsequent passive mixer also not change with temperature, process, and power supply voltage, indicating that the circuit has strong robustness.

[0064] According to the embodiments of the present disclosure, the specific values of M, N, P, N2, P2, N3, P3, VDD, I REF 、R REF involved above can all be flexibly selected according to the requirements of the wake-up receiver's design specifications, and the present disclosure is not limited thereto.

[0065] According to the embodiments of the present disclosure, if only NMOS transistors or only PMOS transistors are used for the MOS transistors for frequency conversion in the subsequent passive mixer, the circuit of the present disclosure can still provide a bias voltage for the passive mixer.

[0066] As can be seen from the above, the advantages and positive effects of the technical solution of the present disclosure compared with the prior art include the following:

[0067] 1. The present disclosure enables the three bias voltages required for a passive mixer in a wake-up receiver (specifically: the gate bias voltage of the NMOS transistor, the gate bias voltage of the PMOS transistor, and the common source-drain common-mode level of the NMOS and PMOS transistors) to be generated in an on-chip manner, without the need to use an off-chip external voltage source to provide them.

[0068] 2. The present disclosure not only generates the three bias voltages required for the passive mixer (specifically: the gate bias voltage VDD of the NMOS transistor, the gate bias voltage V GP of the PMOS transistor, and the common source-drain common-mode level V CM，COPY of the NMOS and PMOS transistors) on-chip, but also designs a compensation module 3. Under the collaborative action of the bias voltage generation module 2 and the compensation module 3, the radio frequency input impedance of the subsequent-stage passive mixer determined by the bias voltages generated by the present disclosure does not change with temperature, process, and power supply voltage during operation, and the overall circuit has strong robustness.

[0069] 3. The present disclosure supports operation at low power supply voltages and extremely low power consumption, and can achieve a power consumption in the nW range, which is of great significance in the design of extremely low-power wake-up receivers.

[0070] 4. The present disclosure has obvious advantages compared with the prior art.

[0071] More specifically, the present disclosure has obvious advantages compared with the prior art shown in Figure 3 :

[0072] (1) In the present disclosure, the output levels of the two operational amplifiers are relatively moderate, and the requirements for the design of the operational amplifiers are relatively low. A low-power operational amplifier with a simple structure can be used to save circuit power consumption. In the prior art shown in Figure 3 , the gate bias voltage V G_BN of the NMOS transistor and the gate bias voltage V G_BP of the PMOS transistor generated by the circuit are both the voltages at the output terminals of the operational amplifiers, which limits the generated bias voltages by the voltage swing at the output terminals of the operational amplifiers. In some applications or under specific process or temperature conditions, it may be required that the value of V G_BN is close to the power supply voltage while the value of V G_BP is close to 0, which increases the complexity and power consumption in the design of the operational amplifier, and may cause the circuit to fail to work due to the deterioration of the DC operating point of the operational amplifier, resulting in a large difference between the equivalent radio frequency input impedance of the subsequent-stage differential passive mixer and the required value, and ultimately deteriorating the performance of the wake-up receiver.

[0073] (2) In the present disclosure, the gate bias voltage of the NMOS transistor in the post-stage passive mixer is the power supply voltage VDD, the gate bias voltage of the PMOS transistor can be as low as close to 0 at minimum, and the common source-drain common-mode level V CM，COPY of the NMOS and PMOS transistors has a variation range of approximately V n to VDD - |V p | (the voltage drop across the resistor R REF is very small and can be ignored), where V n is the minimum drain-source voltage required for the fourth NMOS transistor M4 to operate in the saturation state, and V p is the absolute minimum drain-source voltage required for the first PMOS transistor M1 to operate in the saturation state. This enables the radio frequency input impedance of the post-stage passive mixer determined by the bias voltage generated by the present disclosure to have a large adjustment range, indicating that compared with the Figure 3 shown prior art, it can be applied to the passive mixers of wake-up receivers with different requirements for various indicators.

[0074] (3) In the Figure 3 shown technology, the common source-drain common-mode level V C of the NMOS and PMOS transistors in the post-stage passive mixer is provided by an external off-chip voltage source or generated by an on-chip bandgap reference voltage source, which increases the circuit complexity and power consumption. In the present disclosure, the common source-drain common-mode level V CM，COPY of the NMOS and PMOS transistors in the post-stage passive mixer does not require an external off-chip addition, nor does it require other circuit modules to provide.

[0075] In summary, compared with the Figure 3 shown prior art, the bias voltage generated by the present disclosure has a larger adjustment range, wider applicability, stronger robustness, higher yield, and lower power consumption for the radio frequency input impedance of the post-stage passive mixer.

[0076] The present disclosure has obvious advantages compared with the Figure 4 shown prior art:

[0077] (1) The Figure 4 shown circuit can also generate the gate terminal bias voltage V BN of the NMOS transistor and the gate terminal bias voltage V BP of the PMOS transistor in the post-stage passive mixer on-chip, and the common source-drain common-mode level V CM1 of the NMOS and PMOS transistors is generated by an on-chip bandgap reference source. Since the MOS transistors in the passive mixer operate in the weak inversion state, the small-signal output impedance of the NMOS transistor in the post-stage passive mixer determined by the bias voltage generated by this circuit is proportional to V t / I B , and the small-signal output impedance of the PMOS transistor is also proportional to Vt / I B , and its specific value is related to circuit process parameters. V t is the thermal voltage, V t = kT / q, where k is the Boltzmann constant, T is the thermodynamic temperature, and q is the electric charge of an electron. This indicates that the RF input impedance of the subsequent passive sub-harmonic mixer determined by this bias voltage does not have temperature stability and is affected by the circuit process. However, the RF input impedance of the subsequent passive sub-harmonic mixer determined by the bias voltage generated by the present disclosure does not change with temperature and process.

[0078] (2) Figure 4 The circuit shown can only adjust the small-signal output impedances of the NMOS and PMOS transistors of the subsequent passive sub-harmonic mixer by changing I B , and cannot adjust them separately, which limits the performance of the subsequent passive sub-harmonic mixer. In the present disclosure, when adjusting the compensation module 3 to adjust the small-signal output impedance of the MOS transistor of the subsequent passive sub-harmonic mixer, the small-signal output impedances of the NMOS and PMOS transistors can be separately adjusted by adjusting the values of N2 and P2 in the bias voltage generation module 2.

[0079] So far, the embodiments of the present disclosure have been described in detail with reference to the accompanying drawings. It should be noted that, in the accompanying drawings or the text of the specification, the implementation manners not illustrated or described are all forms known to those of ordinary skill in the art, and no detailed description is given. In addition, the definitions of the above-mentioned various elements and methods are not limited to the specific structures, shapes or manners mentioned in the embodiments, and those of ordinary skill in the art can make simple changes or substitutions thereto.

[0080] Based on the above description, those skilled in the art should have a clear understanding of the circuit for generating the bias voltage of the passive sub-harmonic mixer of the present disclosure.

[0081] In summary, the present disclosure provides a circuit for generating the bias voltage of a passive sub-harmonic mixer. This circuit can provide the gate bias voltage VDD of the NMOS transistor, the gate bias voltage V GP , and the common source-drain common-mode level V CM，COPY of the NMOS and PMOS transistors on-chip for the passive sub-harmonic mixer. And this circuit includes a temperature, process corner, and power supply voltage compensation module to ensure that the RF input impedance of the subsequent passive sub-harmonic mixer during operation remains basically unchanged when the temperature changes, under different process conditions, and at different power supply voltages, which makes the overall circuit have strong robustness. Since the gate bias voltage of the NMOS transistor of the subsequent passive sub-harmonic mixer provided by this circuit is the power supply voltage VDD, and the gate bias voltage of the PMOS transistor is V GPThe lowest can approach 0, and the common source-drain common-mode level V of the NMOS transistor and the PMOS transistor CM，COPY has a change range of approximately V n ~VDD - |V p | (the voltage drop across the resistor R REF is very small and can be ignored), where V n is the minimum drain-source voltage required for the fourth NMOS transistor M4 to operate in the saturation state, and V p is the absolute minimum drain-source voltage required for the first PMOS transistor M1 to operate in the saturation state. This enables the radio frequency input impedance of the subsequent passive mixer to have a large adjustment range, indicating that this circuit can be applied to the passive mixers of wake-up receivers with different requirements for various indicators. This circuit is applicable to a large temperature range, can adapt to process and power supply voltage differences, and has the advantage of extremely low power consumption (in the order of nW).

[0082] It should also be noted that the above are different embodiments provided by the present disclosure. These embodiments are used to illustrate the technical content of the present disclosure, rather than to limit the scope of the claimed protection of the present disclosure. A feature of one embodiment can be applied to other embodiments through appropriate modification, replacement, combination, and separation.

[0083] It should be noted that, in this article, unless otherwise specified, having an element "a" does not limit to having only one such element, but may have one or more such elements.

[0084] In addition, in this article, unless otherwise specified, ordinal numbers such as "first", "second", etc. are only used to distinguish multiple elements with the same name, and do not indicate a rank, level, execution order, or process order between them. A "first" element and a "second" element may appear in the same component together, or in different components separately. The existence of an element with a larger ordinal number does not necessarily imply the existence of another element with a smaller ordinal number.

[0085] In this article, unless otherwise specified, the so-called feature A "or" (or) or "and / or" (and / or) feature B means that A exists alone, B exists alone, or A and B exist simultaneously; the so-called feature A "and" (and) or "and" (and) or "and" (and) feature B means that A and B exist simultaneously; the so-called "comprising", "including", "having", "containing" means including but not limited to this.

[0086] In addition, in this document, terms such as "upper", "lower", "left", "right", "front", "rear", or "between" are only used to describe the relative positions between multiple components, and in the interpretation, it can be extended to include cases of translation, rotation, or mirroring. In addition, in this document, unless specifically specified, the statement that "one component is on another component" or a similar statement does not necessarily mean that the component contacts the other component.

[0087] In addition, unless specifically described or steps that must occur in sequence, the order of the above steps is not limited to those listed above and can be changed or rearranged according to the required design. And the above embodiments can be used in combination with each other or combined with other embodiments based on considerations of design and reliability, that is, the technical features in different embodiments can be freely combined to form more embodiments.

[0088] The specific embodiments described above further elaborate on the purpose, technical solutions, and beneficial effects of the present disclosure. It should be understood that the above are only specific embodiments of the present disclosure and are not used to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present disclosure shall be included within the protection scope of the present disclosure.

Claims

1. A circuit for generating a bias voltage for a passive mixer, comprising: A bias module for providing a bias current; A bias voltage generation module for generating a gate bias voltage required for the PMOS transistor of the subsequent passive mixer and the source-drain common-mode level of the NMOS and PMOS transistors of the subsequent passive mixer under the action of the bias current; And A compensation module for compensating the bias voltage and the source-drain common-mode level so that the RF input impedance of the subsequent passive mixer during operation does not change with temperature, process, and power supply voltage; Wherein, the gate bias voltage required for the NMOS transistor of the subsequent passive mixer is directly provided by the power supply voltage VDD; The bias module includes a reference current source I R and a second NMOS transistor M2; wherein the reference current source I R is used to provide a bias current I REF , and the bias current I REF does not change with temperature, process corner, and power supply voltage; for the second NMOS transistor M2, its gate and drain are connected together and are connected to the lower end of the reference current source I R , and the source of the second NMOS transistor M2 is grounded; the upper end of the reference current source I R is connected to the power supply voltage VDD; The bias voltage generation module includes a first NMOS transistor unit and a first PMOS transistor unit; the first NMOS transistor unit includes a plurality of NMOS transistors connected in series, wherein the source of the previous NMOS transistor is connected to the drain of the next NMOS transistor, the drain of the first NMOS transistor is connected to the power supply voltage VDD, the source of the last NMOS transistor is connected to the first node CN1, and the gates of the plurality of series-connected NMOS transistors are commonly connected to the power supply voltage VDD; the first PMOS transistor unit includes a plurality of PMOS transistors connected in series, wherein the source of the previous PMOS transistor is connected to the drain of the next PMOS transistor, the drain of the first PMOS transistor is connected to the second node CN2 and then connected to the drain of the third NMOS transistor M3, the source of the last PMOS transistor is connected to the first node CN1, and the gates of the plurality of series-connected PMOS transistors are commonly connected to the drain of the third NMOS transistor M3; the gate of the third NMOS transistor M3 is connected to the gate of the second NMOS transistor M2, and the source of the third NMOS transistor M3 is grounded; The compensation module includes: a first PMOS transistor M1, a first operational amplifier OP1, a second NMOS transistor unit, a fourth NMOS transistor M4, a second PMOS transistor unit, and a resistor R REF , a second operational amplifier OP2, a fifth NMOS transistor M5, and a sixth NMOS transistor M6; wherein, the source of the first PMOS transistor M1 is connected to the power supply voltage VDD, and the drain is connected to the third node CN3; the inverting input terminal of the first operational amplifier OP1 is connected to the first node CN1, the non-inverting input terminal is connected to the third node CN3, and the output terminal is connected to the gate of the first PMOS transistor M1; the second NMOS transistor unit includes a plurality of serially connected NMOS transistors, wherein the drain of the previous NMOS transistor is connected to the source of the next NMOS transistor, the source of the first NMOS transistor is connected to the fourth node CN4, and the drain of the last NMOS transistor is connected to the third node CN3, and the gates of the plurality of serially connected NMOS transistors are commonly connected to the power supply voltage VDD; the drain of the fourth NMOS transistor M4 is connected to the fourth node CN4, the gate is connected to the gate of the third NMOS transistor M3, and the source is grounded; the second PMOS transistor unit includes a plurality of serially connected PMOS transistors, wherein the source of the previous PMOS transistor is connected to the drain of the next PMOS transistor, the drain of the first PMOS transistor is connected to the fourth node CN4, and the source of the last PMOS transistor is connected to the third node CN3, and the gates of the plurality of serially connected PMOS transistors are commonly connected to the second node CN2; the upper end of the resistor R REF is connected to the third node CN3; the inverting input terminal of the second operational amplifier OP2 is connected to the fourth node CN4, and the non-inverting input terminal is connected to the fifth node CN5 and then connected to the lower end of the resistor R REF ; the drain of the fifth NMOS transistor M5 is connected to the non-inverting input terminal of the second operational amplifier OP2, the source is grounded, and the gate is connected to the gate of the fourth NMOS transistor M4; the gate of the sixth NMOS transistor M6 is connected to the output terminal of the second operational amplifier OP2, the drain is connected to the second node CN2, and the source is grounded.

2. The circuit for generating a bias voltage for a passive mixer according to claim 1, wherein the plurality of series-connected NMOS transistors in the first NMOS transistor unit have the same size and are equal to the size of the NMOS transistor for frequency conversion in the subsequent passive mixer; the plurality of series-connected PMOS transistors in the first PMOS transistor unit have the same size and are equal to the size of the PMOS transistor for frequency conversion in the subsequent passive mixer; the size of the third NMOS transistor M3 is the same as the size of the second NMOS transistor M2 in the bias module, but the third NMOS transistor M3 is equivalent to the parallel connection of M second NMOS transistors M2, so that the drain-source current of the third NMOS transistor M3 is M times the drain-source current of the second NMOS transistor M2, M≥1.

3. The circuit for generating a bias voltage for a passive mixer according to claim 1, wherein the plurality of NMOS transistors in the second NMOS transistor unit have the same size and are equal to the size of the NMOS transistor for frequency conversion in the subsequent passive mixer, and the plurality of PMOS transistors in the second PMOS transistor unit have the same size and are equal to the size of the PMOS transistor for frequency conversion in the subsequent passive mixer.

4. The circuit for generating a bias voltage of a source - free mixer according to claim 1, wherein the size of the fourth NMOS transistor M4 is the same as that of the second NMOS transistor M2 in the bias module, but the fourth NMOS transistor M4 is equivalent to the parallel connection of N second NMOS transistors M2, such that the drain - source current of the fourth NMOS transistor M4 is N times the drain - source current of the second NMOS transistor M2, where N≥1.

5. The circuit for generating a bias voltage of a source - free mixer according to claim 1, wherein the size of the fifth NMOS transistor M5 is the same as that of the second NMOS transistor M2 in the bias module, but the fifth NMOS transistor M5 is equivalent to the parallel connection of P second NMOS transistors M2, such that the drain - source current of the fifth NMOS transistor M5 is P times the drain - source current of the second NMOS transistor M2, where P≥1.

6. The circuit for generating a bias voltage of a source - free mixer according to claim 1, which is clamped by the first operational amplifier OP1 to make the potentials of the first node CN1 and the third node CN3 equal.

7. The circuit for generating a bias voltage of a source - free mixer according to claim 1, which is clamped by the second operational amplifier OP2 to make the potentials of the non - inverting input terminal and the inverting input terminal of the second operational amplifier OP2 equal.

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