Multi-channel amplitude and phase calibration ultra-wideband receiver

Abstract

The invention discloses an ultra-wideband receiver for multichannel amplitude and phase calibration. The ultra-wideband receiver comprises a first signal acquisition module, a second signal acquisition module and an FPGA (Field Programmable Gate Array), the first signal acquisition module comprises a first gating switch, a second gating switch, a third gating switch, and a first mixer, a first intermediate frequency filter, a first amplifier, a first numerical control attenuator, a second intermediate frequency filter, a first AGC and a first AD converter which are connected in sequence. And the second signal acquisition module comprises a one-out-of-eight switch gating array, and a second frequency mixer, a third intermediate frequency filter, a second amplifier, a second numerical control attenuator, a fourth intermediate frequency filter, a second AGC and a second AD converter which are connected in sequence. According to the invention, frequency conversion acquisition is realized through two frequency conversion channels, and signal amplitude and phase calibration is realized; the device is few in device, small in size, easy to integrate and low in cost.

Description

Technical Field

[0001] The present invention relates to the field of receivers, and in particular to an ultra-wideband receiver for multi-channel amplitude and phase calibration. Background Art

[0002] A receiver is an important part of technical reconnaissance technology, space technology, and communication technology. Frequency conversion processing and calibration of frequency signals have extensive applications in fields such as communication, radar, electronic countermeasures, and instrumentation. To cope with the increasingly complex electronic environment today, receivers are required to have characteristics such as ultra-wideband, multi-channel, low spurious, and wide dynamic range. Therefore, designing an ultra-wideband, multi-channel, and low-spurious receiver is an important means for frequency amplitude and phase calibration.

[0003] Currently, the main manifestations of ultra-wideband receivers in the industry are large volume, heavy weight, and disadvantages that are not conducive to product integration and miniaturization. The popular technical solution is to use radio frequency preselection, image frequency suppression, second mixing or multiple mixings, intermediate frequency filtering, signal amplification, and A / D sampling at the input front end to achieve, which has a complex implementation scheme, many devices, large volume, and high cost, as Figure 1 shown. The radio frequency signal can effectively suppress harmonics and image frequencies through the radio frequency preselector group, reduce intermodulation products, and reduce spurious signals; the amplifier compensates for the loss of signal amplitude and improves the gain; after mixing, an intermediate frequency signal is obtained, and through the intermediate frequency filter 1, out-of-band signals can be effectively suppressed, improving the intermediate frequency rejection ratio; the signal is mixed again to obtain a second intermediate frequency signal, and through the intermediate frequency filter 2, out-of-band signals are suppressed again, effectively suppressing the entry of spurious signals, and entering the FPGA for processing through A / D sampling.

[0004] Due to the ultra-wide frequency band (1M - 50GHz), this technical solution has redundant radio frequency preselector groups, two mixings (or multiple mixings), two intermediate frequency filterings, and related amplifications; there are many devices, large volume, and high cost; for eight channels, there are even more devices, huge volume, higher cost, and it is difficult to integrate and miniaturize, resulting in less market competitiveness. Summary of the Invention

[0005] The purpose of the present invention is to overcome the deficiencies of the prior art and provide an ultra-wideband receiver for multi-channel amplitude and phase calibration, which realizes frequency conversion acquisition through two frequency conversion channels and realizes signal amplitude and phase calibration; it has the advantages of few devices, small volume, easy integration, and low cost.

[0006] The purpose of the present invention is achieved through the following technical solutions: an ultra-wideband receiver for multi-channel amplitude and phase calibration, including a first signal acquisition module, a second signal acquisition module, and an FPGA; The first signal acquisition module includes a first gating switch, a second gating switch, a third gating switch, and a first mixer, a first intermediate frequency filter, a first amplifier, a first digital control attenuator, a second intermediate frequency filter, a first AGC, and a first AD converter connected in sequence; the first input terminal of the first gating switch is connected to the CH_1 channel, and the second input terminal is grounded through a first resistor; the output terminal of the first gating switch is connected to the first input terminal of the second gating switch, and the second input terminal of the second gating switch is grounded through a second resistor; the output terminal of the second gating switch is connected to the first input terminal of the third gating switch, the second input terminal of the third gating switch is grounded through a third resistor, and the output terminal of the third gating switch is connected to the signal input terminal of the first mixer; the output terminal of the first AD converter is connected to the FPGA; The second signal acquisition module includes an eight-to-one switch gating array, and a second mixer, a third intermediate frequency filter, a second amplifier, a second digital control attenuator, a fourth intermediate frequency filter, a second AGC, and a second AD converter connected in sequence; the first input terminal of the switch gating array is grounded through a second resistor, and the remaining seven input terminals are respectively connected to the CH_2, CH_3, CH_4, CH_5, CH_6, CH_7, CH_8 channels. The output terminal of the switch gating switch is connected to the signal input terminal of the second mixer, and the output terminal of the second AD converter is connected to the FPGA; The FPGA identifies the phase and amplitude of the signal output by the first signal acquisition module to form standard sample data; and when the switch gating array selects the CH2, CH_3, CH_4, CH_5, CH_6, CH_7, CH_8 channels respectively, it calculates the amplitude and phase sample data of each channel and compares them with the standard sample data. If there is an error that does not meet the conditions of the sample data of CH_1, it sends a request for amplitude and phase adjustment of CH_2, CH_3, CH_4, CH_5, CH_6, CH_7, CH_8 to the host computer connected to the FPGA.

[0007] For the input data, the FPGA converts the radio frequency signal to the baseband through digital down-conversion. The converted fixed-frequency signal is filtered by a CIC+FIR filter and quadrature demodulated, decomposed into in-phase I and quadrature Q components, and the out-of-band noise and sample decimation are filtered out; then the CORDIC algorithm module and arctangent operation are used to obtain the phase and amplitude: In vector mode, ensure the synchronization of I-channel and Q-channel data, avoid phase errors, and perform vector amplitude and phase calculations. The following formula: Amplitude = Phase = arctan(Q / I).

[0008] The beneficial effects of the present invention are as follows: The present invention realizes frequency conversion acquisition of multiple ultra-wideband signals through two frequency conversion channels, and realizes signal amplitude and phase calibration; it has the characteristics of few components, small volume, easy integration, and low cost, and is an ideal choice for amplitude and phase calibration in multi-channel frequency conversion. Description of the Drawings

[0009] Figure 1 It is a schematic diagram of the principle of an existing ultra-wideband receiver; Figure 2 It is a schematic diagram of the principle of the present invention; Figure 3 It is a schematic diagram of data processing of the FPGA; Figure 4 It is a schematic diagram of the principle of the local oscillator module. Detailed Embodiments

[0010] The technical solution of the present invention will be further described in detail below with reference to the drawings, but the protection scope of the present invention is not limited to the following.

[0011] As Figure 2 shown, an ultra-wideband receiver for multi-channel amplitude and phase calibration includes a first signal acquisition module, a second signal acquisition module, and an FPGA 18; The first signal acquisition module includes a first gating switch 1, a second gating switch 2, a third gating switch 22, and a first mixer 3, a first intermediate frequency filter 4, a first amplifier 5, a first digital control attenuator 6, a second intermediate frequency filter 7, a first AGC 8, and a first AD converter 9 connected in sequence; the first input terminal of the first gating switch 1 is connected to the CH_1 channel, and the second input terminal is grounded through a first resistor; the output terminal of the first gating switch is connected to the first input terminal of the second gating switch 2, and the second input terminal of the second gating switch 2 is grounded through a second resistor; the output terminal of the second gating switch 2 is connected to the first input terminal of the third gating switch 22, and the second input terminal of the third gating switch 22 is grounded through a third resistor, and the output terminal of the third gating switch 22 is connected to the signal input terminal of the first mixer 3; the output terminal of the first AD converter 9 is connected to the FPGA 18; The second signal acquisition module includes an eight-to-one switch selection array, and a second mixer 11, a third intermediate frequency filter 12, a second amplifier 13, a second digital control attenuator 14, a fourth intermediate frequency filter 15, a second AGC 16, and a second AD converter 17 connected in sequence; the first input terminal of the switch selection array is grounded through a second resistor, and the remaining seven input terminals are respectively connected to the CH_2, CH_3, CH_4, CH_5, CH_6, CH_7, and CH_8 channels. The output terminal of the switch selection switch is connected to the signal input terminal of the second mixer 11, and the output terminal of the second AD converter 17 is connected to the FPGA 18; The FPGA 18 identifies the phase and amplitude of the signals output by the first signal acquisition module to form standard sample data; and when the switch selection array selects channels CH_2, CH_3, CH_4, CH_5, CH_6, CH_7, and CH_8 respectively, it calculates the amplitude and phase sample data of each channel and compares them with the standard sample data. If there is an error in the sample data of a channel that does not meet the conditions compared with that of CH_1, it sends a request to the host computer connected to the FPGA to adjust the amplitude and phase of the channel that does not meet the conditions. After receiving the instruction, the host computer will adjust the amplitude and phase of the channel that does not meet the conditions.

[0012] Acquisition of the standard signal: The radio frequency signal enters channel CH_1 through the selection input of the one - in - two switch, is frequency - converted into an intermediate - frequency signal by the mixer, enters the intermediate - frequency filter to filter out out - of - band spurious signals to ensure the purity of the signal, is amplified by the amplifier to compensate for the frequency - conversion loss, enters the digital - controlled attenuator for attenuation (controlling the signal gain to match the signal level range of the A / D sampling), enters the intermediate - frequency filter for secondary filtering, and then is amplified by the AGC (programmable gain amplifier) (the link losses of different frequencies in the link are different, and the high - frequency loss is larger. The gain of the AGC is adjusted by program control to compensate for the high - frequency loss to match the level range of the A / D sampling), and then is converted into a digital signal by A / D sampling. The FPGA identifies the phase and amplitude to form standard sample data; The sampling principle of channels CH_2, CH_3, CH_4, CH_5, CH_6, CH_7, and CH_8 is the same as that of CH_1. The sampled channel signal sample data of CH_2, CH_3, CH_4, CH_5, CH_6, CH_7, and CH_8 are compared with the sample data of CH_1. If there is an error in the sample data of a channel that does not meet the conditions compared with that of CH_1, the host computer adjusts the frequency, phase, and amplitude of the input signals of CH_2, CH_3, CH_4, CH_5, CH_6, CH_7, and CH_8.

[0013] The number of one - in - two switches before frequency conversion of CH_1 and the two frequency - conversion channels of CH_2, CH_3, CH_4, CH_5, CH_6, CH_7, and CH_8 is the same, and their layout and wiring are symmetrically distributed, and the lengths of the wiring are equal; the same number of one - in - two switches and the same wiring length ensure that the link losses of the 8 - channel input signals are the same, ensuring that the signal gains of each channel are consistent (the same); the same wiring length ensures that the delays of the link signals are the same, thus ensuring that the phases of the signals on the link are the same; after frequency conversion, the two channels also ensure that the device is symmetrically distributed and the wiring lengths are equal, minimizing the amplitude and phase errors generated by the link to the greatest extent.

[0014] The transmission loss and frequency conversion loss of the output signal levels of CH_1, CH_2, CH_3, CH_4, CH_5, CH_6, CH_7, and CH_8 (e.g., signal dynamic range: -90 dBm to +8 dBm) on the link do not match the sampling level range of the ADC (SFDR: 90 dBc, 2.7 Vp-p), resulting in the inability to calibrate the output signal levels of CH_1, CH_2, CH_3, CH_4, CH_5, CH_6, CH_7, and CH_8 and inaccurate output levels. Therefore, the FPGA needs to set the sampling level range. If the level of the actual signal is not within the range, the FPGA automatically starts the control programs of the AGC and the digital attenuator to adjust the gain of the frequency conversion channel, so that the input signal level is within the sampling level range of the ADC, thereby ensuring that the output signal levels of CH_1, CH_2, CH_3, CH_4, CH_5, CH_6, CH_7, and CH_8 have a large dynamic range and high accuracy. Different frequency signals have different transmission losses on the transmission link. Lower frequency signals have smaller losses on the transmission link, while higher (millimeter wave) frequency signals have larger losses on the same transmission link. The calibration program automatically starts the control programs of the AGC and the digital attenuator according to the size of the signal level on the link, so that the signal level on the link meets the sampling conditions of the ADC.

[0015] As Figure 3 shown, the sampled data of the AD ADC is sent to the FPGA, and the radio frequency signal is frequency-converted to the baseband through digital down-conversion (DDC). The frequency-converted fixed-frequency signal is filtered through a CIC+FIR filter (signal bandwidth: 100 kHz / 10 kHz), subjected to quadrature demodulation, decomposed into in-phase (I) and quadrature (Q) components, filtered out of the out-of-band noise, and decimated; then the CORDIC algorithm module's algorithm and arctangent operation are used to obtain the phase and amplitude, ensuring the synchronization of the I-channel and Q-channel data in the vector mode, avoiding phase errors, and performing vector magnitude and phase calculations, as shown in the following formulas: Amplitude = Phase = arctan(Q / I) If there are fluctuations in amplitude and phase, the AGC gain module (or digital controlled attenuator) can be adjusted to adjust the link gain and make it work within an appropriate power range. Through the processing of the sampled data of the AD analog-to-digital converter by the above digital function modules, the digital signal has a smaller resolution when sampled at a smaller bandwidth, with less signal jitter, resulting in higher phase and amplitude consistency. This provides an accurate basis for the host computer to issue phase and amplitude adjustments for multiple (CH_2, CH_3, CH_4, CH_5, CH_6, CH_7, CH_8) signal sources, thus ensuring the consistency of the amplitude and phase of the signal output.

[0016] As Figure 4 shown, in the embodiment of the present application, the local oscillator module includes a PLL circuit 28, a third amplifier 29, an eleventh strobe switch 30, a frequency multiplier 31, a first filter bank 32, a twelfth strobe switch 33, a fourth amplifier 34, a third digital controlled attenuator 35, a fifth amplifier 36, a DDS module 37, a second filter bank 38, and a third filter bank 39; The output end of the PLL circuit 28 is respectively connected to the third amplifier 29 and the DDS module 37. The output end of the third amplifier 29 is connected to the eleventh strobe switch 30. The output end of the eleventh strobe switch 30 is respectively connected to the frequency multiplier 31 and the second filter bank 38. The output end of the frequency multiplier 31 is connected to the first filter bank 32. The output end of the DDS module 37 is connected to the third filter bank 39. The output ends of the first filter bank 32, the second filter bank 38, and the third filter bank 39 are all connected to the twelfth strobe switch 33. The output end of the twelfth strobe switch 33 is sequentially connected to the fourth amplifier 34, the third digital controlled attenuator 35, and the fifth amplifier 36 and then connected to the power splitter 27. The frequency signal generated by the PLL (frequency synthesizer) suppresses harmonics through the filter bank, is amplified to the power level required by the mixer by the amplifier, and after being split by the power splitter, goes to the mixer to mix with the signals input from CH_1, CH_2, CH_3, CH_4, CH_5, CH_6, CH_7, and CH_8 to become intermediate frequency signals. Since the frequency of this invention is relatively wide, the PLL cannot directly generate high enough or low enough frequency signals. The higher frequency signals are filtered and amplified by frequency doubling and then go to the mixer to mix with the signals of CH_1, CH_2, CH_3, CH_4, CH_5, CH_6, CH_7, and CH_8 to become intermediate frequency signals. The lower frequency signals are generated by the DDS, filtered and amplified, and then go to the mixer to mix with the signals of the CH_1, CH_2, CH_3, CH_4, CH_5, CH_6, CH_7, and CH_8 channels to become intermediate frequency signals. The digital controlled attenuator is used for large signal attenuation in the link, attenuating to the power level required by the mixer to mix with the signals of CH_1, CH_2, CH_3, CH_4, CH_5, CH_6, CH_7, and CH_8.

[0017] The above are the preferred embodiments of the present invention. It should be understood that the present invention is not limited to the forms disclosed herein, should not be regarded as excluding other embodiments, but can be used in other combinations, modifications, and environments, and can be changed within the scope of the concept described herein through the above teachings or the technology or knowledge in related fields. Any changes and modifications made by those skilled in the art without departing from the spirit and scope of the present invention shall fall within the protection scope of the appended claims of the present invention.

Claims

1. A multi-channel amplitude and phase calibration ultra-wideband receiver, characterized in that: It includes a first signal acquisition module, a second signal acquisition module, and an FPGA (18); The first signal acquisition module includes a first gating switch (1), a second gating switch (2), a third gating switch (22), and a first mixer (3), a first intermediate frequency filter (4), a first amplifier (5), a first digital control attenuator (6), a second intermediate frequency filter (7), a first AGC (8), and a first AD converter (9) connected in sequence; the first input terminal of the first gating switch (1) is connected to the CH_1 channel, and the second input terminal is grounded through a first resistor; the output terminal of the first gating switch is connected to the first input terminal of the second gating switch (2), and the second input terminal of the second gating switch (2) is grounded through a second resistor; the output terminal of the second gating switch (2) is connected to the first input terminal of the third gating switch (22), the second input terminal of the third gating switch (22) is grounded through a third resistor, and the output terminal of the third gating switch (22) is connected to the signal input terminal of the first mixer (3); the output terminal of the first AD converter (9) is connected to the FPGA (18); The second signal acquisition module includes an eight-to-one switch selection array, and a second mixer (11), a third intermediate frequency filter (12), a second amplifier (13), a second digital control attenuator (14), a fourth intermediate frequency filter (15), a second AGC (16), and a second AD converter (17) connected in sequence; the first input terminal of the switch selection array is grounded through a second resistor, and the remaining seven input terminals are respectively connected to the CH_2, CH_3, CH_4, CH_5, CH_6, CH_7, and CH_8 channels. The output terminal of the switch selection switch is connected to the signal input terminal of the second mixer (11), and the output terminal of the second AD converter (17) is connected to the FPGA (18); The FPGA (18) identifies the phase and amplitude of the signal output by the first signal acquisition module to form standard sample data; and when the switch selection array selects the CH_2, CH_3, CH_4, CH_5, CH_6, CH_7, and CH_8 channels respectively, it calculates the amplitude and phase sample data of each channel and compares them with the standard sample data. If there is an error that does not meet the conditions with the sample data of CH_1, it sends a request to the host computer connected to the FPGA to adjust the amplitude and phase of the channel that does not meet the conditions.

2. The multi-channel amplitude and phase calibration ultra-wideband receiver according to claim 1, characterized in that: The switch selection array includes a fourth selection switch to a tenth selection switch. The first input terminal of the fourth selection switch (19) is grounded through a fourth resistor, and the second input terminal is connected to the CH_2 channel. The input terminals of the fifth selection switch (23), the sixth selection switch (24), and the seventh selection switch (25) are respectively connected to the CH_3, CH_4, CH_5, CH_6, CH_7, and CH_8 channels. The input terminal of the eighth selection switch (20) is respectively connected to the output terminals of the fourth selection switch (19) and the fifth selection switch (23). The input terminal of the ninth selection switch (26) is respectively connected to the output terminals of the sixth selection switch (24) and the seventh selection switch (25). The input terminal of the tenth selection switch (21) is respectively connected to the output terminals of the eighth selection switch (20) and the ninth selection switch (26), and the output terminal of the tenth selection switch (21) is connected to the signal input terminal of the second mixer (11).

3. The multi-channel amplitude and phase calibration ultra-wideband receiver according to claim 2, characterized in that: The first selection switch to the tenth selection switch are all two - way selection switches.

4. A multi-channel amplitude and phase calibration ultra-wideband receiver according to claim 1, characterized in that: The resistance values of the first resistor to the fourth resistor are all 50 ohms.

5. A multi-channel amplitude and phase calibration ultra-wideband receiver according to claim 1, characterized in that: The ultra - wideband receiver further includes a local oscillator module (10) and a power splitter (27). The output terminal of the local oscillator module (10) is connected to the power splitter (27), and the output terminal of the power splitter (27) is respectively connected to the local oscillator input terminals of the first mixer (3) and the second mixer (11).

6. The multi-channel amplitude and phase calibration ultra-wideband receiver according to claim 1, characterized in that: For the input data, the FPGA converts the radio frequency signal to the baseband through digital down - conversion. The converted fixed - frequency signal is filtered and quadrature - demodulated through a CIC + FIR filter, decomposed into in - phase I and quadrature Q components, the out - of - band noise is filtered out and sample decimation is performed; then the CORDIC algorithm module and the arctangent operation are used to obtain the phase and amplitude: In vector mode, ensure the synchronization of the I - channel and Q - channel data, avoid phase error, and perform vector amplitude and phase calculations. The following formula: Amplitude = Phase = arctan(Q / I).

7. A multi-channel amplitude and phase calibration ultra-wideband receiver according to claim 1, characterized in that: When the amplitude and phase fluctuate, the FPGA adjusts the link gain by adjusting the first AGC, the second AGC, the first digital control attenuator, or the second digital control attenuator.

8. A multi-channel amplitude and phase calibration ultra-wideband receiver according to claim 5, characterized in that: The local oscillator module includes a PLL circuit (28), a third amplifier (29), an eleventh selection switch (30), a frequency multiplier (31), a first filter bank (32), a twelfth selection switch (33), a fourth amplifier (34), a third digital control attenuator (35), a fifth amplifier (36), a DDS module (37), a second filter bank (38), and a third filter bank (39); The output terminals of the PLL circuit (28) are respectively connected to a third amplifier (29) and a DDS module (37). The output terminal of the third amplifier (29) is connected to an eleventh gating switch (30). The output terminal of the eleventh gating switch (30) is respectively connected to a frequency multiplier (31) and a second filter bank (38). The output terminal of the frequency multiplier (31) is connected to a first filter bank (32). The output terminal of the DDS module (37) is connected to a third filter bank (39). The output terminals of the first filter bank (32), the second filter bank (38), and the third filter bank (39) are all connected to a twelfth gating switch (33). The output terminal of the twelfth gating switch (33) is sequentially connected to a power divider (27) through a fourth amplifier (34), a third digitally controlled attenuator (35), and a fifth amplifier (36).

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