Power supply circuit and semiconductor device

Abstract

An embodiment of the present application provides a power supply circuit and a semiconductor device that can be protected against application of an ESD stress that rises in a shorter time. According to the embodiment, the power supply circuit includes a first transistor, a feedback voltage generation circuit, a first voltage generation circuit, and a protection circuit. The first transistor is connected between an input terminal into which an input voltage is input and an output terminal from which an output voltage is output. The feedback voltage generation circuit generates a feedback voltage by dividing the output voltage. The first voltage generation circuit supplies a voltage to a first control terminal of the first transistor via a first node in such a manner that the output voltage coincides with or approximates a set value, on the basis of the feedback voltage and a reference voltage. The protection circuit outputs a voltage that makes the first transistor non-conductive or shows a prescribed high resistance value to the first control terminal in a case where the input voltage increases beyond a first threshold voltage within a prescribed time.

Description

[0001] Related application: This application enjoys priority based on Japanese Patent Application No. 2021-184206 (filed on November 11, 2021). This application incorporates the entire contents of the basic application by reference to that basic application. Technical Field

[0002] Embodiments of the present invention relate to power supply circuits and semiconductor devices. Background Technology

[0003] In semiconductor devices, electrostatic discharge (ESD) protection circuits are assembled to protect internal circuitry from ESD stress as a countermeasure. However, when subjected to rapidly increasing ESD stress, these circuits may fail to function as ESD protection circuits, potentially damaging the internal circuitry. Summary of the Invention

[0004] The present invention provides a power supply circuit and a semiconductor device capable of protecting against the application of ESD stress.

[0005] According to this embodiment, the power supply circuit includes a first transistor, a feedback voltage generation circuit, a first voltage generation circuit, and a protection circuit. The first transistor is connected between an input terminal for receiving an input voltage and an output terminal for receiving an output voltage. The feedback voltage generation circuit divides the output voltage to generate a feedback voltage. Based on the feedback voltage and a reference voltage, the first voltage generation circuit supplies a voltage to the first control terminal of the first transistor via a first node, such that the output voltage is the same as or approximately the set value. If the input voltage increases beyond a first threshold voltage within a predetermined time, the protection circuit outputs a voltage to the first control terminal that causes the first transistor to become non-conductive or exhibit a predetermined high resistance value. Attached Figure Description

[0006] Figure 1 This is a schematic diagram illustrating an example of an integrated circuit for a semiconductor device.

[0007] Figure 2 This is a block diagram representing an example of the configuration of a digital isolator with one channel quantity.

[0008] Figure 3 This is a circuit diagram illustrating an example of a power supply circuit configuration.

[0009] Figure 4 This is a circuit diagram illustrating an example of a protection circuit configuration.

[0010] Figure 5 Figures (a) to (c) illustrate the electrostatic discharge protection circuit and its operation.

[0011] Figure 6 This is a graph representing the simulation results.

[0012] Figure 7 This is a circuit diagram illustrating the configuration example of the power supply circuit for the comparative example.

[0013] Figure 8 This is a graph showing the simulation results for the comparative examples.

[0014] Figure 9 This is a circuit diagram illustrating an example of the protection circuit configuration in the second embodiment.

[0015] Figure 10 This is a circuit diagram illustrating an example of the configuration of the protection circuit in the third embodiment. Detailed Implementation

[0016] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In the following embodiments, the description will focus on the characteristic configuration and operation of the power supply circuit and the semiconductor device, but there may be configurations and operations in the power supply circuit and the semiconductor device that are omitted in the following description.

[0017] (First Implementation)

[0018] Figure 1 This is a schematic diagram illustrating an example of an integrated circuit for semiconductor device 1. Semiconductor device 1 is, for example, configured as an 8-pin integrated circuit. Figure 1 As shown, the semiconductor device 1 is, for example, an example of a galvanic isolation 2-channel digital isolator. Furthermore, the semiconductor device 1 has pins configured for power supply and GND on the primary and secondary sides, respectively. Additionally, the semiconductor device 1 uses chips with two or more voltage ratings: high voltage for external I / F and low voltage for internal I / F. For example, 5 volts is used for high voltage external I / F, and 1.5 volts is used for low voltage internal I / F.

[0019] In this digital isolator, the input signal input to the primary side signal input terminal VIN1 is output as an output signal from the secondary side signal output terminal VOUT1 via an electrically insulated transformer. For example, when a logic signal such as "1" is input to the signal input terminal VIN1, the modulated signal passes through the electrically insulated transformer, is demodulated, and a logic signal such as "1" is output from the signal output terminal VOUT1. Furthermore, in this embodiment, a digital isolator is used as an example of the configuration of semiconductor device 1, but it is not limited to this. For example, any circuit requiring protection against ESD stress can be configured using a semiconductor device other than a digital isolator.

[0020] Figure 2 It means Figure 1 The block diagram shown is an example of the configuration of a 1-channel digital isolator 2. Figure 2 As shown, the digital isolator 2 consists of a primary-side chip 10 and a secondary-side chip 20 that are electrically isolated. The digital isolator 2 has multiple power supply circuits 100, an input buffer 102, a first level shifter 104, a modulator 106, a driver circuit (DRV) 108, a transformer 110, an amplifier (RFAmp) 112, a detector circuit 114, a second level shifter 116, and an output buffer 118.

[0021] in addition, Figure 2 The lower part schematically represents the signals output by each circuit. The vertical axis represents the signal level, and the horizontal axis represents time. Signals G100 to G106 represent the corresponding signals. That is, signal G100 represents the situation where signals G102 to G106 change sequentially over time. More specifically, signal G100 represents a square wave logic signal example input from signal input terminal VIN1 to input buffer 102. For example, a 5-volt high input (HIGHINPUT) corresponds to "1", and a 0-volt low input (LOWINPUT) corresponds to "0".

[0022] Signal G102 represents a 500 MHz on / off keying (OOK) signal output from driver circuit 108. Signal G104 represents a detection circuit signal output from detector circuit 114. Signal G106 represents a square wave logic signal output from output terminal VOUT1. For example, a 5-volt (V) high input (HIGHINPUT) corresponds to "1", and a 0-volt low input (LOWINPUT) corresponds to "0".

[0023] like Figure 2As shown, the high-speed circuit module A10 needs to operate at high speed, and therefore is composed of a MOS (metal-oxide-semiconductor) capable of high-speed operation. The high-speed MOS has a lower withstand voltage and supply voltage, so the power supply circuit 100 adjusts the external voltage (Vdd1, Vdd2) from, for example, 5 volts to a lower voltage of, for example, 1.5 volts, and supplies it to the high-speed circuit module A10. Thus, the high-speed circuit module A10 has a lower withstand voltage compared to circuits in other areas, and is therefore vulnerable to electrostatic discharge (ESD). Therefore, in this embodiment, to protect the circuits within the high-speed circuit module A10 from ESD stress such as ESD, the power supply circuit 100 is equipped with a protection circuit. Thus, even if ESD stress such as ESD, or a high voltage that rises in a short time such as 20 nanoseconds (nsec) when power is supplied to the VDD1 terminal 5, is applied to the semiconductor device 1, the transmission of overvoltage from the power supply circuit 100 to the high-speed circuit module A10 can be suppressed. Further details of the power supply circuit 100 will be described later.

[0024] A rectangular wave logic signal G100 is input to input buffer 102, for example. This logic signal G100 is, for example, a rectangular wave signal with a speed of 150 megabits per second (Mbps). Input buffer 102 outputs the rectangular wave logic signal G100 to the first level shifter 104 while maintaining the shape of the rectangular wave.

[0025] The first level shifter 104 modifies the amplitude of the logic signal G100. For example, the first level shifter 104 converts a 5-volt high-input (HIGHINPUT) rectangular wave into a 1.5-volt rectangular wave.

[0026] Modulator 106 has an oscillator that generates a high-frequency differential on / off keying signal G102 corresponding to the rectangular wave signal input from first level shifter 104, and outputs it to drive circuit 108. This on / off keying signal G102 is a signal multiplied with the modulated signal on a 500 MHz carrier. While a 500 MHz carrier is used in this embodiment, it is not a limitation. For example, carriers ranging from several hundred MHz to several GHz can also be generated.

[0027] The driving circuit 108 drives the transformer 110 to send the 500 MHz on / off keying signal G102 to the secondary-side chip 20. The transformer 110 transmits the on / off keying signal G102 to the secondary-side chip 20 while ensuring electrical insulation. The transformer 110 in this embodiment has two transformers, thereby improving insulation performance and functional safety. Alternatively, a single transformer configuration can be used to suit applications where insulation performance is less critical. Furthermore, in the semiconductor device 1 of this embodiment, electrical insulation uses magnetic coupling, but is not limited to this method. For example, capacitive coupling or optical coupling can also be used. Furthermore, the semiconductor device 1 of this embodiment transmits the on / off keying signal, but is not limited to this method. For example, frequency modulation, edge signal transmission, or a combination of these methods can also be used.

[0028] Amplifier 112 amplifies the input signal from transformer 110 and outputs it to detector circuit 114. Detector circuit 114 detects the input differential on / off keying signal, outputs detector circuit output G104, and converts it into a 1.5V rectangular wave, which is then output to second level shifter 116.

[0029] The second level shifter 116 converts 1.5V and 0V rectangular waves into logic signals G106, which are 5V and 0V rectangular waves, and outputs them to the output buffer 118. The output buffer 118 maintains the rectangular waveform of the logic signal G106 while outputting from the output terminal VOUT1. Thus, the digital isolator 2, while maintaining electrical isolation between the primary-side chip 10 and the secondary-side chip 20, modulates the logic signal G100 input to the signal input terminal VIN1 and outputs the demodulated logic signal G106 from the signal output terminal VOUT1. Furthermore, the configuration of the digital isolator 2 is an example and is not limited to this circuit configuration.

[0030] Figure 3 This is a circuit diagram illustrating an example of the configuration of a power supply circuit 100. For example... Figure 3 As shown, the power supply circuit 100 is, for example, a low-drop output (LDO) regulator, having a first transistor 130, an output capacitor C10, a feedback voltage generation circuit 132, an error amplifier 134, an electrostatic discharge (ESD) protection circuit 136, and a protection circuit 200. Furthermore, in this embodiment, the error amplifier 134 corresponds to the first voltage generation circuit, and the ESD protection circuit 136 corresponds to the fourth transistor.

[0031] Protection circuit 200 is activated when the input voltage to terminal 5 of VDD1 exceeds a first threshold Vthm (see below) within a specified time. Figure 5In the event of an increase in resistance, a protection circuit outputs a control voltage that de-conducts the first transistor 130 or indicates a state with a predetermined high resistance value. This high resistance value is, for example, a resistance value that makes the potential between the VOUT output node 7 and the GND terminal 8 below the withstand voltage of the high-speed MOS when ESD stress is applied to the VDD1 terminal 5. In other words, the control voltage is set to a high resistance value corresponding to the assumed ESD stress. This protection circuit 200 includes a second transistor 202 and a voltage generation circuit 204. Further details of the protection circuit 200 will be provided later. Figure 4 As will be described later. Furthermore, the voltage generation circuit 204 in this embodiment corresponds to the second voltage generation circuit, and the VOUT output node 7 corresponds to the output terminal.

[0032] like Figure 3 As shown, the power supply circuit 100 forms a first transistor 130 between the VDD1 terminal 5 and the VOUT output node 7. The first transistor 130 is, for example, a PMOS (p-Channel Metal-Oxide Semiconductor) transistor, with its source connected to the VDD1 terminal 5, its drain connected to the VOUT output node 7, and its gate connected to node n2. In this embodiment, node n2 corresponds to the first node.

[0033] A high-speed circuit module A10 is connected as a load between the VOUT output node 7 and the GND terminal 8. Similarly, an output capacitor C10 and a feedback voltage generation circuit 132 are connected in parallel with the high-speed circuit module A10 between the VOUT output node 7 and the GND terminal 8.

[0034] The feedback voltage generation circuit 132 has two resistors R12 and R14 connected in series between the VOUT output node 7 and the GND terminal 8. The feedback voltage generation circuit 132 generates a voltage divider proportional to the output voltage Vout through node n4 between resistors R12 and R14, which serves as the feedback voltage FB.

[0035] A DC voltage, such as 5 volts, is input to terminal 5 of VDD1 from a battery, accumulator, or other DC power source (not shown). The reference voltage VREF is set to correspond to the set output voltage Vout, such as 1.5 volts.

[0036] The inverting input terminal of the error amplifier 134 is connected to node n4. Thus, the inverting input terminal receives the feedback voltage FB. Conversely, the non-inverting input terminal receives the reference voltage VREF. Furthermore, the output terminal of the error amplifier 134 is connected to the control terminal (gate) of the first transistor 130. Therefore, the error amplifier 134 amplifies the error between the reference voltage VREF and the feedback voltage FB, and outputs a voltage ER corresponding to the error to the control terminal (gate) of the first transistor 130. The resistance between the source and drain of the first transistor 130 varies according to the voltage ER applied to the gate. Thus, the voltage between the source and drain of the first transistor 130 is adjusted by the voltage ER applied to the gate. Then, through feedback control based on the error amplifier 134, the output voltage Vout is stabilized with a target value of Vout = VREF × (R12 + R14) / R14. That is, the reference voltage VREF and the resistance values ​​of resistors R12 and R14 are set such that Vout becomes 1.5 volts.

[0037] An electrostatic discharge (ESD) protection circuit 136 is provided in the power supply circuit 100. The ESD protection circuit 136 is connected between the VDD1 terminal 5 and the GND terminal 8. The GND terminal 8 is a potential terminal with a lower potential than the potential Vdd applied to the VDD1 terminal 5, for example, the potential is set to 0 volts.

[0038] Additionally, for example, when the voltage input to terminal 5 of VDD1 exceeds the specified foldback voltage Vs (see below) Figure 5 When the electrostatic discharge (ESD) occurs, the electrostatic protection circuit 136 generates a snapback. As a result, the impedance of the VDD1 terminal 5 and the GND terminal 8 decreases, becoming a path for ESD current.

[0039] The electrostatic discharge (ESD) protection circuit 136 is, for example, an ESD protection transistor connected between the VDD1 terminal 5 and the GND terminal 8. More specifically, the ESD protection transistor is, for example, an NMOS (n-Channel Metal-Oxide Semiconductor) transistor, and specifically a so-called ggNMOS (Gate Grounded NMOS) transistor with its gate and source connected to the GND terminal 8.

[0040] In this electrostatic discharge protection circuit 136, when electrostatic discharge is applied to the VDD1 terminal 5, the avalanche current generated by the avalanche breakdown of the drain terminal of the NMOS transistor causes the substrate potential to rise, activating the parasitic bipolar device. Through the activation of this parasitic bipolar device, a low-impedance current path is formed between the drain and source of the NMOS transistor, allowing current to flow due to electrostatic discharge, thus protecting the circuit connected between the VDD1 terminal 5 and the GND terminal 8.

[0041] Figure 4 This is a circuit diagram illustrating an example of the configuration of protection circuit 200. For example... Figure 4 As shown, the protection circuit 200 includes a second transistor 202 and a voltage generation circuit 204. The second transistor 202 is, for example, a PMOS transistor, with its source connected to the VDD1 terminal 5 and its drain connected to the control terminal, i.e., the gate, of the first transistor 130. The first transistor 130 is, for example, a PMOS transistor, so when the voltage at the drain of the second transistor 202 increases in the positive direction, the resistance of the first transistor 130 increases, and when it exceeds a predetermined threshold voltage, the first transistor 130 becomes off.

[0042] The voltage generation circuit 204 controls the voltage at the control terminal, i.e., the gate, of the second transistor 202 based on the input voltage at terminal VDD1 5. For example, the voltage generation circuit 204 applies a positive surge voltage to terminal VDD1 5. When the positive surge voltage exceeds a first threshold Vthm (refer to...), the voltage generation circuit 204... Figure 5 When the second transistor 202 is in a conducting state or close to a conducting state, a predetermined low-resistance control voltage is applied to the control terminal of the second transistor 202. When the second transistor 202 is in a conducting state or close to a conducting state with a predetermined low resistance, the voltage at the drain of the second transistor 202 becomes the voltage Vdd at terminal 5 of VDD1. Alternatively, the voltage at the drain of the second transistor 202 is close to the voltage Vdd at terminal 5 of VDD1. In addition, the positive surge voltage includes not only electrostatic discharge but also the voltage when the input power supply at terminal 5 of VDD1 rises. The voltage generation circuit 204 is configured to output a control voltage corresponding to ESD stress that rises sharply, for example, within a time of less than 20 nanoseconds.

[0043] More specifically, the voltage generation circuit 204 includes a first capacitor C20, a first resistor R20, a second resistor R22, and a third transistor 206. The first capacitor C20 is connected between the VDD1 terminal 5 and node n6. The first capacitor C20 has, for example, an electrostatic capacitance of 2 pF. Additionally, a capacitor is sometimes referred to as a capacitance. Furthermore, in this embodiment, node n6 corresponds to the second node.

[0044] Additionally, a first resistor R20 is connected between GND terminal 8 and node n6. The first resistor R20 is, for example, 30 kΩ. The combination of the first capacitor C20 and the first resistor R20 can be set, for example, according to the transient state during the rise of the input power supply at VDD1 terminal 5, or based on the ESD stress of electrostatic discharge.

[0045] The third transistor 206 is, for example, an NMOS transistor, with its drain connected to node n8 and its source connected to the GND terminal 8. The control terminal, i.e., the gate, of the third transistor 206 is connected to node n6. Furthermore, in this embodiment, node n8 corresponds to the third node. One end of the second resistor R22 is connected to node n8, and the other end is connected to the VDD1 terminal 5.

[0046] Here, the second element will be explained. The second element is sometimes called a dummy element. During the transistor manufacturing process, characteristic deviations can sometimes become significant due to the density of the pattern and the surrounding equipment. Therefore, multiple second elements are arranged in the end regions or adjacent regions of the area formed by multiple NMOS or PMOS transistors, which are multiple first elements. Thus, for example, an integrated circuit is composed of multiple first elements (i.e., a first element group) and multiple second elements (i.e., a second element group) arranged relative to the first element group at the end side of the integrated circuit. This second element group is, for example, an element arranged to reduce characteristic deviations during the manufacturing process of NMOS or PMOS transistors, and is arranged as described above at the end side of the integrated circuit closer to the first element group. In other words, during the manufacturing process of the second element, it is difficult to ensure uniformity of the influence from the surrounding environment when forming the second element. Therefore, the second element will exhibit performance deviations relative to the first element.

[0047] The second transistor 202 and the third transistor 206 of this embodiment operate as switches, thus requiring digital operation and no high precision. Therefore, even using the second element, the conditions for controlling the operation of the second transistor 202 and the third transistor 206 can be met. Furthermore, the amount of current flowing in the second element can be reduced compared to the first element, and the area can be smaller. That is, the second transistor 202 and the third transistor 206 of this embodiment can be used via wiring to connect to the second element, which is normally a dummy element and not connected to wiring. As described above, the second element is positioned at an end of the integrated circuit formed by the first transistor 130. For example, the second element is positioned at the end of the integrated circuit formed by the first transistor 130. This allows for further miniaturization of the semiconductor device 1.

[0048] The above is an explanation of an example of the configuration of semiconductor device 1. (Refer to...) Figure 3 as well as Figure 4 ,use Figure 5 An example of the operation of electrostatic discharge protection circuit 136 and protection circuit 200 will be explained. Figure 5 This is a diagram illustrating the operation of electrostatic discharge protection circuit 136 and protection circuit 200. Figure 5 In (a), the horizontal axis represents time, and the vertical axis represents the positive surge voltage as the Vdd voltage input to terminal 5 of VDD1. Figure 5In (b), the horizontal axis represents time, and the vertical axis represents node n6 (see reference). Figure 4 The voltage Vx. Figure 5 The horizontal axis of (c) represents time, and the vertical axis represents the time at node n8 (see reference). Figure 4 The current Ix is flowing. The interval between time t0 and time t1 is, for example, 20 nanoseconds.

[0049] like Figure 5 As shown in (a), an example is illustrated where electrostatic discharge is applied as a positive surge voltage (ESD voltage) at time t0. When the positive surge voltage is applied between the VDD input terminal 5 and the GND terminal 8, the Vdd voltage rises sharply. Then, when the foldback voltage Vs of the ggNMOS transistor in the electrostatic protection circuit 136 is reached at time t1, the parasitic bipolar device of the ggNMOS operates to become a holding voltage Vh, and ESD current flows. The first threshold voltage Vthm is the threshold voltage at which the first transistor 130 becomes non-conductive or exhibits a predetermined high resistance value when the Vdd voltage exceeds this first threshold voltage Vthm.

[0050] When ESD current flows, the Vdd voltage decreases gradually. Furthermore, in this embodiment, the rapidly rising voltage applied between the VDD input terminal 5 and the GND terminal 8 due to electrostatic discharge is sometimes referred to as ESD stress. Additionally, the ESD stress experimentally applied to the semiconductor device 1 includes the Human Body Model (HBM). Figure 5 In (a), for example, a 2 kV human body discharge mode is applied as a positive surge voltage.

[0051] At this time, as Figure 5 As shown in (b), node n6 (refer to) Figure 4 The voltage Vx of the first capacitor C20 (refer to) is determined according to the voltage Vx of the first capacitor C20 (refer to) Figure 4 ) and the first resistor R20 (refer to Figure 4The voltage Vx rises sharply along with the rapid rise of voltage Vdd due to the transient characteristics of the transistor 206, and exceeds the threshold voltage Vthn of the third transistor 206 at time t2. The first voltage Vthn is the voltage corresponding to the first threshold voltage Vthm. Voltage Vx continues to rise further with the increase of voltage Vdd, reaching a holding voltage Vh at time t1. When the rise of voltage Vx ends, the voltage decreases within a time constant of 60 nanoseconds (assuming the capacitance of the first capacitor C20 is 2 picofarads and the first resistor R20 is 30 kΩ), and at time t3, the holding voltage Vh is lower than the threshold voltage Vthn of the third transistor 206. Furthermore, this time constant only needs to be designed to be greater than 20 nanoseconds for the ESD (HBM) rise, allowing for operation with a relatively small time constant. Additionally, due to the relatively small time constant, the capacitor and resistor can be designed to be smaller.

[0052] At this time, as Figure 5 As shown in (c), during the period from t2 to t3, the voltage Vx exceeds the first voltage Vthn, which serves as a threshold voltage, and therefore a current Ix flows between the source and drain of the third transistor 206. This current is limited by the voltage Vdd and the first resistor R20. For example, when the voltage Vh is kept at 10 volts and the first resistor R20 is 10 kilohms, the current Ix becomes 1 milliampere (mA). Therefore, a large current does not flow in the third transistor 206, thus suppressing the risk of damage.

[0053] Then, due to the voltage drop caused by the current Ix and the second resistor R22, the gate potential of the second transistor 202 decreases, and the second transistor 202 becomes in the conducting state (on). Furthermore, because the second transistor 202 becomes in the conducting state (on), a voltage Vdd or close to Vdd is applied to the gate of the first transistor 130 as described above, causing it to become in the non-conducting state (off) or close to the non-conducting state. A simulation example of the voltage at the VOUT output node 7 after the first transistor 130 becomes in the non-conducting state (off) or close to the non-conducting state will be used... Figure 6 As will be described later. In addition, as mentioned above, both the second transistor 202 and the third transistor 206 have low current flow and perform switching operations, so the power supply circuit 100 can be made smaller by using the second element.

[0054] Figure 6 This is a graph showing the simulation results when a 2 kV positive surge voltage (ESD voltage) is applied between the VDD input terminal 5 and the GND terminal 8. The horizontal axis represents time, and the vertical axis represents voltage.

[0055] Line L7A represents the Vdd voltage, and line L7B represents the VOUT output voltage at node 7. For example... Figure 6As shown, even if the Vdd voltage changes drastically, the voltage at the VOUT output node 7 is suppressed to below 2 volts. That is, as described above, by turning on the second transistor 202, the gate of the first transistor 130 is subjected to the Vdd voltage, becoming either off or close to the off resistance value, thus suppressing the voltage at the VOUT output node 7 to below 2 volts. As can be seen from this, even if a positive surge voltage (ESD voltage) is applied as ESD stress, the circuits within the high-speed circuit module A10 will not exceed the withstand voltage and will be protected.

[0056] Figure 7 This is a circuit diagram illustrating an example configuration of the power supply circuit 100 for comparison. For example... Figure 7 As shown, the power supply circuit 100 of the comparative example is a power supply circuit without the protection circuit 200 installed.

[0057] Figure 8 It indicates that it is used as a comparative example. Figure 7 The diagram shows the simulation results of the power supply circuit 100. It illustrates the simulation results when a 2 kV positive surge voltage (ESD voltage) is applied between the VDD input terminal 5 and the GND terminal 8. The horizontal axis represents time, and the vertical axis represents voltage. Line L8A represents the Vdd voltage, and line L8B represents the voltage at the VOUT output node 7. Figure 8 As shown, in the power supply circuit 100 without the protection circuit 200 installed, the initial value of the gate voltage of the first transistor 130 is 0. Furthermore, the bandwidth of the error amplifier 134 is several MHz. Therefore, when the VDD voltage changes drastically, the first transistor 130 turns on, and thus the voltage at the VOUT output node 7 rises to 6V or higher. Consequently, the circuitry within the high-speed circuit module A10 may exceed its withstand voltage, potentially causing damage.

[0058] As explained above, in the semiconductor device 1 of this embodiment, when the input voltage at the VDD1 terminal 5 increases beyond the first threshold Vthn within a predetermined time, the protection circuit 200 outputs a voltage to the control terminal of the first transistor 130 that makes the first transistor 130 non-conductive or close to non-conductive, causing the first transistor 130 to become non-conductive. Therefore, even if a positive surge voltage (ESD voltage) or the like is applied that exceeds the first threshold Vthn within a predetermined time, the voltage at the VOUT output node 7 connected to one end of the first transistor 130 can be suppressed to below a predetermined value. Thus, the circuits within the high-speed circuit module A10 are protected from exceeding their withstand voltage.

[0059] (Second Implementation)

[0060] The difference between the semiconductor device 1 of the second embodiment and the semiconductor device 1 of the first embodiment is that the protection circuit 200 further includes a transistor that makes the voltage of the VOUT output node 7 reach the ground GND potential. The differences from the semiconductor device 1 of the first embodiment will be explained below.

[0061] Figure 9 This is a circuit diagram illustrating an example of the configuration of the protection circuit 200 in the second embodiment. For example... Figure 9 As shown, the voltage generation circuit 204 differs from the protection circuit 200 of the first embodiment in that it further has a fifth transistor 208.

[0062] The fifth transistor 208 is an equivalent element to the third transistor 206, and is an NMOS transistor with a threshold voltage Vthn. Its drain is connected to the VOUT output node 7, and its source is connected to the GND terminal 8. The control terminal, i.e., the gate, of the fifth transistor 208 is connected to node n6.

[0063] With this configuration, as described above Figure 5 As shown in (b), the voltage Vx at node n6 rises along with the sharp rise in voltage Vdd due to the transient characteristics of the first capacitor C20 and the first resistor R20, and exceeds the threshold voltage Vthn of the fifth transistor 208 at time t2. When the rise of voltage Vx ends, the voltage decreases, and at time t3, voltage Vh remains below the threshold voltage Vthn of the third transistor 206. Thus, the fifth transistor 208 is in the on state between time t2 and time t3. Therefore, between time t2 and time t3, the potential of the VOUT output node 7 becomes equal to the potential of the GND terminal 8. As can be seen from this, during time t2 to time t3, the potential of the VOUT output node 7 can be made equal to the potential of the GND terminal 8 regardless of the state of the first transistor 130. Therefore, the circuits in the high-speed circuit module A10 are more stably protected during time t2 to time t3, regardless of the state of the first transistor 130.

[0064] (Third Implementation)

[0065] The difference between the semiconductor device 1 of the third embodiment and the semiconductor device 1 of the first embodiment is that the protection circuit 200 is composed of a resistor and a capacitor connected in series. The differences from the semiconductor device 1 of the first embodiment will be explained below.

[0066] Figure 10 This is a circuit diagram illustrating an example of the configuration of the protection circuit 200 in the third embodiment. For example... Figure 10As shown, the voltage generation circuit 204 differs from the protection circuit 200 of the first embodiment in that it is composed of a third resistor R24 ​​and a second capacitor C22.

[0067] One end of the third resistor R24 ​​is connected to the VDD input terminal 5, and the other end of the third resistor R24 ​​is connected to node n10. One end of the second capacitor C22 is connected to node n10, and the other end of the second capacitor C22 is connected to the GND terminal 8. In addition, node n10 in this embodiment corresponds to the fourth node.

[0068] When a positive surge voltage is applied to the VDD input terminal 5, current flows in the third resistor R24, resulting in a voltage drop due to the current and the third resistor R24. This causes the second transistor 202 to become conductive. With the second transistor 202 in a conductive state, the gate of the first transistor 130 is subjected to a Vdd voltage, becoming either non-conductive (off) or close to a non-conductive resistance value. Therefore, as described above... Figure 6 Similarly, the potential of output node 7 (VOUT) can be suppressed to within the withstand voltage potential of high-speed circuit module A10.

[0069] Thus, even if a voltage that rises sharply within a specified time, i.e., 20 nanoseconds, is applied, the voltage at the VOUT output node 7 connected to one end of the first transistor 130 can be suppressed. Therefore, the circuits within the high-speed circuit module A10 are protected from exceeding their withstand voltage.

[0070] Several embodiments of the present invention have been described, but these embodiments are merely illustrative and not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included within the scope and spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

Claims

1. A power supply circuit, comprising: The first transistor is connected between the input terminal for input voltage and the output terminal for output voltage. The feedback voltage generation circuit divides the above output voltage to generate a feedback voltage. The first voltage generation circuit, based on the aforementioned feedback voltage and reference voltage, supplies voltage to the first control terminal of the first transistor via the first node in such a manner that the aforementioned output voltage is consistent with the set value. as well as The protection circuit, when the input voltage increases and exceeds a first threshold voltage within a specified time, outputs a voltage to the first control terminal that causes the first transistor to become non-conductive or exhibit a specified high resistance value. The above protection circuit has the following features: The second transistor is connected between the aforementioned input terminal and the aforementioned first node; and The second voltage generation circuit supplies voltage to the second control terminal of the second transistor based on the time variation of the input voltage. The second voltage generation circuit described above has: The first capacitor is connected between the aforementioned input terminal and the second node; The first resistor is connected between the second node and the grounding terminal. A third transistor is connected between the aforementioned ground terminal and the third node, and the third control terminal of the third transistor is connected to the aforementioned second node; and The second resistor is connected between the aforementioned input terminal and the aforementioned third node. The third node mentioned above is connected to the second control terminal mentioned above. The power supply circuit described above also includes a fourth NMOS transistor, the gate and source of which are connected to the ground terminal, and the drain of which is connected to the input terminal. The aforementioned first threshold voltage is set lower than the foldback voltage of the aforementioned fourth transistor. The aforementioned protection circuit outputs a voltage to the first control terminal to make the first transistor non-conducting or to indicate a specified high resistance value when the potential of the second node reaches a first potential corresponding to the first threshold voltage.

2. The power supply circuit as described in claim 1, wherein, The above protection circuit is as follows: If the potential at the second node reaches the potential corresponding to the first threshold voltage within 20 nanoseconds... The third transistor becomes on, and then the second transistor becomes on. Through the second transistor, which is on, a voltage is output to the first control terminal to make the first transistor off or to a specified high resistance value.

3. The power supply circuit as described in claim 1 or 2, wherein, The second voltage generation circuit described above also has: The fifth transistor is connected between the ground terminal and the output terminal, and the fifth control terminal of the fifth transistor is connected to the second node.

4. The power supply circuit as described in claim 2, wherein, The first transistor, the second transistor, and the third transistor constitute an integrated circuit. The integrated circuit has a first element group and a second element group disposed at the end side of the integrated circuit relative to the first element group. The first transistor is any element in the first element group, and at least one of the second transistor and the third transistor is any element in the second element group.

5. A semiconductor device, while maintaining electrical isolation between a primary-side chip and a secondary-side chip, modulates a logic signal input to a signal input terminal of the primary-side chip, and outputs a demodulated logic signal from a signal output terminal of the secondary-side chip. In the aforementioned semiconductor device, The power supply circuit comprising any one of claims 1 to 4 The drive is performed using the output voltage supplied from the power supply circuit described above.

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