Integrated circuit with self-referenced impedance

Abstract

The present disclosure relates to an integrated circuit with a self-referenced impedance, comprising input / output pins, a local impedance, a reference power supply circuit, a switching circuit, and a control circuit. The input / output pins are used for connecting an external impedance. The switching circuit conducts the connection between the input / output pins and the reference power supply circuit in a first state, and conducts the connection between the local impedance and the reference power supply circuit in a second state. The control circuit is used to detect whether the input / output pins are connected to an external impedance and generate a detection signal; and according to the indication of the detection signal, control the switching circuit to the first state or the second state. When the switching circuit is controlled to the first state, the reference power supply circuit generates a reference signal based on the external impedance. When the switching circuit is controlled to the second state, the reference power supply circuit generates a reference signal based on the local impedance.

Description

Technical Field

[0001] The present invention relates to a reference power generation technology, in particular to an integrated circuit with self-reference impedance for generating a reference power supply. Background Art

[0002] Many chips, devices, or circuits require a reference power supply to implement certain functions. Therefore, these chips, devices, or circuits typically use external resistors to generate the reference power supply. However, external resistors are susceptible to noise interference. Furthermore, external resistors take up space in the product formed by the chip, device, or circuit, increasing the manufacturing cost of the product. Summary of the Invention

[0003] In light of the above background, the present invention provides an integrated circuit with self-referenced impedance. According to some embodiments, the present invention can reduce the area occupied by a chip, device, or circuit in a product, thereby lowering the manufacturing cost of the product. According to some embodiments, the present invention can also reduce the probability of noise interference with the reference power supply.

[0004] According to some embodiments, an integrated circuit with a self-referenced impedance includes an input / output pin, a local impedance, a reference power supply circuit, a switching circuit, and a control circuit. The input / output pin is used to connect an external impedance. The switching circuit is connected between the input / output pin, the local impedance, and the reference power supply circuit so as to conduct the connection between the input / output pin and the reference power supply circuit in a first state and conduct the connection between the local impedance and the reference power supply circuit in a second state. The control circuit is used to detect whether the input / output pin is connected to the external impedance and generate a detection signal; and based on the indication of the detection signal, control the switching circuit to the first state or the second state. When the switching circuit is controlled to the first state, the reference power supply circuit generates a reference signal based on the external impedance. When the switching circuit is controlled to the second state, the reference power supply circuit generates a reference signal based on the local impedance. The reference signal is used as a reference power supply for the integrated circuit.

[0005] In summary, according to some embodiments, the use of either an external impedance or a local impedance to generate a reference signal is not limited to a single method. In some embodiments, the external impedance may be used to generate the reference signal when an external impedance is connected to an input or output pin, thereby reducing the required area of ​​the integrated circuit design and lowering manufacturing costs. In some embodiments, the local impedance may be used to generate the reference signal, thereby reducing the probability of noise interference with the reference power supply. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] [ Figure 1] is a block diagram of an integrated circuit with self-referenced impedance according to some embodiments of the present invention.

[0007] [ Figure 2 ] is a flow chart of the first adjustment procedure of some embodiments of the present invention.

[0008] [ Figure 3 ] is a flow chart of the second adjustment procedure of some embodiments of the present invention.

[0009] [ Figure 4 ] is a schematic diagram of a portion of an integrated circuit of some embodiments of the present invention.

[0010] List of reference numerals: 10: integrated circuit; 20-22: input / output pins; 30: local impedance; 40: reference power supply circuit; 41: operational amplifier; M4: fourth transistor; 50: switching circuit; 51-53: switches; 60: control circuit; 61: processor; 62: first comparator; 63: pull-down impedance; 64: voltage divider circuit; M1: first transistor; M2: second transistor; 65: regulation circuit; 66: storage; 67: second comparator; 70: external impedance; 80: reference power supply drawing circuit; 90: comparison impedance; M3: third transistor; M5: fifth transistor; M6: sixth transistor; I1: output current; I3-I6: current; I DET : Detection current; I ref : Reference current; V DET : Detection voltage; V CPK : Correction voltage; V bias : bias voltage; V BG : Comparison voltage; V FB : Feedback voltage; V T1 : first voltage threshold; V T2 : second voltage threshold; DT: detection signal; S201~S207: steps; S301~S309: steps. DETAILED DESCRIPTION

[0011] As used herein, the terms "first" and "second" are used to distinguish the elements referred to, and are not used to order or limit the differences between the elements referred to, nor are they used to limit the scope of the present invention. Furthermore, the terms "connected" and "connected" refer to two or more elements being in direct physical or electrical contact with each other, or indirect physical or electrical contact with each other. For example, if a first device is described as being coupled to a second device, it means that the first device can be directly electrically connected to the second device, or indirectly electrically connected to the second device through other devices or connection means.

[0012] Reference Figure 1, is a block diagram of an integrated circuit 10 with self-referenced impedance according to some embodiments of the present invention. The integrated circuit 10 with self-referenced impedance (hereinafter referred to as integrated circuit 10) includes an input / output pin 20, a local impedance 30, a reference power circuit 40, a switch circuit 50, and a control circuit 60. The switch circuit 50 is connected between the input / output pin 20, the local impedance 30, and the reference power circuit 40. The control circuit 60 is connected to the input / output pin 20, the local impedance 30, the reference power circuit 40, and the switch circuit 50.

[0013] I / O pin 20 is connected to an external impedance 70. In some embodiments, integrated circuit 10 is implemented as a chip, with external impedance 70 located externally, I / O pin 20 being an I / O pin of the chip, and local impedance 30, reference power supply circuit 40, switch circuit 50, and control circuit 60 located internally. In some embodiments, external impedance 70 and local impedance 30 are also connected to ground. For example, a first end of external impedance 70 and a first end of local impedance 30 are connected to ground, a second end of external impedance 70 is connected to I / O pin 20, and a second end of local impedance 30 is connected to switch circuit 50. In other words, external impedance 70 is connected between I / O pin 20 and ground, and local impedance 30 is connected between switch circuit 50 and ground.

[0014] In some embodiments, the external impedance 70 and the local impedance 30 can be formed by passive components such as resistors, capacitors, and inductors. In a preferred embodiment, the external impedance 70 and the local impedance 30 can be resistors. Figure 1 The external impedance 70 and the local impedance 30 are represented by only one resistor symbol, but the present invention is not limited thereto. A plurality of resistors connected in series and / or in parallel may be included according to actual design requirements.

[0015] In some embodiments, local impedance 30 can be a resistor implemented by a metal oxide semiconductor (MOS) transistor, or a resistor implemented by a well region formed by ion implantation. In some embodiments, local impedance 30 can be a poly resistor, such as a resistor formed by the RPO layer, P+ layer, Poly layer, Contact layer, and Resdummy layer of a MOS transistor. This can save the design area occupied by local impedance 30 in integrated circuit 10 and reduce manufacturing costs. In other words, local impedance 30 can be implemented by some transistors in integrated circuit 10, without the need for additional components to implement local impedance 30.

[0016] The control circuit 60 is used to detect whether the input / output pin 20 is connected to the external impedance 70 and generate a detection signal DT. Then, the control circuit 60 controls the switch circuit 50 to be in the first state or the second state according to the indication of the detection signal DT.

[0017] The switch circuit 50 conducts the connection between the input / output pin 20 and the reference power supply circuit 40 in the first state. When the switch circuit 50 is controlled to the first state, the reference power supply circuit 40 generates a reference signal according to the external impedance 70. The switch circuit 50 conducts the connection between the local impedance 30 and the reference power supply circuit 40 in the second state. When the switch circuit 50 is controlled to the second state, the reference power supply circuit 40 generates a reference signal according to the local impedance 30. In this way, the generation of the reference signal is not limited to a single method. Furthermore, since the local impedance 30 can be used to generate the reference signal in some cases, the probability of the reference signal being interfered with by noise can be reduced. The reference signal is used as a reference power supply for the integrated circuit 10. For example, Figure 1 As shown, the reference signal can be a reference power source for a reference power source circuit 80 of the integrated circuit 10. The reference power source circuit 80 is used to implement certain functions, such as an overload protection function of the integrated circuit 10. The reference power source can be a reference voltage or a reference current (e.g. Figure 1 The reference current I shown ref ).

[0018] In some embodiments, as Figure 1 As shown, the switch circuit 50 includes a plurality of switches 51-52. Switch 51 is connected between the reference power circuit 40 and the local impedance 30. Switch 52 is connected between the reference power circuit 40 and the input / output pin 20. In a first state, switch 52 connects the reference power circuit 40 to the input / output pin 20, thereby connecting the reference power circuit 40 to the external impedance 70. At this time, switch 51 disconnects (is not conductive) the reference power circuit 40 from the local impedance 30. In a second state, switch 51 connects the reference power circuit 40 to the local impedance 30, while switch 52 disconnects (is not conductive) the reference power circuit 40 from the input / output pin 20, thereby disconnecting (is not conductive) the reference power circuit 40 from the external impedance 70. Switches 51-52 can be implemented as electronic switches (e.g., transistors).

[0019] In some embodiments, when the control circuit 60 detects that the external impedance 70 is connected to the I / O pin 20, it generates a detection signal DT indicating a first state and controls the switch circuit 50 to the first state. When the control circuit 60 detects that the external impedance 70 is not connected to the I / O pin 20, it generates a detection signal DT indicating a second state and controls the switch circuit 50 to the second state. In other words, when the external impedance 70 is connected to the I / O pin 20, the external impedance 70 is initially used to generate the reference signal; when the external impedance 70 is not connected to the I / O pin 20, the local impedance 30 is used to generate the reference signal. This simplifies the design area required for the integrated circuit 10 and reduces manufacturing costs. For example, there is no need to reserve space on the integrated circuit 10 for the external impedance 70.

[0020] In some embodiments, as Figure 1 As shown, the control circuit 60 includes a processor 61. The processor 61 is connected to the switch circuit 50. The switching state of the switch circuit 50 is controlled by the processor 61. For example, when the switch circuit is in the second state and the detection signal DT indicates the first state, the processor 61 issues a switch signal, and the switch circuit 50 switches from the second state to the first state in response to the switch signal. When the switch circuit is in the first state and the detection signal DT indicates the second state, the processor 61 issues a switch signal, and the switch circuit 50 switches from the first state to the second state in response to the switch signal. In other words, when the state of the switch circuit 50 is different from the state indicated by the detection signal DT, the processor 61 issues a switch signal to switch the switch circuit 50. Conversely, when the state of the switch circuit 50 is the same as the state indicated by the detection signal DT, the processor 61 does not issue a switch signal to maintain the state of the switch circuit 50. The processor 61 can be a computing circuit such as a central processing unit, a microprocessor, or an application-specific integrated circuit (ASIC).

[0021] In some embodiments, as Figure 1 As shown, the control circuit 60 includes a first comparator 62 and a pull-down resistor 63. The first comparator 62 is connected to the input / output pin 20 and the pull-down resistor 63. The first comparator 62 is used to compare a detection voltage V DET and a first voltage threshold V T1 , to generate a detection signal DT. The detection voltage V DETAccording to the external impedance 70 and the pull-down impedance 63, the first comparator 62 changes. In some embodiments, the first comparator 62 is further connected to the processor 61 to output the detection signal DT to the processor 61. In some embodiments, the first input terminal of the first comparator 62 is connected to the input / output pin 20 and the pull-down impedance 63, and the output terminal of the first comparator 62 is connected to the processor 61. In some embodiments, the first voltage threshold V T1 The bandgap reference voltage source may be generated by a bandgap reference voltage generating circuit (not shown), and the bandgap reference voltage source is connected to the second input terminal of the first comparator 62 .

[0022] In some embodiments, the pull-down impedance 63 can be formed by passive components such as resistors, capacitors, and inductors. In a preferred embodiment, the pull-down impedance 63 can be a resistor with a small resistance value, for example, the pull-down impedance 63 can be a resistor less than 5 ohms (Ω). Figure 1 The pull-down impedance 63 is represented by only one resistor symbol, but the present invention is not limited thereto and may include multiple resistors connected in series and / or in parallel according to actual design requirements. Furthermore, the resistor may be implemented using a MOS transistor or a well region formed by ion implantation.

[0023] In some embodiments, when the input / output pin 20 is connected to the external impedance 70, the detection voltage V DET Greater than the first voltage threshold V T1 , and the first comparator 62 detects the voltage V DET Greater than the first voltage threshold V T1 When , a detection signal DT indicating the first state is generated. For example, the first comparator 62 generates a high level signal to indicate the first state.

[0024] In some embodiments, as Figure 1 As shown, the control circuit 60 includes a voltage divider circuit 64. The voltage divider circuit 64 is connected to the input / output pin 20, the first comparator 62 and the pull-down resistor 63. The voltage divider circuit 64 is used to generate a detection current I according to the external impedance 70 when the input / output pin 20 is connected to the external impedance 70. DET The pull-down impedance 63 is based on the detection current I DET , generating a voltage greater than the first threshold voltage V T1 Detection voltage V DET , causing the first comparator 62 to generate a detection signal DT indicating a first state. In some embodiments, the pull-down resistor 63 generates a voltage greater than the first voltage threshold V T1 Detection voltage V DET , is equal to or approximately equal to the detection current I DET The value obtained by multiplying the pull-down impedance 63.

[0025] In some embodiments, the pull-down impedance 63 is further connected to the ground. For example, the first end of the pull-down impedance 63 is connected to the ground, the second end of the pull-down impedance 63 is connected to the voltage divider circuit 64 and the first input end of the first comparator 62, and the pull-down impedance 63 generates a detection voltage V at the first input end of the first comparator 62. DET That is, the pull-down impedance 63 is connected between the first input terminal of the first comparator 62 and the ground terminal, and is also connected between the voltage divider circuit 64 and the ground terminal.

[0026] In some embodiments, as Figure 1 As shown, the voltage divider circuit 64 includes a first transistor M1 and a second transistor M2. The first transistor M1 and the second transistor M2 can be P-type MOS transistors or P-type bipolar transistors. The first transistor M1 and the second transistor M2 are described as P-type bipolar transistors. The collector of the first transistor M1 is connected to the input / output pin 20. The emitter of the first transistor M1 is connected to the emitter of the second transistor M2. The collector of the second transistor M2 is connected to the first input terminal of the first comparator 62 and the pull-down impedance 63. The base of the first transistor M1 and the base of the second transistor M2 respectively receive a bias voltage V from a bias circuit (not shown). bias , to start the action. Figure 1 The base of the first transistor M1 and the base of the second transistor M2 are shown to receive the same bias voltage, but the present invention is not limited to this. The base of the first transistor M1 and the base of the second transistor M2 can receive different bias voltages. When the input / output pin 20 is connected to the external impedance 70 and the first transistor M1 is activated, the first transistor M1 generates an output current I1 according to the external impedance 70. When the second transistor M2 is activated, the second transistor M2 generates a detection current I according to the output current I1. DET , thereby causing the first comparator 62 to generate a detection signal DT indicating the first state.

[0027] In some embodiments, when the input / output pin 20 is not connected to the external impedance 70, the detection voltage V DET is pulled down by the pull-down resistor 63 and is not greater than the first voltage threshold V T1 The first comparator 62 detects the voltage V DET Not greater than the first voltage threshold V T1 When the input / output pin 20 is not connected to the external impedance 70, the path between the pull-down impedance 63 and the voltage divider circuit 64 does not have the detection current I DET Therefore, the detection voltage V DETPulled down by the pull-down resistor 63 to a potential equal to or close to the ground terminal. For example, the detection voltage V DET Pulled down to 0 volts (V) or close to 0 volts (e.g., 0.1 volts). In some embodiments, when the input / output pin 20 is not connected to the external impedance 70, in addition to generating the detection signal DT indicating the second state through the pull-down impedance 63, the pull-down impedance 63 can also be used to ensure that the first input terminal of the first comparator 62 is not floating.

[0028] In some embodiments, when the switch circuit 50 is controlled to the second state, the control circuit 60 adjusts the impedance value of the local impedance 30 in response to a correction signal. The local impedance 30 may be a variable impedance. In a preferred embodiment, the local impedance 30 may be a variable resistor. In some embodiments, the control circuit 60 generates a correction signal when the impedance value of the local impedance 30 deviates from a target impedance value. In other words, the correction signal is generated when the impedance value of the local impedance 30 is to be changed. For example, assume that the local impedance 30 is a poly resistor, and the poly resistor is adjustable. Since the poly resistor may have a deviation of plus or minus 20%, the reference signal may be inaccurate (i.e., the reference signal also has deviation). Therefore, when the impedance value of the local impedance 30 deviates from the target impedance value (i.e., the impedance value of the local impedance 30 deviates), the impedance value of the local impedance 30 is adjusted to generate an accurate reference signal (i.e., a reference signal without deviation).

[0029] In some embodiments, the impedance value of the external impedance 70 may not have deviations compared to the local impedance 30, that is, the external impedance 70 may be a precise impedance. Therefore, when the external impedance 70 is used to generate the reference signal, the impedance value of the external impedance 70 may not need to be adjusted.

[0030] In some embodiments, as Figure 1 As shown, the control circuit 60 includes a memory 66. The memory 66 is connected to the processor 61. The memory 66 stores the impedance target value. The memory 66 can be a volatile storage medium (such as a random access memory) or a non-volatile storage medium (such as a read-only memory).

[0031] In some embodiments, as Figure 1 As shown, the control circuit 60 includes an adjustment circuit 65. The adjustment circuit 65 is connected to the processor 61 and the local impedance 30. For example, the processor 61 detects the impedance value of the local impedance 30 through the adjustment circuit 65 and obtains the target impedance value from the memory 66. When the processor 61 detects that the impedance value of the local impedance 30 does not match the target impedance value, the processor 61 generates a correction signal and controls the adjustment circuit 65 to adjust the impedance value of the local impedance 30 in response to the correction signal.

[0032] In some embodiments, after the control circuit 60 responds to the calibration signal, the control circuit 60 determines, based on an adjustment instruction, whether to adjust the impedance value of the local impedance 30 using a first adjustment procedure or a second adjustment procedure. In some embodiments, the adjustment instruction is parsed by the processor 61, and the processor 61 determines, based on the parsed result, whether to control the adjustment circuit 65 to adjust the impedance value of the local impedance 30 using the first adjustment procedure or the second adjustment procedure.

[0033] In some embodiments, the adjustment instruction can be input to the processor 61 by the user through an input / output interface (not shown). The input / output interface may be, for example, but not limited to, a keyboard, a mouse, a touch input device, or a voice input device. In some embodiments, the adjustment instruction can be a flag value and can be pre-stored in the memory 66. When the logic level of the flag value is "0", it indicates the execution of the first adjustment procedure, and when the logic level of the flag value is "1", it indicates the execution of the second adjustment procedure. However, the present invention is not limited to this. It can be that when the logic level of the flag value is "1", it indicates the execution of the first adjustment procedure, and when the logic level of the flag value is "0", it indicates the execution of the second adjustment procedure. In this way, after each response to the calibration signal, the processor 61 can directly obtain the flag value as the adjustment instruction from the memory 66 and use it, without having to perform the instruction input process each time the adjustment instruction is to be used.

[0034] In some embodiments, as shown in Table 1, memory 66 stores a lookup table and a plurality of different levels. The lookup table includes the plurality of levels and a plurality of different impedance change amounts, and the plurality of levels correspond to the plurality of impedance change amounts. An impedance change of "+5%" represents a 5% increase in the impedance value of the local impedance 30, and an impedance change of "-5%" represents a 5% decrease in the impedance value of the local impedance 30.

[0035] [Table 1] is a comparison table

[0036] grade Impedance change 0 +5％ 1 +10％ 2 +20％ 3 -5％ 4 -10％ 5 -20％

[0037] Reference Figure 2, is a flow chart of the first adjustment process in some embodiments of the present invention. In some embodiments, first, the processor 61 receives a change selection signal (step S201). The change selection signal is input to the processor 61 by the user via the input / output interface. Next, the processor 61 selects one of the multiple levels in the memory 66 (step S203). Specifically, the processor 61 selects the level based on the change selection signal. Then, based on the selected level and a comparison table, the processor 61 obtains the impedance change corresponding to the selected level (step S205). The processor 61 then controls the adjustment circuit 65 to adjust the impedance value of the local impedance 30 based on the obtained impedance change (step S207). For example, if the obtained impedance change is "+5%," the adjustment circuit 65 increases the impedance value of the local impedance 30 by 5%; if the obtained impedance change is "-5%," the adjustment circuit 65 decreases the impedance value of the local impedance 30 by 5%. Thus, by adjusting the impedance value of the local impedance 30 through calculation by the processor 61 , the architecture of the integrated circuit 10 can be simplified.

[0038] In some embodiments of step S203, the processor 61 selects the level from the plurality of levels that results in the adjusted impedance value of the local impedance 30 being closest to or equal to the target impedance value. This can correct for some deviations in the local impedance 30 and improve the accuracy of the reference signal.

[0039] Reference Figure 3 , is a flow chart of the second adjustment process of some embodiments of the present invention. In some embodiments, Figure 1 As shown, the control circuit 60 includes a second comparator 67. The second comparator 67 is connected to the adjustment circuit 65. The second adjustment process is described below. In some embodiments, Figure 3 As shown, first, the second comparator 67 compares the second voltage threshold V T2 and the calibration voltage V from the reference impedance 90 CPK (Step S301), and output the comparison result to the adjustment circuit 65. The impedance value of the reference impedance 90 may not have deviation, that is, the reference impedance 90 may be an accurate impedance. The adjustment circuit 65 determines the correction voltage V according to the comparison result. CPK Is it greater than, equal to, or less than the second voltage threshold V T2 (Step S303). CPK Greater than the second voltage threshold V T2 When the adjustment voltage V CPK Less than the second voltage threshold V T2When the adjustment circuit 65 increases the impedance value of the local impedance 30 (step S307). CPK Equal to the second voltage threshold V T2 When the impedance value of the local impedance 30 is maintained by the adjustment circuit 65 (step S309), the impedance value of the local impedance 30 can be automatically calibrated so that the impedance value of the local impedance 30 does not have deviation.

[0040] In some embodiments of step S309, the adjustment circuit 65 maintains the impedance value of the local impedance 30, at which point the impedance value of the local impedance 30 is equal to the impedance value of the reference impedance 90, and the impedance value of the reference impedance 90 is the impedance target value. CPK Equal to the second voltage threshold V T2 When , the impedance value of the local impedance 30 is the impedance target value.

[0041] In some embodiments, due to variability within integrated circuits 10, the impedance value deviation range of local impedance 30 may vary between different integrated circuits 10. The first adjustment procedure adjusts the impedance value of local impedance 30 based on a percentage of the impedance value of local impedance 30. Therefore, the impedance values ​​of local impedance 30 adjusted through the first adjustment procedure may vary between different integrated circuits 10, resulting in different reference signal accuracy across different integrated circuits 10. Compared to the first adjustment procedure, the second adjustment procedure adjusts the impedance value of local impedance 30 based on reference impedance 90. Therefore, the impedance values ​​of local impedance 30 adjusted through the second adjustment procedure can be the same across different integrated circuits 10, and the accuracy of reference signals across different integrated circuits 10 can be the same. In other words, the first adjustment procedure can be implemented for applications that require less accurate reference signals, while the second adjustment procedure can be implemented for applications that require more accurate reference signals.

[0042] In some embodiments, the first input terminal of the second comparator 67 is connected to the reference impedance 90 to receive the correction voltage V from the reference impedance 90. CPK , and the output terminal of the second comparator 67 is connected to the regulating circuit 65 to output the comparison result to the regulating circuit 65. In some embodiments, the second voltage threshold V T2 The second voltage threshold V T2 Different from the first voltage threshold V T1 , but the present invention is not limited thereto, the second voltage threshold V T2 Can be equal to the first voltage threshold V T1 .

[0043] Reference Figure 4 , is a schematic diagram of a portion of an integrated circuit 10 according to some embodiments of the present invention. In some embodiments, Figure 1 As shown, the integrated circuit 10 is implemented as a chip, and the control impedance 90 is located inside the chip. In other words, the external impedance 70 is located outside the chip, the input and output pins 20 are the input and output pins of the chip, and other components in the integrated circuit 10 can be located inside the chip. However, the present invention is not limited to this. In other embodiments, such as Figure 4 As shown, the integrated circuit 10 further includes another input / output pin 22 for connection to the reference impedance 90. In this case, when the integrated circuit 10 is implemented as a chip, the reference impedance 90 and the external impedance 70 are located outside the chip, the input / output pin 20 and the input / output pin 22 are the input / output pins of the chip, and other components in the integrated circuit 10 may be located inside the chip.

[0044] In some embodiments, the comparison impedance 90 can be formed by passive components such as resistors, capacitors, and inductors. In a preferred embodiment, the comparison impedance 90 can be a resistor. Figure 1 and Figure 4 The reference impedance 90 is represented by only one resistor symbol, but the present invention is not limited thereto. A plurality of resistors connected in series and / or in parallel may be included according to actual design requirements.

[0045] Re-reference Figure 1 In some embodiments, the integrated circuit 10 includes a third transistor M3. The switch circuit 50 is connected between the reference impedance 90 and the third transistor M3. When the switch circuit 50 is controlled to the second state and the second adjustment process is executed, the switch circuit 50 conducts the connection between the reference impedance 90 and the third transistor M3, so that the reference impedance 90 generates a correction voltage V according to the current I3 of the third transistor M3. CPK . The third transistor M3 can be a P-type MOS transistor or a P-type bipolar transistor. The third transistor M3 is described as a P-type bipolar transistor. For example, the switching circuit 50 includes a switch 53. The switch 53 is connected between the reference impedance 90 and the collector of the third transistor M3, and is controlled by the processor 61. In the second state, and when the second adjustment program is executed, the processor 61 sends a conduction signal, and the switch 53 responds to the conduction signal to conduct the connection between the reference impedance 90 and the third transistor M3. In the first state, the processor 61 sends a disconnection signal, and the switch 53 responds to the disconnection signal to disconnect (not conduct) the connection between the reference impedance 90 and the third transistor M3. When the connection between the reference impedance 90 and the collector of the third transistor M3 is conducted, the collector of the third transistor M3 generates a current I3, and the reference impedance 90 generates a correction voltage V according to the current I3. CPK For example, the correction voltage V CPKIt is equal to or approximately equal to the value obtained by multiplying the current I3 by the impedance value of the reference impedance 90. In some embodiments, the switch 53 can be implemented by an electronic switch (such as a transistor).

[0046] In some embodiments, similar to switch 53, the on and off operations of switches 51-52 are controlled by processor 61. In some embodiments, comparison impedance 90 is also connected to ground. For example, a first end of comparison impedance 90 is connected to ground, and a second end of comparison impedance 90 is connected to switch circuit 50. In other words, comparison impedance 90 is connected between switch circuit 50 and ground.

[0047] In some embodiments, memory 66 stores a temporary value. The temporary value is used to indicate whether to test the input / output pin 20. For example, the temporary value can be implemented as a flag value. When the flag value has a logic level of "0," it indicates that the input / output pin 20 is tested, and when the flag value has a logic level of "1," it indicates that the input / output pin 20 is not tested. However, the present invention is not limited to this. Alternatively, when the flag value has a logic level of "0," it indicates that the input / output pin 20 is not tested, and when the flag value has a logic level of "1," it indicates that the input / output pin 20 is tested.

[0048] The control circuit 60 determines whether to generate a detection signal DT based on the indication of the temporary value. When the temporary value indicates that the input / output pin 20 should not be detected, the control circuit 60 does not generate the detection signal DT and controls the switch circuit 50 to the first state. When the temporary value indicates that the input / output pin 20 should be detected, the control circuit 60 detects whether the input / output pin 20 is connected to the external impedance 70 and generates the detection signal DT. For example, when the temporary value indicates that the input / output pin should not be detected, the processor 61 controls the switch circuit 50 to the first state, and the first comparator 62 stops detecting the detection current I in the path between the pull-down impedance 63 and the voltage divider circuit 64. DET , and stops the detection voltage V DET When the temporary value indicates the detection input / output pin 20, the first comparator 62 detects whether the path between the pull-down impedance 63 and the voltage divider circuit 64 has a detection current I DET , and the detection voltage V DET Detect the changes.

[0049] In some embodiments, the temporary value can be input into the memory 66 by the user through the input / output interface (not shown). In some embodiments, the temporary value can be preset to indicate the detection of the input / output pin 20. In some cases, the user can know in advance that the input / output pin is connected to the external impedance 70 and input the temporary value indicating that the input / output pin 20 is not detected into the memory 66. In this way, the load of the integrated circuit 10 can be saved. For example, the first comparator 62 does not need to detect the current IDET And the detection voltage V DET Conduct testing.

[0050] In some embodiments, the adjustment circuit 65 includes a plurality of transistors, each of which is connected in parallel with the local impedance 30. For illustration, the plurality of transistors are P-type bipolar transistors. The adjustment circuit 65 varies the impedance of the plurality of transistors by varying the voltage at the base of the plurality of transistors, thereby adjusting the impedance of the local impedance 30. To increase the impedance of the local impedance 30, the adjustment circuit 65 reduces the voltage at the base of the plurality of transistors to increase the impedance of the plurality of transistors, thereby increasing the impedance of the local impedance 30. To reduce the impedance of the local impedance 30, the adjustment circuit 65 increases the voltage at the base of the plurality of transistors to reduce the impedance of the plurality of transistors, thereby reducing the impedance of the local impedance 30.

[0051] In some embodiments, the reference power circuit 40 may be a linear regulator (eg, a low-dropout regulator, LDO). Figure 1 As shown, the reference power circuit 40 includes an operational amplifier 41 and a fourth transistor M4. The output terminal of the operational amplifier 41 is connected to the fourth transistor M4. The fourth transistor M4 is described as an N-type bipolar transistor. The fourth transistor M4 is used to generate a reference current I according to the voltage of its base. ref (ie, reference signal). When the switch circuit 50 is controlled to the first state, the operational amplifier 41 generates a signal according to the reference current I ref and external impedance 70 to obtain feedback voltage V FB When the switch circuit 50 is controlled to the second state, the operational amplifier 41 is controlled according to the reference current I ref and local impedance 30 to obtain the feedback voltage V FB The operational amplifier 41 is based on the comparison voltage V BG And feedback voltage V FB , controls the voltage of the base of the fourth transistor M4 so that the reference current I ref is stably maintained at a current level. For example, at the reference current I ref When the reference current I ref ; At the reference current I ref When the voltage of the base of the fourth transistor M4 is increased due to some circumstances, the operational amplifier 41 reduces the voltage of the base of the fourth transistor M4 to reduce the reference current I ref , so that the reference current I ref is maintained at a stable current level.

[0052] In some embodiments, when the switch circuit 50 is controlled to the first state, the feedback voltage V FB is equal to or approximately equal to the reference current I ref The value obtained by multiplying the impedance value of the external impedance 70. When the switch circuit 50 is controlled to the second state, the feedback voltage V FB is equal to or approximately equal to the reference current I ref The value obtained by multiplying the impedance value by the local impedance 30.

[0053] In some embodiments, the comparison voltage V BG The comparison voltage V BG Can be different from the first voltage threshold V T1 and the second voltage threshold V T1 One or both of them, but the present invention is not limited thereto, the comparison voltage V BG Can be equal to: the first voltage threshold V T1 and the second voltage threshold V T1 One or both of them.

[0054] In some embodiments, as Figure 1 As shown, the integrated circuit 10 includes a fifth transistor M5 and a sixth transistor M6. The fifth transistor M5 is connected to the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, and the sixth transistor M6. The first transistor M1 is connected to the input / output pin 20. The second transistor M2 is connected to the pull-down impedance 63 and the first comparator 62. The sixth transistor M6 is connected to the reference power supply circuit 80. The fifth transistor M5 is used to obtain the reference current I obtained from the fourth transistor M4. ref (i.e., the reference signal) is output to the first transistor M1, the second transistor M2, the third transistor M3, and the sixth transistor M6. Thus, the first transistor M1, the second transistor M2, the third transistor M3, and the sixth transistor M6 can generate currents (e.g., the output current I1 of the first transistor M1, the detection current I DET , the current I3 of the third transistor M3 and the current I6 of the sixth transistor M6).

[0055] In some embodiments, the fifth transistor M5 can form a current mirror circuit with the first transistor M1, the second transistor M2, the third transistor M3 and the sixth transistor M6 to ensure that the reference current I ref The output current I1 of the first transistor M1 and the detection current I DET, the ratio between the current I3 of the third transistor M3 and the current I6 of the sixth transistor M6 is fixed or settable. For example, if the current mirror circuit is an adjustable current mirror, the ratio is settable. Specifically, the first transistor M1, the second transistor M2, the third transistor M3, the fifth transistor M5 and the sixth transistor M6 are N-type bipolar transistors for explanation. The base of the first transistor M1, the base of the second transistor M2, the base of the third transistor M3, the base of the fifth transistor M5 and the base of the sixth transistor M6 respectively receive a bias voltage V from a bias circuit (not shown). bias , to perform an action. The action may be, for example, starting to generate current or starting to transmit current. The collector of the fifth transistor M5 is connected to the base of the first transistor M1, the base of the second transistor M2, the base of the third transistor M3, the base of the fifth transistor M5, and the base of the sixth transistor M6, so that the fifth transistor M5 forms a current mirror circuit with the first transistor M1, the second transistor M2, the third transistor M3, and the sixth transistor M6.

[0056] It is worth noting that the transistors described herein can be implemented as N-type MOS transistors, N-type bipolar transistors, P-type MOS transistors, or P-type bipolar transistors. When implementing the transistors in a manner different from that described in the aforementioned embodiments, the disclosure of the present invention can be used to deduce how to appropriately adjust the architecture of the integrated circuit 10.

[0057] In summary, according to some embodiments, the use of either an external impedance or a local impedance to generate a reference signal is not limited to a single method for reference signal generation. In some embodiments, when an external impedance is connected to an input or output pin, the external impedance is initially used to generate the reference signal, thereby reducing the required area of ​​the integrated circuit design and lowering manufacturing costs. In some embodiments, the use of a local impedance to generate the reference signal reduces the probability of noise interference with the reference power supply.

Claims

1. An integrated circuit with self-referenced impedance, characterized in that include: Input and output pins for external impedance connection; local impedance; Reference power supply circuit; a switch circuit connected between the input / output pin, the local impedance, and the reference power circuit, so as to conduct the connection between the input / output pin and the reference power circuit in a first state and conduct the connection between the local impedance and the reference power circuit in a second state; and Control circuit for detecting whether the input / output pin is connected to the external impedance, and generating a detection signal; and controlling the switch circuit to be in the first state or the second state according to the detection signal; When the switch circuit is controlled to the first state, the reference power circuit generates a reference signal according to the external impedance. When the switch circuit is controlled to the second state, the reference power circuit generates the reference signal according to the local impedance. The reference signal is used as a reference power supply for the integrated circuit. When the control circuit detects that the input / output pin is connected to the external impedance, it generates the detection signal indicating the first state and controls the switch circuit to the first state. When the control circuit detects that the input / output pin is not connected to the external impedance, it generates the detection signal indicating the second state and controls the switch circuit to the second state. The control circuit includes a first comparator and a pull-down impedance. The first comparator is connected to the input / output pin and the pull-down impedance. The first comparator is used to compare the detection voltage with a first voltage threshold to generate the detection signal, wherein the detection voltage changes according to the external impedance and the pull-down impedance.

2. The integrated circuit with self-referenced impedance according to claim 1, wherein: When the input / output pin is connected to the external impedance, the detection voltage is greater than the first voltage threshold.

3. The integrated circuit with self-referenced impedance according to claim 2, wherein: The control circuit further includes a voltage divider circuit connected to the input / output pin, the first comparator, and the pull-down impedance. The voltage divider circuit is configured to generate a detection current according to the external impedance when the input / output pin is connected to the external impedance. The pull-down impedance generates the detection voltage greater than the first voltage threshold according to the detection current.

4. The integrated circuit with self-referenced impedance according to claim 1, wherein: When the input / output pin is not connected to the external impedance, the detection voltage is pulled down by the pull-down impedance and is not greater than the first voltage threshold.

5. The integrated circuit with self-referenced impedance according to claim 1, wherein: When the impedance value of the local impedance does not match the impedance target value, the control circuit generates a correction signal. When the switch circuit is controlled to the second state, the control circuit adjusts the impedance value in response to the correction signal, and the control circuit decides whether to adjust the impedance value using the first adjustment procedure or the second adjustment procedure based on the adjustment instruction.

6. The integrated circuit with self-referenced impedance according to claim 5, wherein: The control circuit includes a memory, the memory storing a comparison table and a plurality of different levels, the comparison table having the plurality of levels and a plurality of different impedance changes, and the plurality of levels respectively corresponding to the plurality of impedance changes, the first adjustment procedure including: Select one of the multiple levels; Obtaining the impedance change corresponding to the selected level according to the selected level and the comparison table; and The impedance value is adjusted according to the obtained impedance change.

7. The integrated circuit with self-referenced impedance according to claim 5, wherein: The control circuit includes a second comparator and a regulating circuit, and the second regulating process includes: The second comparator compares the second voltage threshold with the calibration voltage from the reference impedance; When the correction voltage is greater than the second voltage threshold, the regulating circuit reduces the impedance value; When the correction voltage is less than the second voltage threshold, the regulating circuit increases the impedance value; and When the correction voltage is equal to the second voltage threshold, the regulating circuit maintains the impedance value.

8. The integrated circuit with self-referenced impedance according to claim 1, characterized in that The control circuit includes a memory storing a temporary value for indicating whether to detect the input / output pin. The control circuit determines whether to generate the detection signal based on the indication of the temporary value. When the temporary value indicates not to detect the input / output pin, the control circuit does not generate the detection signal and controls the switch circuit to the first state. When the temporary value indicates to detect the input / output pin, the control circuit detects whether the input / output pin is connected to the external impedance and generates the detection signal.

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