Solid state drive and method of operating the same

Abstract

The application discloses a solid state disk and a running method thereof. The solid state disk comprises a main circuit board, a solid state disk master control chip, a storage chip and a data signal control module. The solid state disk master control chip and the storage chip are arranged on the main circuit board. The data signal control module is connected with the storage chip. The data signal control module is connected with the peripheral signal pin of the master control unit and controls the output of the data signal of the master control unit. The application can actively control the master control disconnection of the storage chip, thereby controlling the output of the data signal of the master control unit, avoiding the transmission interference of the data signal. When the master control unit needs to be started, the data signal control module can be used to start the master control unit. The error correction mechanism of the application can be used to correct the data signal, the working frequency of the error correction mechanism in the solid state disk master control chip is reduced, and the service life of the solid state disk is prolonged.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of data storage, and particularly relates to a solid state disk and a running method thereof. BACKGROUND

[0002] The development of NAND flash memory technology promotes the solid state disk industry. The solid state disk uses high-speed serial interfaces such as SATA, PICe and the like between the solid state disk and the host computer, and is internally composed of a group of NAND memory chips for storing data and a solid state disk controller (SSD Controller).

[0003] In the production process of the memory chip, some defective or poorly adapted problem memory chips are often generated, or there are defective or poorly adapted problem chips in some chip particles purchased, causing waste of the memory chip. How to utilize these problem chips to avoid cost waste becomes a problem to be solved. SUMMARY

[0004] The present application aims to provide a solid state disk and a running method thereof, which utilizes the problem memory chip to prepare the solid state disk, so as to reduce cost waste.

[0005] The present application discloses a solid state disk, which comprises a main circuit board, a solid state disk controller, a memory chip and a data signal control module, the solid state disk controller is arranged on the main circuit board; the memory chip is arranged on the main circuit board and connected with the solid state disk controller; the data signal control module is connected with the memory chip; wherein the memory chip comprises a master control unit and a wafer, the master control unit is integrated on the wafer, the data signal control module is connected with the peripheral signal pin of the master control unit and controls the output of the data signal of the master control unit.

[0006] Optionally, the memory chip comprises a UFS chip, the data signal control module comprises a control power circuit, the master control unit comprises a state indication pin, the state indication pin is connected with the control power circuit through a wire; the control power circuit controls the level of the state indication pin to control the output of the output signal of the memory chip.

[0007] Optionally, the solid state disk comprises a timing module, the timing module is connected with the storage chip and a control power supply circuit, the timing module records the time when the storage chip disconnects the data signal output; the control power supply circuit is connected with the master control unit of the storage chip, the solid state disk master control chip controls the conduction and shutdown of the control power supply circuit and the master control unit of the storage chip; when the timing module records the time when the storage chip disconnects the data signal output exceeds the preset time, the power supply circuit is controlled to disconnect the power supply to the master control unit.

[0008] Optionally, the master control unit comprises a first controller and a first error correction circuit, the first controller is connected with the first error correction circuit; the first controller is used for monitoring the erase times of the flash memory, controlling the first error correction circuit to determine whether to perform error correction according to the erase times, and controlling to disconnect the output of the data signal stored by the storage chip if the error correction stops.

[0009] Optionally, the solid state disk master control chip comprises a second controller and a second error correction circuit, the second controller and the second error correction circuit are connected; when the storage chip disconnects the output of the data signal, the second controller starts the second error correction circuit to perform error correction on the stored data.

[0010] The application also discloses a running method of a solid state disk, the running method is used for the solid state disk as any one of the above, and the running method comprises the steps of:

[0011] starting a first running mechanism of the solid state disk to control the data signal output of the storage chip; and

[0012] starting a second running mechanism of the solid state disk to control to disconnect the data signal output of the storage chip.

[0013] Optionally, before the step of starting the first running mechanism of the solid state disk to control the data signal output of the storage chip, the method comprises the steps of:

[0014] monitoring the erase times of the storage chip, if the erase times are less than the preset erase times, starting the first running mechanism of the solid state disk, and if the erase times are greater than the preset erase times, starting the second running mechanism of the solid state disk.

[0015] Optionally, the step of starting the first running mechanism of the solid state disk to control the data signal output of the storage chip comprises the steps of:

[0016] starting an error correction mechanism of the storage chip and stopping an error correction mechanism of the solid state disk master control chip.

[0017] Optionally, before the step of starting the second running mechanism of the solid state disk to control to disconnect the data signal output of the storage chip, the method comprises the steps of:

[0018] controlling the state indication pin level of the storage chip to be pulled high, and disconnecting the power supply to the storage chip.

[0019] Optionally, the step of monitoring the erasing times of the storage chip, if the erasing times are less than the preset erasing times, starting the first running mechanism of the solid state disk, if the erasing times are greater than the preset erasing times, starting the second running mechanism of the solid state disk comprises:

[0020] if the erasing times are less than the preset erasing times, starting the first running mechanism of the solid state disk, starting the error correction mechanism of the storage chip, stopping the error correction mechanism of the solid state disk master control chip; when the erasing times are greater than the preset erasing times, disconnecting the output of the data signal of the storage chip, starting the error correction mechanism of the solid state disk master control chip; the solid state disk master control chip starts the garbage collection mechanism, and the storage chip receives the garbage collection mechanism of the flash memory.

[0021] Compared with the prior art of using the master control damaged storage chip to prepare the solid state disk, the application can use the storage chip with the master control damaged but the wafer not damaged to prepare the solid state disk, and can also use the storage chip with low adaptability but the master control and wafer not damaged to prepare the solid state disk. By increasing the data signal control module, the master control of the storage chip can be actively disconnected, so as to control the output of the data signal of the master control unit, avoid the transmission interference of the data signal, and also start the master control unit through the data signal control module when needed, so as to correct the data signal by using the error correction mechanism of the storage chip, reduce the working times of the error correction mechanism in the solid state disk master control chip, and improve the service life of the solid state disk. BRIEF DESCRIPTION OF DRAWINGS

[0022] The accompanying drawings, which are included to provide a further understanding of the embodiments of the application and constitute a part of the specification, illustrate the embodiments of the application and together with the text description serve to explain the principles of the application. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative labor. In the drawings:

[0023] Figure 1 is a structural schematic diagram of a solid state disk of the first embodiment of the application;

[0024] Figure 2 is a structural schematic diagram of a solid state disk of the second embodiment of the application;

[0025] Figure 3 is a structural schematic diagram of a solid state disk of the third embodiment of the application;

[0026] Figure 4 This is a flowchart illustrating the operation method of the third embodiment of this application.

[0027] Among them, 100 is a solid-state drive; 200 is a main circuit board; 300 is a solid-state drive main control chip; 310 is a second controller; 320 is a second error correction circuit; 400 is a storage chip; 410 is a main control unit; 411 is a status indicator pin; 412 is a first controller; 413 is a first error correction circuit; 420 is a wafer; 500 is a data signal control module; 510 is a control power supply circuit; and 600 is a timing module. Detailed Implementation

[0028] It should be understood that the terminology, specific structural and functional details used herein are merely for describing particular embodiments and are representative. However, this application may be implemented in many alternative forms and should not be construed as being limited to the embodiments set forth herein.

[0029] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating relative importance or implying the number of technical features indicated. Therefore, unless otherwise stated, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature; "multiple" means two or more. The term "comprising" and any variations thereof mean non-exclusive inclusion, where one or more other features, integers, steps, operations, units, components, and / or combinations thereof may be present or added.

[0030] In addition, terms such as “center,” “horizontal,” “up,” “down,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inner,” and “outer” that indicate orientation or positional relationship are based on the orientation or relative positional relationship shown in the accompanying drawings. They are only for the purpose of simplifying the description of this application and do not indicate that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0031] Furthermore, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium, or internal connections between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0032] The present application will now be described in detail with reference to the accompanying drawings and optional embodiments.

[0033] likeFigure 1 As shown, as the first embodiment of the present application, a solid state disk 100 is disclosed, which comprises a main circuit board 200, a solid state disk master control chip 300, a storage chip 400 and a data signal control module 500, the solid state disk master control chip 300 is arranged on the main circuit board 200; the storage chip 400 is arranged on the main circuit board 200 and connected with the solid state disk master control chip 300 through corresponding wiring on the main circuit board 200; the data signal control module 500 is connected with the storage chip 400 through corresponding wiring on the main circuit board 200; wherein the storage chip 400 comprises a master control unit 410 and a wafer 413, the master control unit 410 is integrated on the wafer 413, the data signal control module 500 is connected with the peripheral signal pin of the master control unit 410 and controls the output of the data signal of the master control unit 410.

[0034] The data signal control module 500 in the solid state disk 100 is redesigned in the present application, which is mainly used for controlling the signal output of the storage chip 400 to avoid the interference of the signal output by the master control unit 410 of the storage chip 400 to other signals; the storage chip 400 used in the preparation of the solid state disk 100 of the present application is mainly a UFS chip with problems in the chip preparation process or purchased chip, of course, it can also be an EMMC chip; the Nand Flash signal pin connected with the UFS chip is used to design the solid state disk 100 in combination with the data signal control module 500, which not only can use the storage chip 400 with damaged master control but without problem wafer 413 to prepare the solid state disk 100, but also can use the storage chip 400 with low adaptability but without damaged master control and wafer 413 to prepare the solid state disk 100, by increasing the data signal control module 500, the master control of the storage chip 400 can be actively controlled to be disconnected, so as to control the output of the data signal of the master control unit 410, avoid the transmission interference of the data signal, at the same time, when the master control unit 410 needs to be started, it can also be started through the data signal control module 500, and then the error correction mechanism of the present application can be used to correct the data signal, reduce the working frequency of the error correction mechanism in the solid state disk master control chip 300, improve the service life of the solid state disk master control chip 300, and then improve the service life of the solid state disk 100.

[0035] Further, as Figure 2As shown, the data signal control module 500 includes a control power supply circuit 510, the master control unit 410 includes a state indication pin 411, and the state indication pin is connected to the control power supply circuit 510 through a wire; the control power supply circuit 510 controls the level of the state indication pin 411 (RB) to control the output of the output signal of the storage chip 400, and the level of the RB pin is pulled high by the peripheral control power supply circuit 510 to inform the master control unit 410 of the storage chip 400 that no data transmission is performed at this time, and the master control unit 410 enters a sleep state; when data transmission is required, the level of the RB pin is pulled low by the control power supply circuit 510 to inform the master control unit 410 of the storage chip 400 to perform data transmission, and the master control unit 410 enters a data transmission state.

[0036] In addition, the solid state disk 100 includes a timing module 600 connected to the storage chip 400 and the control power supply circuit 510, the timing module 600 records the time when the storage chip 400 disconnects the data signal output; the control power supply circuit 510 is connected to the master control unit 410 of the storage chip 400, and the solid state disk master control chip 300 controls the conduction and shutdown of the control power supply circuit 510 and the master control unit 410 of the storage chip 400; when the timing module 600 records the time when the storage chip 400 disconnects the data signal output exceeds the preset time, the power supply circuit is controlled to disconnect the power supply to the master control unit 410, and when the master control unit 410 of the storage chip 400 does not need to work, the power supply to the master control unit 410 can be directly cut off.

[0037] When no data transmission is performed for a long time, the solid state disk 100 controller directly disconnects the power supply of the master control unit 410 of the UFS or EMMC chip through the peripheral circuit, further reducing the chip power consumption. When data transmission is performed, the solid state disk 100 controller turns on the power supply of the master control unit 410 of the UFS chip and informs the master control unit 410 to enter the corresponding working state.

[0038] As shown in Figure 3 As a third embodiment of the present application, it is a further refinement of the above embodiments, referring to Figures 1 to 3As shown, the master control unit 410 includes a first controller 412 (also referred to as controller Core) and a first error correction circuit 413 (LDPC engine), and the first controller 412 is connected with the first error correction circuit 413; the first controller 412 is used for monitoring the erase times of the flash memory, and controlling the first error correction circuit 413 to determine whether to perform error correction according to the erase times, and if the error correction is stopped, controlling to disconnect the output of the data signal stored by the storage chip 400. The solid state disk master control chip 300 includes a second controller 310 and a second error correction circuit 320, and the second controller 310 and the second error correction circuit 320 are connected; when the storage chip disconnects the output of the data signal, the second controller 310 starts the second error correction circuit 320 to perform error correction on the stored data; it should be noted that, whether it is the solid state disk master control chip 300 or the storage chip 400, there is a master control unit 410 and a wafer 413, the master control is integrated on the wafer 413, the nand interface is arranged on the master control unit 410, and there is a corresponding controller Core and LDPC engine.

[0039] The solid state disk 100 is designed by using the Nand Flash signal pin of the UFS or EMMC chip, and the second controller 310 in the solid state disk 100 control chip and the first controller 412 in the UFS or EMMC are used together to improve the SSD flash data error correction, improve the data transmission reliability, service life and user experience.

[0040] Considering that the storage of data in the flash memory is represented by injecting and releasing the number of electrons in the smallest storage unit Cell in the flash memory. The use of the flash memory has a service life, and as the number of erase times of the flash memory increases, the probability of escape of electrons in the Cell increases, resulting in changes in the stored data. The first controller 412 in the UFS or EMMC is used to monitor the erase times of the flash memory, and when the erase times are low in the early stage, the first controller 412 of the UFS chip is used for data error correction and verification, and the error correction engine of the second controller 310 is released, which is responsible for data transmission. When the number of erase times increases, the first controller 412 of the UFS chip releases the data error correction and verification, and gives it to the second controller 310 of the solid state disk 100 chip which has stronger error correction capability; at the same time, the second controller 310 releases its own garbage collection mechanism, and the chip controller takes over the garbage collection mechanism of the flash memory, and the error correction mechanisms of the storage chip 400 and the master control chip are used alternately, so that the reliability of data transmission can be guaranteed, and the transmission performance is not reduced.

[0041] As shown in Figure 4 As a fourth embodiment of the present application, a running method of a solid state disk 100 is disclosed, and the running method is used for the solid state disk 100 as described in any of the above embodiments, and the running method includes the following steps:

[0042] S1: starting a first running mechanism of the solid state disk, controlling data signal output of the storage chip; and

[0043] S2: starting a second running mechanism of the solid state disk, controlling disconnection of data signal output of the storage chip.

[0044] By designing the solid state disk 100 with some bad or poorly adapted storage chips 400 or peripheral connection of Nand Flash signal pins of some bad chips or problem chips that cannot be adapted in the purchased chip particles, combined with the data signal control module, the solid state disk 100 can use two running mechanisms. If the bad chip is directly used, that is, the chip of the main control unit 410 is damaged, the first running mechanism can be directly used to disconnect the data signal output of the main control unit 410 to avoid interference of the output signal with other signals. The storage chip 400 with low adaptability can be compatible with the two running mechanisms. In the second running mechanism, the main control chip of the solid state disk 100 can also share data error correction verification, which can avoid errors caused by long-time running of the main control chip.

[0045] In addition, step S1 includes:

[0046] Starting the error correction mechanism of the storage chip and stopping the error correction mechanism of the main control chip 300 of the solid state disk.

[0047] When the main control unit 410 of the storage chip starts the error correction mechanism, the main control chip of the solid state disk 100 does not need to start the error correction mechanism, so that the working load of the main control chip of the solid state disk 100 can be reduced. Of course, in order to verify the accuracy of the data, the main control chip can also perform error correction again after the storage chip 400 completes error correction. Generally, the first controller 412 in the main control unit 410 of the storage chip 400 and the second controller 310 in the SSD decide which controller is responsible for decoding according to the number of flash memory erasures.

[0048] Before step S2 includes:

[0049] Controlling to pull up the level of the state indication pin of the storage chip and disconnecting the power supply to the storage chip.

[0050] When the second operation mechanism is started, in order to make the master unit 410 in the storage chip 400 invalid, the RB pin level is pulled high by the peripheral control power supply circuit 510 to inform the master unit 410 of the storage chip 400, at this time, no data transmission is performed, the master unit 410 enters a sleep state, when data transmission is required, the RB pin level is pulled low by the control power supply circuit 510 to inform the master unit 410 of the storage chip 400 to perform data transmission, and the master unit 410 enters a data transmission state.

[0051] Further, the timing module 600 is connected with the storage chip 400 and the control power supply circuit 510, the timing module 600 records the time when the storage chip 400 disconnects the data signal output, when the recorded time exceeds the preset time, the solid state disk master control chip 300 controls the control power supply circuit 510 to shut down the master unit 410 of the storage chip 400, disconnects the power supply to the master unit 410, and the master unit 410 of the storage chip 400 does not output the data signal.

[0052] Generally, before step S1, the following steps are further included:

[0053] S0: monitoring the erase times of the storage chip, if the erase times are less than the preset erase times, starting the first operation mechanism of the solid state disk, if the erase times are greater than the preset erase times, starting the second operation mechanism of the solid state disk.

[0054] Further, the step of monitoring the erase times of the storage chip, if the erase times are less than the preset erase times, starting the first operation mechanism of the solid state disk, if the erase times are greater than the preset erase times, starting the second operation mechanism of the solid state disk includes:

[0055] If the erase times are less than the preset erase times, the first operation mechanism of the solid state disk is started, the error correction mechanism of the storage chip is started, and the error correction mechanism of the solid state disk master control chip is stopped; when the erase times are greater than the preset erase times, the output of the data signal of the storage chip is disconnected, and the error correction mechanism of the solid state disk master control chip is started; the garbage collection mechanism of the solid state disk master control chip is started, and the garbage collection mechanism of the flash memory is received by the storage chip.

[0056] The application monitors the erase times of the flash memory by using the first controller 412 in the UFS or EMMC, when the erase times are low, the first controller 412 of the UFS chip is used for data error correction verification, the SSD controller error correction engine is released, and is responsible for data transmission; when the erase times increase, the first controller 412 of the UFS chip releases the data error correction verification, and gives the second controller 310 of the solid state disk 100 chip with stronger error correction capability. At the same time, the second controller 310 releases its own garbage collection mechanism, and the chip controller takes over the garbage collection mechanism of the flash memory. In this way, the reliability of data transmission can be guaranteed, the transmission performance is not reduced, and the data transmission reliability, service life and user experience are improved.

[0057] It should be noted that the limitations of the steps involved in the present scheme do not constitute a limitation on the order of the steps without affecting the implementation of the specific scheme. The steps written in the front can be executed first, or executed later, or even executed simultaneously, as long as the present scheme can be implemented, it should be considered to belong to the protection scope of the present application.

[0058] It should be noted that the inventive concept of the present application can form a very large number of embodiments, but the length of the application file is limited and cannot be listed one by one. Therefore, on the premise of not conflicting, the above described various embodiments or technical features can be combined to form new embodiments, and the combination of each embodiment or technical feature will enhance the original technical effect.

[0059] The above is a further detailed description of the present application in combination with specific optional embodiments, and the specific implementation of the present application cannot be limited to these descriptions. For ordinary skilled persons in the art to which the present application belongs, without departing from the concept of the present application, a number of simple deductions or substitutions can be made, which should be considered to belong to the protection scope of the present application.

Claims

1. A solid state drive, characterized by, The application relates to a solid state disk, which comprises the following components: a main circuit board; a solid state disk control chip arranged on the main circuit board; a storage chip arranged on the main circuit board and connected with the solid state disk control chip; a data signal control module connected with the storage chip; wherein the storage chip comprises a control unit and a wafer, the control unit is integrated on the wafer, the data signal control module is connected with the peripheral signal pin of the control unit and controls the output of the data signal of the control unit; the storage chip comprises a UFS chip, the data signal control module comprises a control power supply circuit, the control unit comprises a state indication pin, and the state indication pin is connected with the control power supply circuit through wiring; the control power supply circuit controls the level of the state indication pin to control the output of the output signal of the storage chip; the solid state disk comprises a timing module, the timing module is connected with the storage chip and the control power supply circuit, and the timing module records the time when the storage chip disconnects the data signal output; the control power supply circuit is connected with the control unit of the storage chip, and the solid state disk control chip controls the conduction and shutdown of the control power supply circuit and the control unit of the storage chip; when the time recorded by the timing module when the storage chip disconnects the data signal output exceeds a preset time, the power supply circuit is controlled to disconnect the power supply of the control unit; the control unit comprises a first controller and a first error correction circuit, and the first controller is connected with the first error correction circuit; the first controller is used for monitoring the erasing times of a flash memory, controlling the first error correction circuit to determine whether to perform error correction according to the erasing times, and controlling the output of the data signal stored by the storage chip to be disconnected if the error correction is stopped; the solid state disk control chip comprises a second controller and a second error correction circuit, and the second controller and the second error correction circuit are connected; when the storage chip disconnects the data signal output, the second controller starts the second error correction circuit to perform error correction on the stored data; the first controller monitors the erasing times of the flash memory, performs data error correction verification when the erasing times are low in the early stage, releases the error correction engine of the second controller, and is specially responsible for data transmission; when the erasing times increase, the first controller releases the data error correction verification and gives the second controller of the solid state disk chip which has stronger error correction capability; meanwhile, the second controller releases the garbage collection mechanism thereof, the chip controller takes over the garbage collection mechanism of the flash memory, and the error correction mechanisms of the storage chip and the control chip are alternately used.

2. A method of operating a solid state drive, characterized by, The operation method is used for the solid state disk in the application, and the operation method comprises the following steps: starting a first operation mechanism of the solid state disk to control the data signal output of the storage chip; and starting a second operation mechanism of the solid state disk to control the data signal output of the storage chip to be disconnected.

3. The method of operating of claim 2, wherein, The starting of the first operation mechanism of the solid state disk to control the data signal output of the storage chip comprises the following steps: The erase times of the storage chip are monitored, if the erase times are less than preset erase times, a first running mechanism of the solid state disk is started, if the erase times are greater than preset erase times, a second running mechanism of the solid state disk is started.

4. The method of operating of claim 2, wherein, The step of controlling the data signal output of the storage chip in the first running mechanism of the solid state disk comprises: The error correction mechanism of the storage chip is started, and the error correction mechanism of the solid state disk main control chip is stopped.

5. The method of operating of claim 2, wherein, The step of controlling the disconnection of the data signal output of the storage chip in the second running mechanism of the solid state disk comprises: The state indication pin level of the storage chip is pulled high, and the power supply to the storage chip is disconnected.

6. The method of operating of claim 3, wherein, The step of monitoring the erase times of the storage chip, if the erase times are less than preset erase times, a first running mechanism of the solid state disk is started, if the erase times are greater than preset erase times, a second running mechanism of the solid state disk is started, comprises: If the erase times are less than preset erase times, the first running mechanism of the solid state disk is started, the error correction mechanism of the storage chip is started, and the error correction mechanism of the solid state disk main control chip is stopped; if the erase times are greater than preset erase times, the output of the data signal of the storage chip is disconnected, and the error correction mechanism of the solid state disk main control chip is started; the garbage collection mechanism of the solid state disk main control chip is started, and the garbage collection mechanism of the flash memory is received by the storage chip.

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