An aviation ARINC429 bus receiving and decoding circuit system

Abstract

The present invention relates to the field of modular integrated circuits, and particularly to an aviation ARINC429 bus receiving and decoding circuit system. It includes: an input overvoltage protection unit, a common-mode rejection unit, a linear difference and attenuation unit, an anti-self-excitation unit, a reference level unit, and a comparison decoding and output unit. The input overvoltage protection unit is used to eliminate interference signals such as bus overshoot interference and electrostatic shock; the common-mode rejection unit can provide a reference zero potential in case of transmission line ground fault, reduce common-mode interference, and provide a signal loop; the linear difference and attenuation unit converts the bus bipolar differential-ended zeroed signal into a single-ended signal. This circuit adopts an overvoltage protection unit, a common-mode rejection unit, and a comparison decoding and output unit, eliminates bus overshoot interference and electrostatic shock interference signals, reduces common-mode interference, and the comparison decoding and output unit realizes hysteresis comparison, reduces the interference caused by signal glitches, and improves the reliability of aviation bus signal transmission.

Description

Technical Field

[0001] This solution belongs to the field of modular integrated circuits, and specifically relates to an aviation ARINC429 bus receiving and decoding circuit system. Background Art

[0002] The ARINC429 data bus can transmit thousands of different types of parameters between systems and devices, and is widely used in various fields such as aviation and aerospace today. This specification has rich data resources, high data accuracy, simple structure, stable performance, reliable transmission, and strong anti-interference ability, and is widely adopted by civil aviation and military avionics systems. The localization of aviation integrated circuits plays an important role in the scientific research of the aviation industry, the sustainable development of aviation, and military construction.

[0003] On the market, there are various types of ARINC-429 bus receiving and sending boards. In terms of the interface with industrial control computers, there are ISA interfaces, PCI interfaces, VXI interfaces, USB interfaces, etc. Regardless of the interface with the industrial control computer, the following problems generally exist in existing ARINC-429 bus receiving and sending boards: (1) The number of receiving and sending channels is small; (2) The received and sent data is unstable, the repeatability of the received and sent data is poor, and the received data is often lost; (3) When receiving and sending ARINC-429 data, there are often crashes.

[0004] The patent with the application number CN205983465U discloses a 6-receiving and 3-sending ARINC-429 bus receiving and sending board, which includes a circuit board and an embedded 16-BIT CPU (MSP430F149), 3 two-way data buffers (74HC245), 3 ARINC 429 transceivers (DEI 1016), 3 429 transmitters (BD429), JTAG-1 interface, hardware watchdog circuit, two-way data buffer, dual-port RAM-data memory (IDT7133SA55J68), two-way data buffer (74HC245), FPGA address decoder (EPM7032SLC44), and JTAG-2 interface installed on the circuit board.

[0005] This solution can be controlled by an embedded CPU (MSP430F149) and an industrial control computer to achieve 6-channel reception and 3-channel transmission of the ARINC-429 bus. This solution has little problem in low-speed, single LABEL number (each LABEL corresponds to a data type) reception applications, but in high-speed, multi-LABEL number cases, especially when the adjacent data interval time is small, it is easy to cause data loss due to interference signals such as bus overshoot interference and electrostatic shock. Summary of the Invention

[0006] This solution provides a receiving and decoding circuit system for an anti-interference ARINC429 bus.

[0007] To achieve the above object, this solution provides an aviation ARINC429 bus receiving and decoding circuit system, including an input overvoltage protection unit, a common-mode suppression unit, and a comparison decoding and output unit.

[0008] The input overvoltage protection unit is used to eliminate bus overshoot interference and electrostatic shock interference signals.

[0009] The common-mode suppression unit includes a base layer. One surface of the base layer forms a grounding layer through a dielectric layer and is set as a reference plane, and the relative other surface is a signal plane. Differential signal pairs are formed on the signal plane, and the middle value of the differential signals is connected to the receiving end GND.

[0010] The comparison decoding and output unit converts the single-ended signal into two digital signals for output to achieve hysteresis comparison.

[0011] An FPGA or MCU controller is used in combination to realize the reception and conversion of ARINC429 bus data.

[0012] The principle of this solution: Using controllers such as FPGA and MCU in combination with this circuit can realize the reception and conversion of ARINC429 bus data; the overvoltage protection unit eliminates bus overshoot interference and electrostatic shock interference signals; the common-mode suppression unit is connected to the signal ground of the receiving end after voltage division, provides a reference zero potential in case of a transmission ground wire fault, reduces common-mode interference, and provides a signal loop; the comparison decoding and output unit realizes hysteresis comparison and reduces the interference caused by signal glitches.

[0013] The beneficial effects of this solution:

[0014] (1) This circuit can convert the differential analog signal in the ARINC bus into a timing level recognizable by the digital system, and it is a circuit protocol conversion system that conforms to the electrical specification protocol of the ARINC429 bus.

[0015] (2) This circuit uses an overvoltage protection unit, a common-mode suppression unit, and a comparison decoding and output unit. In the case of high speed, multiple LABEL numbers, especially when the adjacent data interval time is relatively small, it eliminates bus overshoot interference and electrostatic shock interference signals, reduces common-mode interference. At the same time, the comparison decoding and output unit realizes hysteresis comparison, reduces the interference caused by signal glitches, and improves the reliability of aviation bus signal transmission.

[0016] (3) The ARINC429 signal can be adjusted to output different waveform signals for the FPGA and MCU controllers to recognize.

[0017] (4) Compared with imported chips such as HI-8588 and HI-8444 widely used in the industry, whose cost is about 120 yuan, the cost can be reduced to about 10 yuan by using the technical method of the present invention, which can greatly save costs for relevant enterprises and departments.

[0018] (5) This circuit can use domestic chips and components to make this system, replacing imported chips to meet the requirements of the avionics bus interface circuit.

[0019] Further, the input overvoltage protection unit uses a zener diode, which can eliminate interference signals such as bus overshoot interference, electrostatic shock, and lightning.

[0020] Further, the common-mode rejection unit includes two resistors of more than 200 KΩ. The common-mode rejection unit takes the middle value of the differential signal and connects it to the receiving end GND. After voltage division, it is connected to the signal ground of the receiving end and provides a signal loop.

[0021] Further, it also includes a linear difference attenuation unit, which is used to convert the bus bipolar differential zero signal into a single-ended signal, and the signal level range is 0-VCC. This unit uses an input-output rail-to-rail operational amplifier. When VCC is powered by 5V, the differential voltage is attenuated by 25%, and the ±10V differential signal can be converted into a 0-5V single-ended signal output. When VCC uses 3.3V, an output rail-to-rail operational amplifier is used, and still 25% attenuation can be used.

[0022] Further, it also includes an anti-self-excitation unit, which includes a capacitor bridging the output terminal and the inverting input terminal of the operational amplifier. The anti-self-excitation unit is used to prevent the system from self-exciting oscillation caused by high-frequency interference.

[0023] Further, it also includes the reference level unit. The reference level unit uses precision resistor voltage division and a voltage follower to implement three groups of reference levels. Among them, VREF is 1 / 2VCC, which is used to provide an intermediate reference level for single power supply. VH and VL are used for signal positive and negative level comparison. By adjusting the voltage division resistors of VH and VL, the threshold level can be modified. Among them, OUTA outputs a high level representing the binary digit 1, and OUTB outputs a high level representing the binary digit 0. The two outputs perform a binary "OR" operation to obtain the bus clock signal CLK. The reference level unit uses resistor voltage division and a voltage follower to implement a stable output reference level. The present invention can adjust the resistance and capacitance parameters according to the application environment, and then adjust the comparison level (threshold level) to improve the anti-interference ability to adapt to the environment.

[0024] Further, the comparison decoding output unit uses a hysteresis comparator to implement level comparison to improve the anti-interference characteristics. The two comparator output signals are used for digital system identification and analysis. The two comparison units are implemented using dedicated comparators or operational amplifiers, and the voltage conversion rate of the operational amplifier is not less than 5V / us.

[0025] Further, the power supply unit uses single power supply, and the power supply range is 3.3 - 5V. The power supply range is wide.

[0026] Further, the anti-self-oscillation unit uses a capacitor to prevent the system from self-oscillating due to high-frequency interference. When the single gain bandwidth of the operational amplifier is 10MHz, the capacitance of the anti-self-oscillation unit can be taken as 12pF - 20pF.

[0027] Further, the reference level unit uses resistor voltage division and a voltage follower to achieve a stable output reference level. Description of the Drawings

[0028] Figure 1 It is a schematic diagram of the technical principle structure of the present invention;

[0029] Figure 2 It is a detailed schematic diagram of a circuit of an implementation case adopting the present invention;

[0030] Figure 3 It is an interface definition and printed circuit board diagram of an implementation case of the present invention;

[0031] Figure 4 It is a waveform diagram of two-way decoding output of the ARINC429 bus in the actual application of the present invention. Detailed Implementation Modes

[0032] The following is a further detailed description through specific implementation modes:

[0033] The implementation example is basically as shown in the Figures 1-3 drawings:

[0034] An aviation ARINC429 bus receiving and decoding circuit system includes an input overvoltage protection unit, a common-mode rejection unit, a linear difference and attenuation unit, an anti-self-oscillation unit, a reference level unit, and a comparison decoding output unit. The power supply unit uses single power supply, and the power supply range is 3.3 - 5V.

[0035] The input overvoltage protection unit is used to eliminate bus overshoot interference and electrostatic impact interference signals; the input overvoltage protection unit uses a PSM712 integrated diode with 4 PN junctions to be protected from ESD, EFT, and lightning surges, and to eliminate the interference signals of the bus.

[0036] The common-mode rejection unit is used to connect the middle value of the differential signal to the receiving end GND, provide a reference zero potential in case of a transmission line ground fault, reduce common-mode interference, and provide a signal loop.

[0037] The common-mode rejection unit includes two resistors of more than 200KΩ.

[0038] The linear difference attenuation unit converts the bus bipolar differential zeroing signal into a single-ended signal; the signal level range is 0 - VCC. This unit uses an input-output rail-to-rail operational amplifier. When VCC is powered by 5V, the differential voltage is attenuated by 25%, and the ±10V differential signal can be converted into a 0 - 5V single-ended signal output. When VCC is 3.3V, an output rail-to-rail operational amplifier is used, and still 25% attenuation can be achieved.

[0039] The linear difference attenuation unit is implemented by operational amplifier U1.2, RG, RH, RE, and RF. In the linear difference attenuation unit, RE and RH use 51KΩ resistors, and RF and RH use 200KΩ resistors. The signal voltage attenuation ratio is 51K / 200K≈0.25. The differential voltage +10V to -10V will be converted into a "bipolar return-to-zero code" within the range of 0 - 5V for comparison output.

[0040] The anti-self-excitation unit is implemented by C1. The anti-self-excitation unit uses a capacitor to connect across the output terminal and the inverting input terminal of the operational amplifier. It prevents the system from self-exciting oscillation caused by high-frequency interference. When the single-gain bandwidth of the operational amplifier is 10MHz, the capacitance of the anti-self-excitation unit can be taken as 12pF - 20pF.

[0041] The comparison decoding output unit realizes voltage comparison by comparators U1.3 and U1.4 in combination with additional resistors RJ, RK, RM, and RN. When the voltage conversion rate of U1.3 and U1.4 is relatively low, these 4 resistors here can be omitted.

[0042] The reference level unit can provide three groups of reference levels required by the circuit; among them, VREF is 1 / 2VCC, which is used to provide an intermediate reference level for single-power supply. VH and VL are used for signal positive and negative level comparison. By adjusting the voltage-dividing resistors of VH and VL, the threshold level can be modified; among them, OUTA outputting a high level represents binary digit 1, and OUTB outputting a high level represents binary digit 0. The two-way output is used for binary "OR" operation to obtain the bus clock signal CLK.

[0043] The reference level unit uses resistor voltage division and a voltage follower to achieve a stable output reference level. The reference level unit is implemented by resistors RA, RB, RC, RD, and operational amplifier U1.1. RA and RD are taken as 11K, and RB and RC are taken as 10K. Then the threshold level VH is 5V * 31K / 42K = 3.69V, and VL is 5V * 11K / 42K = 1.31V. VH - VL = 2.38V, and differential signals between ±2.38 will be recognized as NULL (invalid) signals. Adjusting the resistance values of RA, RB, RC, and RD can configure the threshold level recognition range.

[0044] The comparison and decoding output unit converts a single-ended signal into two-channel digital signals for output. The comparison and decoding output unit uses a hysteresis comparator to implement level comparison to improve the anti-interference characteristics. The two-channel comparator output signals are used for digital system identification and analysis. The two-channel comparison unit can be implemented using a dedicated comparator or an operational amplifier, and the voltage conversion rate of the operational amplifier is not less than 5V / us.

[0045] As shown in the Figure 4 appendix:

[0046] Apply an ARINC429 signal of 100kbps at the circuit input terminal, and observe two output signals simultaneously at the circuit output terminal for use by controllers such as FPGA and MCU for identification.

[0047] The above are only embodiments of the present invention. Well-known specific structures and characteristics and other common knowledge are not described in detail here. It should be noted that for those skilled in the art, without departing from the structure of the present invention, several modifications and improvements can be made, and these should also be regarded as the protection scope of the present invention, and these will not affect the implementation effect of the present invention and the practicality of the patent. The protection scope required by this application should be based on the content of its claims, and the specific implementation manners described in the specification can be used to interpret the content of the claims.

Claims

1. An aviation ARINC429 bus receiving and decoding circuit system, characterized in that: It includes an input overvoltage protection unit, a common-mode suppression unit, and a comparison decoding output unit. The input overvoltage protection unit is used to eliminate bus overshoot interference and electrostatic impact interference signals. The common-mode suppression unit includes a base layer. One surface of the base layer forms a ground layer through a dielectric layer and is set as a reference plane, and the relative other surface is a signal plane. Differential signal pairs are formed on the signal plane. The differential signals take the intermediate value and are connected to the receiving end GND. The comparison decoding output unit converts the single-ended signal into two digital signals for output to achieve hysteresis comparison. An FPGA or MCU controller is combined with the system circuit to realize the reception and conversion of ARINC429 bus data. It also includes a linear difference attenuation unit. The linear difference attenuation unit is used to convert the bus bipolar differential zero signal into a single-ended signal, and the signal level range is 0 - VCC. This unit uses an input-output rail-to-rail operational amplifier. When VCC is powered by 5V, the differential voltage is attenuated by 25%, and the ±10V differential signal can be converted into a 0 - 5V single-ended signal for output. When VCC uses 3.3V, an output rail-to-rail operational amplifier is used, and still 25% attenuation can be used. It also includes an anti-self-excitation unit for preventing the system from self-exciting oscillation caused by high-frequency interference. The anti-self-excitation unit includes a capacitor bridging the output terminal and the inverting input terminal of the operational amplifier. It also includes the reference level unit. The reference level unit uses precision resistor voltage division and a voltage follower to realize three groups of reference levels. Among them, VREF is 1 / 2VCC, which is used to provide an intermediate reference level when powered by a single power supply. VH and VL are used for the comparison of the positive and negative signal levels. The threshold level is modified by adjusting the voltage division resistors of VH and VL. Among them, OUTA outputs a high level representing the binary digit 1, and OUTB outputs a high level representing the binary digit 0. The two outputs perform a binary "OR" operation to obtain the bus clock signal CLK.

2. The aviation ARINC429 bus receiving and decoding circuit system according to claim 1, wherein: The input overvoltage protection unit uses a zener diode.

3. The aviation ARINC429 bus receiving and decoding circuit system according to claim 1, wherein: The common-mode suppression unit includes two resistors of more than 200KΩ. The common-mode suppression unit takes the intermediate value of the differential signals and connects them to the receiving end GND.

4. The aviation ARINC429 bus receiving and decoding circuit system according to claim 1, characterized in that: The comparison decoding output unit uses a hysteresis comparator to realize level comparison to improve the anti-interference characteristics.

5. The aviation ARINC429 bus receiving and decoding circuit system according to claim 1, wherein: The power supply unit uses a single power supply for power supply, and the power supply range is 3.3 - 5V.

6. The aviation ARINC429 bus receiving and decoding circuit system according to claim 1, characterized in that: The anti-self-excitation unit uses a capacitor to prevent the system from self-exciting oscillation caused by high-frequency interference. When the single-gain bandwidth of the operational amplifier is 10MHz, the capacitance of the anti-self-excitation unit can be taken as 12pF - 20pF.

7. An aviation ARINC429 bus receiving and decoding circuit system according to claim 1, characterized in that: The reference level unit uses resistor voltage division and a voltage follower to realize a stable output reference level.

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